A semiconductor memory device and a method of manufacturing the same

Abstract

The application provides a semiconductor storage device and a preparation method thereof, and is applied to the technical field of semiconductor preparation. In the application, by synchronously forming the polycrystalline silicon material of the polycrystalline silicon resistor in the resistance region in the process of forming the gate structure of the high-voltage device in the logic region, the manufacturing method of the polycrystalline silicon resistor can be simplified without additional process technology, the corresponding structure of the polycrystalline silicon resistor is achieved, the related mask of the silicide blocking layer is provided with feasibility, and the process cost is reduced and the manufacturing period is shortened.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor memory device and its fabrication method. Background Technology

[0002] Polysilicon resistors are widely used in semiconductor chip circuit design. Circuit designers typically employ traditional N-type or P-type polysilicon resistors, but these resistors require a silicide block layer (SAB) as an additional mask during manufacturing to protect the silicon wafer surface. Under this protection, the silicon wafer does not form undesirable metal silicides with other metals such as Ti and Co, necessitating an additional photolithography step. Specifically, in existing technologies, N-type or P-type doped polysilicon used as polysilicon resistors is formed by N-type ion implantation (typically high-concentration boron (B) ion implantation) or P-type ion implantation (typically high-concentration phosphorus (P) ion implantation) on logic polysilicon (which is itself undoped). Both methods require a silicide block layer as a photomask. However, the introduction of the silicide block layer increases the complexity of the process and the manufacturing cost. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to address the above-mentioned defects in the prior art by providing a method that can prevent the formation of metal silicides on the surface of polysilicon resistors without using a silicide barrier layer, thereby increasing the resistivity of polysilicon resistors, simplifying the manufacturing method of polysilicon resistors, and providing the corresponding polysilicon resistor and semiconductor memory device structure.

[0004] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for fabricating a semiconductor memory device, comprising at least the following steps:

[0005] Provides a base, including a storage area, a logic area, and a resistor area;

[0006] A first storage polysilicon layer and an isolation layer are formed, wherein the first storage polysilicon layer is located on the substrate of the storage region, the logic region, and the resistor region, and the isolation layer is located on the first storage polysilicon layer;

[0007] Remove a portion of the isolation layer and a portion of the first storage polysilicon layer on the logic region, exposing a portion of the substrate of the logic region;

[0008] A second storage polysilicon layer is formed on the exposed portion of the substrate of the logic region and the isolation layer of the resistive region;

[0009] A conductive plug is formed on the resistive region, and the bottom of the conductive plug is electrically connected to the top surface of the first storage polysilicon layer in the resistive region.

[0010] In an optional example, prior to forming the conductive plug, the following may also be included:

[0011] A portion of the second storage polysilicon layer in the logic region is removed to form at least one discrete gate structure on the logic region.

[0012] In an optional example, during the removal of a portion of the second storage polysilicon layer in the logic region, a portion of the second storage polysilicon layer in the resistor region is also removed simultaneously to expose a portion of the first storage polysilicon layer in the resistor region.

[0013] In an optional example, prior to forming the second storage polysilicon layer, the following may also be included:

[0014] A gate oxide layer for the logic region is formed on the exposed portion of the substrate of the logic region and the isolation layer of the resistive region.

[0015] In an optional example, prior to forming the first storage polysilicon layer, the following may also be included:

[0016] A trench isolation structure is formed within the substrate of the resistive region.

[0017] In an optional example, the first storage polysilicon layer located in the resistive region may serve as a polysilicon resistor.

[0018] In an optional example, the logic region may include a high-voltage device region; the portion of the substrate exposed when a portion of the isolation layer and the first storage polysilicon layer on the logic region is removed is aligned with the high-voltage device region.

[0019] In an optional example, after forming the first storage polysilicon layer, the following may also be included:

[0020] An ion implantation process is performed on the first storage polysilicon layer in the resistive region.

[0021] In an optional example, the first storage polysilicon layer may include a word line layer of a memory cell in an embedded memory device.

[0022] Secondly, based on the same inventive concept, the present invention also provides a semiconductor memory device, which can be fabricated using the semiconductor memory device fabrication method described above, wherein the substrate includes a resistive region, the resistive region including: a first storage polysilicon layer, an isolation layer, a logic gate oxide layer, and a second storage polysilicon layer.

[0023] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0024] The present invention provides a method for fabricating a semiconductor memory device, comprising: providing a substrate including a memory region, a logic region, and a resistor region; forming a first memory polysilicon layer and an isolation layer, wherein the first memory polysilicon layer is located on the substrate of the memory region, the logic region, and the resistor region, and the isolation layer is located on the first memory polysilicon layer; removing a portion of the isolation layer and a portion of the first memory polysilicon layer on the logic region, exposing a portion of the substrate of the logic region; forming a second memory polysilicon layer located on the exposed portion of the substrate of the logic region and the isolation layer of the resistor region; forming a conductive plug located on the resistor region, wherein the bottom of the conductive plug is electrically connected to the top surface of the first memory polysilicon layer in the resistor region.

[0025] In this invention, on the one hand, by simultaneously forming polysilicon material for polysilicon resistors in the resistor region during the formation of the gate structure of the high-voltage device in the logic region, the manufacturing method and structure of polysilicon resistors can be simplified without adding additional process technology. On the other hand, by stacking a first storage polysilicon layer and a second storage polysilicon layer in the resistor region, the second storage polysilicon layer acts as a shield to prevent the formation of metal silicides in the underlying first storage polysilicon layer, which serves as a polysilicon resistor, thus achieving the same function as a silicide barrier layer. Therefore, this invention advantageously avoids the use of a silicide barrier layer by utilizing the second storage polysilicon layer as a mask for a non-silicide structure, eliminating all process technology required to form a silicide barrier layer, thereby further simplifying the process technology of semiconductor memory devices, reducing process costs, and shortening the manufacturing cycle. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0027] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor memory device according to an embodiment of the present invention.

[0028] Figures 2-5 This is a schematic diagram of the semiconductor memory device provided in one embodiment of the present invention during the fabrication process.

[0029] Among them, Figures 2-5 middle:

[0030] 100 - Substrate; 101 - Storage region; 102 - Logic region; 103 - Resistor region; 102HN - High voltage N region; 102HP - High voltage P region; 102LN - Low voltage N region; 102LP - Low voltage P region; 110 - Coupling oxide layer; 120 - Shallow trench isolation structure; 130 - Storage cell; 140 - First storage polysilicon layer; 150 - Isolation layer; 160 - Logic region gate oxide layer; 170 - Second storage polysilicon layer; 180 - Photoresist layer; 190 - Gate structure; 200 - Conductive plug.

[0031] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0032] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0033] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" means not only "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.

[0034] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0035] In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0036] Please refer to Figure 1 The illustration shows a flowchart of a method for fabricating a semiconductor memory device according to an embodiment of the present invention. The semiconductor device of the present invention can be used to manufacture embedded flash memory devices, and without departing from the spirit of the present invention, it can also be applied to other types of memory.

[0037] like Figure 1 As shown, the method for fabricating the semiconductor memory device includes the following steps:

[0038] Step S101: Provide a substrate, including a storage area, a logic area, and a resistor area.

[0039] Step S102: A first storage polysilicon layer and an isolation layer are formed. The first storage polysilicon layer is located on the substrate of the storage region, the logic region, and the resistor region, and the isolation layer is located on the first storage polysilicon layer.

[0040] Step S103: Remove a portion of the isolation layer and a portion of the first storage polysilicon layer on the logic region, exposing a portion of the substrate of the logic region.

[0041] Step S104: A second storage polysilicon layer is formed on the exposed portion of the substrate of the logic region and the isolation layer of the resistive region.

[0042] Step S105: A conductive plug is formed on the resistive region, and the bottom of the conductive plug is electrically connected to the top surface of the first storage polysilicon layer in the resistive region.

[0043] In the method for fabricating a semiconductor memory device according to the present invention, the memory region is used to fabricate the MOS transistor of the memory cell of a semiconductor memory device, such as an embedded flash memory device; the logic region is used to fabricate the logic MOS device of a semiconductor memory device, such as an embedded flash memory device; and the resistor region is used to fabricate the resistor of the memory region or the logic region, such as a polysilicon resistor, but not limited thereto. Furthermore, the logic region can be specifically divided into a high-voltage device region and a low-voltage region, etc., based on the actual operating voltage of the logic MOS device, but is not limited thereto. Therefore, the present invention can simplify the manufacturing method of polysilicon resistors and the corresponding polysilicon resistor structure without adding additional process technology by simultaneously forming the polysilicon material of the polysilicon resistor in the resistor region during the process of forming the gate structure of the high-voltage device in the logic region. It also provides feasibility for reducing the number of masks related to the silicide stop layer, thereby reducing process costs and shortening the manufacturing cycle.

[0044] To enable those skilled in the art to easily understand the fabrication method of the semiconductor memory device in the embodiments of this invention, the fabrication method of the semiconductor memory device proposed in this invention will be further described below with reference to various structural schematic diagrams during the fabrication process. Please refer to... Figures 2-5 As shown, the illustration is a structural schematic diagram of the fabrication process of the semiconductor memory device provided in the embodiment of the present invention.

[0045] To perform step S101 above, please refer to [link / reference]. Figure 2 A substrate 100 is provided, which may include a storage region 101, a logic region 102, and a resistor region 103. In one embodiment, the substrate 100 may be, for example, a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a III-V compound substrate (e.g., a silicon nitride substrate or a gallium arsenide substrate), a silicon carbide substrate or a stacked structure thereof, or a diamond substrate, or other semiconductor material substrates known to those skilled in the art. Exemplarily, the substrate 100 is a silicon substrate, but this is not a limitation. The storage region 101, the logic region 102, and the resistor region 103 may be arranged adjacent to each other, but this is not a limitation. The logic region 102 may specifically include a high-voltage device region and a low-voltage device region. The high-voltage device region may further include a high-voltage N-region 102HN for forming NMOS transistors and a high-voltage N-region 102HP for forming PMOS transistors. Similarly, the low-voltage device region may also include a low-voltage N-region 102LN for forming NMOS transistors and a low-voltage N-region 102LP for forming PMOS transistors, but is not limited thereto.

[0046] It should be understood that, in order to form the high-voltage or low-voltage NMOS transistor or PMOS transistor, after providing the substrate 100, N-type or P-type ion implantation can be performed on different parts of the substrate 100 based on different partitions of the substrate 100 to form N-wells or P-wells adapted to the types of different types of transistors to be formed in the different partitions, as well as multiple shallow trench isolation structures 120 for isolating the different partitions, but not limited thereto.

[0047] To perform step S102 above, please refer to the following: Figure 2 Using at least one of deposition processes, such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition, a coupling oxide layer 110 is formed on the entire surface of the substrate 100. Then, using photolithography and etching processes, the plurality of shallow trench isolation structures 120 are formed, and a plurality of memory cells 130 are formed on the memory region 101 of the substrate 100. The memory cells 130 may be dual-bit memory structures sharing a source line. For the sake of simplicity, the figures in this embodiment of the invention only show one memory cell 130 on the memory region 101. Then, using a deposition process such as chemical vapor deposition, a first memory polysilicon layer 140 and an isolation layer 150 are sequentially and conformally formed on the memory region 101, the logic region 102, and the resistor region 103 of the substrate 100.

[0048] In one embodiment, the coupling oxide layer 110 and the shallow trench isolation structure 120 may be made of oxides, such as silicon dioxide. The memory cell 130 may include components and / or devices such as a floating gate layer (not shown), an interlayer dielectric layer (not shown), a control gate layer (not shown), sidewalls (not shown), and source lines (not shown). The first memory polysilicon layer 140 is made of polysilicon, and it may be the word line polysilicon layer (MPOL) of the memory cell 130, but is not limited thereto. The isolation layer 150 may be made of oxides such as silicon dioxide, or nitrides such as silicon nitride, but is not limited thereto.

[0049] In other embodiments, at least one of the shallow trench isolation structures 120 may also be located within the substrate 100 of the resistive region 103, so that the subsequently formed film structure is located on the shallow trench isolation structure 120, but this is not a limitation; after the formation of the first storage polysilicon layer 140, an ion implantation process may be further used to perform N-type or P-type ion implantation on the first storage polysilicon layer 140 located in the resistive region 103 to change the resistance value of the first storage polysilicon layer 140, which is a polysilicon resistor, but this is not a limitation.

[0050] It should be understood that "common" in the embodiments of the present invention refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.

[0051] To perform step S103 above, please refer to [link / reference]. Figure 3 First, a photoresist layer (not shown) is formed to shield the storage region 101, the resistor region 103, and part of the logic region 102 of the substrate 100. The portion of the logic region 102 exposed by the photoresist layer may be the high-voltage device region 102H. Then, using the photoresist layer as a mask, an etching process, such as a dry etching process, is used to remove the isolation layer 150 and the first storage polysilicon layer 140 located in the high-voltage device region 102H that are not shielded by the photoresist layer, so as to re-expose the coupling oxide layer 110 of the high-voltage device region.

[0052] To perform step S104 above, please refer to [link / reference]. Figure 4 Furthermore, using a deposition process such as chemical vapor deposition, a logic region gate oxide layer 160 and a second storage polysilicon layer 170 are conventionally formed from bottom to top on the storage region 101, the logic region 102, and the resistive region 103 of the substrate 100. In one embodiment, the logic region gate oxide layer 160 is made of silicon dioxide and is used as the gate oxide for high-voltage devices NMOS transistors and PMOS transistors, and the second storage polysilicon layer 170 may be made of polysilicon and is used as the gate layer for high-voltage devices NMOS transistors and PMOS transistors.

[0053] To perform step S105 above, please refer to [link / reference]. Figure 5 First, a portion of the second storage polysilicon layer 170 in the logic region 102 and a portion of the second storage polysilicon layer 170 in the resistor region 103 can be formed, exposing a photoresist layer 180 in the logic region 102 and the resistor region 103. Then, using the photoresist layer 180 as a mask, the second storage polysilicon layer 170 and the logic region gate oxide layer 160 not covered by the photoresist layer 180 are etched downwards in a direction perpendicular to the surface of the substrate 100 to remove the second storage polysilicon layer 170 and the logic region gate oxide layer 160, so as to form a plurality of gate structures 190, such as the gate structures of the high voltage device NMOS transistor and PMOS transistor, in the high voltage device region 102H of the logic region 102. Furthermore, during the process of removing a portion of the second storage polysilicon layer 170 in the logic region 102, a portion of the second storage polysilicon layer 170 in the resistor region 103 is also removed simultaneously to expose a portion of the first storage polysilicon layer 140 in the resistor region 103.

[0054] Next, a dielectric layer (not shown) may be formed within the resistive region 103 of the substrate 100, and a plurality of conductive plugs 200 electrically connected through the dielectric layer to the first storage polysilicon layer 140 exposed in the resistive region 103. In one embodiment, the dielectric layer may be made of an insulating material, such as silicon oxide or silicon nitride, and the conductive plugs 200 may be made of tungsten or aluminum, but are not limited thereto.

[0055] Furthermore, based on the same inventive concept, the present invention also provides a semiconductor memory device formed using the semiconductor memory device fabrication method described above, wherein the semiconductor memory device includes a substrate 100, the substrate 100 includes a resistive region 103, the resistive region 103 includes: a first storage polysilicon layer 140, an isolation layer 150, a logic region gate oxide layer 160, and a second storage polysilicon layer 170, the specific formation process of which can be referred to the explanation of the fabrication method described above, and the present invention will not repeat it here.

[0056] In summary, the present invention provides a method for fabricating a semiconductor memory device, comprising: providing a substrate including a memory region, a logic region, and a resistor region; forming a first memory polysilicon layer and an isolation layer, wherein the first memory polysilicon layer is located on the substrate of the memory region, the logic region, and the resistor region, and the isolation layer is located on the first memory polysilicon layer; removing a portion of the isolation layer and a portion of the first memory polysilicon layer on the logic region, exposing a portion of the substrate of the logic region; forming a second memory polysilicon layer located on the exposed portion of the substrate of the logic region and the isolation layer of the resistor region; forming a conductive plug located on the resistor region, wherein the bottom of the conductive plug is electrically connected to the top surface of the first memory polysilicon layer in the resistor region.

[0057] In this invention, on the one hand, by simultaneously forming polysilicon material for polysilicon resistors in the resistor region during the formation of the gate structure of the high-voltage device in the logic region, the manufacturing method and structure of polysilicon resistors can be simplified without adding additional process technology. On the other hand, by stacking a first storage polysilicon layer and a second storage polysilicon layer in the resistor region, the second storage polysilicon layer acts as a shield to prevent the formation of metal silicides in the underlying first storage polysilicon layer, which serves as a polysilicon resistor, thus achieving the same function as a silicide barrier layer. Therefore, this invention advantageously avoids the use of a silicide barrier layer by utilizing the second storage polysilicon layer as a mask for a non-silicide structure, eliminating all process technology required to form a silicide barrier layer, thereby further simplifying the process technology of semiconductor memory devices, reducing process costs, and shortening the manufacturing cycle.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor memory device, characterized by, Comprising: providing a substrate including a memory region, a logic region, and a resistance region; forming a first storage polysilicon layer on the substrate of the memory region, the logic region, and the resistance region, and forming an isolation layer on the first storage polysilicon layer; removing part of the isolation layer and part of the first storage polysilicon layer on the logic region, and exposing part of the substrate of the logic region; forming a second storage polysilicon layer on the exposed part of the substrate of the logic region and the isolation layer of the resistance region; forming a conductive plug on the resistance region, a bottom of the conductive plug being electrically connected with a top surface of the first storage polysilicon layer in the resistance region; before forming the conductive plug, further comprising: removing part of the second storage polysilicon layer in the logic region to form at least one discrete gate structure on the logic region.

2. The method of manufacturing a semiconductor memory device according to claim 1, wherein In the process of removing part of the second storage polysilicon layer in the logic region, part of the second storage polysilicon layer in the resistance region is also removed synchronously to expose part of the first storage polysilicon layer in the resistance region.

3. The method of producing a semiconductor memory device according to Claim 1, wherein before forming the second storage polysilicon layer, further comprising: forming a logic region gate oxide layer on the exposed part of the substrate of the logic region and the isolation layer of the resistance region.

4. The method of producing a semiconductor memory device according to Claim 1, wherein before forming the first storage polysilicon layer, further comprising: forming a trench isolation structure in the substrate of the resistance region.

5. The method of producing a semiconductor memory device according to Claim 1, wherein The first storage polysilicon layer in the resistance region serves as a polysilicon resistor.

6. The method of producing a semiconductor memory device according to Claim 1, wherein The logic region includes a high-voltage device region; the part of the substrate exposed when part of the isolation layer and the first storage polysilicon layer on the logic region are removed is aligned with the high-voltage device region.

7. The method of producing a semiconductor memory device according to Claim 1, wherein after forming the first storage polysilicon layer, further comprising: performing an ion implantation process on the first storage polysilicon layer in the resistance region.

8. The method of producing a semiconductor memory device according to Claim 1, wherein The first storage polysilicon layer includes a word line layer of a memory cell in an embedded storage device.

9. A semiconductor memory device, characterized by comprising: The semiconductor storage device is prepared by the preparation method of any one of claims 1-8, wherein the substrate includes a resistance region, and the resistance region includes a first storage polysilicon layer, an isolation layer, a logic region gate oxide layer, and a second storage polysilicon layer.

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