Semiconductor device and manufacturing method thereof
By performing multi-step decomposition and real-time online monitoring in the cleaning process of NORD flash memory devices, combined with the use of barrier layers, the leakage problem caused by the wet side digging of the trench isolation of the flash memory device during the wet etching process is solved, and the reliability and performance of the device are improved.
Patent Information
- Application Number
- CN202510238108.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-06-03
AI Technical Summary
During the wet etching process of NORD flash memory devices, the etching rate of the insulating material becomes faster, resulting in the wet trench isolation being pulled out by the wet trench. The distance between the control gate layer and the word line is too close, making leakage problems prone to occur.
By performing multi-step decomposition of the cleaning process before forming the gate oxide layer, and real-time online monitoring of the thickness of the trench isolation, combined with the use of the barrier layer, the problem of the distance between the control gate layer and the word line is avoided.
It effectively avoids the leakage problem caused by wet side digging of trench isolation, improves the reliability and performance of NORD flash memory devices, simplifies the process technology, and reduces the production cost.
Smart Images
Figure CN120091565A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art
[0002] As a non-volatile memory device, a flash memory device controls the switching of a gate channel by changing the critical voltage of a transistor or a memory cell, so as to achieve the purpose of storing data, and the data stored in the memory will not be lost due to power interruption.
[0003] For NORD flash memory devices, the trench isolation (such as a shallow trench isolation structure, STI) used to isolate different active region strips will have a faster etching rate of the insulating material (such as oxide) contained therein during the wet etching process after the ion implantation and etching processes of the NORD flash memory device. Therefore, in the wet pre-cleaning process before forming the gate oxide layer, the trench isolation is inevitably undercut by wet etching, and the control gate layer and the word line located on the trench isolation are too close, resulting in leakage problems. Summary of the Invention
[0004] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, by decomposing the cleaning process before forming the gate oxide layer into multiple steps and combining with real-time online monitoring of the thickness of the trench isolation, to avoid the problem of leakage caused by the control gate layer and the word line being too close due to the undercut of the trench isolation by wet etching.
[0005] In a first aspect, to solve the above technical problems, the present invention provides a manufacturing method of a semiconductor device, which at least includes the following steps:
[0006] Provide a substrate, including a plurality of active regions and a head region located on one side of the plurality of active regions;
[0007] Form a flash memory device component on the substrate in the active region and the head region, and the flash memory device component includes a floating gate layer, a shallow trench isolation structure, an interlayer dielectric layer, a control gate layer, and a first sidewall;
[0008] Form a barrier layer on the outer surface of the first sidewall in the head region and on a part of the top surface of the control gate layer;
[0009] Etch and remove a part of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active region and the head region, and form a plurality of mutually spaced storage units in the active region.
[0010] Optionally, the barrier layer may be at least one of a spin-on hard mask material, a spin-on carbon material, an anti-reflection coating, or a photoresist.
[0011] Optionally, during the process of etching away a part of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active region and the end region, the photoresist material can be used as the mask for the barrier layer.
[0012] Optionally, the substrate may further include a logic region, a gate structure may be provided on the logic region, and the first sidewall may further extend to cover the sidewalls of the gate structure.
[0013] Optionally, the method for manufacturing the semiconductor device further includes:
[0014] Forming a second sidewall on the sidewalls of the first sidewall in the active region and the logic region.
[0015] Optionally, the step of forming a flash memory device on the substrate in the active region and the end region may include:
[0016] Forming the floating gate layer on the substrate in the active region and the end region;
[0017] Forming a plurality of shallow trench isolation structures spaced apart from each other on the active region and the end region, the shallow trench isolation structures including a first shallow trench isolation structure in the active region and a second trench isolation structure in the end region;
[0018] Forming the interlayer dielectric layer and the control gate layer stacked in sequence on the floating gate layer and the shallow trench isolation structures;
[0019] Forming an opening in the middle region of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active region to expose a part of the substrate or a part of the shallow trench isolation structures;
[0020] Forming a gate oxide layer and a word line layer in the opening, the gate oxide layer being on the inner surface of the opening, and the word line layer filling the remaining space of the opening.
[0021] Optionally, the top surface of the shallow trench isolation structure may be flush with the top surface of the floating gate layer.
[0022] Optionally, the width of the first shallow trench isolation structure in the horizontal direction may be less than the width of the second shallow trench isolation structure in the horizontal direction.
[0023] Optionally, after forming a plurality of the memory cells in the active region by etching, a part of the control gate layer may remain on a part of the second shallow trench isolation structure that is in direct contact with the first sidewall in the end region.
[0024] Optionally, the memory cell may include a dual storage bit structure sharing a word line.
[0025] In a second aspect, based on the same inventive concept, the present invention also provides a semiconductor device, which can be specifically fabricated by using the manufacturing method of the semiconductor device described above.
[0026] Optionally, the semiconductor device may have a substrate, and the substrate may include an end region, and the end region may include a first sidewall and a second shallow trench isolation structure; wherein, a control gate layer is formed on a part of the second shallow trench isolation structure that is in direct contact with the first sidewall.
[0027] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:
[0028] The present invention provides a manufacturing method of a semiconductor device, including: providing a substrate including a plurality of active regions and an end region on one side of the plurality of active regions, forming a flash memory device component on the substrate of the active regions and the end region, the flash memory device component including a floating gate layer, a shallow trench isolation structure, an interlayer dielectric layer, a control gate layer, and a first sidewall, forming a blocking layer on an outer surface of the first sidewall in the end region and a part of a top surface of the control gate layer, etching and removing a part of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active region and the end region, and forming a plurality of spaced-apart memory cells in the active region.
[0029] In the present invention, a part of the control gate layer and the first sidewall in the end region are shielded by the blocking layer. Then, after etching the control gate layer to form a plurality of discrete memory cells subsequently, a part of the control gate layer that is in direct contact with the first sidewall in the end region is retained, that is, the width at the position of the first sidewall in the end region is increased in the horizontal direction, avoiding the problem that the first sidewall in the end region is prone to peeling due to a large aspect ratio at this position. Further, by setting the blocking layer as a photoresist mask layer during the process of etching the control gate layer to form a plurality of discrete memory cells subsequently, the manufacturing process is simplified, the manufacturing cost is reduced, and the reliability and performance of the NORD flash memory device are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 is a schematic flow chart of the manufacturing method of the semiconductor device in an embodiment of the present invention.
[0031] Figures 2 to 10 is a schematic structural diagram of the manufacturing method of the semiconductor device in an embodiment of the present invention during the manufacturing process.
[0032] Among them, in Figures 1 to 10 :
[0033] 100 - Substrate, 101 - Storage area, 102 - End area, 103 - Logic area, AR - Active region, 110 - Coupling oxide layer, 120 - Floating gate layer, 130 - Shallow trench isolation structure, 131 - First shallow trench isolation structure, 132 - Second shallow trench isolation structure, 140 - Interlayer dielectric layer, 150 - Control gate layer, 160 - Sidewall, 161 - First sidewall, 162 - Second sidewall, 170 - Gate oxide layer, 180 - Word line layer, 191 - First sidewall, 192 - Second sidewall, 200 - Barrier layer, 251 - Gate structure in the logic area, 210 - Tunneling oxide layer, 220 - Gate layer. Detailed implementation manners
[0034] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present invention and to be able to convey the scope of the present invention completely to those skilled in the art.
[0035] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present invention will be clearer according to the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non - precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "overhead...", in the present invention should be interpreted in the broadest way, so that "on..." not only means "on" something "without any intermediate features or layers (i.e., directly on something)", but also includes the meaning of "on" something "with intermediate features or layers".
[0036] In addition, for the sake of convenience of description, spatial relative terms such as "on...", "above...", "overhead...", "upper", "upper part", etc. can be used in this article to describe the relationship between one element or feature and another element or feature as shown in the figures. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive words used herein can be interpreted accordingly.
[0037] In the embodiments of the present invention, terms such as "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be combined arbitrarily without conflict.
[0038] It should be noted that the manufacturing method of the semiconductor device provided in the embodiments of the present invention is used for the manufacturing process of a dual-bit flash memory device with shared word lines. Under this setting, hereinafter, the flash memory device in the accompanying drawings with the structure of a dual-bit flash memory device with shared word lines will be used as an example to draw the accompanying drawings and explain the manufacturing process method.
[0039] Please refer to Figure 1 , Figure 1 The flowchart shown is of the manufacturing method of the semiconductor device in an embodiment of the present invention. The manufacturing method provided by the present invention may at least include:
[0040] Step S101: Provide a substrate including a plurality of active regions and a head region located on one side of the plurality of active regions.
[0041] Step S102: Form a flash memory device component on the substrate of the active region and the head region. The flash memory device component includes a floating gate layer, a shallow trench isolation structure, an interlayer dielectric layer, a control gate layer, and a first sidewall.
[0042] Step S103: Form a blocking layer on the outer surface of the first sidewall in the head region and on a part of the top surface of the control gate layer.
[0043] Step S104: Etch and remove part of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active region and the head region, and form a plurality of spaced-apart memory cells in the active region.
[0044] In the manufacturing method of the semiconductor device provided by the present invention, after the control gate layer is integrally formed on the substrate, etching is not directly performed in a direction perpendicular to the surface of the substrate to form a plurality of spaced-apart memory cells. Instead, the pattern of the photoresist layer or the photoresist layer in the etching process is adjusted so that the photoresist layer can simultaneously shield the first sidewall in the head region and a part of the control gate layer related thereto. Thus, after etching the control gate layer to form a plurality of discrete memory cells subsequently, the part of the control gate layer directly in contact with the first sidewall in the head region is retained. That is, by widening the width at the position of the first sidewall in the head region, the problem of peeling due to a large aspect ratio of the first sidewall at the boundary in the head region is avoided, the manufacturing process is simplified, the manufacturing cost is reduced, and the reliability and performance of the NORD flash memory device are improved.
[0045] In order to enable those of ordinary skill in the technical field to which the present invention pertains to easily understand the manufacturing method of the semiconductor device in the embodiments of the present invention, hereinafter, the manufacturing method of the semiconductor device proposed by the present invention will be further described in combination with the respective structural schematic diagrams in the manufacturing process. Please refer to Figures 2 to 10As shown, the figure depicts a schematic structural diagram of the manufacturing method of a semiconductor device provided in an embodiment of the present invention during the manufacturing process.
[0046] Please refer to Figures 2 to 10 , Figure 2 The figure depicts a partial top view of a semiconductor device in an embodiment of the present invention. Figure 3 What is depicted is Figure 2 Schematic structural diagrams of the partial structure of the semiconductor device shown along the AA tangent and the BB tangent, respectively. Figure 4 What is depicted is Figure 2 A schematic structural diagram of the logic region of the semiconductor device shown. Figures 5 to 10 What is depicted are, respectively, Figure 3 or Figure 4 Partial corresponding subsequent structures formed based on the semiconductor device shown. It should be understood that the semiconductor device of the present invention can be used to manufacture flash memory devices, such as NORD flash memory devices. The NORD flash memory devices may include a plurality of memory cells, and each memory cell may be a dual-bit structure sharing a word line. Without departing from the spirit of the present invention, the present invention can also be applied to other types of memories.
[0047] As Figure 3 and Figure 4 shown, perform the above step S101: Provide a substrate 100. The substrate 100 may include a storage region and a logic region 103. The storage region may include a plurality of active regions 101 and a head region 102 located on one side of the plurality of active regions 101. In one embodiment, the substrate 100 may be, for example, a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a III-V compound substrate (such as a silicon nitride substrate or a gallium arsenide substrate), a silicon carbide substrate, or a stacked structure thereof, or a diamond substrate, or other semiconductor material substrates well known to those skilled in the art. Exemplarily, the substrate 100 is a silicon substrate, but not limited thereto.
[0048] Continue as Figure 3 and Figure 4As shown, the above-mentioned step S102 is performed: using a deposition process such as at least one of chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process, a coupling oxide layer 110 and a floating gate layer 120 are sequentially formed from bottom to top on the substrate 100. In one embodiment, the material of the coupling oxide layer 110 may be an oxide, such as silicon dioxide, and the material of the floating gate layer 120 may be a conductive material, such as polysilicon, but not limited thereto. Then, at least one of etching processes such as dry etching process or wet etching process may be used to etch the floating gate layer 120, the coupling oxide layer 110, and a part of the substrate 100 downward in a direction perpendicular to the surface of the substrate 100 (hereinafter simply referred to as the vertical direction) to form a plurality of trenches (not shown) in the substrate 100; and then a deposition process such as chemical vapor deposition process is used to fill an insulating material such as silicon dioxide in the plurality of trenches to form a plurality of shallow trench isolation structures 130 in the substrate 100 that define or define a plurality of active regions 101, the active regions 101, and the end regions 102. In one embodiment, the plurality of active regions 101 may be arranged at intervals in a direction parallel to the surface of the substrate 100 (hereinafter simply referred to as the horizontal direction), and a first trench isolation structure 131 is provided between adjacent active regions 101. The floating gate layer 120 may also be a combination of a plurality of independent strip structures, and the floating gate layer 120 extends horizontally across the plurality of active regions 101. Exemplarily, the shape of the active region 101 may be a long strip, the shape of the first shallow trench isolation structure 131 may also be a long strip, and the top surface of the trench isolation 131 may be flush with the top surface of the floating gate layer 120, but not limited thereto. A second trench isolation structure 132 is formed in the end region 102, and the width of the second trench isolation structure 132 in a direction parallel to the surface of the substrate 100 (hereinafter simply referred to as the horizontal direction) is greater than the width of the first shallow trench isolation structure 131 in the horizontal direction, but not limited thereto.
[0049] Thereafter, a deposition process such as chemical vapor deposition is used to sequentially form an interlayer dielectric layer 140, a control gate layer 150, and an inner spacer 160 on the substrate 100. In one embodiment, the interlayer dielectric layer 140 may specifically include a three-layer film structure, such as an ONO structure of oxide-nitride-oxide stack, but not limited thereto. The inner spacer 160 is located on a partial top surface and sidewalls of the control gate layer 150, and extends to cover sidewalls of the interlayer dielectric layer 140. The inner spacer 160 may specifically be a composite structure, such as a composite structure of a first inner spacer 161 and a second inner spacer 162. In one embodiment, the first inner spacer 161 and the second inner spacer 162 may be made of different insulating materials. For example, the first inner spacer 161 is silicon dioxide, and the second inner spacer 162 is silicon nitride, but not limited thereto. Thereafter, a deposition process such as chemical vapor deposition is used to correspondingly form the gate oxide layer 170 and the word line layer 180.
[0050] It should be understood that during the process of forming the interlayer dielectric layer 130, the control gate layer 140, the inner spacer 160, the gate oxide layer 170, and the word line layer 180 on the active region 101, the multi-layer film structure also laterally extends in most regions of the end region 102, as Figure 3 shown, and on the logic region 103, the correspondingly formed film structure is a tunneling oxide layer 210 and a gate layer 220, which is to prepare for forming a gate structure on the logic region 103 later.
[0051] As Figure 5 shown, following the above step S102, a photoresist layer (not shown) that covers the active region 101 and the end region 102 and exposes the top surface of a part of the gate layer 220 in the logic region 103 may be first formed. Then, using this photoresist layer as a mask, a part of the gate layer 220 and the tunneling oxide layer 210 are etched away vertically downward to form a plurality of discrete gate structures 251 on the logic region 103, that is, the gate structure on the logic region of the NORD flash memory device needs to be formed first.
[0052] As Figure 6 and Figure 7As shown, following the above step S102: A first sidewall 181 can be further formed on both sidewalls of the inner sidewall 160 on the active region 101 and on both sidewalls of each discrete gate structure 251 on the logic region 103 by using a deposition process such as chemical vapor deposition. In one embodiment, the first sidewall 181 is also synchronously deposited on the control gate layer 150, the interlayer dielectric layer 140, and the sidewalls of a part of the second shallow trench isolation structure 132 in the end region 102. The material of the first sidewall 191 can be an insulating material, such as an oxide like silicon dioxide, or a silicon nitride like silicon nitride, but is not limited thereto.
[0053] As Figure 8 shown, perform the above step S103: A barrier layer 200 is formed on the active region 101 and the end region 102 of the substrate 100 by using a deposition process such as physical vapor deposition; wherein, an opening pattern is defined in the barrier layer 200, and the opening pattern exposes the surface of a part of the control gate layer 150 in the active region 101, a part of the control gate layer 150 in the end region 102, and the second shallow trench isolation structure 132. The barrier layer 200 can be at least one of a spin-on hard mask material, a spin-on carbon material, an anti-reflection coating, or a photoresist. In one embodiment, the barrier layer 200 is preferably a photoresist, and this photoresist (i.e., the barrier layer 200) can be used as a mask layer for subsequent etching to form the memory cell 151 on the active region 101, but is not limited thereto. It should be understood that during this step, the film layer structure on the logic region 103 does not change, so Figure 8 the specific structure on the logic region 103 is not shown in the figure.
[0054] As Figure 9As shown, perform the above step S104: Using the blocking layer 200 (preferably photoresist) as a mask, perform an etching process, such as at least one of a dry etching process or a wet etching process, on the film layer structures on the active region 101 and the end region 102 on the substrate 100 that are not shielded by the blocking layer 200, such as part of the control gate layer 150, the interlayer dielectric layer 140, the floating gate layer 120, and the coupling oxide layer 110, to form a plurality of spaced-apart memory cells 151 in the active region 101, and at the same time remove part of the control gate layer 150, the interlayer dielectric layer 140, the floating gate layer 120, the coupling oxide layer 110, and part of the height of the second shallow trench isolation structure 132 on the end region 102 in the vertical direction, and retain part of the control gate layer 150 in the end region 102 that is in direct contact with the first sidewall 191 and the interlayer dielectric layer 140 therebelow, that is, widen the width at the position of the first sidewall 191 in the end region 102 in the horizontal direction, avoiding the problem that the first sidewall 191 at this position has a large aspect ratio and is prone to peeling of the first sidewall 191 in the end region 102.
[0055] As Figure 10 shown, following the above step S104: Further use a deposition process such as chemical vapor deposition to conformally form a second sidewall 192 on the outside of the first sidewall 191 on the active region 101 and the end region 102. In one embodiment, the material of the second sidewall 192 may be an insulating material different from the material of the first sidewall 191, such as nitride or silicon dioxide, but not limited thereto.
[0056] It can be understood that after forming the second sidewall 192, other components such as bit lines (not shown), source electrodes (not shown), and drain electrodes (not shown) may be further formed in the manufacturing method provided in the embodiments of the present invention. This is prior art and will not be elaborated in the present invention.
[0057] It should be understood that since the main inventive point of the embodiments of the present invention lies in the active region and the end region, the film layer structures of only the active region and the end region are shown in the drawings corresponding to some steps, and the logic region is not shown. For the sake of distinction, the film layer structure of the logic region is added in the drawings corresponding to some steps. Those skilled in the art should easily obtain the film layer structures of the corresponding unshown parts.
[0058] In addition, based on the same inventive concept, the present invention further provides a flash memory device formed by using the manufacturing method of the semiconductor device as described above. The flash memory device has a dual storage bit structure sharing word lines, and specifically may include a substrate 100, where the substrate 100 may include an end region 102, and the end region 102 includes a first sidewall 191 and a second shallow trench isolation structure 132. A control gate layer 150 is formed on a part of the second shallow trench isolation structure 132 in direct contact with the first sidewall 191. The specific formation process may refer to the explanation of the manufacturing method as described above, and the present invention will not repeat it here.
[0059] It should be understood that "conformal" in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the similarity and correlation in the morphology between two or more shapes.
[0060] In summary, the present invention provides a manufacturing method of a semiconductor device, including: providing a substrate including a plurality of active regions and an end region on one side of the plurality of active regions, forming a flash memory device component on the substrate of the active regions and the end region, the flash memory device component including a floating gate layer, a shallow trench isolation structure, an interlayer dielectric layer, a control gate layer, and a first sidewall, forming a barrier layer on the outer surface of the first sidewall in the end region and a part of the top surface of the control gate layer, etching and removing a part of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active regions and the end region, and forming a plurality of spaced-apart memory cells in the active regions. In the present invention, the barrier layer is used to shield a part of the control gate layer and the first sidewall in the end region. After etching the control gate layer to form a plurality of discrete memory cells subsequently, a part of the control gate layer in direct contact with the first sidewall in the end region is retained, that is, the width at the position of the first sidewall in the end region is increased in the horizontal direction, avoiding the problem that the first sidewall in the end region is prone to peeling due to a large aspect ratio at this position. Further, by setting the barrier layer as a photoresist mask layer during the process of etching the control gate layer to form a plurality of discrete memory cells subsequently, the manufacturing process is simplified, the manufacturing cost is reduced, and the reliability and performance of the NORD flash memory device are improved.
[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, comprising a plurality of active regions and a terminal region located on one side of the plurality of active regions; Forming a flash memory device component located on the substrate in the active area and the terminal area, the flash memory device component comprising a floating gate layer, a shallow trench isolation structure, an interlayer dielectric layer, a control gate layer, and a first sidewall; forming a barrier layer on the outer surface of the first spacer in the terminal region and on a portion of the top surface of the control gate layer; Parts of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active area and the terminal area are removed by etching, and a plurality of storage cells spaced apart from each other are formed in the active area.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The barrier layer is selected from at least one of a spin-on hard mask material, a spin-on carbon material, an anti-reflective coating or a photoresist.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: In the process of etching away parts of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active area and the terminal area, the barrier layer made of the photoresist may be used as a mask.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate further includes a logic region having a gate structure, and the first spacer further extends to cover the sidewall of the gate structure.
5. The method for manufacturing a semiconductor device according to claim 4, wherein: Also includes: A second spacer is formed on the sidewalls of the first spacer in the active area and the logic area.
6. The method for manufacturing a semiconductor device according to claim 4, wherein: The step of forming a flash memory device located on the substrate in the active area and the terminal area comprises: Forming the floating gate layer on the substrate located in the active area and the terminal area; Forming a plurality of shallow trench isolation structures spaced apart from each other and located on the active area and the terminal area, wherein the shallow trench isolation structures include a first shallow trench isolation structure located in the active area and a second shallow trench isolation structure located in the terminal area; The interlayer dielectric layer and the control gate layer are sequentially stacked and located on the floating gate layer and the shallow trench isolation structure; Forming an opening in the middle region of the control gate layer, the interlayer dielectric layer, and the floating gate layer in the active region to expose a portion of the substrate or a portion of the shallow trench isolation structure; A gate oxide layer and a word line layer are formed in the opening, wherein the gate oxide layer is located on an inner surface of the opening, and the word line layer fills up a remaining space of the opening.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: The top surface of the shallow trench isolation structure is flush with the top surface of the floating gate layer.
8. The method for manufacturing a semiconductor device according to claim 6, wherein: A width of the first shallow trench isolation structure in the horizontal direction is smaller than a width of the second shallow trench isolation structure in the horizontal direction.
9. The method for manufacturing a semiconductor device according to claim 6, wherein: After a plurality of the memory cells are formed in the active region by etching, the control gate layer remains on a portion of the second shallow trench isolation structure that is in direct contact with the first sidewall in the terminal region.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: The memory cell includes a dual storage bit structure sharing a word line.
11. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 10.
12. The semiconductor device according to claim 11, wherein include: A substrate comprises an end region, wherein the end region comprises a first sidewall spacer and a second shallow trench isolation structure; wherein a control gate layer is formed on a portion of the second shallow trench isolation structure that is in direct contact with the first sidewall spacer.