Novel semiconductor nonvolatile memory and preparation method and application thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and discloses a novel semiconductor nonvolatile memory and a preparation method and application thereof. The memory comprises a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer and a top electrode which are sequentially arranged from bottom to top, the preparation method comprises the steps of (1) cleaning the substrate, (2) depositing the bottom electrode, (3) forming the amorphous oxide interface layer, (4) depositing the ferroelectric medium layer, and forming the ultrathin ferroelectric medium layer with uniform composition and good ferroelectricity on the amorphous MoO3 interface layer, (5) patterning and depositing the top electrode, and (6) performing rapid thermal annealing treatment. The memory is applied to a three-dimensional stacked nonvolatile memory array or construction of a back gate type ferroelectric transistor structure. According to the invention, the formation of a non-ferroelectric phase is effectively inhibited, the preferred orientation arrangement of the ferroelectric phase is promoted, the polarization intensity is enhanced, and the ferroelectric performance of the device is improved. The material has the advantages of low thermal budget, high process compatibility and excellent ferroelectric performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a novel semiconductor non-volatile memory and its preparation method and application, which are applicable to application scenarios such as non-volatile memories, high-density three-dimensional integrated systems, and brain-like computing chips. Background Art

[0002] With the advent of the big data and artificial intelligence era, the electronic information industry has put forward more stringent technical requirements for non-volatile storage devices in terms of high density, low power consumption, and high reliability. As an important candidate for the new generation of non-volatile storage technology, hafnium oxide (HfO 2 )-based ferroelectric devices have received extensive attention and in-depth research in recent years due to their excellent thickness scaling potential, stable nano-scale ferroelectricity, and good compatibility with complementary metal oxide semiconductor (CMOS) processes.

[0003] However, at the present stage, hafnium oxide (HfO 2 )-based ferroelectric memories generally have the technical bottleneck of relatively high operating voltages (usually about 3V), large power consumption, which limits their further application in low-power integrated systems. Promoting the thickness scaling of ferroelectric films is considered a feasible path that combines economy and efficiency. On the one hand, film thickness scaling can effectively increase the electric field strength of the device and reduce the operating voltage; on the other hand, it can reduce power consumption and optimize the thermal management performance of the device in high-density packaging scenarios, improving integration stability. In addition, reducing the thickness of ferroelectric films can also shorten the atomic layer deposition (ALD) process time, improve production line efficiency, enhance thickness uniformity and device process consistency. At the same time, the current heat treatment temperature of hafnium oxide (HfO 2 -based ferroelectric films is generally relatively high (usually ≥400°C), which severely limits their compatibility with advanced three-dimensional integration and back-end interconnect (BEOL) processes. Therefore, there is an urgent need to develop a new ferroelectric performance regulation strategy with simple process, low thermal budget, and back-end process compatibility.

[0004] Existing research shows that the ferroelectricity of hafnium oxide (HfO 2 )-based films mainly originates from the stable formation of the orthorhombic phase and its preferred orientation. Although there have been methods to try to increase the proportion of the ferroelectric phase through electrode engineering or introducing an intermediate layer (such as β-W, WS 2 etc.), these techniques are mostly applicable to relatively thick film layers, and there are problems such as complex processes and high integration difficulties, which are difficult to meet the dual requirements of performance and process for ultra-thin devices. Summary of the Invention

[0005] Aiming at the deficiencies of the existing technology, the present invention aims to solve the current hafnium oxide (HfO 2The compatibility issues of reducing the thermal budget and thickness scaling of hafnium-based ferroelectric thin films, especially the technical bottlenecks in aspects such as insufficient polarization intensity, increasing proportion of non-ferroelectric phases, and reliability degradation. Therefore, a new type of semiconductor non-volatile memory with a low thermal budget and back-end process compatibility is proposed. This memory is based on an amorphous interface layer to improve the ferroelectric performance of the device and enhance its stability and reliability. At the same time, a preparation method for this memory is provided. On the basis of ensuring the simplicity of the process and the compatibility with BEOL integration, it realizes the effective regulation of the stability of the ferroelectric phase and the out-of-plane ferroelectric domain orientation.

[0006] The new type of semiconductor non-volatile memory of the present invention includes a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer, and a top electrode, which are sequentially arranged from bottom to top.

[0007] The material of the substrate is Si and SiO 2 ; the material of the bottom electrode is Mo, and the amorphous oxide interface layer is amorphous MoO 3 interface layer (amorphous molybdenum oxide (a-MoO 3 )); the ferroelectric dielectric layer is a hafnium-based ferroelectric material (such as Si:HfO 2 , La:HfO 2 , Zr:HfO 2 , etc.); the material of the top electrode includes but is not limited to Mo, TiN, W, and Pt.

[0008] The thickness of the bottom electrode is 20 - 100 nm, the thickness of the ferroelectric dielectric layer is 5 - 10 nm, the thickness of the top electrode is 20 - 100 nm, and the thickness of the amorphous oxide interface layer is 1 - 2 nm.

[0009] The ferroelectric dielectric layer is a HZO ferroelectric dielectric layer, and HfO 2 and ZrO 2 are sequentially deposited from bottom to top by an interlayer stacking (alternate deposition) method to regulate the crystal phase evolution process; the single-layer thickness of HfO 2 and ZrO 2 is 0.5 - 1 nm, and the molar ratio of HfO 2 to ZrO 2 is 1:1.

[0010] In the present invention, by precisely regulating the oxidation reaction on the surface of the Mo bottom electrode in the atomic layer deposition (ALD) process, an amorphous MoO 3 interface layer is introduced between the Mo bottom electrode and the HZO ferroelectric dielectric layer. This amorphous interface layer effectively inhibits the formation of paraelectric and antiferroelectric phases by regulating the interface energy and crystal phase growth mechanism, significantly promotes the preferential orientation and spontaneous stability of the ferroelectric orthorhombic phase in the out-of-plane direction, thereby enhancing the remanent polarization intensity and improving the overall ferroelectric performance of the thin film.

[0011] The preparation method of the above-mentioned novel semiconductor non-volatile memory includes the following steps:

[0012] (1) Substrate cleaning;

[0013] Ultrasonic cleaning is carried out using acetone, absolute ethanol and deionized water to remove organic substances and particle contamination, and then drying is carried out in a nitrogen environment.

[0014] (2) Bottom electrode deposition;

[0015] On the cleaned substrate, metal Mo is deposited as the bottom electrode by physical vapor deposition (PVD) method, and the thickness is controlled within 20 - 100 nm to ensure good conductivity and stable crystal structure.

[0016] The deposition by the physical vapor deposition (PVD) method is carried out by using a magnetron sputtering process. The sputtering power is set to 55 W, the working atmosphere is Ar, the flow rate is 3 sccm, and the deposition rate is 1 Å / s.

[0017] (3) Formation of an amorphous oxide interface layer;

[0018] After the deposition of the Mo bottom electrode is completed, an atomic layer deposition (ALD) process is adopted, and an oxidizing gas (the oxidant includes but is not limited to H 2 O, O 3 and H 2 O 2 ) is introduced for interface oxidation treatment; by controlling the oxidation time, temperature and oxidant flow rate (such as treating for 60 seconds at 300 °C), an amorphous MoO 3 interface layer with a thickness of 1 - 2 nm is induced to form on the Mo surface.

[0019] (4) Ferroelectric dielectric layer deposition;

[0020] On the amorphous MoO 3 interface layer, HfO 2 layers and ZrO 2 layers are alternately deposited by an atomic layer deposition (ALD) process in a 1:1 molar ratio. The oxygen source is a water source or an ozone source. The thickness of each layer is controlled within 0.5 - 1 nm, and the total thickness is controlled within 5 - 10 nm (to meet the requirements of low power consumption and high-density integration), forming an ultrathin HZO ferroelectric dielectric layer with uniform composition and good ferroelectricity.

[0021] (5) Top electrode patterning and deposition;

[0022] Spin-coat photoresist on the HZO ferroelectric dielectric layer, complete pattern exposure and development using standard lithography processes. Then, deposit the Mo top electrode by physical vapor deposition (PVD) method, with the thickness controlled within 20 - 100 nm. Finally, complete electrode patterning through the Lift-off process.

[0023] (6) Rapid thermal annealing (RTA) treatment;

[0024] Perform rapid thermal annealing treatment on the above structure in an inert nitrogen atmosphere to promote the crystallization of the HZO thin film to form a stable ferroelectric orthorhombic phase and stimulate its ferroelectricity. The rapid thermal annealing treatment is carried out at 300 - 400 °C for 250 - 350 seconds in a nitrogen atmosphere.

[0025] The above method regulates the oxidation state on the surface of the molybdenum (Mo) bottom electrode through atomic layer deposition process, and can form a stable amorphous MoO 3 (a - MoO 3 ) interfacial layer. This amorphous interfacial layer can effectively inhibit the growth of non - ferroelectric paraelectric phase, promote the spontaneous and stable arrangement of the ferroelectric phase in the out - of - plane direction, and significantly improve the ferroelectric properties of the thin film. Experiments prove that compared with the devices without introducing the a - MoO 3 interfacial layer or using a crystalline MoO 3 (c - MoO 3 ) interfacial layer, the back - end - compatible ultra - thin HfO 2 - based ferroelectric devices prepared by the present invention exhibit higher polarization intensity and more excellent reliability, and are suitable for the practical applications of next - generation low - power high - density integrated memories.

[0026] The novel semiconductor non - volatile memory of the present invention is applied to a three - dimensional stacked non - volatile memory array. The architecture adopts a 2TnC cell array, that is, each column is vertically integrated by two transistors and n (2 - 100) novel semiconductor non - volatile memories proposed by the present invention to achieve high - density vertical stacked storage.

[0027] The novel semiconductor non - volatile memory of the present invention can also be applied to construct a back - gate ferroelectric transistor structure. This structure uses Mo as the back - gate metal, and optimizes the performance of the ferroelectric layer through the amorphous (a - MoO 3 ) interfacial engineering process proposed by the present invention, thereby effectively improving the switching characteristics, threshold voltage regulation ability and data retention characteristics of the device.

[0028] By introducing an amorphous interface layer between the bottom electrode and the ferroelectric dielectric layer, the present invention effectively suppresses the formation of non-ferroelectric phases, promotes the preferred orientation arrangement of ferroelectric phases, enhances the polarization intensity, and improves the ferroelectric performance of the device, without introducing additional doping elements, sacrificing the thickness of the functional layer, and maintaining a simple process. It has a low thermal budget, high process compatibility, and excellent ferroelectric performance, and can be widely applied to the preparation of key devices in next-generation HfO 2 -based ferroelectric capacitors, ferroelectric transistors, 3D flash memory architectures, 3D DRAM architectures, neuromorphic computing units, and other non-volatile memories and brain-inspired chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic structural diagram of the novel semiconductor non-volatile memory of the present invention.

[0030] Figure 2 is a flowchart for the preparation of the novel semiconductor non-volatile memory of the present invention.

[0031] Figure 3 is the HZO ferroelectric capacitor without the MoO 3 interface layer in Comparative Example 1 (without the MoO 3 group) of the structural schematic diagram.

[0032] Figure 4 is the HZO ferroelectric capacitor with a crystalline MoO 3 interface layer in Comparative Example 2 (c-MoO 3 group) of the structural schematic diagram.

[0033] Figure 5 is the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO 3 group) and the remanent polarization intensity and operating voltage diagrams of the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (without the MoO 3 group and c-MoO 3 group).

[0034] Figure 6 is the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO 3 group) and the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (without the MoO 3 group and c-MoO 3 group) (without the MoO 3 group and c-MoO 3 group) of the polarization hysteresis loop diagrams.

[0035] Figure 7 is the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO 3 group) and the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (without the MoO 3 group and c-MoO3 Retention characteristic diagram of (group).

[0036] Figure 8 It is the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO 3 (group) and the electric field cycling life diagrams of the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (without MoO 3 (group) and c-MoO 3 (group).

[0037] Figure 9 It is the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO 3 (group) and the constant voltage operating life diagrams of the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (without MoO 3 (group) and c-MoO 3 (group).

[0038] Figure 10 It is a schematic structural diagram of a three-dimensional stacked non-volatile memory array.

[0039] Figure 11 It is a schematic circuit diagram of a three-dimensional stacked non-volatile memory array.

[0040] Figure 12 It is a schematic structural diagram of a back-gate ferroelectric transistor.

[0041] In the figure: 1. Substrate, 2. Bottom electrode, 3. Amorphous oxide interface layer, 4. Ferroelectric dielectric layer, 5. Top electrode, 6. Substrate. Detailed implementation manners

[0042] For the novel semiconductor non-volatile memory provided by the present invention, by precisely controlling the oxidation reaction on the surface of the Mo bottom electrode in the atomic layer deposition (ALD) process, an amorphous MoO 3 interface layer is introduced between the Mo bottom electrode and the HZO ferroelectric dielectric layer. This amorphous interface layer effectively inhibits the formation of the paraelectric phase and the antiferroelectric phase by regulating the interface energy and the crystal phase growth mechanism, significantly promotes the out-of-plane preferred orientation and spontaneous stability of the ferroelectric orthorhombic phase, thereby enhancing the remanent polarization intensity and improving the overall ferroelectric performance of the thin film.

[0043] The novel semiconductor non-volatile memory of the present invention has a structure as Figure 1 shown, and sequentially includes a substrate: 1, a bottom electrode 2, an amorphous oxide interface layer 3, a ferroelectric dielectric 4, and a top electrode 5 from bottom to top. The material of the substrate 1 is Si or SiO 2 , and the thickness is 300 nm. The materials of the bottom electrode 2 and the top electrode 5 are Mo, and the thickness is 20 - 100 nm. The material of the amorphous oxide interface layer 3 is MoO 3, with a thickness of 1 - 2 nm. The material of the ferroelectric dielectric layer 4 is HZO, with a thickness of 5 - 10 nm, and HfO is deposited successively from bottom to top in a layer - by - layer stacking manner 2 and ZrO 2 , HfO 2 and ZrO 2 has a single - layer thickness of 0.5 - 1 nm, and the molar ratio of HfO 2 to ZrO 2 is 1:1.

[0044] Figure 2 The specific preparation process of the novel semiconductor non - volatile memory of the present invention is given.

[0045] The following describes the novel semiconductor non - volatile memory of the present invention and its preparation process in detail with reference to embodiments, and the performance of the ultra - thin ferroelectric capacitor of the present invention is described with reference to comparative examples.

[0046] Example 1

[0047] This example prepares a novel semiconductor non - volatile memory based on an amorphous MoO 3 interface layer, and its structure is shown in Figure 1 , the material of the substrate 1 is SiO 2 , with a thickness of 300 nm. The thicknesses of both the bottom electrode 2 and the top electrode 5 are 100 nm. The thickness of the amorphous oxide interface layer 3 is 2 nm. The thickness of the ferroelectric dielectric layer 4 is 5 nm.

[0048] Refer to Figure 2 , the specific process of this example includes the following steps.

[0049] Step S1: Clean the substrate 1;

[0050] Select a SiO 2 silicon substrate with a thickness of 300 nm, ultrasonically clean it with acetone and absolute ethanol for 5 minutes in sequence, rinse it with deionized water, and dry it with nitrogen for standby.

[0051] Step S2: Deposit the Mo bottom electrode 2;

[0052] Use a sputtering process to prepare the Mo bottom electrode 2. The sputtering process includes but is not limited to magnetron sputtering, ion beam sputtering, reactive sputtering, etc. In this example, a magnetron sputtering process is used to deposit the Mo electrode with a deposition thickness of 100 nm. The target material is high - purity Mo (99.99%), the set sputtering power is 55 W, the working atmosphere is Ar (flow rate 3 sccm), and the deposition rate is about 1 Å / s.

[0053] Step S3: Form the amorphous oxide interface layer 3;

[0054] In-situ oxidation of the Mo bottom electrode by atomic layer deposition process, and the oxidant includes but is not limited to H 2 O, O 3 , H 2 O 2 etc. In this embodiment, O 3 is used as the oxygen source and treated at 300 °C for 60 s to form an amorphous MoO 3 layer with a thickness of about 2 nm on the Mo surface.

[0055] Step S4: Deposit the ferroelectric dielectric layer 4;

[0056] Continue to deposit a 5-nm-thick HZO ferroelectric thin film (ferroelectric dielectric layer 4) by atomic layer deposition process. First deposit a 0.5-nm-thick HfO 2 layer, and then deposit a 0.5-nm-thick ZrO 2 layer, and stack them in turn until the target thickness of 5 nm is reached. The precursors are Hf[N(C 2 H 5 )CH 3 4 , Zr[N(C 2 H 5 )CH 3 4 , and the oxygen source is H 2 O, and the deposition temperature is set at 300 °C.

[0057] Step S5: Pattern the top electrode region;

[0058] Spin-coat photoresist (positive photoresist) on the surface of the HZO thin film, pre-bake at 100 °C, and then expose and develop after 60 s. The development time is 30 s, and the developer is a conventional alkaline developer. Then rinse with deionized water and dry with nitrogen.

[0059] Step S6: Deposit the Mo top electrode 5;

[0060] Deposit a 100-nm Mo top electrode by magnetron sputtering process, and the sputtering parameters are the same as those for depositing the Mo bottom electrode 2 in step S2.

[0061] Step S7: Photoresist stripping;

[0062] Place the sample in acetone and ultrasonicate for 30 s to perform Lift-off to remove the photoresist, and then clean and dry with ethanol and deionized water.

[0063] Step S8: Rapid thermal annealing treatment (RTA);

[0064] ​​The sample was rapidly thermally annealed for 300 seconds (adjustable between 250 - 350 seconds) at 350 °C (adjustable between 300 - 400 °C) in a nitrogen atmosphere to promote the crystallization of HZO, stabilize the ferroelectric phase, and stimulate ferroelectricity.

[0065] Example 2

[0066] This example prepared a novel semiconductor non - volatile memory based on an amorphous MoO 3 interface layer. In its structure, the material of substrate 1 is Si with a thickness of 300 nm. The thicknesses of both the bottom electrode 2 and the top electrode 5 are 20 nm. The thickness of the amorphous oxide interface layer 3 is 1 nm. The thickness of the ferroelectric dielectric layer 4 is 7 nm.

[0067] The steps of its preparation process are the same as those in the example, except that the corresponding thicknesses of each layer are adjusted according to the above - mentioned specific thicknesses. In step S4, the thicknesses of the deposited HfO 2 layer and ZrO 2 layer are also adjusted.

[0068] Example 3

[0069] This example prepared a novel semiconductor non - volatile memory based on an amorphous MoO 3 interface layer. In its structure, the material of substrate 1 is SiO 2 , with a thickness of 300 nm. The thicknesses of both the bottom electrode 2 and the top electrode 5 are 60 nm. The thickness of the amorphous oxide interface layer 3 is 1.5 nm. The thickness of the ferroelectric dielectric layer 4 is 10 nm.

[0070] The steps of its preparation process are the same as those in the example, except that the corresponding thicknesses of each layer are adjusted according to the above - mentioned specific thicknesses. In step S4, the thicknesses of the deposited HfO 2 layer and ZrO 2 layer are also adjusted.

[0071] Comparative Example 1

[0072] This Comparative Example 1 is an ultra - thin HZO ferroelectric capacitor without introducing the MoO 3 interface layer. Different from the novel semiconductor non - volatile memory in Example 1, it does not contain the MoO 3 interface layer. As Figure 3 shown, its structure from bottom to top sequentially includes a substrate 1, a bottom electrode 2, a ferroelectric dielectric 4, and a top electrode 5.

[0073] The preparation process of this comparative example 1 is different from that of Example 1 in that step S3 (oxidation of the bottom electrode) is omitted, that is, the surface oxidation treatment of the bottom electrode is not performed before the HZO dielectric layer is deposited, and the HZO layer is directly grown on the surface of the Mo electrode. The remaining steps such as substrate cleaning, Mo electrode deposition, HZO layer deposition, patterning, top electrode deposition, photoresist stripping and thermal annealing remain the same.

[0074] Comparative Example 2

[0075] In this comparative example 2, based on crystalline MoO 3 Ultrathin HZO ferroelectric capacitor with interfacial layer composed of crystalline MoO 3 The interface layer replaces the amorphous MoO2 of the novel semiconductor non-volatile memory in Example 1. 3 Interface layer. Figure 4 As shown, the capacitor structure of Comparative Example 2 includes a substrate 1, a bottom electrode 2, a crystalline oxide interface layer 6, a ferroelectric dielectric 4 and a top electrode 5 from bottom to top.

[0076] The main difference between the preparation process of this comparative example 2 and that of Example 1 is that step S3 (oxidation of the bottom electrode) adopts a long-term oxidation method to form a crystalline phase MoO 3 Specifically, the atomic layer deposition process is used to form an interface layer of O 3 As an oxygen source, the Mo bottom electrode was in situ oxidized for 20 minutes to form MoO with a clear crystal structure on its surface. 3 layer, followed by the deposition of the HZO layer.

[0077] The specific performance evaluation comparison of the embodiment and the comparative example is given below.

[0078] A probe station (Cascade Summit 12000) and a semiconductor device parameter analyzer (Keysight B1500A) were used to perform high-precision electrical tests and systematically evaluate the electrical performance.

[0079] 1. Polarization intensity characteristic test;

[0080] Evaluation of amorphous MoO 3 Interface layer (a-MoO 3 group) on the residual polarization intensity (Pr) of the device.

[0081] The amorphous MoO 3 A new semiconductor non-volatile memory (a-MoO 3 Group), Comparative Example 1 without MoO 3 Interfacial layer ferroelectric capacitor (without MoO 3 Group) and Comparative Example 2 contain crystalline MoO 3 Interfacial layer ferroelectric capacitor (c-MoO3 The scanning voltage test was carried out on the [group]. During the test, the top electrode was pressurized and the bottom electrode was grounded. The PUND method was used to extract the polarization current by scanning with a 2 kHz triangular pulse, and the polarization amount was calculated by integration. The scanning voltage ranged from ±0.5 V to ±3 V with a step of 0.25 V. The results are as Figure 5 shown. In this voltage range, the a-MoO in Example 1 3 group exhibited the highest remanent polarization intensity.

[0082] As Figure 6 shown, under the application of a ±1.5 V electric field, the ferroelectric hysteresis loop of the novel semiconductor non-volatile memory with the amorphous MoO 3 interface layer (a-MoO 3 group) showed a 2Pr of 44.5 μC / cm 2 , significantly higher than that of Comparative Example 1 (28.7 μC / cm 2 ) and Comparative Example 2 (11.5 μC / cm 2 ).

[0083] 2. Retention characteristic test;

[0084] Evaluate the influence of the amorphous MoO 3 interface layer (a-MoO 3 group) on the polarization retention characteristics of the device.

[0085] The novel semiconductor non-volatile memory containing the amorphous MoO 3 interface layer in Example 1 (a-MoO 3 group), the ferroelectric capacitor without the MoO 3 interface layer in Comparative Example 1 (without MoO 3 group), and the ferroelectric capacitor containing the crystalline MoO 3 interface layer in Comparative Example 2 (c-MoO 3 group) were tested. A ±1.5 V, 2 kHz triangular wave PUND read pulse was used to extract the polarization current and integrate to obtain the polarization intensity. As Figure 7 shown by the results, when extended to a retention time of 10 years, the positive and negative polarization states of the a-MoO 3 group in Example 1 retained 98% and 94% of the polarization values respectively, significantly better than the comparative example samples.

[0086] 3. Electric field cycling life test;

[0087] During the test, a ±1.5 V, 1 MHz square wave was used as the cycling pulse, and the PUND scheme (±1.5 V, 2 kHz triangular wave) was used as the read pulse. As Figure 8 shown by the results, after applying 10 12 cycles, the a-MoO in Example 13 The group still retains approximately 90% of the window width, significantly superior to Comparative Example 1 (58%) and Comparative Example 2 (10%).

[0088] 4. Constant voltage working life test;

[0089] The test evaluates the time-dependent dielectric breakdown characteristics of the device at different voltages by applying a constant voltage to the top electrode. According to the Weibull distribution fitting, the characteristic breakdown time T when 63.2% of the devices fail is extracted 63 and its long-term life is extrapolated using the power-law model.

[0090] As Figure 9 the results shown, if a 10-year working life is targeted, the a-MoO in Example 1 3 group can withstand a working voltage of 2.44 V, superior to Comparative Example 1 (2.13 V) and Comparative Example 2 (2.25 V).

[0091] In summary, the novel semiconductor non-volatile memory based on the amorphous MoO 3 interface proposed by the present invention not only exhibits excellent ferroelectric properties but also has significantly improved long-term working stability and reliability, providing strong technical support for practical applications.

[0092] In addition, the present invention can also be extended to the following application scenarios.

[0093] 1. Three-dimensional stacked non-volatile memory array.

[0094] Figure 10 Shows Figure 1 the extended application structure of the novel semiconductor non-volatile memory of the present invention in a three-dimensional stacked non-volatile memory array as shown in. The architecture uses a 2TnC cell array, that is, each column is vertically integrated by two transistors and n (2 - 100) novel semiconductor non-volatile memories proposed by the present invention to achieve high-density vertical stacked storage.

[0095] Figure 11 is the circuit principle corresponding to the three-dimensional stacked non-volatile memory array, showing its control and read mechanisms.

[0096] 2. Back-gate ferroelectric transistor.

[0097] Figure 12 Gives Figure 1 the back-gate ferroelectric transistor structure constructed by the novel semiconductor non-volatile memory of the present invention as shown in. This structure uses Mo as the back-gate metal and passes through the amorphous (a-MoO 3Interface engineering technology optimizes the performance of the ferroelectric layer, thus effectively improving the switching characteristics, threshold voltage regulation ability and data retention characteristics of the device, providing a new solution for high-performance and low-power non-volatile devices.

Claims

1. A new type of semiconductor non-volatile memory, characterized in that: The invention comprises a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer and a top electrode which are arranged in sequence from bottom to top.

2. The novel semiconductor nonvolatile memory according to claim 1, characterized in that: The material of the substrate is Si and SiO2; the material of the bottom electrode is Mo, the amorphous oxide interface layer is an amorphous MoO3 interface layer, and the ferroelectric dielectric layer is a hafnium-based ferroelectric material; the material of the top electrode includes but is not limited to Mo, TiN, W and Pt.

3. The novel semiconductor nonvolatile memory according to claim 1 is characterized in that: The bottom electrode has a thickness of 20-100 nm, the ferroelectric dielectric layer has a thickness of 5-10 nm, the top electrode has a thickness of 20-100 nm, and the amorphous oxide interface layer has a thickness of 1-2 nm.

4. The novel semiconductor nonvolatile memory according to claim 1 is characterized in that: The ferroelectric dielectric layer is a HZO ferroelectric dielectric layer, and HfO2 and ZrO2 are deposited in an interlayer stacking manner.

5. The novel semiconductor nonvolatile memory according to claim 4 is characterized in that: The single layer thickness of HfO2 and ZrO2 is 0.5-1 nm, and the molar ratio of HfO2 to ZrO2 is 1:

1.

6. A method for preparing the novel semiconductor non-volatile memory according to any one of claims 1 to 5, characterized in that: The steps include: (1) Substrate cleaning; (2) Bottom electrode deposition; The metal Mo is deposited on the substrate by physical vapor deposition as the bottom electrode, and the thickness is controlled at 20-100nm; (3) Formation of an amorphous oxide interface layer; After the Mo bottom electrode is deposited, an atomic layer deposition process is used to introduce an oxidizing gas for interface oxidation treatment; by controlling the oxidation time, temperature and oxidant flow rate, an amorphous MoO3 interface layer with a thickness of 1-2nm is induced on the Mo surface; (4) Deposition of ferroelectric dielectric layer; On the amorphous MoO3 interface layer, HfO2 layers and ZrO2 layers are alternately deposited in a 1:1 molar ratio by atomic layer deposition process, with the thickness of each layer controlled at 0.5-1nm and the total thickness controlled at 5-10nm; (5) Top electrode patterning and deposition; Spin-coat photoresist on the ferroelectric dielectric layer, use photolithography to complete pattern exposure and development, then use physical vapor deposition to deposit the top electrode with a thickness controlled at 20 to 100 nm, and finally use lift-off process to complete electrode patterning; (6) Rapid thermal annealing treatment.

7. The method for preparing the novel semiconductor non-volatile memory according to claim 6, characterized in that: The physical vapor deposition method in step (2) is deposition using a magnetron sputtering process, with the sputtering power set to 55 W, the working atmosphere to Ar, the flow rate to 3 sccm, and the deposition rate to 1 Å / s.

8. The method for preparing the novel semiconductor non-volatile memory according to claim 6, characterized in that: The rapid thermal annealing treatment in step (6) is a rapid thermal annealing treatment at 300-400° C. for 250-350 seconds in a nitrogen atmosphere.

9. An application of the novel semiconductor non-volatile memory according to any one of claims 1 to 5, characterized in that: For three-dimensional stacked non-volatile memory arrays, each column is composed of two transistors and n new semiconductor non-volatile memories vertically integrated to achieve high-density vertical stacking storage.

10. An application of the novel semiconductor non-volatile memory according to any one of claims 1 to 5, characterized in that: Used to construct back-gate ferroelectric transistor structures.

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