Gallium oxide junction barrier Schottky diode and preparation method thereof

Abstract

The invention relates to a gallium oxide junction barrier Schottky diode and a preparation method thereof, and belongs to the technical field of semiconductor devices. The preparation method comprises the following steps: providing an epitaxial wafer comprising an n + Ga2O3 layer and an n-Ga2O3 layer which are laminated, and forming a p-GaN layer on the surface of the n-Ga2O3 layer; forming a cathode metal layer on the surface of the n + Ga2O3 layer; forming a plurality of grooves in the p-GaN layer in a penetrating manner so as to expose a part of the n-Ga2O3 layer, and forming a junction termination extension structure at the periphery of the grooves; and anode metal layers are formed in the grooves, on the p-GaN layer between the adjacent grooves and on the surface of at least part of the junction termination extension structure. According to the preparation method, a groove filling process can be avoided, the processing difficulty is reduced, the uniformity and consistency of the p-GaN layer are ensured, the performance of the device is more stable and controllable, and the prepared junction barrier Schottky diode can effectively reduce reverse leakage current and improve breakdown voltage.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a gallium oxide junction barrier Schottky diode and a preparation method thereof. Background Art

[0002] Schottky diodes have good reverse recovery characteristics and are the mainstream devices for power switch applications. However, because the electric field easily gathers near the edge of the anode metal layer of the Schottky diode, the device breaks down prematurely at the edge of the anode metal layer, causing the breakdown voltage of the device to fail to reach the expected value, which also limits the application scenarios of the device. In addition, due to the mirror barrier lowering effect and the tunneling effect, the reverse leakage current of the device increases, resulting in increased power consumption when the device is turned off. Studies have shown that junction terminal extension technology combined with the junction barrier Schottky diode structure can effectively improve the above problems.

[0003] At present, the common preparation methods of junction barrier Schottky diode structures include etching the gallium oxide drift layer (n - Ga 2 O 3 ) to form a trench, and then fill the trench with p-type nickel oxide (p-NiO). However, the process of filling the trench is complex and difficult, and the leakage current of the device is still high, and the breakdown voltage needs to be further improved. Summary of the invention

[0004] To solve the above problems, the purpose of the embodiments of the present application includes providing a gallium oxide junction barrier Schottky diode and a preparation method thereof, which can effectively reduce the reverse leakage current of the device and increase the breakdown voltage while simplifying the preparation process.

[0005] In a first aspect, the present invention provides a method for preparing a gallium oxide junction barrier Schottky diode, comprising the following steps: providing an epitaxial wafer, the epitaxial wafer comprising stacked n + Ga 2 O 3 Layer and n - Ga 2 O 3 layer, and in n - Ga 2 O 3 Layer deviation n + Ga 2 O 3 The p-GaN layer is formed on the surface of the layer; + Ga 2 O 3 Layer deviation n - Ga 2 O 3 A cathode metal layer is formed on the surface of the p-GaN layer; a plurality of grooves are formed through the p-GaN layer to expose a portion of the n- Ga 2 O 3 layer, and a junction termination extension structure is formed around the trench; an anode metal layer is formed on the surface of the p-GaN layer in the trench, between adjacent trenches, and at least on the surface of part of the junction termination extension structure.

[0006] In the above technical solution, by first forming a p-GaN layer on the surface of the n - Ga 2 O 3 layer, and then synchronously forming trenches and a junction termination extension structure in the p-GaN layer, a series of problems such as voids, defects, filling uniformity, and consistency caused by first forming trenches and then filling in the prior art can be solved, filling the trenches is avoided, the processing difficulty is reduced, while ensuring the uniformity and consistency of the p-GaN layer, the device performance is more stable and controllable. The preparation method is simple and efficient, and the obtained junction barrier Schottky diode can significantly improve the problem of large reverse leakage current of the Schottky structure, and reduce the power consumption caused by the leakage current when the traditional Schottky diode is turned off. Moreover, the existence of the junction termination extension structure can significantly relieve the electric field concentration at the edge of the device, has a good improvement effect on the breakdown voltage of the device, and enables the switching device to have a better application prospect in high-voltage and high-power scenarios. In addition, since the etching process is not used to sacrifice part of the n - Ga 2 O 3 layer, the breakdown voltage of the device can be further improved by effectively improving the breakdown voltage resistance of the vertical device.

[0007] In some embodiments of the present application, the method for forming the p-GaN layer includes: depositing a p-GaN layer on the surface of the n - Ga 2 O 3 layer by metal organic chemical vapor deposition; optionally, the deposition temperature is 300°C to 600°C.

[0008] In some embodiments of the present application, the thickness of the p-GaN layer is 500 nm to 1000 nm, the p-GaN layer is doped with Mg, and the doping concentration of Mg is 10 18 cm -3 to 10 20 cm -3 .

[0009] In some embodiments of the present application, the plurality of trenches are distributed at equal intervals.

[0010] In some embodiments of the present application, the number of trenches is 4 to 6, the width of the trenches is 10 μm to 15 μm, and the distance between every two adjacent trenches is 6 μm to 10 μm.

[0011] In the above technical solution, when the size of the anode metal layer is determined, the number of grooves is mainly determined by the width of the grooves and the spacing between adjacent grooves. When the spacing between adjacent grooves is determined, the larger the width of the grooves, the fewer the number of grooves, the larger the Schottky contact area, the larger the current density of the device, the smaller the turn-on resistance, and the breakdown voltage gradually decreases while the reverse leakage current is larger. When the width of the grooves is determined, the larger the spacing between adjacent grooves, the larger the PN junction area, the current density of the device decreases accordingly, the turn-on resistance increases, the breakdown voltage gradually increases, and the reverse leakage current is smaller. In the present application, by controlling the number of grooves, the width of the grooves, and the spacing between adjacent grooves within a suitable range, the breakdown voltage can be further increased and the reverse leakage current can be reduced.

[0012] In some embodiments of the present application, the method for forming the grooves includes: coating, photolithography, etching, and stripping are sequentially performed on the surface of the p-GaN layer to form a plurality of grooves.

[0013] In some embodiments of the present application, the width of the junction termination extension structure is 5 μm to 20 μm.

[0014] In some embodiments of the present application, the method for forming the cathode metal layer includes: sequentially depositing metals Ti and Au on the surface of the n - Ga 2 O 3 layer by using an electron beam evaporation process; the method for forming the anode metal layer includes: sequentially depositing metals Ni and Au on the surface of the p-GaN layer by using an electron beam evaporation process.

[0015] In some embodiments of the present application, the material of the n + Ga 2 O 3 layer is β-Ga 2 O 3 doped with Sn, the doping concentration of Sn is 10 17 cm -3 to 10 19 cm -3 ; the thickness of the n + Ga 2 O 3 layer is 600 μm to 700 μm; the material of the n - Ga 2 O 3 layer is unintentionally doped β-Ga 2 O 3 , the electron concentration is 10 15 cm -3 to 10 17 cm -3 ; the n - Ga2 O 3 The thickness of the layer is 8 μm to 15 μm.

[0016] In a second aspect, an embodiment of the present application provides a gallium oxide junction barrier Schottky diode, including the following steps: a cathode metal layer, an n + Ga 2 O 3 layer, an n - Ga 2 O 3 layer, a p-GaN layer, and an anode metal layer that are stacked in sequence. The p-GaN layer has a plurality of through trenches and a junction termination extension structure surrounding the periphery of the trenches. The anode metal layer fills the trenches and covers the surface of the p-GaN layer between adjacent trenches and at least part of the junction termination extension structure.

[0017] In the above technical solution, by disposing the p-GaN layer on the surface of the n - Ga 2 O 3 layer and providing trenches and a junction termination extension structure in the p-GaN layer, the problem of relatively large reverse leakage current in the Schottky structure can be significantly improved, and the power consumption caused by the leakage current when the traditional Schottky diode is turned off can be reduced. Moreover, the junction termination extension structure can significantly relieve the electric field concentration at the edge of the device, has a good effect on improving the breakdown voltage of the device, and enables the switching device to have a better application prospect in high-voltage and high-power scenarios. In addition, compared with the prior art, the device structure of the present application has a complete n - Ga 2 O 3 layer. Compared with the n - Ga 2 O 3 layer structure with trenches in the prior art, the voltage withstand capacity of the vertical device can be effectively improved, and the breakdown voltage of the device can be further increased. The breakdown voltage of the gallium oxide junction barrier Schottky diode in the present application can be as high as 1630 V, and the reverse leakage current can be as low as 10 -10 A / cm 2 .

[0018] In some embodiments of the present application, the thickness of the p-GaN layer is 500 nm to 1000 nm; the p-GaN layer is doped with Mg, and the doping concentration of Mg is 10 18 cm -3 ~10 20 cm -3 .

[0019] In some embodiments of the present application, the number of trenches is 4 to 6, the width of the trenches is 10 μm to 15 μm, and the distance between every two adjacent trenches is 6 μm to 10 μm. Brief Description of the Drawings

[0020] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 It is a process flow chart of a preparation method of a gallium oxide junction barrier Schottky diode provided by an embodiment of the present application.

[0022] Figure 2 For the n - Ga 2 O 3 Cross-sectional schematic diagram after forming a p-GaN layer on the surface of the layer.

[0023] Figure 3 For Figure 2 As shown in the n + Ga 2 O 3 Cross-sectional schematic diagram after forming a cathode metal layer on the surface of the layer.

[0024] Figure 4 For Figure 3 Cross-sectional schematic diagram after forming a trench and a junction termination extension structure in the p-GaN layer shown.

[0025] Figure 5 For Figure 4 Cross-sectional schematic diagram after forming an anode metal layer on the surface of the p-GaN layer shown.

[0026] Figure 6 It is a comparison chart of the breakdown voltage / leakage current curves between the gallium oxide junction barrier Schottky diode (JBS) and the existing Schottky diode (SBD) in Embodiment 1 of the present application.

[0027] Main element symbol description:

[0028] 10 - Epitaxial wafer; 11 - n + Ga 2 O 3 Layer; 13 - n - Ga 2 O 3 Layer; 20 - p-GaN layer; 30 - Cathode metal layer; 40 - Trench; 50 - Junction termination extension structure; 60 - Anode metal layer. Detailed Embodiments

[0029] Hereinafter, the gallium oxide junction barrier Schottky diode and the method for preparing the same of the present application are specifically disclosed in detail with appropriate reference to the accompanying drawings. However, there may be cases where unnecessary detailed descriptions are omitted. For example, there are cases where detailed descriptions of well-known matters and repeated descriptions of actually the same structure are omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate the understanding of those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0030] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0031] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0032] If there is no special explanation, all steps of the present application can be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), which means that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, the method may further include step (c), which means that step (c) may be added to the method in any order. For example, the method may include steps (a), (b) and (c), or may include steps (a), (c) and (b), or may include steps (c), (a) and (b), etc.

[0033] At present, the common preparation method of the junction barrier Schottky diode structure includes etching the gallium oxide epitaxial layer to form a groove, and then filling the groove with p-NiO. Among them, when filling in the groove, a series of problems such as voids and defects, as well as the uniformity and consistency of filling are prone to occur, resulting in uncontrollable performance of the entire device, the filling process is difficult, and the leakage current of the device is still high, and the breakdown voltage needs to be further improved. However, when facing the technical problem of the junction barrier Schottky diode, existing research usually further improves the structure of the junction barrier Schottky diode. For example, in patent application CN112186032A, a dielectric layer and an anode field plate are further set on the surface of the anode metal layer, which makes the structure of the device more complicated, more difficult to manufacture, and more expensive.

[0034] Based on this, the embodiment of the present application provides a method for preparing a gallium oxide junction barrier Schottky diode by - Ga 2 O 3First, a p-GaN layer is formed on the layer surface, and then trenches and a junction termination extension structure are simultaneously formed in the p-GaN layer, which can solve a series of problems such as voids, defects, filling uniformity, and consistency caused by first etching trenches and then filling in the prior art, avoid filling trenches, reduce the processing difficulty, ensure the uniformity and consistency of the p-GaN layer, and at the same time make the device performance more stable and controllable. The prepared junction barrier Schottky diode can significantly improve the problem of large reverse leakage current in the Schottky structure and reduce the power consumption caused by the leakage current when the traditional Schottky diode is turned off. Moreover, the junction termination extension structure can significantly relieve the electric field concentration at the edge of the device, has a good effect on improving the breakdown voltage of the device, and enables the switching device to have better application prospects in high-voltage and high-power scenarios.

[0035] The following details the specific structure and preparation method of the gallium oxide junction barrier Schottky diode provided by the embodiments of the present application with reference to the accompanying drawings.

[0036] Figure 1 It is a process flow chart of a preparation method of a gallium oxide junction barrier Schottky diode provided by an embodiment of the present application. Figures 2 to 5 It is a schematic diagram of the preparation process of the gallium oxide junction barrier Schottky diode. Please refer to Figures 1 to 5 The preparation method of the gallium oxide junction barrier Schottky diode provided by the embodiments of the present application includes the following steps:

[0037] S10: Please refer to Figure 1 , provide an epitaxial wafer 10, the epitaxial wafer 10 includes a stacked n + Ga 2 O 3 layer 11 and an n - Ga 2 O 3 layer 13, and form a p-GaN layer 20 on the surface of the n - Ga 2 O 3 layer 13 facing away from the n + Ga 2 O 3 layer 11.

[0038] n + Ga 2 O 3 layer 11 is a highly doped substrate layer, and its material is β-Ga 2 O 3 doped with Sn, and the doping concentration of Sn is 10 17 cm -3 ~10 19 cm -3 . In some embodiments, n + Ga 2 O 3The thickness of layer 11 is 600 μm to 700 μm. As an example, n + Ga 2 O 3 The doping concentration of Sn in layer 11 is 6.4×10 18 cm -3 , and the thickness is 650 μm.

[0039] n - Ga 2 O 3 Layer 13 is a low-doped drift layer, and its material is unintentionally doped β-Ga 2 O 3 , and the electron concentration is 10 15 cm -3 to 10 17 cm -3 . In some embodiments, n - Ga 2 O 3 The thickness of layer 13 is 8 μm to 15 μm. As an example, n - Ga 2 O 3 The electron concentration of layer 13 is 2.5×10 16 cm -3 , and the thickness is 11 μm.

[0040] Among them, in nature, gallium oxide has five isomers, and the most stable one at room temperature is monoclinic gallium oxide, i.e., β-Ga 2 O 3 , which is a better choice for preparing new semiconductor devices. The critical breakdown field strength of β-Ga 2 O 3 can reach 8 MV / cm, which is about three times that of silicon carbide (SiC) and GaN materials. In addition, β-Ga 2 O 3 can be obtained by the melt growth technique, which is more conducive to obtaining low-cost, large-size bulk crystal materials, and is expected to achieve the performance of similar or even silicon carbide and gallium nitride devices only at the cost of silicon.

[0041] It can be understood that the epitaxial wafer 10 in this application is not limited to including the two-layer structures of n + Ga 2 O 3 layer 11 and n - Ga 2 O 3 layer 13. For example, in n + Ga 2 O 3 layer 11 and n - Ga 2 O 3A buffer layer and other epitaxial layer structures may also be included between layer 13.

[0042] The p-GaN layer 20 is a highly doped p-type gallium nitride layer, and the doping concentration of Mg in the p-GaN layer 20 is 10 18 cm -3 ~10 20 cm -3 . In some embodiments, the thickness of the p-GaN layer 20 is 500 nm to 1000 nm. By way of example, the doping concentration of Mg in the p-GaN layer 20 is 5×10 19 cm -3 , and the thickness is 900 nm.

[0043] In some embodiments, metalorganic chemical vapor deposition (MOCVD) is used to deposit p-GaN on the surface of the n - Ga 2 O 3 layer 13 to form the p-GaN layer 20. Further, it may include: using trimethylgallium (TMGa), high-purity ammonia gas (NH 3 ), and cyclopentadienylmagnesium (Cp 2 Mg) as the gallium source, nitrogen source, and p-type doping source respectively, and using high-purity hydrogen gas (H 2 ) as the carrier gas, and the deposition temperature may be 300 °C to 600 °C.

[0044] In this application, by selecting the p-GaN material, the p-GaN layer 20 can be simply deposited by the MOCVD method without using complex processes such as ion implantation or thermal oxidation. Moreover, the MOCVD method has a mature process and can be well compatible with the existing semiconductor manufacturing processes. The prepared p-GaN layer 20 has good uniformity, consistency, and high quality, thereby further reducing the processing difficulty and improving the device performance reliability. In addition, p-GaN has a high carrier mobility and can precisely control the doping concentration, and can better match with the n - Ga 2 O 3 to form a relatively ideal PN heterojunction, which is beneficial to further improving the device performance.

[0045] In some embodiments, before forming the p-GaN layer 20, cleaning and drying the epitaxial wafer 10 are also included. Specifically, it may include the steps of: soaking the epitaxial wafer 10 in acetone, isopropanol, and deionized water for 3 min to 5 min in sequence, drying it in a high-purity nitrogen atmosphere, and then immediately heating it on a hot plate to remove the residual moisture on the surface.

[0046] S20: Please refer to Figure 3 , on the n + Ga 2 O 3Layer 11 faces away from n - Ga 2 O 3 A cathode metal layer 30 is formed on the surface of layer 13.

[0047] In some embodiments, the material of the cathode metal layer 30 may include Ti, Al, Ni, Au, etc., and it can be a single-layer structure or a multi-layer structure. As an example, the cathode metal layer 30 can be Ti / Au or Ti / Al / Ni / Au.

[0048] When the cathode metal layer 30 is Ti / Au, the thickness of the Ti layer can be 10 nm to 50 nm, such as 20 nm; the thickness of the Au layer can be 50 nm to 200 nm, such as 80 nm.

[0049] In some embodiments, the method for forming the cathode metal layer 30 includes: using an electron beam evaporation process to deposit metals Ti and Au successively on the surface of n + Ga 2 O 3 Layer 11. Specifically, it may include the steps of: spin-coating a photoresist on the surface of n + Ga 2 O 3 Layer 11 facing away from n - Ga 2 O 3 The surface of layer 13, using an electron beam evaporation device to deposit metals Ti / Au (20 nm / 80 nm) successively on the surface of n + Ga 2 O 3 Layer 11, then placing it in a dimethyl sulfoxide (DMSO) solution at 80 °C to remove the photoresist on the surface, and then placing it in a heat treatment device (such as an RTP device) for a 60 s annealing treatment in a nitrogen atmosphere at 500 °C to form an ohmic contact and obtain the cathode metal layer 30.

[0050] S30: Please refer to Figure 4 , forming a plurality of trenches 40 through the p-GaN layer 20 to expose a part of n - Ga 2 O 3 Layer 13, and forming a junction termination extension structure 50 around the trenches 40.

[0051] In some embodiments, the plurality of trenches 40 are distributed at equal intervals. By setting the plurality of trenches 40 and distributing them at equal intervals, the contact area between the subsequent anode and n - Ga 2 O 3 Layer 13 can be increased, thereby further reducing the conduction loss, improving the distribution uniformity of the current and electric field in the device, reducing the reverse leakage current, and further increasing the breakdown voltage.

[0052] In some embodiments, the number of grooves 40 is 4 to 6, the width of the grooves 40 is 10 μm to 15 μm, and the spacing between every two adjacent grooves 40 is 6 μm to 10 μm. By way of example, the number of grooves 40 is 6, the width of the grooves 40 is 10 μm, and the spacing between every two adjacent grooves 40 is 6 μm.

[0053] It can be understood that the grooves 40 penetrate through the p-GaN layer 20, that is, the depth of the grooves 40 is equal to the thickness of the p-GaN layer 20.

[0054] In some embodiments, the width of the junction termination extension structure 50 is 5 μm to 20 μm. By way of example, the width of the junction termination extension structure 50 is 5 μm, 10 μm, 15 μm, 20 μm, etc. It can be understood that the junction termination extension structure 50 is the part of p-GaN formed in the peripheral area of the grooves 40, that is, the thickness of the junction termination extension structure 50 is equal to the thickness of the p-GaN layer 20. By controlling the width of the junction termination extension structure 50 within a suitable range, the uniformity of the electric field distribution can be further improved, the electric field intensity at the edge can be reduced, the breakdown voltage can be increased, and it is helpful to further reduce the edge electric field intensity, thereby reducing the reverse leakage current.

[0055] In some embodiments, step S30 includes: coating, photolithography, etching, and stripping on the surface of the p-GaN layer 20 in sequence to form a plurality of grooves 40 and a junction termination extension structure 50.

[0056] Further, step S30 may include:

[0057] S31: Dropwise coat a tackifier (such as HMDS) on the surface of the p-GaN layer 20, spin coat it at a rotation speed of 3000 rpm for 25 s in a spin coater, and then let it stand for 1 min to 2 min. After that, dropwise coat a photoresist (1 μm) and spin coat it at a rotation speed of 3000 rpm for 40 s. After the photoresist spin coating is completed, bake it on a hot plate at 100 °C for 3 min for pre-baking.

[0058] S32: Use a photomask aligner for photolithography alignment, expose and remove the photoresist in the photolithography area of the grooves 40 in hard contact mode, shake and develop it in a developer for 30 s, rinse it with deionized water, and blow it dry with a nitrogen gun. Finally, bake it on a hot plate at 120 °C for 90 s for post-baking and film hardening.

[0059] S33: Place it in the reaction chamber of an inductively coupled plasma (ICP) etching instrument, and use Cl 2 , BCl 3 as the reaction gas, set the reaction chamber pressure to 5 mtorr, and set the RF radio frequency source to 150 W. Etch the p-GaN layer 20 to form a plurality of grooves 40 until a part of n is exposed- Ga 2 O 3 Layer 13. Among them, a plurality of trenches 40 are formed in the middle region of the p-GaN layer 20, and a part of the p-GaN layer 20 in the peripheral region of the trench 40 forms a junction termination extension structure 50.

[0060] During the etching process, due to the poor heat dissipation performance of the Ga 2 O 3 material, it is necessary to apply thermal grease on the surface of the p-GaN layer 20 before etching to assist heat dissipation and avoid damage to the device performance caused by a large amount of heat.

[0061] S34: After completing the etching process, place it in an acetone solution for ultrasonic cleaning to remove the photoresist and thermal grease, and then soak it in a piranha solution (H 2 SO 4 :H 2 O 2 = 4:1, v / v) for 20 min to remove the residual thermal grease and the plasma remaining on the surface after etching, then place it under deionized water for rinsing, and blow it dry with a nitrogen gun.

[0062] S40: Please refer to Figure 5 , and form an anode metal layer 60 on the surface of the p-GaN layer 20 inside the trench 40, between adjacent trenches 40, and at least part of the surface of the junction termination extension structure 50.

[0063] Among them, the anode metal layer 60 contacts the n - Ga 2 O 3 layer 13 through the trench 40 to form a Schottky barrier.

[0064] In some embodiments, the material of the anode metal layer 60 may include Pt, Ni, Au, etc., and it may be a single-layer structure or a multi-layer structure. As an example, the cathode metal layer 30 is Ni / Au or Pt / Au.

[0065] When the anode metal layer 60 is Ni / Au, the thickness of the Ni layer can be 10 nm to 50 nm, such as 50 nm; the thickness of the Au layer can be 100 nm to 200 nm, such as 200 nm.

[0066] In some embodiments, the preparation method of the anode metal layer 60 includes: sequentially depositing metals Ni and Au on the surface of the etched p-GaN layer 20 by using an electron beam evaporation process.

[0067] Further, the method for preparing the anode metal layer 60 may include the steps of: First, implement pattern transfer of the anode metal layer 60 region (e.g., a circular region with a diameter of 100 μm) through a bilayer resist process. Drop a tackifier (e.g., HMDS) on the surface of the p-GaN layer 20, spin coat it at a speed of 2500 - 3000 revolutions per minute in a spin coater for 30 s, and then let it stand for 1 min. Then drop a photoresist (LOR) and spin coat it at a speed of 3500 - 4000 revolutions per minute for 1 min. After the photoresist spin coating is completed, bake it on a hot plate at 170 °C for 7 min - 9 min, and then drop a photoresist and spin coat it at a speed of 3000 revolutions per minute for 35 s. After the photoresist spin coating is completed, place it on a hot plate at 100 °C and bake it for 180 s for pre-baking. Then use an electron beam evaporation device to sequentially deposit metals Ni / Au (50 nm / 200 nm) on the etched p-GaN layer 20 surface as the anode metal layer 60. Then place it in a DMSO solution at 80 °C to strip the metals in the non-anode region.

[0068] Please refer to Figure 5 , an embodiment of the present application further provides a gallium oxide junction barrier Schottky diode prepared by the above preparation method, including a cathode metal layer 30, an n + Ga 2 O 3 layer 11, an n - Ga 2 O 3 layer 13, a p-GaN layer 20, and an anode metal layer 60, which are stacked in sequence. The p-GaN layer 20 has a plurality of through trenches 40 and a junction termination extension structure 50 surrounding the periphery of the trenches 40. The anode metal layer 60 is filled in the trenches 40 and covers the p-GaN layer 20 between adjacent trenches 40 and at least a part of the surface of the junction termination extension structure 50.

[0069] In one embodiment, the cathode metal layer 30 is Ti / Au (20 nm / 100 nm); n + Ga 2 O 3 layer 11 has a thickness of 650 μm, and its material is β-Ga 2 O 3 doped with Sn, and the doping concentration of Sn is 6.4×10 18 cm -3 ; n - Ga 2 O 3 layer 13 has a thickness of 11 μm, and its material is unintentionally doped β-Ga 2 O 3 , and the electron concentration is 2.5×10 16 cm -3; The thickness of the p-GaN layer 20 is 900 nm, and the doping concentration of Mg in the p-GaN layer 20 is 5×10 19 cm -3 ; The number of the trenches 40 is 6, the width is 10 μm, and the spacing between every two adjacent trenches 40 is 6 μm; the width of the junction termination extension structure 50 is 20 μm; the anode metal layer 60 is Ni / Au (50 nm / 200 nm), and the diameter is 100 μm.

[0070] Figure 6 It is a comparison chart of the breakdown voltage / leakage current curves of the above-mentioned gallium oxide junction barrier Schottky diode (corresponding to JBS in the figure) and the existing Schottky diode (corresponding to SBD in the figure). From Figure 6 it can be seen that the breakdown voltage of the existing SBD device is 570 V, and the order of magnitude of the leakage current is 10 -9 A / cm 2 , while the breakdown voltage of the JBS device prepared in the embodiment of the present application is as high as 1630 V, and the order of magnitude of the leakage current can be as low as 10 -10 A / cm 2 .

[0071] The embodiments described above are some embodiments of the present application, rather than all embodiments. The detailed description of the embodiments of the present application is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

Claims

1. A method for preparing a gallium oxide junction barrier Schottky diode, characterized in that: The following steps are involved: An epitaxial wafer is provided, the epitaxial wafer comprising stacked n + Ga2O3 layer and n - Ga2O3 layer, and the n - The Ga2O3 layer deviates from the n + A p-GaN layer is formed on the surface of the Ga2O3 layer; In the above + The Ga2O3 layer deviates from the n - A cathode metal layer is formed on the surface of the Ga2O3 layer; A plurality of trenches are formed through the p-GaN layer to expose a portion of the n-GaN layer. - Ga2O3 layer, and forming a junction terminal extension structure at the periphery of the trench; An anode metal layer is formed in the trench, on the surface of the p-GaN layer between adjacent trenches, and on the surface of at least a portion of the junction terminal extension structure.

2. The preparation method according to claim 1, characterized in that: The method for forming the p-GaN layer comprises: using a metal organic chemical vapor deposition method to deposit the p-GaN layer on the n - The Ga2O3 layer deviates from the n + p-GaN is deposited on the surface of the Ga2O3 layer to form the p-GaN layer.

3. The preparation method according to claim 1 or 2, characterized in that: The thickness of the p-GaN layer is 500nm to 1000nm; The p-GaN layer is doped with Mg, and the doping concentration of Mg is 10 18 cm -3 ~10 20 cm -3 .

4. The preparation method according to claim 1, characterized in that: The number of the grooves is 4 to 6, the width of the grooves is 10 μm to 15 μm, and the distance between every two adjacent grooves is 6 μm to 10 μm.

5. The preparation method according to claim 1 or 4, characterized in that: The method for forming the grooves includes: performing resist coating, photolithography, etching and resist stripping in sequence on the surface of the p-GaN layer to form a plurality of the grooves.

6. The preparation method according to claim 1, characterized in that: The width of the junction terminal extension structure is 5 μm to 20 μm.

7. The preparation method according to claim 1, characterized in that: The method for forming the cathode metal layer comprises: using an electron beam evaporation process to form a cathode metal layer on the n - Metal Ti and Au are deposited on the surface of the Ga2O3 layer in sequence; The method for forming the anode metal layer comprises: using an electron beam evaporation process to sequentially deposit metal Ni and Au on the surface of the p-GaN layer.

8. The preparation method according to claim 1, characterized in that: The + The material of the Ga2O3 layer is β-Ga2O3 doped with Sn, and the doping concentration of Sn is 10 17 cm -3 ~10 19 cm -3 , the n + The thickness of the Ga2O3 layer is 600μm to 700μm; The - The material of the Ga2O3 layer is unintentionally doped β-Ga2O3 with an electron concentration of 10 15 cm -3 ~10 17 cm -3 , the n - The thickness of the Ga2O3 layer is 8μm to 15μm.

9. A gallium oxide junction barrier Schottky diode, characterized in that: The cathode metal layer and the n + Ga2O3 layer, n - A Ga2O3 layer, a p-GaN layer and an anode metal layer, wherein the p-GaN layer has a plurality of through grooves and a junction terminal extension structure surrounding the outer periphery of the grooves, and the anode metal layer fills the grooves and covers the p-GaN layer between adjacent grooves and at least a portion of the surface of the junction terminal extension structure.

10. The gallium oxide junction barrier Schottky diode according to claim 9, characterized in that: The number of the grooves is 4 to 6, the width of the grooves is 10 μm to 15 μm, and the distance between every two adjacent grooves is 6 μm to 10 μm.

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