Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure which comprises a substrate and a multi-channel heterojunction layer which are arranged in a stacked mode, the multi-channel heterojunction layer comprises a plurality of heterojunction layers, each heterojunction layer comprises a channel layer and a barrier layer, and the multi-channel heterojunction layer is provided with a plurality of grooves; and the P-type epitaxial layer comprises a plurality of first P-type regions for filling the grooves. The transverse PN junction is formed through the first P-type region and the two-dimensional electron gas in the heterojunction, the depletion region of the PN junction is broadened during reverse biasing so as to pinch off a current channel, the Schottky junction with low barrier height is effectively shielded, the Schottky barrier lowering effect can be inhibited, reverse leakage current can be controlled, and therefore the breakdown voltage is improved, and the low turn-on voltage is kept. And meanwhile, a plurality of parallel two-dimensional electron gas passages are formed between the cathode and the anode by utilizing stacking of a plurality of heterojunctions, so that depletion of two-dimensional electron gas by the first P-type region is compensated, and the forward current of the diode is ensured.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As an enhanced Schottky diode, the junction barrier Schottky (JBS) diode has become a research hotspot. The outstanding advantages of the junction barrier Schottky diode are the on-state and fast switching characteristics of the Schottky barrier diode, as well as the off-state and low leakage current characteristics of the PIN diode. GaN stands out in the preparation of high-performance power devices with its larger bandgap width, higher critical breakdown electric field, higher electron saturation drift velocity, and excellent physical and chemical properties such as stable chemical properties, high temperature resistance, and radiation resistance, and has great application potential.

[0003] Due to the dislocation problem of the GaN material, the leakage current of the GaN-based junction barrier Schottky diode is relatively large, and the structural advantages of the junction barrier Schottky diode cannot be fully utilized. In the field of high-voltage switch applications, obtaining a GaN diode with a small reverse leakage current, a large reverse breakdown voltage, a small forward conduction voltage drop, and a simple process is still a problem in the prior art. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to further reduce the reverse leakage current of the GaN-based junction barrier Schottky diode and fully utilize the structural advantages of the junction barrier Schottky diode.

[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, characterized by comprising:

[0006] A substrate and a multi-channel heterojunction layer stacked, the multi-channel heterojunction layer includes the 1st, 2nd, …, nth heterojunction layers in the direction away from the substrate, n≥2, each heterojunction layer includes a channel layer and a barrier layer, the multi-channel heterojunction layer has a plurality of grooves, the bottom surface of at least one of the grooves is located in the channel layer of the 1st heterojunction layer, the plurality of grooves are located at one end of the multi-channel heterojunction layer and are spaced along a first direction, and each groove extends along a second direction perpendicular to the first direction and parallel to the plane where the substrate is located;

[0007] A P-type epitaxial layer, the P-type epitaxial layer includes a plurality of first P-type regions filling the grooves.

[0008] As an alternative embodiment, the contact interface between the channel layer and the barrier layer in each of the heterojunction layers has a two-dimensional electron gas, and the lengths of the first P-type regions in the second direction and / or the lengths in the first direction at different two-dimensional electron gases are different.

[0009] As an alternative embodiment, the length of each of the first P-type regions in the second direction increases uniformly or stepwise in a direction away from the substrate.

[0010] As an alternative embodiment, the length of each of the first P-type regions in the first direction increases uniformly or stepwise in a direction away from the substrate.

[0011] As an alternative embodiment, the bottom surface of the groove has a (1-100) crystal plane or a (11-20) crystal plane.

[0012] As an alternative embodiment, the P-type epitaxial layer further includes a second P-type layer located on the multi-channel heterojunction layer and the plurality of first P-type regions, and the second P-type layer is connected to the plurality of first P-type regions.

[0013] As an alternative embodiment, the length of the second P-type layer in the second direction is greater than or equal to the length of the first P-type region in the second direction.

[0014] As an alternative embodiment, the second P-type layer entirely covers the multi-channel heterojunction layer.

[0015] As an alternative embodiment, the lengths of at least two of the first P-type regions in the first direction are different.

[0016] As an alternative embodiment, the spacing distances of at least two of the first P-type regions in the first direction are different.

[0017] As an alternative embodiment, the material of the P-type epitaxial layer includes a P-type gallium nitride-based material.

[0018] As an alternative embodiment, the semiconductor structure further includes:

[0019] An anode and a cathode, located at two ends of the multi-channel heterojunction layer, and the anode is in contact with the first P-type region and is located at the same end of the multi-channel heterojunction layer.

[0020] As an alternative embodiment, at least one end of the first P-type region close to the cathode has a tip.

[0021] As an alternative embodiment, the semiconductor structure further includes:

[0022] A passivation layer, entirely covering the multi-channel heterojunction layer and the P-type epitaxial layer.

[0023] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which is characterized by including the following steps:

[0024] S1. Provide a substrate, and grow a multi-channel heterojunction layer on the substrate. In the direction away from the substrate, the multi-channel heterojunction layer is the 1st, 2nd, …, nth heterojunction layers, where n≥2. Each heterojunction layer includes a channel layer and a barrier layer;

[0025] S2. Etch a plurality of grooves at one end of the multi-channel heterojunction layer. The bottom surface of at least one groove is located in the channel layer of the 1st heterojunction layer. The plurality of grooves are arranged at intervals in a first direction, and each groove extends in a second direction perpendicular to the first direction and parallel to the plane where the substrate is located;

[0026] S3. Secondarily epitaxially grow a first P-type region in the groove.

[0027] As an optional embodiment, the method for manufacturing the semiconductor structure further includes:

[0028] S4. Continuously epitaxially grow a healed second P-type layer on the first P-type region.

[0029] As an optional embodiment, the method for manufacturing the semiconductor structure further includes:

[0030] S5. Etch both ends of the multi-channel heterojunction layer to form an anode region and a cathode region. The anode region is in contact with the first P-type region and is located at the same end of the multi-channel heterojunction layer. An anode is provided in the anode region, and a cathode is provided in the cathode region.

[0031] The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked. In the direction away from the substrate, the multi-channel heterojunction layer is the 1st, 2nd, …, nth heterojunction layers, where n≥2. Each heterojunction layer includes a channel layer and a barrier layer. The multi-channel heterojunction layer has a plurality of grooves. The bottom surface of at least one groove is located in the channel layer of the 1st heterojunction layer. The plurality of grooves are located at one end of the multi-channel heterojunction layer and are arranged at intervals in a first direction. Each groove extends in a second direction perpendicular to the first direction and parallel to the plane where the substrate is located; a P-type epitaxial layer, and the P-type epitaxial layer includes a plurality of first P-type regions filling the grooves.

[0032] The present disclosure forms a lateral PN junction by the first P-type region and the two-dimensional electron gas in the heterojunction. When reverse-biased, the depletion region of the PN junction expands to pinch off the current channel, effectively shielding the Schottky junction with a low barrier height, suppressing the Schottky barrier lowering effect and controlling the reverse leakage current, increasing the breakdown voltage, while maintaining a low turn-on voltage. At the same time, the stacking of multiple heterojunctions forms multiple parallel two-dimensional electron gas paths between the anode and the cathode, greatly reducing the on-resistance of the diode, compensating for the depletion of the two-dimensional electron gas by the first P-type region, and ensuring a large forward current of the diode. The first P-type region and the second P-type layer can cooperate to redistribute the surface electric field of the heterojunction structure between the anode and the cathode, improve the electric field distribution at the anode edge, prevent avalanche breakdown, further increase the device breakdown voltage and reduce the reverse leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0034] Figure 2 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0035] Figure 3 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0036] Figures 4a to 4b The figure shows a front view of a semiconductor structure provided by an embodiment of the present disclosure.

[0037] Figures 5a to 5b The figure shows a side view of a semiconductor structure provided by an embodiment of the present disclosure.

[0038] Figure 6 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0039] Figures 7a to 7b The figure shows a side view of a semiconductor structure provided by an embodiment of the present disclosure.

[0040] Figure 8 The figure shows a top view of a semiconductor structure provided by an embodiment of the present disclosure.

[0041] Figure 9 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0042] Figure 10 The figure shows a flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure.

[0043] Figures 11 - 14 The figure shows a schematic diagram of an intermediate structure in the manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0045] In order to further reduce the reverse leakage current of the GaN-based junction barrier Schottky diode and give full play to the structural advantages of the junction barrier Schottky diode, the present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked thereon. The multi-channel heterojunction layer includes multiple heterojunction layers, and each heterojunction layer includes a channel layer and a barrier layer. The multi-channel heterojunction layer has multiple grooves; a P-type epitaxial layer, and the P-type epitaxial layer includes multiple first P-type regions filling the grooves. By forming a lateral PN junction between the first P-type region and the two-dimensional electron gas in the heterojunction, when reverse-biased, the depletion region of the PN junction widens to pinch off the current channel, effectively shielding the Schottky junction with a low barrier height, suppressing the Schottky barrier lowering effect and controlling the reverse leakage current, thereby increasing the breakdown voltage and maintaining a low turn-on voltage. At the same time, the stacking of multiple heterojunctions forms multiple parallel two-dimensional electron gas paths between the anode and the cathode to compensate for the depletion of the two-dimensional electron gas by the first P-type region and ensure the forward current of the diode.

[0046] Next, in combination with Figures 1 to 14 A semiconductor structure and a manufacturing method thereof mentioned in the present disclosure will be further illustrated by examples.

[0047] Figure 1 The following shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 2 The following shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. As Figure 1 shown, the semiconductor structure includes a substrate 10 and a multi-channel heterojunction layer 20 stacked thereon. In the direction away from the substrate 10 of the multi-channel heterojunction layer 20, there are the first, second,..., nth heterojunction layers, n≥2. Each heterojunction layer includes a channel layer 21 and a barrier layer 22. The multi-channel heterojunction layer 20 has multiple grooves 201. The bottom surface of at least one groove 201 is located in the channel layer 21 of the first heterojunction layer. The multiple grooves 201 are located at one end of the multi-channel heterojunction layer 20 and are spaced along a first direction. Each groove 201 extends along a second direction perpendicular to the first direction and parallel to the plane where the substrate 10 is located; a P-type epitaxial layer 30, and the P-type epitaxial layer 30 includes multiple first P-type regions 31 filling the grooves 201. As Figure 2As shown, the semiconductor structure further includes: an anode 41 and a cathode 42, located at both ends of the multi-channel heterojunction layer 20. The anode 41 is in contact with the first P-type region 31 and is located at the same end of the multi-channel heterojunction layer 20.

[0048] In this embodiment, the multi-channel heterojunction layer 20 may include only two heterojunction layers, namely, the first heterojunction layer and the second heterojunction layer stacked in the direction away from the substrate 10. In other embodiments, the multi-channel heterojunction layer 20 may include three or more heterojunction layers, namely, the first heterojunction layer, the second heterojunction layer... the nth heterojunction layer stacked in the direction away from the substrate 10, where n≥3. Each heterojunction layer includes a channel layer 21 and a barrier layer 22. The bandgap width of the material of the barrier layer 22 is greater than that of the material of the channel layer 21. The material of the channel layer 21 and the material of the barrier layer 22 may include group III nitride materials. A two-dimensional electron gas may be formed at the interface between the channel layer 21 and the barrier layer 22. In an alternative solution, the channel layer 21 is a GaN layer and the barrier layer 22 is an AlGaN layer. In other alternative solutions, the material combination of the channel layer 21 and the barrier layer 22 may also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN or InN / InAlN. The materials of the multi-layer heterojunction layers may be the same or different, and the present disclosure does not make specific limitations.

[0049] In this embodiment, the bottom surface of the groove 201 in the multi-channel heterojunction layer 20 has a (1-100) crystal plane or a (11-20) crystal plane. The groove 201 with a bottom surface having a (1-100) crystal plane or a (11-20) crystal plane is beneficial to reducing the electric field intensity at the sharp corners of the groove in the subsequent manufactured device. The groove 201 may also be secondarily etched to form a bottom rounded corner structure, which can also reduce the electric field intensity at the sharp corners of the groove in the subsequent manufactured device. The material of the P-type epitaxial layer 30 provided in the groove 201 includes a P-type gallium nitride-based material. Figure 3 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In this embodiment, the groove 201 may be located inside and at both ends of the multi-channel heterojunction layer 20, as Figure 1 shown. In another embodiment, the groove 201 may be only located inside the multi-channel heterojunction layer 20, as Figure 3 shown.

[0050] Figures 4a to 4b The figure shows a front view of a semiconductor structure provided by an embodiment of the present disclosure. Figures 5a to 5bThe following is a side view of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, the contact interface between the channel layer 21 and the barrier layer 22 in each heterojunction layer has a two-dimensional electron gas, and the lengths of the first P-type regions 31 in the second direction and / or the lengths in the first direction at different two-dimensional electron gases are different. Specifically, the length of each first P-type region 31 in the second direction increases uniformly (as shown in Figure 4a ), or increases in a stepped manner (as shown in Figure 4b ) in the direction away from the substrate 10, and / or the length of each first P-type region 31 in the first direction increases uniformly (as shown in Figure 5a ) or increases in a stepped manner (as shown in Figure 5b ) in the direction away from the substrate 10. By changing the lengths of the first P-type regions 31 in the second direction and the first direction, on the one hand, the channel shape can be changed to increase the electron movement path, thereby reducing the on-state resistance, and on the other hand, the depletion layer width can be changed to reduce the peak electric field, thereby increasing the breakdown voltage.

[0051] Figure 6 The following is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, as shown in Figure 1 , the P-type epitaxial layer 30 further includes a second P-type layer 32 located on the multi-channel heterojunction layer 20 and a plurality of first P-type regions 31, and the second P-type layer 32 is connected to the plurality of first P-type regions 31. The length of the second P-type layer 32 in the second direction is greater than or equal to the length of the first P-type region 31 in the second direction. Optionally, as shown in Figure 6 , the second P-type layer 32 entirely covers the multi-channel heterojunction layer 20. The first P-type region 31 and the second P-type layer 32 can cooperate to redistribute the surface electric field of the heterojunction structure between the anode 41 and the cathode 42, can improve the electric field distribution at the edge of the anode 41, prevent avalanche breakdown, and further increase the device breakdown voltage and reduce the reverse leakage current.

[0052] Figures 7a to 7b The following is a side view of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, as shown in Figure 7a , the lengths of at least two first P-type regions 31 in the first direction are different (a 1 , a 2 ). In another embodiment, as shown in Figure 7b , the spacing distances of at least two first P-type regions 31 in the first direction are different (b 1 , b 2 ). By changing the lengths and spacing distances of the plurality of first P-type regions 31 in the first direction, the channel shape and the depletion layer width can be further changed, the electron movement path and the peak electric field can be adjusted, thereby reducing the on-state resistance while increasing the breakdown voltage.

[0053] Figure 8The top view of a semiconductor structure provided by an embodiment of the present disclosure is shown. In one embodiment, as Figure 8 shown, at least one end of the first P-type region 31 close to the cathode 42 has a tip. Designing a tip at one end of the first P-type region 31 can further improve the electric field distribution between the anode 41 and the cathode 42.

[0054] Figure 9 The structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown. In one embodiment, as Figure 9 shown, the semiconductor structure further includes: a passivation layer 43, which entirely covers the multi-channel heterojunction layer 20 and the P-type epitaxial layer 30. The material of the passivation layer 43 can be SiN, SiO 2 、SiON, Al 2 O 3 、MgO, Ga 2 O 3 or HfO 2 , and is used to isolate external water and oxygen from entering the P-type epitaxial layer 30 and the multi-channel heterojunction layer 20.

[0055] According to another aspect of the present disclosure, Figure 10 The flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure is shown, Figures 11 - 14 The intermediate structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure during manufacturing is shown. As Figure 10 shown, the manufacturing method of the semiconductor structure provided by an embodiment of the present disclosure includes the following steps:

[0056] Step S1: Provide a substrate, and grow a multi-channel heterojunction layer on the substrate. In the direction away from the substrate, the multi-channel heterojunction layer is the 1st, 2nd, …, nth heterojunction layer, n≥2, and each heterojunction layer includes a channel layer and a barrier layer.

[0057] Specifically, as Figure 11 shown, provide a substrate 10, and grow a multi-channel heterojunction layer 20 on the substrate 10. In the direction away from the substrate 10, the multi-channel heterojunction layer 20 is the 1st, 2nd, …, nth heterojunction layer, n≥2, and each heterojunction layer includes a channel layer 21 and a barrier layer 22. The material of the substrate 10 includes Si, Al 2 O 3, any one or a combination of more than one of GaN, SiC, or AlN. The method of growing the multi-channel heterojunction layer 20 on the substrate 10 can be in-situ growth, or can be obtained by atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0058] Step S2: Etch a plurality of grooves at one end of the multi-channel heterojunction layer, the bottom surface of at least one groove is located in the channel layer of the first layer heterojunction layer, the plurality of grooves are arranged at intervals in the first direction, and each groove extends in a second direction perpendicular to the first direction and parallel to the plane where the substrate is located.

[0059] Specifically, as Figure 12 shown, etch a plurality of grooves 201 at one end of the multi-channel heterojunction layer 20, the bottom surface of at least one groove 201 is located in the channel layer 21 of the first layer heterojunction layer, the plurality of grooves 201 are arranged at intervals in the first direction, and each groove 201 extends in a second direction perpendicular to the first direction and parallel to the plane where the substrate 10 is located. By controlling the shape and spacing of the grooves 201, the shape and spacing of the first P-type regions 31 grown in the grooves 201 can be controlled.

[0060] Step S3: Secondarily epitaxially grow a first P-type region in the groove.

[0061] Specifically, as Figure 13 shown, secondarily epitaxially grow a first P-type region 31 in the groove 201. Controlling the shape and spacing of the first P-type regions 31 grown in the grooves 201 can regulate the channel shape and depletion layer width of the semiconductor structure, adjust the electron movement path and peak electric field, thereby reducing the on-state resistance while increasing the breakdown voltage.

[0062] Step S4: Continuously epitaxially grow a healed second P-type layer on the first P-type region.

[0063] Specifically, as Figure 14As shown, a healed second P-type layer 32 is epitaxially formed on the first P-type region 31. The first P-type region 31 and the second P-type layer 32 can cooperate to redistribute the surface electric field of the heterojunction structure between the subsequently provided anode 41 and cathode 42, improve the electric field distribution at the electrode edge, prevent avalanche breakdown, further increase the device breakdown voltage and reduce the reverse leakage current.

[0064] Step S5: Etch both ends of the multi-channel heterojunction layer to form an anode region and a cathode region. The anode region is in contact with the first P-type region and is located at the same end of the multi-channel heterojunction layer. An anode is provided in the anode region and a cathode is provided in the cathode region.

[0065] Specifically, etch both ends of the multi-channel heterojunction layer 20 to form an anode region and a cathode region. The anode region is in contact with the first P-type region 31 and is located at the same end of the multi-channel heterojunction layer 20. An anode 41 is provided in the anode region and a cathode 42 is provided in the cathode region to form a semiconductor structure as shown in Figure 2 The semiconductor structure provided by the present disclosure is used to fabricate a junction barrier Schottky diode, which can reduce the reverse leakage current of the junction barrier Schottky diode and give full play to the structural advantages of the junction barrier Schottky diode.

[0066] The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked thereon. In the direction away from the substrate, the multi-channel heterojunction layer is the 1st, 2nd, …, nth heterojunction layer, n≥2. Each heterojunction layer includes a channel layer and a barrier layer. The multi-channel heterojunction layer has a plurality of grooves. The bottom surface of at least one groove is located in the channel layer of the 1st heterojunction layer. The plurality of grooves are located at one end of the multi-channel heterojunction layer and are arranged at intervals along the first direction. Each groove extends along a second direction perpendicular to the first direction and parallel to the plane where the substrate is located; a P-type epitaxial layer, and the P-type epitaxial layer includes a plurality of first P-type regions filling the grooves.

[0067] The present disclosure forms a lateral PN junction through the first P-type region and the two-dimensional electron gas in the heterojunction. When reverse-biased, the depletion region of the PN junction widens to pinch off the current channel, effectively shielding the Schottky junction with a low barrier height, suppressing the Schottky barrier lowering effect and controlling the reverse leakage current, increasing the breakdown voltage, and at the same time maintaining a low turn-on voltage. At the same time, the stacking of multiple heterojunctions forms multiple parallel two-dimensional electron gas paths between the anode and the cathode, greatly reducing the on-resistance of the diode, compensating for the depletion of the two-dimensional electron gas by the first P-type region, and ensuring a large forward current of the diode. The first P-type region and the second P-type layer can cooperate to redistribute the surface electric field of the heterojunction structure between the anode and the cathode, improve the electric field distribution at the anode edge, prevent avalanche breakdown, further increase the device breakdown voltage and reduce the reverse leakage current.

[0068] It should be understood that the term "including" and its variations used in this disclosure are open-ended, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0069] The above are only the preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, comprising: A substrate (10) and a multi-channel heterojunction layer (20) stacked thereon. In the direction away from the substrate (10), the multi-channel heterojunction layer (20) is composed of the 1st, 2nd, …, nth heterojunction layers, where n≥2. Each heterojunction layer includes a channel layer (21) and a barrier layer (22). The multi-channel heterojunction layer (20) has a plurality of grooves (201). The bottom surface of at least one of the grooves (201) is located in the channel layer (21) of the 1st heterojunction layer. The plurality of grooves (201) are located at one end of the multi-channel heterojunction layer (20) and are spaced apart along a first direction. Each groove (201) extends along a second direction perpendicular to the first direction and parallel to the plane where the substrate (10) is located; A P-type epitaxial layer (30), and the P-type epitaxial layer (30) includes a plurality of first P-type regions (31) filling the grooves (201).

2. The semiconductor structure according to claim 1, characterized in that, The contact interface between the channel layer (21) and the barrier layer (22) in each heterojunction layer has a two-dimensional electron gas, and the lengths of the first P-type regions (31) at different two-dimensional electron gas locations in the second direction and / or in the first direction are different.

3. The semiconductor structure according to claim 2, characterized in that, The length of each first P-type region (31) in the second direction increases uniformly or stepwise in the direction away from the substrate (10).

4. The semiconductor structure according to claim 2, characterized in that, The length of each first P-type region (31) in the first direction increases uniformly or stepwise in the direction away from the substrate (10).

5. The semiconductor structure according to claim 1, characterized in that, The bottom surface of the groove (201) has a (1-100) crystal plane or a (11-20) crystal plane.

6. The semiconductor structure according to claim 1, characterized in that, The P-type epitaxial layer (30) further includes a second P-type layer (32) located on the multi-channel heterojunction layer (20) and the plurality of first P-type regions (31), and the second P-type layer (32) is connected to the plurality of first P-type regions (31).

7. The semiconductor structure according to claim 6, characterized in that, The length of the second P-type layer (32) in the second direction is greater than or equal to the length of the first P-type region (31) in the second direction.

8. The semiconductor structure according to claim 7, characterized in that, The second P-type layer (32) entirely covers the multi-channel heterojunction layer (20).

9. The semiconductor structure according to claim 1, characterized in that, The lengths of at least two of the first P-type regions (31) in the first direction are different.

10. The semiconductor structure according to claim 1, characterized in that, The spacing distances of at least two of the first P-type regions (31) in the first direction are different.

11. The semiconductor structure according to claim 1, characterized in that, The material of the P-type epitaxial layer (30) includes a P-type gallium nitride-based material.

12. The semiconductor structure according to claim 1, wherein, the semiconductor structure further comprises: an anode (41) and a cathode (42), located at two ends of the multi-channel heterojunction layer (20), the anode (41) being in contact with the first P-type region (31) and located at the same end of the multi-channel heterojunction layer (20).

13. The semiconductor structure according to claim 12, wherein, at least one end of the first P-type region (31) close to the cathode (42) has a tip.

14. The semiconductor structure according to claim 1, wherein, the semiconductor structure further comprises: a passivation layer (43), covering the multi-channel heterojunction layer (20) and the P-type epitaxial layer (30) entirely.

15. A manufacturing method of a semiconductor structure, wherein, it comprises the following steps: S1. Provide a substrate (10), and grow a multi-channel heterojunction layer (20) on the substrate (10). In the direction away from the substrate (10), the multi-channel heterojunction layer (20) is the 1st, 2nd, …, nth heterojunction layer, n≥2, and each heterojunction layer comprises a channel layer (21) and a barrier layer (22); S2. Etch a plurality of grooves (201) at one end of the multi-channel heterojunction layer (20), the bottom surface of at least one groove (201) being in the channel layer (21) of the 1st heterojunction layer. The plurality of grooves (201) are arranged at intervals in a first direction, and each groove (201) extends in a second direction perpendicular to the first direction and parallel to the plane where the substrate (10) is located; S3. Secondarily epitaxially grow a first P-type region (31) in the groove (201).

16. The manufacturing method of the semiconductor structure according to claim 15, wherein, the manufacturing method of the semiconductor structure further comprises: S4. Continuously epitaxially grow a healed second P-type layer (32) on the first P-type region (31).

17. The manufacturing method of the semiconductor structure according to claim 15, wherein, the manufacturing method of the semiconductor structure further comprises: S5. Etch two ends of the multi-channel heterojunction layer (20) to form an anode region and a cathode region. The anode region is in contact with the first P-type region (31) and located at the same end of the multi-channel heterojunction layer (20). An anode (41) is arranged in the anode region, and a cathode (42) is arranged in the cathode region.

Images