Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; sequentially forming a coupling oxide layer and a floating gate on the surface of the substrate in the first region; forming a photoresist layer on the surface of the substrate in the second region; forming an initial shallow trench with a first depth by adopting the substrate exposed by the anisotropic etching window; performing isotropic etching on the initial shallow trench to form a final shallow trench; and filling an isolation layer in the final shallow trench to form shallow trench isolation. Forming an initial shallow trench with a first depth by adopting anisotropic etching, and then forming a final shallow trench by adopting isotropic etching on the initial shallow trench; the bottom corner of the final shallow trench is rounded, the gap at the bottom corner of the final shallow trench is avoided, the breakdown voltage is effectively improved, and the on-resistance is not obviously increased. The final shallow trench is formed through step-by-step etching, and the initial shallow trench is subjected to isotropic etching, so that the uniformity of the depth of the final shallow trench on the whole wafer is improved; finally, the vertex angle of the shallow trench becomes larger, and the pressure resistance is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device and a preparation method thereof. Background Art

[0002] LDMOS is a laterally doped MOS transistor. A drift region is formed between the active region and the drain region, and a shallow trench isolation is formed in the drift region. The depth and angle of the shallow trench isolation are crucial for the breakdown voltage and leakage current of the LDMOS device. The shallow trench isolation is usually formed by filling an oxide layer in the shallow trench.

[0003] In the current manufacturing process, on the one hand, the depth uniformity of the shallow trench isolation of the LDMOS devices fabricated on each chip on the whole wafer is poor. The depth of the shallow trench isolation of the LDMOS devices fabricated on the chips in the central region of the wafer is relatively shallow. The reduction of the depth of the shallow trench isolation will lead to a decrease in the breakdown voltage. On the other hand, the bottom corner topography of the shallow trench is not good, there is a notch at the bottom corner, which affects the breakdown voltage. On the other hand, the top angle of the inverted trapezoid of the shallow trench is relatively small (for example, about 45°). The smaller the top angle, the larger the leakage current density and the smaller the withstand voltage. Summary of the Invention

[0004] The purpose of the present invention is to provide a preparation method of a semiconductor device. An initial shallow trench with a first depth is first formed by anisotropic etching, and then the initial shallow trench is etched isotropically to form a final shallow trench; the bottom corner of the final shallow trench is made more rounded, and the smooth transition avoids the notch at the bottom corner of the final shallow trench, effectively improving the breakdown voltage, and the on-resistance does not increase significantly. The final shallow trench is formed by stepwise etching, and the initial shallow trench is etched isotropically, improving the depth uniformity of the final shallow trench on the whole wafer; the top angle of the final shallow trench becomes larger, improving the withstand voltage performance.

[0005] The present invention provides a preparation method of a semiconductor device, including:

[0006] S1. Provide a substrate, where the substrate includes a first region for forming a flash memory and a second region for forming an LDMOS device;

[0007] S2. Sequentially form a coupling oxide layer and a floating gate on the surface of the substrate in the first region;

[0008] S3. Form a patterned photoresist layer on the surface of the substrate in the second region. The patterned photoresist layer has a window, and the window exposes the region of the substrate corresponding to form the shallow trench isolation;

[0009] S4. Anisotropically etch the substrate exposed by the window to form an initial shallow trench with a first depth;

[0010] S5. Anisotropically etch the initial shallow trench to form a final shallow trench;

[0011] S6. Fill the final shallow trench with an isolation layer to form shallow trench isolation.

[0012] Further, in a cross-section perpendicular to the substrate, the final shallow trench is trapezoidal in an inverted shape, and the apex angle of the inverted trapezoid is: 60° to 75°.

[0013] Further, the depth of the final shallow trench is: 2000 Å ± 200 Å.

[0014] Further, in an upper region of the substrate in the second region, a drift region and a P-type body region are formed. Shallow trench isolation is formed in the substrate on a side of the drift region away from the P-type body region, and shallow trench isolation is also formed in an upper region inside the drift region.

[0015] Further, a polysilicon layer is formed above the substrate, and the polysilicon layer serves as the gate of the LDMOS device; an N-type ion-doped region in an upper region of the P-type body region is the source, and an N-type ion-doped region in an upper region of the drift region is the drain; the concentration gradient of the drift region decreases from the drain to the source of the LDMOS device.

[0016] Further, after step S2 and before step S3, it further includes:

[0017] Deposit a silicon nitride layer, and the silicon nitride layer covers the floating gate.

[0018] Further, the substrate includes a single-layer silicon substrate or an SOI substrate, and the SOI substrate includes a bottom silicon layer, an N-type buried layer, and a top silicon layer from bottom to top.

[0019] The present invention also provides a semiconductor device, including:

[0020] A substrate, the substrate includes a first region for forming a flash memory and a second region for forming an LDMOS device;

[0021] A coupling oxide layer and a floating gate are sequentially formed on the surface of the substrate in the first region;

[0022] A final shallow trench is formed in the substrate in the second region;

[0023] The final shallow trench is filled with an isolation layer to form shallow trench isolation.

[0024] Further, a drift region and a P-type body region are formed in the upper region of the substrate in the second region. A shallow trench isolation is formed in the substrate on the side of the drift region away from the P-type body region, and the shallow trench isolation is also formed in the upper region inside the drift region.

[0025] Further, a source line polysilicon layer is formed on the surface of the substrate in the first region. On both sides of the source line polysilicon layer, a coupling oxide layer, a floating gate, and a floating gate sidewall are formed in sequence on the substrate in a mirror image manner; a word line is further formed on the side of the floating gate sidewall away from the source line polysilicon layer.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method includes: S1. Providing a substrate, which includes a first region for forming a flash memory and a second region for forming an LDMOS device; S2. Sequentially forming a coupling oxide layer and a floating gate on the surface of the substrate in the first region; S3. Forming a patterned photoresist layer on the surface of the substrate in the second region. The patterned photoresist layer has a window, and the window exposes the region of the substrate corresponding to form a shallow trench isolation; S4. Using anisotropic etching to etch the substrate exposed by the window to form an initial shallow trench with a first depth; S5. Using isotropic etching to etch the initial shallow trench to form a final shallow trench; S6. Filling an isolation layer in the final shallow trench to form a shallow trench isolation. The present invention first forms an initial shallow trench with a first depth by anisotropic etching, and then uses isotropic etching to etch the initial shallow trench to form a final shallow trench; making the bottom corner of the final shallow trench more rounded, and the smooth transition avoids the notch at the bottom corner of the final shallow trench, effectively improving the breakdown voltage, and the on-resistance does not increase significantly. The final shallow trench is formed by step-by-step etching, and the initial shallow trench is etched isotropically, improving the uniformity of the depth of the final shallow trench on the whole wafer; the top angle of the final shallow trench becomes larger, improving the breakdown voltage performance. Description of the Drawings

[0028] Figure 1 The first schematic diagram of the notch existing at the bottom corner after shallow trench etching.

[0029] Figure 2 The second schematic diagram of the notch existing at the bottom corner after shallow trench etching.

[0030] Figure 3 The schematic flow chart of the manufacturing method of a semiconductor device according to an embodiment of the present invention.

[0031] Figure 4 The schematic diagram of the flash memory part in the semiconductor device according to an embodiment of the present invention.

[0032] Figure 5Schematic diagram of the final shallow trench of the LDMOS device part in the semiconductor device of the embodiment of the present invention.

[0033] Figure 6 Schematic diagram of the LDMOS device part in the semiconductor device of the embodiment of the present invention.

[0034] Figure 7 Schematic diagram of the avalanche ionization distribution of the breakdown voltage simulation of the LDMOS device at different angles of the top corner of the inverted trapezoid of the shallow trench in the LDMOS device.

[0035] Among them, the reference numerals are as follows:

[0036] 01 - Oxide layer; 02 - Photoresist; 03 - Mask;

[0037] 10 - Substrate; 100 - Bottom silicon; 101 - N-type buried layer; 102 - Top silicon; 11 - LDMOS device; 111 - Drift region; 112 - P-type body region; 113 - Shallow trench isolation; 114 - Polysilicon layer; 12 - Flash memory; 121 - Coupling oxide layer; 122 - Floating gate; 123 - Source line polysilicon layer; 124 - Floating gate sidewall; 125 - Word line; 126 - LDD sidewall; 127 - Isolation layer; 128 - Metal silicide layer; 129 - Bit line. Detailed implementation manners

[0038] As in the background art, the bottom corner morphology of the shallow trench is not good, there is a notch at the bottom corner, which affects the breakdown voltage. The reasons are as follows. On the one hand, as Figure 1 shown, a photoresist 02 is formed on the oxide layer 01. The photoresist 02 has a window corresponding to the shallow trench. A mask 03 corresponding to the pattern of the photoresist 02 is provided above the photoresist 02. The oxide layer 01 is dry-etched with the photoresist 02 as a mask to form a shallow trench. The mask 03 carries a positive charge. During the dry-etching process, there is a positive charge at the bottom of the shallow trench. Like charges repel each other. During the dry-etching process, the charges that should be etched towards the bottom are repelled to the two corners, resulting in a notch at the bottom corner of the shallow trench. On the other hand, as Figure 2 shown, during the dry plasma etching process, there is sputtering reflection of the plasma. The ions hitting the sidewall of the shallow trench are reflected and reach Figure 2 the place of the red circle. Due to the boundary effect of the dry etching, the plasma bounces to the corner, making the etching at the bottom corner faster, which will also cause a notch at the bottom corner of the shallow trench.

[0039] The present invention will be further described in detail below with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0040] For ease of description, some embodiments of the present application may use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the respective drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatial relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawing is flipped, an element or component described as "below" or "beneath" other elements or components will subsequently be positioned "above" or "over" the other elements or components. The terms "first", "second", etc. in the following text are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms may be replaced where appropriate.

[0041] Embodiments of the present invention provide a method for manufacturing a semiconductor device, as Figure 3 shown, including:

[0042] S1. Provide a substrate, the substrate including a first region for forming a flash memory and a second region for forming an LDMOS device;

[0043] S2. Sequentially form a coupling oxide layer and a floating gate on the surface of the substrate in the first region;

[0044] S3. Form a patterned photoresist layer on the surface of the substrate in the second region, the patterned photoresist layer having a window that exposes the region of the substrate corresponding to form a shallow trench isolation;

[0045] S4. Anisotropically etch the substrate exposed by the window to form an initial shallow trench with a first depth;

[0046] S5. Isotropically etch the initial shallow trench to form a final shallow trench;

[0047] S6. Fill the final shallow trench with an isolation layer to form a shallow trench isolation.

[0048] The following details each step of the method for manufacturing a semiconductor device according to the embodiments of the present invention with reference to the accompanying drawings.

[0049] Step S1. As Figure 4 and Figure 5As shown, a substrate 10 is provided. The substrate 10 includes a first region for forming a flash memory 12 and a second region for forming an LDMOS device 11. Subsequent processes integrate the LDMOS device 11 and the flash memory 12 on the same substrate 10. Among them, the substrate 10 can be any suitable substrate material known in the art, for example, at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, etc., or is silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or can also be a double-sided polished silicon wafer. Exemplarily, in this embodiment, the substrate is, for example, a silicon wafer.

[0050] Step S2: Sequentially form a coupling oxide layer 121 and a floating gate 122 in the flash memory 12 on the surface of the substrate 10 in the first region. After step S2, it may further include: depositing a silicon nitride layer, and the silicon nitride layer covers the floating gate 122.

[0051] Step S3: Form a patterned photoresist layer on the surface of the substrate in the second region. The patterned photoresist layer has a window, and the window exposes the region of the substrate corresponding to forming the shallow trench isolation in the LDMOS device 11.

[0052] Step S4: Use anisotropic etching to etch the substrate exposed by the window to form an initial shallow trench with a first depth;

[0053] Step S5: Use isotropic etching to etch the initial shallow trench to form a final shallow trench V. In a cross-section perpendicular to the substrate, the final shallow trench V is trapezoidal in reverse, and the apex angle ∠BAC (i.e., angle θ) of the trapezoid in reverse is: 60° - 75°. The apex angle of the trapezoid in reverse of the final shallow trench V becomes larger, improving the breakdown voltage performance. The present invention effectively increases the breakdown voltage, and the on-resistance does not increase significantly. Exemplarily, for example, the designed depth of the final shallow trench V is 2700 angstroms, and the conventional process uses dry etching to etch to 2700 angstroms in one step. The present invention uses step S4 and step S5 for step-by-step etching. In step S4, anisotropic etching can be used to etch to a depth of 2400 angstroms; then in step S5, isotropic etching can be used to etch downward by a depth of 300 angstroms. The depth of the final shallow trench is set according to actual needs without limitation. In step S5, isotropic etching has no directionality, and isotropic etching does not bombard the corners of the bottom angle of the trapezoid in reverse of the initial shallow trench, thereby avoiding the formation of notches at the bottom angle due to bombardment.

[0054] Step S6: Fill the final shallow trench with an isolation layer to form a shallow trench isolation.

[0055] Figure 7 It is a schematic diagram of the impact ionization distribution of the breakdown voltage simulation of an LDMOS device at different angles of the top corner of a shallow trench inverted trapezoid. As Figure 7 shown, the smaller the top corner of the shallow trench inverted trapezoid, the closer the impact ionization region is to the surface, and the smaller the breakdown voltage.

[0056] The present invention combines the BCD process and the flash memory process, and forms the final shallow trench by step-by-step etching. The anisotropic etching is first used to form an initial shallow trench with a first depth, and then the isotropic etching is used to etch the initial shallow trench to form the final shallow trench; the bottom corner of the final shallow trench is made more rounded, and the smooth transition avoids the notch at the bottom corner of the final shallow trench; the bottom corner of the final shallow trench has a smooth transition, the electric field is gentle and will not be broken down; the impact ionization region is more uniform, weakening the concentrated and prominent impact ionization region in the morphology before improvement, reducing the weak points of the breakdown voltage, and effectively improving the breakdown voltage. At the same time, the current density distribution will also be more uniform, effectively reducing the hot spot effect of the power array.

[0057] The present invention focuses on elaborating how to form a shallow trench. The present invention also forms the remaining parts of the flash memory 12 and the remaining parts of the LDMOS device 11 in the subsequent process. As Figure 4 and Figure 6 shown, the LDMOS device 11 and the flash memory 12 can be integrated on a single-layer substrate; the LDMOS device 11 and the flash memory 12 can also be integrated on an SOI substrate. Figure 4 and Figure 6 show a case where the substrate 10 is an SOI substrate. As Figure 6 shown, for the LDMOS device 11 part, the substrate 10 includes a bottom silicon layer 100, an N-type buried layer 101, and a top silicon layer 102 (for example, a P-type epitaxial layer) from bottom to top. A drift region 111 and a P-type body region 112 are formed in the upper region of the substrate 10. A shallow trench isolation 113 is formed on one side of the drift region 111 away from the P-type body region 112, and a shallow trench isolation 113 is also formed in the upper region inside the drift region 111. A polysilicon layer 114 is formed above the substrate 10, and the polysilicon layer 114 serves as the gate of the LDMOS device 11.

[0058] The present invention introduces a shallow trench isolation 113 into the drift region 111 of the LDMOS device 11, optimizes the electric field in the drift region 111, and shortens the current path in the drift region 111. Compared with the traditional shallow trench isolation (STI), the shallow trench isolation 113 of the present invention reduces the STI depth, which brings benefits to the breakdown voltage and leakage current characteristics of the LDMOS device. The process flow of the shallow trench isolation 113 is simple and easy to integrate with the CMOS process.

[0059] Further, in the LDMOS device 11, the N-type ion-doped region N+ in the upper region of the P-type body region 112 serves as the source electrode, and the N-type ion-doped region N+ in the upper region of the drift region 111 serves as the drain electrode. The concentration gradient of the drift region 111 from the drain electrode to the source electrode of the LDMOS device 11 decreases, achieving lateral variable doping. Since a new electric field peak is introduced at the junction of the concentration partitions, the electric field in the drift region is optimized, and the breakdown voltage of the LDMOS device 11 is improved. The lateral variable-doping LDMOS achieves a decrease in the concentration gradient of the drift region from the drain electrode to the source electrode to achieve an overall increase in concentration, effectively reducing the on-resistance, and at the same time can effectively increase the breakdown voltage of the device.

[0060] As Figure 4 shown, the structure of the flash memory 12 is not limited and can be set according to actual needs. Exemplarily, the substrate 10 includes a bottom silicon layer 100, an N-type buried layer 101, and a top silicon layer 102 (such as a P-type epitaxial layer) from bottom to top. An active line polysilicon layer 123 is formed on the surface of the substrate 10. On both sides of the active line polysilicon layer 123, a coupled oxide layer 121, a floating gate 122, and a floating gate sidewall 124 are formed in sequence on the substrate 10. A word line 125 is further formed on the side of the floating gate sidewall 124 away from the active line polysilicon layer 123. In the direction perpendicular to the substrate 10, there is a longitudinal isolation layer between the word line 125 and the coupled oxide layer 121, the floating gate 122, and the floating gate sidewall 124 from bottom to top; in the horizontal direction, there is a lateral isolation layer between the word line 125 and the substrate 10; the longitudinal isolation layer and the lateral isolation layer are connected to form an isolation layer 127. An LDD sidewall 126 is formed on the side of the word line 125 away from the floating gate sidewall 124. A bit line 129 is formed in the substrate 10, and a metal silicide layer 128 is formed on the surfaces of the bit line 129, the word line 125, and the active line polysilicon layer 123.

[0061] The present invention also provides a semiconductor device, including:

[0062] a substrate 10, the substrate including a first region for forming the flash memory 12 and a second region for forming the 11 LDMOS device;

[0063] a coupled oxide layer 121 and a floating gate 12 are sequentially formed on the surface of the substrate in the first region;

[0064] a final shallow trench V is formed in the substrate in the second region;

[0065] The final shallow trench is filled with an isolation layer to form a shallow trench isolation 113.

[0066] A drift region 111 and a P-type body region 112 are formed in the upper region of the substrate in the second region. A shallow trench isolation 113 is formed in the substrate on the side of the drift region 111 away from the P-type body region 112, and a shallow trench isolation 113 is also formed in the upper region inside the drift region 111.

[0067] On the surface of the substrate in the first region, an active line polysilicon layer 123 is formed. On both sides of the active line polysilicon layer 123, a coupling oxide layer 121, a floating gate 122, and a floating gate sidewall 124 are formed in sequence on the substrate in a mirror image manner; a word line 125 is further formed on the side of the floating gate sidewall 124 away from the active line polysilicon layer 123.

[0068] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. The manufacturing method includes: S1, providing a substrate, the substrate including a first region for forming a flash memory and a second region for forming an LDMOS device; S2, sequentially forming a coupling oxide layer and a floating gate on the surface of the substrate in the first region; S3, forming a patterned photoresist layer on the surface of the substrate in the second region, the patterned photoresist layer having a window, the window exposing the region of the substrate corresponding to form a shallow trench isolation; S4, using anisotropic etching to etch the substrate exposed by the window to form an initial shallow trench with a first depth; S5, using isotropic etching to etch the initial shallow trench to form a final shallow trench; S6, filling an isolation layer in the final shallow trench to form a shallow trench isolation. The present invention first forms an initial shallow trench with a first depth by anisotropic etching, and then uses isotropic etching to etch the initial shallow trench to form a final shallow trench; making the bottom corner of the final shallow trench more rounded, and the smooth transition avoids the notch at the bottom corner of the final shallow trench, effectively improving the breakdown voltage, and the on-resistance does not increase significantly. The final shallow trench is formed by stepwise etching, and the initial shallow trench is etched isotropically, improving the uniformity of the depth of the final shallow trench on the entire wafer; the top angle of the final shallow trench becomes larger, improving the breakdown voltage performance.

[0069] In the present specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the method disclosed in the embodiments, since it corresponds to the device disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description in the method part.

[0070] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the rights of the present invention in any way. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change, and modification made to the above embodiments according to the technical essence of the present invention without departing from the technical solution of the present invention all belong to the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: S1. providing a substrate, wherein the substrate comprises a first region for forming a flash memory and a second region for forming an LDMOS device; S2, sequentially forming a coupling oxide layer and a floating gate on the surface of the substrate in the first region; S3, forming a patterned photoresist layer on the surface of the substrate in the second region, wherein the patterned photoresist layer has a window, and the window exposes a region of the substrate corresponding to the shallow trench isolation; S4, anisotropically etching the substrate exposed by the window to form an initial shallow trench of a first depth; S5, isotropically etching the initial shallow trench to form a final shallow trench; S6. Filling an isolation layer in the final shallow trench to form shallow trench isolation.

2. The method for preparing a semiconductor device according to claim 1, wherein: On a cross section perpendicular to the substrate, the final shallow trench is in an inverted trapezoidal shape, and the top angle of the inverted trapezoid is 60° to 75°.

3. The method for preparing a semiconductor device according to claim 1, wherein: The depth of the final shallow trench is: 2000 angstroms ± 200 angstroms.

4. The method for preparing a semiconductor device according to claim 1, wherein: A drift region and a P-type body region are formed in an upper region of the substrate of the second region, a shallow trench isolation is formed in the substrate on a side of the drift region away from the P-type body region, and a shallow trench isolation is also formed in an upper region inside the drift region.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: A polysilicon layer is formed on the substrate, and the polysilicon layer serves as the gate of the LDMOS device; the N-type ion doped region in the upper region of the P-type body region serves as the source, and the N-type ion doped region in the upper region of the drift region serves as the drain; The concentration gradient of the drift region decreases from the drain to the source of the LDMOS device.

6. The method for preparing a semiconductor device according to claim 1, wherein: After step S2 and before step S3, the method further includes: A silicon nitride layer is deposited, the silicon nitride layer covering the floating gate.

7. The method for preparing a semiconductor device according to claim 1, wherein: The substrate includes a single-layer silicon substrate or an SOI substrate, and the SOI substrate includes a bottom silicon layer, an N-type buried layer and a top silicon layer from bottom to top.

8. A semiconductor device, characterized in that: The method according to any one of claims 1 to 7 comprises: A substrate, the substrate comprising a first region for forming a flash memory and a second region for forming an LDMOS device; A coupling oxide layer and a floating gate are sequentially formed on the surface of the substrate in the first region; forming a final shallow trench in the substrate of the second region; The final shallow trench is filled with an isolation layer to form shallow trench isolation.

9. The semiconductor device according to claim 8, characterized in that A drift region and a P-type body region are formed in an upper region of the substrate of the second region, a shallow trench isolation is formed in the substrate on a side of the drift region away from the P-type body region, and a shallow trench isolation is also formed in an upper region inside the drift region.

10. The semiconductor device according to claim 8, wherein A source line polysilicon layer is formed on the surface of the substrate of the first region, and the coupling oxide layer, the floating gate and the floating gate sidewalls located on the substrate are mirror-imaged on both sides of the source line polysilicon layer; a word line is also formed on the side of the floating gate sidewall away from the source line polysilicon layer.

Images