Full-transparent tunneling thin film transistor and preparation method thereof

Abstract

The invention discloses a full-transparent tunneling thin film transistor and a preparation method thereof. The preparation method comprises the following steps: depositing a transparent bottom gate electrode on a transparent substrate; after patterning the transparent bottom gate electrode, growing a transparent gate dielectric layer; depositing an active layer on the transparent gate dielectric layer; after the active layer is patterned, growing an ultrathin transparent tunneling layer; and depositing a transparent source electrode and a transparent drain electrode on the ultrathin transparent tunneling layer, and patterning. The transparent conductor is used as an active layer, the transparent insulating layer is used as a gate dielectric layer and grows on the transparent substrate, all materials have extremely high transparency (85-99.9%), the substrate, the dielectric layer and the tunneling layer as well as the electrode and the active layer can respectively use the same insulator and transparent conductor, and the problem that the current SBTFT device is not high in reliability can be solved. Especially, the problems that the oxide semiconductor SBTFT metal electrode cannot be fully transparent, the migration rate is low and the performance is degraded in a low-temperature environment are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of transistors, and particularly relates to a fully transparent tunneling thin film transistor and a preparation method thereof. Background Art

[0002] The statements herein only provide background art related to the present invention and do not necessarily constitute prior art.

[0003] The tunneling thin film transistor is one of the ways to realize the Schottky barrier thin film transistor (hereinafter simply referred to as SBTFT). With the rapid development of wearable devices and flexible electronics technologies, developing oxide semiconductor SBTFTs with low power consumption, high mobility, and excellent stability has become the key to breaking through the bottleneck of flexible integrated circuit technologies.

[0004] Different from traditional TFTs, SBTFTs establish a Schottky barrier between the source / active layer, and the gate voltage precisely controls the effective height of the barrier to achieve precise control of the current magnitude and device switching. This unique structure endows SBTFTs with many advantages. The low saturation voltage characteristic can effectively reduce power consumption and extend the battery life of the device, making it very suitable for application scenarios with strict power consumption requirements, such as wearable devices like smart bracelets and wireless earphones; for complex factors such as bias stress, SBTFTs exhibit good stability, providing new ideas and methods for the design of high-performance and high-reliability thin film digital circuits.

[0005] However, most of the current mainstream SBTFTs use oxide semiconductors as the active layer. For example, indium gallium zinc oxide (IGZO) is a combination of three metal oxide semiconductors In 2 O 3 、ZnO、Ga 2 O 3 Combination. Such devices generally use high work function metals as source and drain electrodes to achieve effective Schottky contact, which directly causes the visible light transmittance in the electrode region to drop sharply to less than 15%. In active light-emitting display scenarios such as AMOLEDs, opaque electrodes will block 30%-40% of the effective light-emitting area, forcing pixel designs to increase the redundant aperture ratio, severely restricting the miniaturization process of 4K / 8K ultra-high resolution displays. More notably, in emerging transparent electronics fields such as transparent smart windows and AR glasses optical waveguides, metal electrodes destroy the overall light transmittance of the device (<50%), making it difficult to meet the industry's basic standards.

[0006] From the perspective of device performance, the channel mobility of oxide semiconductor materials is relatively low. Taking IGZO materials as an example, their electron mobility generally remains at 10-20 cm 2 / Vs, it is difficult to meet the core requirements of fast charge and discharge for high refresh rates. Take an 8K display with a 240Hz refresh rate as an example. The refresh time of a single pixel must be compressed to within 0.5 μs, which has basically reached the upper limit of the theoretical operating frequency of IGZO devices. At the same time, the low mobility means that the channel width needs to be expanded to meet the required current requirements, and the excessively large channel area will severely limit the improvement of pixel density.

[0007] Finally, the currently popular SBTFT mostly adopts a scheme where the active layer is in direct contact with the source electrode. Its carrier transport mechanism highly depends on the synergistic effect of thermionic emission and thermo-field emission. This physical nature results in a strong non-linear correlation between the electrical characteristics of the device and temperature. Especially in a low-temperature environment below 0 °C, there is a strong performance decay. For example, in a low-temperature cold start scenario, the right shift of the threshold voltage leads to start failure and response delay, and the display brightness decays, etc. Summary of the Invention

[0008] Aiming at the deficiencies of the existing technology, the purpose of the present invention is to provide a fully transparent tunneling thin film transistor and its preparation method. Using a transparent conductor thin layer as the active layer and a transparent insulating dielectric layer as the gate dielectric layer, grown on a transparent substrate, all materials have extremely high transparency (85 - 99.9%) in the visible light range, which can solve the problems of the current SBTFT devices, especially the metal electrodes of oxide semiconductor SBTFTs, being unable to achieve full transparency, low mobility, and performance decay in a low-temperature environment; and in the present invention, the transparent substrate, gate insulating layer, and ultra-thin tunneling layer can use the same transparent insulating material, and the gate electrode, source electrode, drain electrode, and active layer can also use the same transparent conductor, making the process simpler and reducing the cost of large-area preparation.

[0009] To achieve the above purpose, the present invention is realized through the following technical solutions:

[0010] In the first aspect, the present invention provides a preparation method of a fully transparent tunneling thin film transistor, including the following steps:

[0011] Deposit a transparent bottom gate electrode on a transparent substrate;

[0012] After patterning the transparent bottom gate electrode, grow a transparent gate dielectric layer;

[0013] Deposit an active layer on the transparent gate dielectric layer;

[0014] After patterning the active layer, grow an ultra-thin transparent tunneling layer;

[0015] Deposit transparent source and drain electrodes on the ultra-thin transparent tunneling layer and pattern them.

[0016] In some embodiments, the material of the transparent substrate is an organic substrate such as fluorinated polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), as well as inorganic substrates such as quartz glass, ZnO, Al 2 O 3 , HfO 2 , ZrO 2 , SiO 2 , SiN X and other inorganic substrates.

[0017] In some embodiments, the material of the transparent bottom gate electrode is ITO, FTO, conductive polymer, metal grid, graphene, CNT, etc.

[0018] Preferably, the material of the transparent bottom gate electrode is ITO, and sputtering deposition is carried out in a pure Ar atmosphere, with a base vacuum of 5 - 9×10 -6 Torr.

[0019] Preferably, the thickness of the ITO transparent bottom gate electrode is 1 - 500 nm, preferably 30 - 80 nm, and further preferably 50 nm.

[0020] In some embodiments, the target of the ITO transparent bottom gate electrode is an ITO ceramic target;

[0021] Preferably, in the ITO ceramic target, the mass ratio of In 2 O 3 and SnO 2 is 8 - 10:1.

[0022] Preferably, the sputtering power is 1 - 100 W, preferably 40 - 80 W, and further preferably 55 - 65 W.

[0023] In some embodiments, the material of the transparent gate dielectric layer is an organic material such as fluorinated polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), as well as Al 2 O 3 , HfO 2 , ZrO 2 , SiO 2 , SiN X and other inorganic dielectric layers.

[0024] Preferably, the material of the transparent gate dielectric layer is selected as Al 2 O 3 , and the growth method is atomic layer deposition, with a growth temperature of 0 - 1000 °C, preferably 100 - 300 °C, and further preferably 200 °C.

[0025] Preferably, the Al 2 O3 The thickness of the transparent gate dielectric layer is 1 - 500 nm, more preferably 20 - 40 nm, and even more preferably 30 nm.

[0026] In some embodiments, the material of the active layer is ATO, FTO, AZO, In 2 O 3 , ITO, ITiO, IMO, and BaSnO 3 and other transparent conductors and / or their mixtures.

[0027] Preferably, the material of the active layer is ITO. During the deposition process, appropriate oxygen doping and annealing in an oxygen atmosphere can effectively fill oxygen defects, improve the film quality, reduce the carrier concentration, and significantly increase the mobility.

[0028] Preferably, the oxygen partial pressure during the deposition of the active layer is 1 - 60%, preferably 10 - 30%.

[0029] More preferably, the sputtering deposition atmosphere of the active layer is a mixed atmosphere of Ar and O 2 , and the oxygen partial pressure is 20%.

[0030] Preferably, the thickness of the active layer is 1 - 40 nm, more preferably 10 - 15 nm, and even more preferably 12 nm.

[0031] In some embodiments, the annealing temperature is 0 - 1200 °C, and the annealing time is 0 - 12 h.

[0032] Preferably, the annealing temperature is 150 - 250 °C, and the annealing time is 0.5 - 1.5 h.

[0033] More preferably, the annealing temperature is 200 °C, and the annealing time is 1 h.

[0034] Preferably, after annealing the sample, it is naturally cooled for 10 - 30 min.

[0035] In some embodiments, the material of the ultrathin transparent tunneling layer is Al 2 O 3 , HfO 2 , ZrO 2 , SiO 2 , GaO X , graphene, CNT, TiSi X , SiN X .

[0036] Preferably, the material of the ultrathin transparent tunneling layer is Al 2 O 3, The growth method is atomic layer deposition, the growth temperature is 0 - 1000 °C, preferably 100 - 300 °C, and further preferably 200 °C.

[0037] Preferably, the Al 2 O 3 The thickness of the ultra-thin transparent tunneling layer is 0.1 - 20 nm, further preferably 1 - 3 nm, and even more preferably 2 nm.

[0038] In some embodiments, the materials of the transparent source and drain electrodes are ITO, FTO, conductive polymers, metal grids, graphene, CNT, etc.

[0039] Preferably, the materials of the source and drain electrodes are selected as ITO, and sputter deposition is carried out in a pure Ar atmosphere, and the base vacuum is 5 - 9×10 -6 Torr.

[0040] Preferably, the thickness of the ITO transparent bottom gate electrode is 1 - 200 nm, preferably 30 - 80 nm, and further preferably 50 nm.

[0041] In a second aspect, the present invention provides a fully transparent tunneling thin film transistor prepared by the preparation method.

[0042] The beneficial effects obtained by one or more of the above embodiments of the present invention are as follows:

[0043] All the materials used in the present invention are transparent thin films, and the materials involved are such as ITO and Al 2 O 3 etc. The band gap of ITO is 3.5 - 4.3 eV, and the light transmittance is 85% - 95%. The band gap of Al 2 O 3 is 3 - 9 eV, and the light transmittance > 95%. Therefore, it can be used as a fully transparent SBTFT device. Under the same backlight intensity, it can increase the light transmittance and improve the screen display brightness.

[0044] For the tunneling thin film transistor obtained by the present invention, a transparent conductor with better conductivity, such as ITO, is selected as the active layer, and after annealing is carried out after depositing the ITO active layer, ITO recrystallizes, and its effective mobility is greatly improved, reaching 30 - 140 cm 2 / Vs, which is 3 - 14 times higher than that of semiconductor channels such as IGZO SBTFT. It is beneficial to reduce the device size. As a driving backplane, it can effectively improve the pixels and reduce the power consumption.

[0045] For the device obtained by the present invention, the transparent substrate, gate insulating layer, and ultra-thin tunneling layer can use the same transparent insulating material, and the electrodes and active layer can also use the same transparent conductor. Therefore, the process is simpler and the cost of large-area preparation is reduced.

[0046] The transparent ultra-thin tunneling layer between the source and the active layer forms an effective Schottky barrier between the two, rather than an ohmic contact. The source barrier region operating in the reverse bias state restricts the injection of carriers from the source and depletes the active layer region below the source, enabling the device to saturate at an extremely low drain voltage. Its saturation voltage can be controlled within 1V, and the change value with respect to the gate voltage is only 0.02V / V. The intrinsic gain is an important parameter for measuring the signal amplification ability of a transistor and can be obtained by multiplying the transconductance g m by the output impedance Z. The depletion region, as a high-resistance region, basically shields the influence of drain voltage changes on the current. Therefore, the output impedance reaches 5×10 9 Ω, and the intrinsic gain consequently reaches over 3000. Based on the fact that this device can maintain a stable current output within a relatively wide range of drain voltages, it is expected to be applied to the current source in a pixel circuit.

[0047] The tunneling probability is only related to the carrier energy, that is, only related to the magnitude of the electric field in the depletion region below the end point on the side of the source close to the drain, and does not depend on temperature changes. Therefore, the SBTFT obtained by the tunneling effect is basically not affected by low temperatures, which is beneficial to the application of the device in a low-temperature environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings forming a part of this invention are used to provide a further understanding of the invention. The schematic embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation to the invention.

[0049] Figure 1 is a schematic structural diagram of a tunneling thin-film transistor in an embodiment of the invention;

[0050] Figure 2 is the transfer characteristic curve of the tunneling thin-film transistor in Embodiment 1 of the invention;

[0051] Figure 3 is the output characteristic curve of the tunneling thin-film transistor in Embodiment 1 of the invention.

[0052] Among them, 1, transparent substrate; 2, bottom gate; 3, gate dielectric layer; 4, active layer; 5, ultra-thin tunneling layer; 6, drain; 7, source. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs.

[0054] The invention will be further described below in conjunction with embodiments.

[0055] Example 1

[0056] The device structure is as Figure 1 shown, and the specific preparation process is as follows:

[0057] (1) Clean the substrate. Place the substrate in a 5% Decon 90 cleaning solution and ultrasonically clean it for 5 min, then ultrasonically clean it with deionized water for 5 min and repeat twice, and dry it with N 2 blower. Then ultrasonically clean it in isopropyl alcohol and ethanol for 5 min in sequence, and finally dry it with N 2 blower.

[0058] (2) Deposit the ITO transparent bottom gate electrode: Sputter-deposit ITO as the bottom gate electrode on the substrate obtained in (1) at room temperature in a pure Ar atmosphere, with a thickness of 80 nm. The target material is an ITO ceramic target (In 2 O 3 :SnO 2 = 9:1), the base vacuum is 8×10 -6 Torr, the Ar gas flow rate is 20 sccm, the sputtering power is 100 W, and the working gas pressure is controlled at 5.7 mTorr.

[0059] (3) Coat the photoresist. Bake the sample obtained in (2) in air to remove surface moisture, then coat the photoresist and bake it in air to evaporate the solvent in the photoresist.

[0060] (4) Ultraviolet lithography. The light source is a mercury lamp with a wavelength of 365 nm and a power density of 12 mW / cm 2 , and expose it in the soft contact mode for 7 s.

[0061] (5) Development. After exposure, soak it in a developer with a concentration of (AR 300-26:H 2 O) = 1:6 for 30 s, rinse it with H 2 O and dry it with N 2 blower.

[0062] (6) Etching. Etch the sample obtained in (5), preferably dry etching. Put it into an ICP dry etching machine, evacuate to 8×10 -6 Torr, set the HF power to 50 W, the ICP power supply power to 200 W, the chamber temperature to 60 °C, the carrier gas N 2 gas flow rate to 20 sccm, and the etching gas is CH 4 and H 2 .

[0063] (7) Stripping. After etching, soak the sample in acetone for 1 h to remove the excess photoresist.

[0064] (8) Grow Al 2 O 3 transparent gate dielectric layer. Place the sample in an atomic layer deposition equipment, set the growth temperature at 200 °C, and grow 30 nm of Al 2 O 3 .

[0065] (9) Deposit a patterned ITO transparent active layer (same as steps (3)-(7)): The sample obtained in (8) is sputter-deposited with ITO in an Ar / O 2 mixed gas with an oxygen partial pressure of 20% at room temperature, with a thickness of 12 nm. The base vacuum is 8×10 -6 Torr, the total gas flow rate is 20 sccm, the sputtering power is 60 W, and the working gas pressure is controlled at 5.7 mTorr.

[0066] (10) Oxygen thermal annealing: The sample obtained in (9) is annealed at atmospheric pressure in a rapid thermal annealing furnace at a temperature of 200 °C. The annealing procedure is as follows: After 60 s, the sample temperature rises from room temperature (25 °C) to 200 °C; it is maintained at 200 °C for 1 h, and after 30 min of natural cooling to 40 °C, the sample is taken out.

[0067] (11) Grow Al 2 O 3 ultra-thin transparent tunneling layer: The procedure is the same as in (8), and 2 nm of Al 2 O 3 .

[0068] (12) Deposit transparent ITO source and ITO drain.

[0069] For the device prepared in this example, the overall light transmittance can reach over 80%, the effective mobility is 132 cm 2 / Vs, and the device can reach saturation within 1 V. After saturation, the output impedance can be as high as 5×10 9 Ω, the intrinsic gain is above 3000, Figure 2 and Figure 3 are the transfer characteristic and output characteristic curves of the device respectively.

[0070] Example 2

[0071] The specific preparation process of the device is as follows:

[0072] (1) Clean the substrate. Place the substrate in a 5% Decon 90 cleaning solution and ultrasonically clean for 5 min, then ultrasonically clean with deionized water for 5 min and repeat twice, and blow dry with N 2 2. Then ultrasonically clean in isopropyl alcohol and ethanol for 5 min each, and finally blow dry with N 2 .

[0073] (2) Depositing ITO transparent bottom gate electrode: The substrate obtained in (1) is sputter-deposited with ITO as the bottom gate electrode in a pure Ar atmosphere at room temperature, with a thickness of 200 nm. The target material is an ITO ceramic target (In 2 O 3 :SnO 2 = 9:1), the base vacuum is 8×10 - 6 Torr, the Ar gas flow rate is 20 sccm, the sputtering power is 50 W, and the working pressure is controlled at 5.7 mTorr.

[0074] (3) Coating photoresist. The sample obtained in (2) is baked in air to remove surface moisture, and then photoresist is coated. After that, it is baked in air to evaporate the solvent in the photoresist.

[0075] (4) UV lithography. The light source is a mercury lamp with a wavelength of 365 nm and a power density of 12 mW / cm 2 , and exposure is carried out in the soft contact mode for 10 s.

[0076] (5) Development. After exposure, the sample is immersed in a developer with a concentration of (AR 300 - 26:H 2 O) = 1:6 for 20 s, rinsed with H 2 O and blown dry with N 2 .

[0077] (6) Etching. The sample obtained in (5) is etched, preferably by dry etching. It is placed in an ICP dry etching machine, evacuated to 8×10 -6 Torr, the HF power is set to 50 W, the ICP power supply power is 200 W, the chamber temperature is 60 °C, the carrier gas N 2 gas flow rate is 20 sccm, and the etching gas is CH 4 and H 2 .

[0078] (7) Photoresist removal. After etching, the sample is soaked in acetone for 1 h to remove the excess photoresist.

[0079] (8) Growing an Al 2 O 3 transparent gate dielectric layer. The sample is placed in an atomic layer deposition equipment, the growth temperature is set to 100 °C, and 100 nm of Al 2 O 3 is grown.

[0080] (9) Depositing a patterned ITO transparent active layer (same as steps (3)-(7)): The sample obtained in (8) is sputter-deposited with ITO at room temperature in an Ar / O 2 mixed gas with an oxygen partial pressure of 30%, with a thickness of 12 nm, and the base vacuum is 8×10-6 Torr, the total gas flow rate is 20 sccm, the sputtering power is 80 W, and the working pressure is controlled at 5.7 mTorr.

[0081] (10) Oxygen thermal annealing: The sample obtained in (9) is annealed at atmospheric pressure in a rapid thermal annealing furnace at a temperature of 200 °C. The annealing procedure can be specifically as follows: After 60 s, the sample temperature rises from room temperature (25 °C) to 200 °C; it is maintained at 200 °C for 1 h, and after natural cooling to 40 °C for 10 min, the sample is taken out.

[0082] (11) Grow HfO 2 ultra-thin transparent tunneling layer, the steps are the same as (8), grow 2 nm of Al 2 O 3 .

[0083] (12) Deposit transparent ITO source and ITO drain.

[0084] Example 3

[0085] The specific preparation process of the device is as follows:

[0086] (1) Clean the substrate. Place the substrate in a 5% Decon 90 cleaning solution and ultrasonically clean it for 5 min, then ultrasonically clean it with deionized water for 5 min and repeat twice, and dry it with N 2 blow dry. Then ultrasonically clean it in isopropyl alcohol and ethanol for 5 min in sequence, and finally dry it with N 2 blow dry.

[0087] (2) Deposit ITO transparent bottom gate electrode: The substrate obtained in (1) is sputter-deposited with ITO as the bottom gate electrode at room temperature in a pure Ar atmosphere, with a thickness of 80 nm. The target material is an ITO ceramic target (In 2 O 3 : SnO 2 = 9:1), the base vacuum is 8×10 -6 Torr, the Ar gas flow rate is 20 sccm, the sputtering power is 20 W, and the working pressure is controlled at 5.7 mTorr.

[0088] (3) Apply photoresist: Bake the sample obtained in (2) in air to remove surface moisture, then apply photoresist, and bake it in air to evaporate the solvent in the photoresist.

[0089] (4) UV lithography. The light source is a mercury lamp with a wavelength of 365 nm and a power density of 12 mW / cm 2 , and expose it in soft contact mode for 10 s.

[0090] (5) Development. After exposure, in a concentration of (AR 300 - 26: H2 Soak it in a developer solution with a ratio of O) = 1:6 for 20 s, rinse it with H 2 O and dry it with N 2 blow dry.

[0091] (6) Etching: Etch the sample obtained in (5), preferably by dry etching. Place it in an ICP dry etching machine, evacuate to 8×10 -6 Torr, set the HF power to 50 W, the ICP power supply power to 200 W, the chamber temperature to 60 °C, and the carrier gas N 2 gas flow rate to 20 sccm. The etching gas is CH 4 and H 2 .

[0092] (7) De-gumming: After etching, soak the sample in acetone for 1 h to remove the excess photoresist.

[0093] (8) Grow an Al 2 O 3 transparent gate dielectric layer: Place the sample in an atomic layer deposition equipment, set the growth temperature to 400 °C, and grow 300 nm of Al 2 O 3 .

[0094] (9) Deposit a patterned ITO transparent active layer (the same as steps (3)-(7)): The sample obtained in (8) is sputter-deposited with ITO in an Ar / O 2 mixed gas with an oxygen partial pressure of 10% at room temperature, with a thickness of 40 nm. The base vacuum is 8×10 -6 Torr, the total gas flow rate is 20 sccm, the sputtering power is 100 W, and the working gas pressure is controlled at 5.7 mTorr.

[0095] (10) Oxygen thermal annealing: Anneal the sample obtained in (9) at atmospheric pressure in a rapid thermal annealing furnace at a temperature of 100 °C. The annealing procedure can be specifically: After 60 s, the sample temperature rises from room temperature (25 °C) to 100 °C; it is maintained at 100 °C for 1 h, and after 30 min of natural cooling to 40 °C, the sample is taken out.

[0096] (11) Grow an Al 2 O 3 ultra-thin transparent tunneling layer, the steps are the same as (8), and 2 nm of Al 2 O 3 is grown.

[0097] (12) Deposit a transparent ITO source electrode and an ITO drain electrode.

[0098] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for preparing a fully transparent tunneling thin film transistor, characterized in that: The steps include: depositing a transparent bottom gate electrode on a transparent substrate; After the transparent bottom gate electrode is patterned, a transparent gate dielectric layer is grown; depositing an active layer on the transparent gate dielectric layer; After the active layer is patterned, an ultrathin transparent tunneling layer is grown; A transparent source electrode and a drain electrode are deposited on the ultra-thin transparent tunneling layer and patterned.

2. The method for preparing a fully transparent tunneling thin film transistor according to claim 1, characterized in that: The material of the transparent substrate is fluorinated polyimide, polyethylene terephthalate, polyimide, quartz glass, ZnO, Al2O3, HfO2, ZrO2, SiO2 or SiN X .

3. The method for preparing a fully transparent tunneling thin film transistor according to claim 1, characterized in that: The material of the transparent bottom gate electrode is ITO, FTO, conductive polymer, metal grid, graphene or CNT; Preferably, the material of the transparent bottom gate electrode is ITO, and the transparent bottom gate electrode is sputtered and deposited in a pure Ar atmosphere, and the background vacuum is 5-9×10 -6 Torr; Preferably, the thickness of the ITO transparent bottom gate electrode is 1-500 nm, preferably 30-80 nm, and more preferably 50 nm.

4. The method for preparing a fully transparent tunneling thin film transistor according to claims 1 and 2, characterized in that: The target material of the ITO transparent bottom gate electrode is an ITO ceramic target; Preferably, in the ITO ceramic target, the mass ratio of In2O3 to SnO2 is 8-10:1; Preferably, the sputtering power is 1-100W, preferably 40-80W, and more preferably 55-65W.

5. The method for preparing a fully transparent tunneling thin film transistor according to claim 1, characterized in that: The material of the transparent gate dielectric layer is fluorinated polyimide, polyethylene terephthalate or polyethylene naphthalate, and Al2O3, HfO2, ZrO2, SiO2 or SiN X ; Preferably, the material of the transparent gate dielectric layer is Al2O3, the growth method is atomic layer deposition, and the growth temperature is 0-1000°C, preferably 100-300°C, and more preferably 200°C; Preferably, the thickness of the Al2O3 transparent gate dielectric layer is 1-500 nm, more preferably 20-40 nm, and even more preferably 30 nm.

6. The method for preparing a fully transparent tunneling thin film transistor according to claim 1, characterized in that: The material of the active layer is one of ATO, FTO, AZO, In2O3, ITO, ITiO, IMO or BaSnO3 or a combination thereof; Preferably, the material of the active layer is ITO; Preferably, the oxygen partial pressure during the deposition of the active layer is 1 to 60%, preferably 10 to 30%; Further preferably, the sputtering deposition atmosphere of the active layer is a mixed atmosphere of Ar and O2, with an oxygen partial pressure of 20%; Preferably, the thickness of the active layer is 1-40 nm, more preferably 10-15 nm, and even more preferably 12 nm.

7. The method for preparing a fully transparent tunneling thin film transistor according to claims 1 and 5, characterized in that: The annealing temperature is 0-1200°C and the annealing time is 0-12h; Preferably, the annealing temperature is 150-250°C and the annealing time is 0.5-1.5h; Further preferably, the annealing temperature is 200° C. and the annealing time is 1 h; Preferably, after the sample is annealed, it is naturally cooled for 10-30 minutes.

8. The method for preparing a fully transparent tunneling thin film transistor according to claim 1, characterized in that: The material of the ultra-thin transparent tunneling layer is Al2O3, HfO2, ZrO2, SiO2, GaO X , graphene, CNT, TiSi X or SiN X ; Preferably, the ultra-thin transparent tunneling layer material is Al2O3, the growth method is atomic layer deposition, and the growth temperature is 0-1000°C, preferably 100-300°C, and more preferably 200°C; Preferably, the thickness of the Al2O3 ultra-thin transparent tunneling layer is 0.1-20 nm, more preferably 1-3 nm, and even more preferably 2 nm.

9. The method for preparing a fully transparent tunneling thin film transistor according to claim 1, characterized in that: The material of the transparent source and drain electrodes is ITO, FTO, conductive polymer, metal grid, graphene or CNT; Preferably, the source and drain materials are selected from ITO, and sputtering deposition is performed in a pure Ar atmosphere with a background vacuum of 5-9×10 -6 Torr; Preferably, the thickness of the ITO transparent bottom gate electrode is 1-200 nm, preferably 30-80 nm, and more preferably 50 nm.

10. A fully transparent tunneling thin film transistor, characterized in that: Prepared by the preparation method according to any one of claims 1 to 9; The device has a light transmittance of at least 70% in the visible light range; Or, the device has at least 10cm 2 / Vs mobility; Or, the device has a maximum of 200 cm 2 / Vs mobility.

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