Preparation method of semiconductor device and semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device and the semiconductor device, and the method comprises the steps: providing a substrate; wherein the base comprises a substrate, a first well region, a second well region and a gate structure, the first well region is located at one side of the substrate, the first well region has a first type of conductivity, the second well region and the first well region are located at the same side of the substrate, the second well region has a second type of conductivity, and the gate structure has a first type of conductivity and a second type of conductivity. The gate structures are located on the sides, away from the substrate, of the first well region and the second well region respectively; growing a silicon oxide film on one side of the substrate by adopting a secondary normal pressure chemical vapor deposition process; injecting silicon ions into the silicon oxide thin film by adopting an ion injection process; and combining the silicon ions with oxygen ions formed by annealing by adopting a first annealing process so as to form a silicon-rich silicon oxide film. According to the invention, no cavity is formed when the silicon-rich silicon oxide film grows on the surface of the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor device fabrication, and more particularly, to a method for fabricating a semiconductor device and a semiconductor device. Background Art

[0002] In the manufacturing process of semiconductor devices, the self-aligned salicide block layer (SBK) process is a key technology widely used in the production of high-performance integrated circuits.

[0003] The main steps of the SBK process include: First, depositing a silicon-rich silicon oxide film (SRO) to grow a silicon-rich silicon oxide film on the wafer surface. Second, selective etching, removing the SRO film in the area where metal silicide needs to be formed by dry etching, while the area where metal silicide does not need to be formed is covered by silicon oxide. Third, metal deposition and annealing, depositing metal in the exposed area and forming metal silicide through the annealing process. Fourth, removing the unreacted metal to complete the formation of metal silicide. The SBK process utilizes the high density of the silicon-rich silicon oxide film to effectively prevent metal ions from penetrating the film and protecting the underlying devices from being affected.

[0004] However, as the semiconductor technology node continues to shrink, the polysilicon pitch gradually decreases. When growing the silicon-rich silicon oxide film (SRO), voids may occur, resulting in inaccurate control during the subsequent dry etching process and further causing Si damage.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] In view of this, the present disclosure provides a method for fabricating a semiconductor device and a semiconductor device to at least solve the problem of voids existing in the preparation process of the existing silicon-rich silicon oxide film.

[0007] In one aspect, an embodiment of the present disclosure provides a method for fabricating a semiconductor device, including:

[0008] Providing a substrate; wherein the substrate includes a substrate, a first well region, a second well region, and a gate structure. The first well region is located on one side of the substrate, the first well region has a first type of conductivity, the second well region is located on the same side of the substrate as the first well region, the second well region has a second type of conductivity, and the gate structure is respectively located on the side of the first well region and the second well region away from the substrate;

[0009] Using a sub-atmospheric chemical vapor deposition process, a silicon oxide thin film is grown on the side of the gate structure facing away from the substrate;

[0010] Using an ion implantation process, silicon ions are implanted into the silicon oxide thin film;

[0011] Using a first annealing process, the silicon ions and the oxygen ions formed by annealing are combined to form a silicon-rich silicon oxide thin film.

[0012] In some embodiments, the process parameters of the sub-atmospheric chemical vapor deposition include: the reaction gas is ozone or tetraethyl orthosilicate gas, the deposition temperature is 400 °C; the thickness of the silicon oxide thin film is

[0013] In some embodiments, the ion implantation process includes multiple silicon ion implantations to fill the fill oxide regions in the shallow trenches of the substrate; the process parameters of the ion implantation include: the temperature is 25 °C to 50 °C, the implantation energy is 20 KeV to 70 KeV, and the implantation dose is 1×10^15 atom / cm 2 to 1×10^17 atom / cm 2 .

[0014] In some embodiments, the first annealing process includes:

[0015] Using a rapid thermal annealing process to combine the silicon ions and the oxygen ions formed by annealing; wherein, the process parameters of the rapid thermal annealing include: the annealing temperature is 1050 °C, and the annealing time is 10 seconds to 60 seconds;

[0016] Using a conventional annealing process to form a silicon-rich silicon oxide thin film; wherein, the process parameters of the conventional annealing include: the annealing temperature is 600 °C to 1050 °C, the annealing time is 10 minutes to 30 minutes, and the heating rate is 10 °C / min to 50 °C / min.

[0017] In some embodiments, the method for manufacturing a semiconductor device further includes:

[0018] Using an etching process to etch away the silicon-rich silicon oxide thin film located in the first well region and the second well region.

[0019] In some embodiments, the method for manufacturing a semiconductor device further includes:

[0020] Growing a nickel-platinum metal layer on the side of the silicon-rich silicon oxide thin film facing away from the substrate.

[0021] In some embodiments, the method for manufacturing a semiconductor device further includes:

[0022] Using a second annealing process to cause the nickel-platinum metal layer to react with the gate, source, and drain of the substrate to form a metal silicide as a barrier layer.

[0023] In some embodiments, the method for manufacturing a semiconductor device further includes:

[0024] Using an etching process to etch away the nickel-platinum metal layer that is not located in the first well region and the second well region.

[0025] In some embodiments, the substrate further includes:

[0026] A shallow trench isolation structure located between the first well region and the second well region;

[0027] A source electrode and a drain electrode, which are respectively located in the first well region and the second well region and are respectively located on both sides of each gate structure;

[0028] A sidewall located on the sidewall of the gate structure.

[0029] On the other hand, an embodiment of the present disclosure further provides a semiconductor device manufactured by the foregoing method. The semiconductor device includes:

[0030] A substrate including a substrate, a first well region, a second well region, a gate structure, a shallow trench isolation structure, a source electrode, a drain electrode, and a sidewall. The first well region is located on one side of the substrate and has a first type of conductivity. The second well region is located on the same side of the substrate as the first well region and has a second type of conductivity. The gate structure is respectively located on the side of the first well region and the second well region away from the substrate. The shallow trench isolation structure is located between the first well region and the second well region. The source electrode and the drain electrode are respectively located in the first well region and the second well region and are respectively located on both sides of each gate structure. The sidewall is located on the sidewall of the gate structure;

[0031] A silicon oxide thin film that is not located in the first well region and the second well region;

[0032] A metal silicide located on the side of the gate structure, the source electrode, and the drain electrode away from the substrate.

[0033] Compared with the prior art, the present disclosure has at least the following technical effects:

[0034] The method for manufacturing a semiconductor device and the semiconductor device of the present disclosure utilize the good step coverage of the sub-atmospheric pressure chemical vapor deposition process to form a silicon oxide thin film on one side surface of the substrate, and then use an ion implantation process to make the silicon oxide thin film form a silicon-rich silicon oxide thin film, thereby ensuring that no voids are formed when growing the silicon-rich silicon oxide thin film on the substrate surface, and avoiding affecting the subsequent dry etching process. Description of the Drawings

[0035] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0036] Figure 1 is a schematic diagram after etching a silicon-rich silicon oxide film of a semiconductor device in the related art;

[0037] Figure 2 is a schematic diagram before etching a silicon-rich silicon oxide film of a semiconductor device in the related art;

[0038] Figure 3 is a flowchart of steps of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;

[0039] Figure 4 is Figure 3 a schematic diagram of the semiconductor device after step S110 in ;

[0040] Figure 5 is Figure 3 a schematic diagram of the semiconductor device after step S120 in ;

[0041] Figure 6 is Figure 3 a schematic diagram of the semiconductor device after steps S130 and S140 in ;

[0042] Figure 7 is a flowchart of steps of another method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;

[0043] Figure 8 is Figure 7 a schematic diagram of the semiconductor device after step S150 in ;

[0044] Figure 9 is Figure 7 a schematic diagram of the semiconductor device after step S160 in ;

[0045] Figure 10 is Figure 7 a schematic diagram of the semiconductor device after steps S170 and S180 in.

[0046] Reference numerals:

[0047] 10 Substrate

[0048] 11 Substrate

[0049] 12 First well region

[0050] 13 The second well region

[0051] 14 The gate structure

[0052] 15 The shallow trench isolation structure

[0053] 16 The source electrode

[0054] 17 The drain electrode

[0055] 18 The sidewall

[0056] 20 The silicon oxide thin film

[0057] 30 The silicon-rich silicon oxide thin film

[0058] 40 The nickel-platinum metal layer

[0059] 50 The metal silicide

[0060] 60 The cavity Detailed implementation manners

[0061] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their repetitive description will be omitted.

[0062] The terms "first", "second", and the like used in the detailed description do not denote any order, quantity, or importance, but are merely used to distinguish different components. In addition, in the description of the present disclosure, the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for convenience of description and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0063] It should be noted that, without conflict, the features in the embodiments of the present disclosure and those in different embodiments can be combined with each other.

[0064] As Figure 1 shown, in the related art, in the manufacturing process of semiconductor devices, the self-aligned polysilicide blocking layer (SBK) process is a key technology for generating the blocking layer of semiconductor devices.

[0065] The SBK process grows a silicon-rich silicon oxide film 30 on the surface of the substrate 10, and then removes the silicon-rich silicon oxide film 30 in the region where the metal silicide 50 needs to be formed by dry etching. The regions where the metal silicide 50 does not need to be formed are not etched and are thus covered by the silicon-rich silicon oxide film 30. Among them, the substrate 10 includes a substrate 11, a first well region 12, a second well region 13, and a gate structure 14. The silicon-rich silicon oxide film 30 has higher density than the ordinary silicon oxide film and can effectively prevent metal ions from passing through the film to reach the underlying structure part.

[0066] As Figure 2 shown, however, as the semiconductor technology node continues to shrink, the spacing between the gate structures 14 of the polysilicon material gradually decreases. When the SBK process grows the silicon-rich silicon oxide film, voids 60 may appear between the sidewalls 18 of the gate structure 14 and the silicon-rich silicon oxide film 30, resulting in the inability to precisely control the subsequent dry etching process and further causing silicon damage.

[0067] In view of this, the present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device to at least solve the problem of voids 60 existing in the process of manufacturing the silicon-rich silicon oxide film in the prior art.

[0068] On the one hand, as Figures 3 to 6 shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including:

[0069] S110. Provide a substrate 10; wherein, the substrate 10 includes a substrate 11, a first well region 12, a second well region 13, and a gate structure 14. The first well region 12 is located on one side of the substrate 11 and has a first-type conductivity. The second well region 13 is located on the same side of the substrate 11 as the first well region 12 and has a second-type conductivity. The gate structures 14 are respectively located on the sides of the first well region 12 and the second well region 13 facing away from the substrate 11;

[0070] S120. Use a sub-atmospheric chemical vapor deposition process to grow a silicon oxide film 20 on one side of the substrate 10;

[0071] S130. Use an ion implantation process to implant silicon ions into the silicon oxide film 20;

[0072] S140. Use a first annealing process to make the silicon ions combine with the oxygen ions formed by annealing to form a silicon-rich silicon oxide film 30.

[0073] Specifically, the material of the substrate 11 can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium gallium, or doped semiconductor material. The first well region 12 can be formed by implanting pentavalent ions into a partial region of the substrate 11 to form an N well, and the second well region 13 can be formed by implanting trivalent ions into a partial region of the substrate 11 to form a P well. The material of the gate structure 14 can be polysilicon (Poly).

[0074] Specifically, the sub-atmospheric chemical vapor deposition (SACVD) process is a technique for depositing a thin film on the surface of the substrate 10 through a chemical reaction under conditions below atmospheric pressure. Compared with the self-aligned silicide barrier layer (SBK) process, the SACVD process has better thin film coverage and denseness, and is suitable for processes with a high filling ratio, such as the deposition of the silicon oxide thin film 20 between the shallow gate structures 14. The ion implantation process is a process of accelerating and implanting doping ions into the silicon oxide thin film 20, which is used to change the electrical properties of the silicon oxide thin film 20, and then form a silicon-rich silicon oxide thin film 30 through an annealing process subsequently. The annealing process is a heat treatment of the silicon oxide thin film 20 after ion implantation to activate the doping ions and form a silicon-rich silicon oxide thin film 30. The annealing process is usually divided into rapid thermal annealing (RTA) and conventional annealing.

[0075] In this embodiment, by utilizing the good step coverage of the sub-atmospheric chemical vapor deposition process, a silicon oxide thin film 20 is formed on one side surface of the substrate 10, and then the ion implantation process is used to make the silicon oxide thin film 20 form a silicon-rich silicon oxide thin film 30, so as to ensure that no voids 60 are formed when the silicon-rich silicon oxide thin film 30 grows on the surface of the substrate 10, and to avoid affecting the subsequent dry etching process.

[0076] In some embodiments, the process parameters of the sub-atmospheric chemical vapor deposition include: the reaction gas is ozone or tetraethyl orthosilicate gas, the deposition temperature is 400 °C; the thickness of the silicon oxide thin film 20 is The ozone in this embodiment has strong oxidizing properties and can promote the oxidation reaction of the silicon source; while TEOS is used as the silicon source and can decompose into silicon oxide under appropriate conditions. The combination of these two gases helps to form a uniform silicon oxide thin film 20 on the surface of the substrate 10. In this embodiment, at a temperature of 400 °C, the decomposition and chemical reaction rates of the reaction gas are moderate, which helps to form a dense and uniform silicon oxide thin film 20. The thickness of the silicon oxide thin film 20 in this embodiment can effectively prevent metal ions from penetrating into the lower device part. If the silicon oxide thin film 20 is too thin, it may not provide sufficient blocking effect, and if the silicon oxide thin film 20 is too thick, it may affect subsequent process steps, such as etching and metal deposition.

[0077] In some embodiments, the ion implantation process includes multiple silicon ion implantations to fill the filled oxide region in the shallow trench of the substrate 10; the process parameters of the ion implantation include: a temperature of 25°C to 50°C, an implantation energy of 20 keV to 70 keV, and an implantation dose of 1×10^15 atom / cm2 to 1×10^17 atom / cm2. In addition, the implantation depth of the ion implantation can be adjusted according to actual needs, and the present application does not limit this. In this embodiment, within this temperature range, the silicon ions can effectively penetrate the silicon oxide film 20 and enter the shallow trench region of the substrate 10. By adjusting the implantation energy, the distribution depth of the silicon ions can be precisely controlled to meet different process requirements. An appropriate implantation dose helps to form a uniform silicon-rich silicon oxide film 30. An excessively low dose may result in a discontinuous film, while an excessively high dose may cause lattice damage.

[0078] In some embodiments, the first annealing process includes: using a rapid thermal annealing process to combine the silicon ions with the oxygen ions formed during annealing; wherein, the process parameters of the rapid thermal annealing include: an annealing temperature of 1050°C and an annealing time of 10 seconds to 60 seconds; using a conventional annealing process to form a silicon-rich silicon oxide film 30; wherein, the process parameters of the conventional annealing include: an annealing temperature of 600°C to 1050°C, an annealing time of 10 minutes to 30 minutes, and a heating rate of 10°C / min to 50°C / min. Specifically, the first annealing process of this embodiment includes two parts: rapid thermal annealing (RTA) and conventional annealing. Among them, during the rapid thermal annealing process, at this high temperature, the silicon ions combine with the oxygen ions generated during annealing to form a silicon-rich silicon oxide film 30. Rapid thermal annealing can effectively repair the lattice damage generated during the ion implantation process and promote the activation of dopants. Conventional annealing helps to eliminate the stress in the material, improve the crystal structure, and further improve the reliability of the device. During the annealing process, the atoms inside the material are rearranged, the lattice defects are repaired, and the impurity atoms and dislocations in the material are arranged orderly, thereby improving the electrical performance and reliability of the semiconductor device.

[0079] In some embodiments, as Figure 7 and Figure 8 shown, the method for manufacturing a semiconductor device further includes:

[0080] S150. Using an etching process to etch away the silicon-rich silicon oxide film 30 located in the first well region 12 and the second well region 13.

[0081] In this step, an appropriate etching method is adopted to remove the silicon-rich silicon oxide film 30 located in the first well region 12 and the second well region 13. The etching process is generally divided into two types: dry etching and wet etching. In this embodiment, the dry etching process is adopted to ensure the high-precision and selective removal of the silicon-rich silicon oxide film 30, and to avoid affecting other regions. During the etching process, the etching time and conditions need to be precisely controlled to ensure that the etching depth and shape meet the design requirements. In addition, after etching, cleaning is required to remove the residual etchant to ensure the smooth progress of the subsequent process.

[0082] In some embodiments, such as Figure 7 and Figure 9 shown, the method for manufacturing a semiconductor device further includes:

[0083] S160. Grow a nickel-platinum metal layer 40 on the side of the silicon-rich silicon oxide film 30 facing away from the substrate 10.

[0084] In this step, first, a nickel-platinum metal layer 40 is grown on the side of the silicon-rich silicon oxide film 30 facing away from the substrate 10. The nickel-platinum metal layer 40 can be deposited by a magnetron sputtering process. Magnetron sputtering is a commonly used thin film deposition technology with a high deposition rate and good film uniformity. In this process, the nickel-platinum alloy target is excited to release nickel and platinum atoms, and these atoms are deposited on the surface of the substrate 10 in a vacuum environment to form the nickel-platinum metal layer 40. The thickness of this film can be about 10 nanometers.

[0085] In some embodiments, continuing to refer to Figure 7 , the method for manufacturing a semiconductor device further includes:

[0086] S170. Adopt a second annealing process to make the nickel-platinum metal layer 40 react with the gate, source 16, and drain 17 of the substrate 10 to form a metal silicide 50 as a barrier layer.

[0087] In this step, the nickel-platinum metal layer 40 undergoes an annealing treatment and reacts with the source 16 and drain 17 located in the first well region 12 and the second well region 13 around the gate structure 14 to form a metal silicide 50 as a barrier layer to prevent metal ions from penetrating into the lower device part. The second annealing process of this embodiment can be a rapid thermal annealing process.

[0088] In some embodiments, such as Figure 7 and Figure 10 shown, the method for manufacturing a semiconductor device further includes:

[0089] S180. Adopt an etching process to etch away the nickel-platinum metal layer 40 that is not located in the first well region 12 and the second well region 13.

[0090] In this embodiment, a dry etching process can be adopted to ensure the high-precision and selective removal of the nickel-platinum target metal layer, avoiding affecting other regions. The nickel-platinum metal layer 40 that is not located in the first well region 12 and the second well region 13 does not participate in the reaction and is an extra structure of the semiconductor device, so it needs to be etched.

[0091] In some embodiments, continuing to refer to Figure 10 , the substrate 10 further includes: a shallow trench isolation structure 15, a source electrode 16, a drain electrode 17, and sidewalls 18. The shallow trench isolation structure 15 is located between the first well region 12 and the second well region 13; the source electrode 16 and the drain electrode 17 are respectively located in the first well region 12 and the second well region 13 and are respectively located on both sides of each gate structure 14; the sidewalls 18 are located on the sidewalls of the gate structure 14. Specifically, the source electrode 16 and the drain electrode 17 can be formed by performing P+ ion doping on the first well region 12 and N+ ion doping on the second well region 13. The sidewalls 18 can be formed by performing pre-cleaning, sintering, and etching on the sidewalls of the gate structure 14.

[0092] On the other hand, continuing to refer to Figure 10 , an embodiment of the present disclosure also provides a semiconductor device prepared by the foregoing method. The semiconductor device includes:

[0093] A substrate 10, the substrate 10 includes a substrate 11, a first well region 12, a second well region 13, a gate structure 14, a shallow trench isolation structure 15, a source electrode 16, a drain electrode 17, and sidewalls 18. The first well region 12 is located on one side of the substrate 11, the first well region 12 has a first type of conductivity, the second well region 13 is located on the same side of the substrate 11 as the first well region 12, the second well region 13 has a second type of conductivity, the gate structure 14 is respectively located on the side of the first well region 12 and the second well region 13 facing away from the substrate 11, the shallow trench isolation structure 15 is located between the first well region 12 and the second well region 13, the source electrode 16 and the drain electrode 17 are respectively located in the first well region 12 and the second well region 13 and are respectively located on both sides of each gate structure 14, and the sidewalls 18 are located on the sidewalls of the gate structure 14;

[0094] A silicon oxide thin film 20, the silicon oxide thin film 20 is not located in the first well region 12 and the second well region 13;

[0095] A metal silicide 50, the metal silicide 50 is respectively located on the side of the gate structure 14, the source electrode 16, and the drain electrode 17 facing away from the substrate 11.

[0096] For the semiconductor device of the present disclosure, its specific implementation manners and technical effects can refer to the embodiments of the foregoing method for preparing a semiconductor device, which will not be elaborated here.

[0097] In summary, in the method for manufacturing a semiconductor device and the semiconductor device of the present disclosure, by utilizing the good step coverage of the sub-atmospheric pressure chemical vapor deposition process, a silicon oxide film is formed on one side surface of the substrate, and then an ion implantation process is used to make the silicon oxide film into a silicon-rich silicon oxide film, thereby ensuring that voids will not be formed when the silicon-rich silicon oxide film is grown on the substrate surface, and avoiding affecting the subsequent dry etching process.

[0098] The above content is a further detailed description of the present disclosure in combination with specific optional implementation manners. It cannot be determined that the specific implementation of the present disclosure is only limited to these descriptions. For those of ordinary skill in the technical field to which the present disclosure pertains, without departing from the concept of the present disclosure, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A substrate is provided; wherein the substrate comprises a substrate, a first well region, a second well region and a gate structure, wherein the first well region is located at one side of the substrate, the first well region has a first type of conductivity, the second well region and the first well region are located at the same side of the substrate, the second well region has a second type of conductivity, and the gate structure is respectively located at a side of the first well region and the second well region away from the substrate; Using a sub-atmospheric pressure chemical vapor deposition process, a silicon oxide film is grown on a side of the gate structure away from the substrate; Using an ion implantation process, silicon ions are implanted into the silicon oxide film; A first annealing process is adopted to combine the silicon ions with the oxygen ions formed by annealing to form a silicon-rich silicon oxide film.

2. The method for preparing a semiconductor device according to claim 1, wherein: The process parameters of sub-atmospheric pressure chemical vapor deposition include: the reaction gas is ozone or tetraethoxysilane gas, and the deposition temperature is 400°C; The thickness of the silicon oxide film is 3. The method for preparing a semiconductor device according to claim 1, characterized in that: The ion implantation process includes multiple silicon ion implantations to fill the oxide filling region in the shallow trench of the substrate; The process parameters of ion implantation include: temperature 25℃ to 50℃, implantation energy 20KeV to 70KeV, and implantation dose 1×10^15atom / cm 2 To 1×10^17atom / cm 2 .

4. The method for preparing a semiconductor device according to claim 1, wherein: The first annealing process comprises: A rapid thermal annealing process is used to combine the silicon ions with the oxygen ions formed by annealing; wherein the process parameters of the rapid thermal annealing include: an annealing temperature of 1050° C. and an annealing time of 10 seconds to 60 seconds; A conventional annealing process is used to form a silicon-rich silicon oxide film; wherein the process parameters of the conventional annealing include: an annealing temperature of 600° C. to 1050° C., an annealing time of 10 minutes to 30 minutes, and a heating rate of 10° C. / min to 50° C. / min.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: Also includes: The silicon-rich silicon oxide film located in the first well region and the second well region is etched away by an etching process.

6. The method for preparing a semiconductor device according to claim 1, wherein: Also includes: A nickel-platinum metal layer is grown on the side of the silicon-rich silicon oxide film facing away from the substrate.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: Also includes: A second annealing process is used to react the nickel-platinum metal layer with the gate, source and drain of the substrate to form metal silicide as a barrier layer.

8. The method for preparing a semiconductor device according to claim 6, characterized in that: Also includes: The nickel-platinum metal layer not located in the first well region and the second well region is etched away by an etching process.

9. The method for preparing a semiconductor device according to claim 1, wherein: The substrate further comprises: A shallow trench isolation structure, wherein the shallow trench isolation structure is located between the first well region and the second well region; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively located in the first well region and the second well region, and are respectively located on two sides of each of the gate structures; A sidewall is located on a sidewall of the gate structure.

10. A semiconductor device, characterized in that: Prepared by the method according to any one of claims 1 to 9; the semiconductor device comprises: A substrate, the substrate comprising a substrate, a first well region, a second well region, a gate structure, a shallow trench isolation structure, a source, a drain and a sidewall, the first well region is located at one side of the substrate, the first well region has a first type of conductivity, the second well region and the first well region are located on the same side of the substrate, the second well region has a second type of conductivity, the gate structure is respectively located at a side of the first well region and the second well region away from the substrate, the shallow trench isolation structure is located between the first well region and the second well region, the source and the drain are respectively located in the first well region and the second well region, and are respectively located at both sides of each of the gate structures, and the sidewall is located at a sidewall of the gate structure; a silicon oxide film, wherein the silicon oxide film is not located in the first well region and the second well region; Metal silicide, wherein the metal silicide is respectively located at a side of the gate structure, the source and the drain away from the substrate.

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