Back contact photovoltaic cell, preparation method thereof and cell assembly

Abstract

The invention discloses a back contact photovoltaic cell, a preparation method thereof and a cell assembly, and relates to the technical field of photovoltaic cells. The problem that the preparation technology of the back contact photovoltaic cell is complex is solved. The preparation method of the back contact photovoltaic cell comprises the following steps: preparing a first oxide layer, a first intrinsic crystalline silicon layer, a second oxide layer and a second intrinsic crystalline silicon layer which are laminated on a silicon substrate from inside to outside, wherein the first oxide layer is a tunneling oxide layer; and doping the second intrinsic crystalline silicon layer and forming a first doped oxide layer. And removing the first doped oxide layer of at least the second polar region by laser. And removing at least the second intrinsic crystalline silicon layer and the second oxide layer in the second polarity region. The first polarity region is provided with a first doped crystalline silicon layer on the inner side of the first doped oxide layer. And preparing a second doped oxide layer on the outer side of the first intrinsic crystalline silicon layer in the second polarity region, and propelling a doping source of the second doped oxide layer to the first intrinsic crystalline silicon layer to form a second doped crystalline silicon layer.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic cells, and in particular, to a back-contact photovoltaic cell, a preparation method thereof, and a battery module. Background Art

[0002] A back-contact photovoltaic cell refers to a photovoltaic cell in which both the emitter and the metal contact are located on the back surface of the cell, and there is no metal electrode shielding on the front surface. Since the front surface of the back-contact photovoltaic cell is not shielded by the emitter and the metal grid lines, compared with a photovoltaic cell with shielding on the front surface, the back-contact cell has a larger light-receiving area, thereby reducing light loss and improving the photoelectric conversion efficiency.

[0003] However, due to the poor passivation contact performance of the back-contact photovoltaic cell, it is necessary to optimize the passivation contact performance of the back-contact photovoltaic cell through the tunneling oxide passivation contact technology to further improve the photoelectric conversion efficiency.

[0004] Thus, since both the positive and negative electrodes are located on the back surface of the cell, the back surface of the cell is alternately provided with two different types of doped regions, and a complex structure such as a tunneling oxide layer is also provided on the back surface of the cell, resulting in a relatively complex preparation process for the back-contact photovoltaic cell applying the tunneling oxide passivation contact technology. Summary of the Invention

[0005] In view of this, the present application provides a back-contact photovoltaic cell, a preparation method thereof, and a battery module to solve the problem of the relatively complex preparation process of the back-contact photovoltaic cell.

[0006] In a first aspect, the present application provides a preparation method for a back-contact photovoltaic cell, including:

[0007] Providing a silicon substrate, the silicon substrate includes a first surface and a second surface disposed opposite to each other, and the first surface includes a first polar region and a second polar region.

[0008] At least on the first surface, a first oxide layer, a first intrinsic silicon layer, a second oxide layer, and a second intrinsic silicon layer are prepared to be stacked from inside to outside, and the first oxide layer is a tunneling oxide layer.

[0009] Doping the second intrinsic silicon layer on the first surface, and forming a first doped oxide layer outside the doped second intrinsic silicon layer.

[0010] Removing at least the first doped oxide layer in the second polar region by laser.

[0011] Removing at least the second intrinsic silicon layer and the second oxide layer in the second polar region.

[0012] A first doped crystalline silicon layer is formed inside the first doped oxide layer in the first polarity region. A second doped oxide layer is prepared outside the first intrinsic crystalline silicon layer in the second polarity region, and the doping source of the second doped oxide layer is pushed into the first intrinsic crystalline silicon layer to form a second doped crystalline silicon layer. The doping type of the first doped crystalline silicon layer is opposite to that of the second doped crystalline silicon layer.

[0013] Advantageous effects: Through the above preparation steps, a photovoltaic cell structure including a tunneling oxide layer (i.e., the first oxide layer), a first doped crystalline silicon layer, and a second doped crystalline silicon layer can be formed on the first side of the silicon substrate, serving as the basic structure of a photovoltaic cell including the tunneling oxide layer passivation contact technology and the full back electrode contact technology. It can achieve efficient passivation by depositing an ultra-thin oxide layer and a doped polysilicon layer on the silicon wafer surface, significantly reducing the recombination of carriers on the surface, thereby increasing the open-circuit voltage and fill factor. Moreover, it can make the front side (i.e., the second side) of the photovoltaic cell free from electrode obstruction, thus maximizing the use of the light-receiving area and reducing optical losses. It has advantages such as high conversion efficiency, low temperature coefficient, long lifespan, and low attenuation.

[0014] Compared with the preparation steps in the related technology that involve two low-pressure chemical vapor depositions of amorphous silicon and two doping source diffusions. In the solution of this application, by using at least part of the outer second oxide layer and the second intrinsic crystalline silicon layer as sacrificial layers, and using the first doped oxide layer as an etching barrier layer, the two-step doping preparation of the first doped crystalline silicon layer and the second doped crystalline silicon layer is realized. In this way, during the film deposition process, only the formation of the first oxide layer, the first intrinsic crystalline silicon layer, the second oxide layer, and the second intrinsic crystalline silicon layer is required, without performing the film deposition process for the preparation of the first doped crystalline silicon layer and the second doped crystalline silicon layer in multiple steps. This is beneficial for simplifying the overall process preparation flow and shortening the overall process time, and can also avoid problems such as leakage caused during the secondary deposition of stacked film layers.

[0015] In a second aspect, the present application provides a back-contact photovoltaic cell, which is prepared by the preparation method in the first side.

[0016] Advantageous effects: Since the back-contact photovoltaic cell in the second aspect is prepared by the preparation method of the back-contact photovoltaic cell in the first aspect, this back-contact photovoltaic cell has all the advantageous effects of the above-mentioned preparation method of the back-contact photovoltaic cell, which will not be elaborated here.

[0017] In a third aspect, the present application provides a battery module, including a plurality of back-contact photovoltaic cells in the second aspect, and the plurality of back-contact photovoltaic cells are electrically connected.

[0018] Advantageous effects: Since the photovoltaic module in the third aspect includes the back-contact photovoltaic cell in the second aspect, this photovoltaic module has all the advantageous effects of the above-mentioned back-contact photovoltaic cell, which will not be elaborated here. Brief Description of the Drawings

[0019] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the disclosed drawings.

[0020] Figure 1 It is the first - part flowchart of the preparation method of the back - contact photovoltaic cell provided by the embodiment of the present application;

[0021] Figure 2 It is a partial structural cross - sectional view during the preparation process of the back - contact photovoltaic cell provided by the embodiment of the present application;

[0022] Figure 3 It is a partial cross - sectional structural view obtained after the treatment of step S400 provided by the embodiment of the present application;

[0023] Figure 4 It is a partial cross - sectional structural view obtained after the treatment of step S500 provided by the embodiment of the present application;

[0024] Figure 5 It is a partial cross - sectional structural view obtained after the treatment of step S600 provided by the embodiment of the present application;

[0025] Figure 6 It is the second - part flowchart of the preparation method of the back - contact photovoltaic cell provided by the embodiment of the present application;

[0026] Figure 7 It is a partial cross - sectional structural view obtained after the treatment of step S700 provided by the embodiment of the present application;

[0027] Figure 8 It is a partial cross - sectional structural view obtained after the treatment of steps S810 to S830 provided by the embodiment of the present application;

[0028] Figure 9 It is a partial cross - sectional structural view obtained after the treatment of step S910 provided by the embodiment of the present application;

[0029] Figure 10 It is a partial cross - sectional structural view obtained after the treatment of step S920 provided by the embodiment of the present application;

[0030] Figure 11 It is a partial cross - sectional structural view obtained after the treatment of step S300 provided by the embodiment of the present application;

[0031] Figure 12It is a flowchart of step S600 in the preparation method of the back-contact photovoltaic cell provided by the embodiment of the present application;

[0032] Figure 13 It is another partial cross-sectional structure schematic diagram obtained after the treatment of step S600 provided by the embodiment of the present application;

[0033] Figure 14 It is another partial cross-sectional structure schematic diagram obtained after the treatment of steps S810 to S830 provided by the embodiment of the present application;

[0034] Figure 15 It is another partial cross-sectional structure schematic diagram obtained after the treatment of step S920 provided by the embodiment of the present application;

[0035] Figure 16 It is a cross-sectional structure schematic diagram of a photovoltaic module provided by the embodiment of the present application.

[0036] Explanation of reference numerals:

[0037] 1000, photovoltaic module;

[0038] 100, back-contact photovoltaic cell;

[0039] 1, silicon substrate; 2, first oxide layer; 3, first intrinsic crystalline silicon layer; 4, second oxide layer; 5, second intrinsic crystalline silicon layer; 6, first doped oxide layer; 7, second doped oxide layer; 8, first doped crystalline silicon layer; 9, second doped crystalline silicon layer; 10, passivation film; 11, antireflection film; 12, first electrode; 13, second electrode. Detailed implementation manners

[0040] To make the purpose and implementation manners of the present application clearer, the following will clearly and completely describe the exemplary implementation manners of the present application with reference to the accompanying drawings in the exemplary embodiments of the present application.

[0041] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further explanations for the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0042] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "include" and / or "comprise" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or their combinations.

[0043] It should be noted that the terms "first", "second", etc. in the description, claims, and above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so as to implement the embodiments of this application described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0044] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or there can also be an intermediate element. Moreover, in the description and claims, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0045] Currently, the preparation route of a back-contact battery with a tunneling oxide passivation contact structure includes process steps such as low-pressure chemical vapor deposition of amorphous silicon, boron diffusion, laser opening, wet etching and cleaning, low-pressure chemical vapor deposition of amorphous silicon, phosphorus diffusion, laser opening, and wet etching and cleaning.

[0046] In the process of preparing the battery through the above processes, it is necessary to perform low-pressure chemical vapor deposition of amorphous silicon twice and two diffusions (i.e., boron diffusion and phosphorus diffusion). The process steps are cumbersome, resulting in a low preparation speed and a low finished product yield of the battery.

[0047] To solve the problem that the preparation process of the back-contact photovoltaic battery is relatively complex. The embodiments of this application provide a back-contact photovoltaic battery, its preparation method, and a battery module.

[0048] The following will combine the attached Figure 1 to the attached Figure 16 to clearly and completely describe the technical solutions in the embodiments of this application.

[0049] In the first aspect, the embodiments of this application provide a preparation method for a back-contact photovoltaic battery, Figure 1 which shows a schematic main flow chart of the preparation method of the back-contact photovoltaic battery. Figures 2 to 5 which shows a schematic diagram of the partial structure on which each process included in the preparation method depends or the partial structure obtained by each process. As Figure 1 shown, the preparation method of the back-contact photovoltaic battery includes the following steps:

[0050] Step S100: Provide a silicon substrate 1, which has a first surface and a second surface arranged opposite to each other, and the first surface has a first polar region and a second polar region.

[0051] The silicon substrate can be a P-type silicon substrate or an N-type silicon substrate.

[0052] In step S100, as Figure 2 shown, it is also possible to polish the first surface and the second surface of the silicon substrate 1 to make the main surface of the silicon substrate 1 flat. Taking the first surface of the silicon substrate 1 as the back surface as an example, only the first surface can be polished, or both surfaces can be polished simultaneously, and this is not limited.

[0053] Among them, on the back surface (i.e., the first surface) of the silicon substrate 1, a P+ crystalline silicon layer and an N+ crystalline silicon layer need to be prepared in different regions, that is, the P region and the N region of the photovoltaic cell are arranged on the first surface of the silicon substrate 1. The first polar region and the second polar region in the first surface are not originally existing region separations, but are positions for setting the P+ crystalline silicon layer (such as the P region) and the N+ crystalline silicon layer (such as the N region) in subsequent steps.

[0054] Step S200: At least on the first surface of the silicon substrate, sequentially prepare a first oxide layer 2, a first intrinsic crystalline silicon layer 3, a second oxide layer 4, and a second intrinsic crystalline silicon layer 5 which are stacked from inside to outside, and the first oxide layer 2 is a tunneling oxide layer.

[0055] In step S200, one or more deposition methods such as Low-pressure Chemical Vapor Deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), Physical Vapor Deposition (PVD), and atomic layer deposition (ALD) can be used to form Figure 2 the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 as shown.

[0056] Among them, the deposited first oxide layer 2 is a tunneling oxide layer to provide excellent surface passivation effect. The first oxide layer 2 can effectively reduce the density of defect states on the surface of the silicon substrate 1 to reduce the recombination rate of carriers on the surface, thereby being beneficial to improving the open-circuit voltage and conversion efficiency of the battery. The first oxide layer 2 is generally a silicon oxide deposition layer.

[0057] Taking the preparation of the first oxide layer 2 by low-pressure chemical vapor deposition as an example. Oxygen is introduced at a high temperature of 600 - 700 °C to oxidize the surface of the silicon substrate 1 and form the first oxide layer 2. By controlling the reaction time between 10 - 20 min, the deposition thickness of the first oxide layer 2 can be 1 - 2 nm, such as 1 nm, 1.2 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.8 nm, or 2 nm.

[0058] The first intrinsic crystalline silicon layer 3 can be a polycrystalline silicon structure, or an amorphous silicon or microcrystalline silicon structure, etc. Taking the first intrinsic crystalline silicon layer 3 being a polycrystalline silicon structure as an example, during the preparation of the first intrinsic crystalline silicon layer 3 by low-pressure chemical vapor deposition, by controlling the deposition temperature at 510 - 610 °C and the deposition time at 1200 - 2400 s, the deposition thickness of the first intrinsic crystalline silicon layer 3 is 50 - 300 nm.

[0059] Similarly, on the outer side of the first intrinsic crystalline silicon layer 3 away from the silicon substrate 1, the second oxide layer 4 is continuously deposited. The second oxide layer 4 can also be prepared by low-pressure chemical vapor deposition. Just adjust the oxidation temperature to 600 - 700 °C, the thickness of the second oxide layer 4 is 1 - 5 nm, and control the oxidation time at 10 - 35 min to make the deposition thickness of the second oxide layer 4 be 1 - 5 nm.

[0060] Correspondingly, on the outer side of the second oxide layer 4 away from the silicon substrate 1, the second intrinsic crystalline silicon layer 5 can be prepared by low-pressure chemical vapor deposition. By controlling the deposition temperature at 600 - 700 °C and the deposition time at 1200 - 2400 s, the deposition thickness of the second intrinsic crystalline silicon layer 5 is 50 - 200 nm.

[0061] It should be noted that in step S200, as Figure 2 shown, the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 arranged in layers can be prepared synchronously on the first side and the second side of the silicon substrate 1. For example, the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 are distributed on the first side and the second side of the silicon substrate 1 from the inside out in sequence.

[0062] Or, the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 arranged in layers can also be prepared on the first side of the silicon substrate 1.

[0063] Step S300: Dope the second intrinsic crystalline silicon layer 5 on the first side, and prepare the first doped oxide layer 6 on the outside of the doped second intrinsic crystalline silicon layer 5.

[0064] In the embodiments of the present application, the distinction between the inner and outer sides of the film layer refers to that, along the stacking direction of multiple film layers, the side close to the silicon substrate 1 is the inner side, and the side far from the silicon substrate 1 is the outer side.

[0065] Among them, as Figure 3 shown, the doping source type of the first doped oxide layer 6 can be opposite to that of the silicon substrate 1. For example, if the silicon substrate 1 is an N-type substrate, the doping source of the first doped oxide layer 6 is boron. This is beneficial to form a P-N junction to achieve efficient carrier separation and transport, reduce recombination loss and optimize the process flow.

[0066] Exemplarily, a patterned local hollow plate CVD (Chemical Vapor Deposition) process can be adopted to perform boron doping on the second intrinsic crystalline silicon layer 5 in the first polar region of the silicon wafer. To form a first doped crystalline silicon layer (such as a boron-doped polysilicon layer) and a first doped oxide layer 6 (such as a borosilicate glass layer).

[0067] Alternatively, boron doping can also be directly performed on the second intrinsic crystalline silicon layer 5 on the first side. It is only necessary to remove the first doped oxide layer 6, the second intrinsic crystalline silicon layer 5 and the second oxide layer 4 in the second polar region in steps S400 and S500. This is beneficial to simplify the preparation process of step S300.

[0068] In the process of preparing the first doped oxide layer 6 and the first doped crystalline silicon layer, by introducing an appropriate flow rate of boron source and controlling the preparation temperature at 840 - 850 °C, a borosilicate glass layer (i.e., the first doped oxide layer 6) is formed.

[0069] After forming the first doped oxide layer 6, the push temperature can also be controlled at 880 - 920 °C, and the push time of the doping source in the first doped oxide layer 6 can be controlled at 8 - 12 min to dope the second intrinsic crystalline silicon layer 5 inside the first doped oxide layer 6, so as to form a first doped crystalline silicon layer on the outside of the second oxide layer 4.

[0070] For example, the push temperature of the first doped crystalline silicon layer can be 900 °C, and the push duration can be 10 min.

[0071] It should be noted that the first doped crystalline silicon layer can be prepared in step S300, or can also be prepared in step S600. It is also possible to further increase the doping degree and depth of the first doped crystalline silicon layer through step S600 after preparing the first doped crystalline silicon layer in step S300, and no limitation is made in this regard.

[0072] Step S400: Remove at least the first doped oxide layer in the second polar region by laser.

[0073] Among them, the first polar region and the second polar region are respectively used to prepare the P region and the N region of the back-contact photovoltaic cell. Taking the doping source of the first doped oxide layer 6 as phosphorus element as an example, the first polar region is used to form the first doped crystalline silicon layer, which is the P region. The second polar region is used to form the second doped crystalline silicon layer, which is the N region.

[0074] Exemplarily, as Figure 3 shown, the first doped oxide layer 6 in the corresponding region can be removed by laser irradiation, so that the region where the first doped oxide layer 6 is removed serves as the second polar region, and the other regions where the first doped oxide layer 6 is retained serve as the first polar region.

[0075] Removing the first doped oxide layer 6 (i.e., the borosilicate glass layer) in the second polar region by laser is beneficial to the cleaning treatment of the second intrinsic crystalline silicon layer and the second oxide layer inside the first doped oxide layer 6 in subsequent steps.

[0076] Step S500: Remove the second intrinsic crystalline silicon layer and the second oxide layer in at least the second polar region.

[0077] As Figure 4 shown, the second intrinsic crystalline silicon layer 5 and the second oxide layer 4 can be removed by means of alkaline solution polishing or laser cleaning, so as to facilitate the doping of the first intrinsic crystalline silicon layer 3 exposed in the second polar region. Among them, the second intrinsic crystalline silicon layer that is partially doped in step S300 can also be regarded as the film layer part of the removed second intrinsic crystalline silicon layer 5.

[0078] Among them, as Figure 2 shown, if the second side of the silicon substrate 1 is deposited with a first oxide layer 2, a first intrinsic crystalline silicon layer 3, a second oxide layer 4, and a second intrinsic crystalline silicon layer 5 from the inside out. In step S500, the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 on the second side can be cleaned to remove the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 until the second side of the silicon substrate 1 is exposed. For example, it can be removed by means of alkaline solution polishing or laser irradiation cleaning.

[0079] Step S600: A first doped crystalline silicon layer 8 is formed inside the first doped oxide layer 6 in the first polar region. A second doped oxide layer 7 is prepared outside the first intrinsic crystalline silicon layer 3 in the second polar region, and the doping source of the second doped oxide layer 7 is pushed into the first intrinsic crystalline silicon layer 3 to form a second doped crystalline silicon layer 9. The doping type of the first doped crystalline silicon layer 8 is opposite to that of the second doped crystalline silicon layer 9.

[0080] As Figure 4As shown, in the first surface of the silicon substrate 1, the region where the second oxide layer 4, the second intrinsic crystalline silicon layer 5, and the first doped oxide layer 6 exist is the first polarity region. The region where the second oxide layer 4, the second intrinsic crystalline silicon layer 5, and the first doped oxide layer 6 are removed is the second polarity region.

[0081] The first polarity region and the second polarity region can be arranged in a finger-like cross pattern, so that the P region and the N region are alternately arranged on the first surface, thereby forming an interdigitated structure. Or, the first polarity region and the second polarity region can also be distributed in other shapes, so that the P region and the N region are alternately arranged on the first surface, and no limitation is imposed on this.

[0082] In this way, combined Figure 4 and Figure 5 , in the first polarity region, by controlling the advancement of the doping source in the first doped oxide layer 6, a first doped crystalline silicon layer 8 is formed inside the first doped oxide layer 6. Taking the doping element of the first doped crystalline silicon layer 8 as boron element as an example, Figure 5 The first doped crystalline silicon layer 8 shown is the P region, generally a boron-doped polysilicon layer.

[0083] Among them, controlling the advancement of the doping source (such as boron element) in the first doped oxide layer 6 to form the first doped crystalline silicon layer 8 or deepen the doping degree of the first doped crystalline silicon layer 8 can be carried out in at least one of step S300 and step S600.

[0084] Then, doping is carried out on the outside of the first intrinsic crystalline silicon layer 3 exposed in the second polarity region to form a second doped oxide layer 7. In this process, taking the doping source as phosphorus element as an example, a suitable flow rate of phosphorus source is introduced, and the preparation temperature is controlled at 830 - 850 °C (such as the preparation temperature is 840 °C) to form a second doped oxide layer 7 (i.e., phosphosilicate glass) on the outside of the first intrinsic crystalline silicon layer 3.

[0085] Subsequently, the temperature is increased so that the advancement temperature is 880 - 900 °C, and the advancement time of the doping source in the second doped oxide layer 7 is controlled for 15 - 25 min. So that the doping source (such as phosphorus element) in the second doped oxide layer 7 advances to the first intrinsic crystalline silicon layer 3 to form Figure 5 the second doped crystalline silicon layer 9 shown.

[0086] Taking the doping element of the second doped crystalline silicon layer 9 as phosphorus element as an example, Figure 5 the second doped crystalline silicon layer 9 shown is the N region, generally a phosphorus-doped polysilicon layer.

[0087] Thus, in the preparation method provided by the solution of the present application, through the above preparation steps, a photovoltaic cell structure including a tunneling oxide layer (i.e., the first oxide layer 2), a first doped crystalline silicon layer 8, and a second doped crystalline silicon layer 9 can be formed on the first side of the silicon substrate 1, so as to serve as the basic structure of a photovoltaic cell including the tunneling oxide layer passivation contact technology and the full back electrode contact technology. It is possible to achieve high-efficiency passivation by depositing an ultra-thin oxide layer and a doped polysilicon layer on the silicon wafer surface, significantly reducing the recombination of carriers on the surface, thereby increasing the open-circuit voltage and the fill factor; it is also possible to ensure that there is no electrode obstruction on the front side (i.e., the second side) of the photovoltaic cell, thus maximizing the use of the illumination area and reducing optical losses. It has the advantages of high conversion efficiency, low temperature coefficient, long lifespan, and low attenuation, etc.

[0088] Compared with the preparation steps of depositing amorphous silicon by low-pressure chemical vapor deposition twice and doping source diffusion twice in the related art. In the preparation steps of the present application, the outer second oxide layer 4 and the second intrinsic crystalline silicon layer 5 are used as sacrificial layers through step S400 and step S500, and the first doped oxide layer 6 is used as an etching stop layer to achieve the two-time doping preparation of the first doped crystalline silicon layer 8 and the second doped crystalline silicon layer 9. In this way, only the film layer deposition needs to be performed in step S100 to form the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5, without performing the film layer deposition process for the preparation of the first doped crystalline silicon layer 8 and the second doped crystalline silicon layer 9 in multiple steps. It is beneficial to simplify the overall process preparation flow and shorten the overall process time, and it can also avoid problems such as leakage caused during the secondary deposition of stacked film layers.

[0089] As Figure 6 shown, after step S600, the preparation method further includes:

[0090] Step S700: Remove at least the second doped oxide layer 7 and the first doped oxide layer 6 in the electrical isolation region through laser, and the electrical isolation region is located between the first polarity region and the second polarity region.

[0091] Step S810: Remove the film layer in the electrical isolation region and clean it until the silicon substrate 1 is exposed.

[0092] Step S820: Remove the first doped oxide layer 6 and the second doped oxide layer 7 and clean them.

[0093] Step S830: Prepare a textured structure on at least the second side of the silicon substrate.

[0094] The electrical isolation region is located between the first polarity region and the second polarity region, and is used to physically separate the first polarity region (such as the first doped crystalline silicon layer 8) and the second polarity region (such as the second doped crystalline silicon layer 9). While preventing short circuits, the setting of the electrical isolation region can reduce the recombination of carriers at the junction of the P region (such as the first polarity region) and the N region (such as the first polarity region), thereby improving the conversion efficiency of the battery.

[0095] such as Figure 7 and Figure 8 As shown, since only the second doped oxide layer 7 and the first doped oxide layer 6 of the electrical isolation region are removed, in the cleaning process of step S810, cleaning agents such as alkaline solutions can be avoided from removing film layers such as the first doped crystalline silicon layer 8 and the second doped crystalline silicon layer 9 of the first polarity region and the second polarity region. Subsequently, step S820 also removes the remaining first doped oxide layer 6 and second doped oxide layer 7 by laser, so as to facilitate the subsequent deposition of a passivation film and an antireflection film on the outer sides of the first doped crystalline silicon layer 8 and the second doped crystalline silicon layer 9. Finally, step S830 fabricates a textured structure on the first side of the silicon substrate 1, which is beneficial to reducing the reflection of sunlight on the second side of the photovoltaic cell.

[0096] Continuing to refer to Figure 6 , after step S830, the preparation method further includes:

[0097] Step S910: Prepare a passivation film 10 and an antireflection film 11 stacked on both sides of the silicon substrate 1.

[0098] Step S920: Prepare a first electrode 12 connected to the first doped crystalline silicon layer 8 and a second electrode 13 connected to the second doped crystalline silicon layer 9.

[0099] such as Figure 9 As shown, the combined use of the passivation film 10 and the antireflection film 11 can significantly improve the overall performance of the photovoltaic cell. The passivation film 10 can reduce the recombination loss of carriers, while the antireflection film 11 in combination with the textured structure can further increase the light absorption efficiency. The synergistic effect of the two enables the photovoltaic cell to improve the conversion efficiency while maintaining high stability and reliability.

[0100] In the process of preparing the passivation film 10 and the antireflection film 11 in step S910, the electrical isolation region is also formed with a passivation film 10 and an antireflection film 11 stacked from the inside out, further improving the electrical isolation effect between the first polarity region and the second polarity region.

[0101] such as Figure 10As shown, the first electrode 12 and the second electrode are prepared on the first side through step S920, so that the first electrode 12 is connected to the first doped crystalline silicon layer 8, and the second electrode 13 is connected to the second doped crystalline silicon layer 9. Good ohmic contact can be achieved by forming silver microcrystals of the first electrode 12 and the second electrode within the passivation film 10. These silver microcrystals can penetrate the passivation film 10 to form a stable contact while reducing the contact resistance.

[0102] In some embodiments, step S300 further includes:

[0103] Advance the dopant source located in the first doped oxide layer 6 to the second intrinsic crystalline silicon layer 5 to form a first doped crystalline silicon layer 8 on the outer side of the second oxide layer 4.

[0104] Combined Figure 2 and Figure 11 , after forming the first doped oxide layer 6, the dopant source within the first doped oxide layer 6 can be continuously advanced inward, so that the first doped crystalline silicon layer 8 is formed in the second intrinsic crystalline silicon layer 5 between the first doped oxide layer 6 and the second oxide layer 4.

[0105] For example, after forming the first doped oxide layer 6, control the advancing temperature to 900 °C and control the advancing time of the dopant source in the first doped oxide layer 6 to 10 min to dope the second intrinsic crystalline silicon layer 5 on the inner side of the first doped oxide layer 6 to form a first doped crystalline silicon layer 8 on the outer side of the second oxide layer 4.

[0106] Subsequently, in steps S400 and S500, the first doped oxide layer 6 and the first doped crystalline silicon layer 8 in the second polar region can be removed to facilitate the preparation of the second doped crystalline silicon layer in the polar region.

[0107] Based on this, as Figure 12 shown, step S600 further includes:

[0108] Step S610: Advance the dopant source of the first doped oxide layer 6 at least to the second intrinsic crystalline silicon layer 5 to form at least a first doped crystalline silicon layer 8 on the outer side of the second oxide layer 4.

[0109] Taking the dopant source as boron element as an example, the second oxide layer 4 and the first doped crystalline silicon layer 8 are the P region of the photovoltaic cell. The prepared thickness of the second oxide layer 4 can be 1 - 2 nm to ensure the tunneling efficiency. The thickness of the second intrinsic crystalline silicon layer 5 can be 100 - 200 nm, and control the speed and deposition quality of the second intrinsic crystalline silicon layer 5 during the deposition process, so that the formed first doped crystalline silicon layer 8 has better film quality.

[0110] Step S620: Prepare a second doped oxide layer 7 outside the first intrinsic crystalline silicon layer 3 in the second polar region, and push the doping source of the second doped oxide layer 7 into the first intrinsic crystalline silicon layer 3 to form a second doped crystalline silicon layer 9.

[0111] In this way, referring to Figure 5 , through step S610 and step S620, the basic structures of the P region and the N region can be prepared and formed on the first surface of the photovoltaic cell.

[0112] Among them, in step S610, the pushing temperature can also be controlled at 950 - 970 °C, and the pushing time of the doping source in the first doped oxide layer 6 can be controlled at 25 - 35 min.

[0113] For example, through the above process, the first doping step S610 further includes:

[0114] Push the doping source of the first doped oxide layer 6 into the second intrinsic crystalline silicon layer 5 and the first intrinsic crystalline silicon layer 3 to form two first doped crystalline silicon layers 8 inside the first doped oxide layer 6.

[0115] Exemplarily, in combination with Figure 11 and Figure 13 , the pushing temperature of 960 °C and the pushing time of 30 min can be adopted, so that the doping source in the first doped oxide layer 6 can be deeply pushed to the first intrinsic crystalline silicon layer 3, thereby forming the first doped crystalline silicon layers 8 on both the inner and outer sides of the second oxide layer 4, and the two first doped crystalline silicon layers 8 use the second oxide layer 4 as a tunneling oxide layer, having a better battery conversion efficiency.

[0116] Alternatively, after step S600, as shown in Figure 13 and Figure 14 , the first doped crystalline silicon layer 8 outside the second oxide layer 4 and the second oxide layer 4 can also be used as sacrificial layers, and only the first doped crystalline silicon layer 8 and the first doped crystalline silicon layer 8 inside the second oxide layer 4 need to be retained.

[0117] Exemplarily, step S820 can further include:

[0118] In the first polarization region, remove the first doped crystalline silicon layer 8 outside the second oxide layer 4 and the second oxide layer 4 and clean until the first doped crystalline silicon layer 8 formed by exposing the first intrinsic crystalline silicon layer 3 is exposed.

[0119] In this way, by providing multiple preparation process directions, it is convenient to flexibly adjust the preparation process.

[0120] When the first doped crystalline silicon layer 8 outside the second oxide layer 4 and the second oxide layer 4 are used as sacrificial layers. The thickness dimension of the second oxide layer 4 can be flexibly adjusted. Correspondingly, the preparation process of the second intrinsic crystalline silicon layer 5 can be accelerated to reduce the production time of the overall process.

[0121] Exemplarily, the thickness of the second oxide layer 4 can be set to be greater than that of the first oxide layer 2. At this time, the second oxide layer 4 serves as a sacrificial layer structure.

[0122] Correspondingly, the deposition temperature of the first intrinsic silicon layer 3 is lower than that of the second intrinsic silicon layer 5. That is, a higher deposition temperature is beneficial to increasing the deposition rate of the second intrinsic silicon layer 5 to reduce the production time of the overall process. Moreover, a lower deposition temperature and deposition rate are beneficial to improving the deposition uniformity and quality of the first intrinsic silicon layer 3.

[0123] Since the second intrinsic silicon layer 5 as the sacrificial layer does not require a large thickness, the deposition time of the second intrinsic silicon layer 5 can be further compressed. The deposition time of the second intrinsic silicon layer 5 is made less than that of the first intrinsic silicon layer 3, thereby reducing the production time of the overall process.

[0124] In some embodiments, step S830 further includes:

[0125] Prepare a textured structure at the silicon substrate 1 in the electrical isolation region and at the silicon substrate 1 with the second surface shape.

[0126] By preparing a textured structure at the silicon substrate 1 exposed in the electrical isolation region, the reflection effect of light at the silicon substrate 1 can be improved to increase the utilization efficiency of light.

[0127] In some embodiments, step S810 further includes:

[0128] Remove a part of the silicon substrate 1 in the electrical isolation region to form a groove structure on the silicon substrate 1.

[0129] That is, by setting the part of the silicon substrate 1 exposed in the electrical isolation region as Figure 15 the groove structure shown. During the process of preparing the passivation film 10 and the antireflection film 11 in step S910, the passivation film 10 and the antireflection film 11 can be made to extend along the inner wall of the groove structure, which is beneficial to increasing the creepage clearance and creepage distance between the P region and the N region, and further improving the electrical isolation effect in a limited space. Or, on the basis of the same electrical isolation effect, through the setting of the groove structure, it is beneficial to reducing the width gap of the electrical isolation region, thereby increasing the structural occupation area of the P region and the N region in the photovoltaic cell.

[0130] Second, as Figure 10 and Figure 15 shown, an embodiment of the present application further provides a back-contact photovoltaic cell 100, and the back-contact photovoltaic cell 100 is obtained by the preparation method in the first aspect.

[0131] Beneficial effects: Since the back-contact photovoltaic cell 100 in the second aspect is obtained by the preparation method of the back-contact photovoltaic cell in the first aspect, the back-contact photovoltaic cell 100 has all the beneficial effects of the above-mentioned preparation method of the back-contact photovoltaic cell, which will not be elaborated here.

[0132] In a third aspect, as Figure 16 shown, an embodiment of the present application further provides a photovoltaic module 1000. The photovoltaic module 1000 includes a plurality of back-contact photovoltaic cells 100 in the second aspect, and the plurality of back-contact photovoltaic cells 100 are electrically connected. For example, the plurality of back-contact photovoltaic cells 100 can be partially in series and partially in parallel, or a plurality of back-contact photovoltaic cells 100 can be arranged in series to output electricity under light.

[0133] Beneficial effects: Since the photovoltaic module 1000 in the third aspect includes the back-contact photovoltaic cell 100 in the second aspect, the photovoltaic module 1000 has all the beneficial effects of the above-mentioned back-contact photovoltaic cell 100, which will not be elaborated here.

[0134] In the description of this specification, the descriptions with reference to the terms "embodiment", "example", "some embodiments", "example", "exemplary", "for example", etc. mean that the specific features, structures, shapes, positions, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0135] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and purposes of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a back-contact photovoltaic cell, characterized in that: include: Step S100: providing a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface arranged opposite to each other, wherein the first surface comprises a first polarity region and a second polarity region; Step S200: preparing, at least on the first surface, a first oxide layer, a first intrinsic crystalline silicon layer, a second oxide layer, and a second intrinsic crystalline silicon layer stacked from the inside out, wherein the first oxide layer is a tunneling oxide layer; Step S300: doping the second intrinsic crystalline silicon layer on the first surface, and forming a first doped oxide layer outside the doped second intrinsic crystalline silicon layer; Step S400: removing at least the first doped oxide layer in the second polarity region by laser; Step S500: removing at least the second intrinsic crystalline silicon layer and the second oxide layer in the second polarity region; Step S600: A first doped crystalline silicon layer is formed on the inner side of the first doped oxide layer in the first polarity region; a second doped oxide layer is prepared on the outer side of the first intrinsic crystalline silicon layer in the second polarity region, and the doping source of the second doped oxide layer is pushed into the first intrinsic crystalline silicon layer to form a second doped crystalline silicon layer; the doping type of the first doped crystalline silicon layer is opposite to the doping type of the second doped crystalline silicon layer.

2. The method for preparing a back contact photovoltaic cell according to claim 1, characterized in that: After step S600, the preparation method further includes: Step S700: removing at least the second doped oxide layer and the first doped oxide layer in an electrical isolation region by laser, wherein the electrical isolation region is located between the first polarity region and the second polarity region; Step S810: removing the film layer in the electrical isolation area and cleaning it until the silicon substrate is exposed; Step S820: removing the first doped oxide layer and the second doped oxide layer and cleaning them; Step S830: preparing a velvet structure at least on the second surface of the silicon substrate.

3. The method for preparing a back contact photovoltaic cell according to claim 2, characterized in that: The step S600 includes: Step S610: advancing the doping source of the first doped oxide layer at least to the second intrinsic crystalline silicon layer, so as to form a first doped crystalline silicon layer at least outside the second oxide layer; Step S620: preparing the second doped oxide layer outside the first intrinsic crystalline silicon layer in the second polarity region, and advancing the doping source of the second doped oxide layer into the first intrinsic crystalline silicon layer to form the second doped crystalline silicon layer.

4. The method for preparing a back contact photovoltaic cell according to claim 3, characterized in that: In the step S610, the advancing temperature is controlled to be 950-970° C., and the advancing time of the doping source in the first doped oxide layer is controlled to be 25-35 minutes.

5. The method for preparing a back contact photovoltaic cell according to claim 3, characterized in that: In the step S620, the preparation temperature of the second doped oxide layer is 830-850° C.; and / or, The advancing temperature is controlled to be 880-900° C., and the advancing time of the doping source in the second doped oxide layer is controlled to be 15-25 minutes.

6. The method for preparing a back contact photovoltaic cell according to claim 3, characterized in that: The step S610 further includes: The doping source of the first doped oxide layer is pushed into the second intrinsic crystalline silicon layer and the first intrinsic crystalline silicon layer to form two first doped crystalline silicon layers inside the first doped oxide layer.

7. The method for preparing a back-contact photovoltaic cell according to any one of claims 1 to 6, characterized in that: The step S300 further includes: The doping source located in the first doped oxide layer is driven into the second intrinsic crystalline silicon layer to form a first doped crystalline silicon layer outside the second oxide layer.

8. The method for preparing a back contact photovoltaic cell according to claim 7, characterized in that: In the step S300, the preparation temperature of the first doped oxide layer is 840-850° C.; and / or, After the first doped oxide layer is formed, the advancing temperature is controlled to be 880-920° C., and the advancing time of the doping source in the first doped oxide layer is controlled to be 8-12 minutes.

9. The method for preparing a back-contact photovoltaic cell according to any one of claims 1 to 6, characterized in that: The oxidation temperature of the first oxide layer is 600-700° C., the thickness of the first oxide layer is 1-2 nm, and the oxidation time of the first oxide layer is 10-20 min; and / or, The deposition temperature of the first intrinsic crystalline silicon layer is 510-610° C., the thickness of the first intrinsic crystalline silicon layer is 50-300 nm, and the deposition time of the first intrinsic crystalline silicon layer is 1200-2400 s; and / or, The oxidation temperature of the second oxide layer is 600-700° C., the thickness of the second oxide layer is 1-5 nm, and the oxidation time of the second oxide layer is 10-35 min; and / or, The deposition temperature of the second intrinsic crystalline silicon layer is 600-700° C., the thickness of the second intrinsic crystalline silicon layer is 50-200 nm, and the deposition time of the second intrinsic crystalline silicon layer is 1200-1400 s.

10. The method for preparing a back contact photovoltaic cell according to claim 6, characterized in that: The step S820 further includes: In the first polarity region, the first doped crystalline silicon layer and the second oxide layer outside the second oxide layer are removed and cleaned until the first doped crystalline silicon layer formed by the first intrinsic crystalline silicon layer is exposed.

11. The method for preparing a back contact photovoltaic cell according to claim 10, characterized in that: The thickness of the second oxide layer is greater than the thickness of the first oxide layer; and / or, The deposition temperature of the first intrinsic crystalline silicon layer is lower than the deposition temperature of the second intrinsic crystalline silicon layer; and / or, The deposition time of the second intrinsic crystalline silicon layer is shorter than the deposition time of the second intrinsic crystalline silicon layer.

12. The method for preparing a back-contact photovoltaic cell according to any one of claims 3 to 6, characterized in that: The second oxide layer is a tunnel oxide layer.

13. The method for preparing a back-contact photovoltaic cell according to any one of claims 2-6 or 10-11, characterized in that: In the step S200, the first oxide layer, the first intrinsic crystalline silicon layer, the second oxide layer and the second intrinsic crystalline silicon layer are formed on the first surface and the second surface of the silicon substrate; The step S500 further includes: The second surface of the silicon substrate is cleaned until the second surface of the silicon substrate is exposed.

14. The method for preparing a back-contact photovoltaic cell according to any one of claims 2-6 or 10-11, characterized in that: The step S830 includes: A velvet structure is prepared on the silicon substrate in the electrical isolation region, and a velvet structure is prepared on the silicon substrate in the second surface shape.

15. The method for preparing a back-contact photovoltaic cell according to any one of claims 2-6 or 10-11, characterized in that: The step S810 further includes: A portion of the silicon substrate is removed at the electrical isolation region to form a groove structure on the silicon substrate.

16. The method for preparing a back-contact photovoltaic cell according to any one of claims 2-6 or 10-11, characterized in that: After step S830, the preparation method further includes: Step S910: preparing a stacked passivation film and an anti-reflection film on both sides of the silicon substrate; Step S920: preparing a first electrode connected to the first doped crystalline silicon layer and a second electrode connected to the second doped crystalline silicon layer.

17. A back contact photovoltaic cell, characterized in that: The back-contact photovoltaic cell is prepared by the preparation method described in any one of claims 1-16.

18. A photovoltaic module, characterized in that: The photovoltaic module comprises a plurality of back-contact photovoltaic cells according to claim 17, and the plurality of back-contact photovoltaic cells are electrically connected.

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