Preparation method of an LED chip structure and an LED chip structure

Abstract

The present disclosure relates to the technical field of LED chips, and in particular, to a method for preparing an LED chip structure and an LED chip structure. The present disclosure provides a method for preparing an LED chip structure and an LED chip structure, wherein the method includes: forming a semiconductor layer on a substrate; periodically and alternately injecting a first ion and a second ion into the semiconductor layer to form a plurality of insulating isolation regions in the semiconductor layer, and the plurality of insulating isolation regions divide the semiconductor layer into a plurality of LED unit structures; wherein the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion; forming a photonic crystal structure in the insulating isolation region to inhibit the lateral diffusion of light. The present disclosure performs periodic and alternate injection of positive ions and negative ions into the semiconductor layer to form a plurality of insulating isolation regions in the semiconductor layer. The alternate injection of positive and negative ions enhances the carrier capture ability, thereby further improving the insulation effect of the insulating isolation regions.

Description

Technical Field

[0001] The present disclosure relates to the technical field of LED chips, and in particular, to a method for preparing an LED chip structure and an LED chip structure. Background Art

[0002] GaN-based LED devices usually use dry etching to form grooves for isolation. However, due to the small size of ultra-high-resolution MicroLEDs (micrometer-scale LEDs), a large amount of GaN sidewalls are exposed during the etching of the mesa. The chip size of micrometer-scale LEDs is usually less than 50 μm, and the chip pitch is small. Therefore, the surface area of the sidewalls exposed during the preparation of micrometer-scale LEDs increases by an order of magnitude compared to conventional LEDs. These surfaces exposed on the sidewalls will form leakage channels due to defects during the operation of micrometer-scale LEDs, affecting the device performance, and further reducing the internal quantum efficiency of micrometer-scale LEDs.

[0003] Currently, the methods for solving the leakage channels formed by surface defects on the sidewalls mainly include sidewall passivation, wet chemical etching, thermal annealing, neutron damage-free etching, and selective area epitaxy. These methods have effectively reduced the leakage current generated by surface damage. However, wet etching and thermal annealing cannot completely remove the sidewall damage, and sidewall passivation, neutron damage-free etching, and selective area epitaxy all increase the difficulty of the growth process, wafer processing, and dry etching conditions of micrometer-scale LEDs. Therefore, how to solve the sidewall defect problem during the preparation of micrometer-scale LEDs is one of the problems that those skilled in the art need to solve. Summary of the Invention

[0004] The present disclosure provides a method for preparing an LED chip structure and an LED chip structure to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, there is provided a method for preparing an LED chip structure, wherein the method includes:

[0006] Providing a substrate;

[0007] Forming a semiconductor layer on the substrate, the semiconductor layer including a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked in sequence from bottom to top;

[0008] Periodically and alternately injecting a first ion and a second ion into the semiconductor layer to form a plurality of insulating isolation regions in the semiconductor layer, the plurality of insulating isolation regions dividing the semiconductor layer into a plurality of LED unit structures; wherein, the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion;

[0009] Forming a photonic crystal structure in the insulating isolation region to inhibit the lateral diffusion of light.

[0010] In one possible implementation, during each injection cycle, the first ions and the second ions are both injected into the semiconductor layer multiple times alternately at a first angle, a second angle, and a third angle.

[0011] In one possible implementation, the range of the first angle is 30° - 45°, the range of the second angle is 50° - 65°, and the range of the third angle is 75° - 90°.

[0012] In one possible implementation, the positive ions include at least one of silicon ions, boron ions, phosphorus ions, arsenic ions, and magnesium ions;

[0013] The negative ions include at least one of fluoride ions, hydrogen ions, and oxygen ions.

[0014] In one possible implementation, the insulating isolation region penetrates through the second doped semiconductor layer and the active layer and is located within the first doped semiconductor layer.

[0015] In one possible implementation, the periodic and alternate injection of the first ions and the second ions into the semiconductor layer includes:

[0016] Forming a mask layer on the semiconductor layer;

[0017] Performing a patterning process on the mask layer to form a plurality of injection region patterns on the mask layer, and the injection region patterns expose a part of the semiconductor layer; wherein, the injection region patterns are in a polygonal sawtooth shape;

[0018] Performing periodic and alternate injection of the first ions and the second ions on the exposed part of the semiconductor layer to form a plurality of insulating isolation regions.

[0019] In one possible implementation, the distance between the insulating isolation region and the injection region pattern is 1 - 3 μm.

[0020] In one possible implementation, forming a photonic crystal structure within the insulating isolation region includes:

[0021] Etching the insulating isolation region to form a groove within the insulating isolation region;

[0022] Forming a passivation layer covering the bottom and side walls of the groove;

[0023] Forming a metal reflection layer covering the passivation layer;

[0024] Forming a photonic crystal structure covering the metal reflection layer and filling the groove.

[0025] In one possible implementation, the method further includes:

[0026] Before forming the semiconductor layer, a first insulating layer is formed on the substrate, wherein the material of the first insulating layer includes AlN, AlGaN or BN.

[0027] According to the second aspect of the present disclosure, an LED chip structure is provided, wherein the LED chip structure includes:

[0028] A substrate;

[0029] A semiconductor layer located on the substrate, the semiconductor layer includes a first doped semiconductor layer, an active layer and a second doped semiconductor layer stacked in sequence from bottom to top;

[0030] A plurality of insulating isolation regions located in the semiconductor layer, the insulating isolation regions include a first ion and a second ion, and the plurality of insulating isolation regions divide the semiconductor layer into a plurality of LED unit structures; wherein, the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion;

[0031] A photonic crystal structure located in the insulating isolation region to inhibit the lateral diffusion of light.

[0032] In an implementable embodiment, the positive ion includes at least one of silicon ion, boron ion, phosphorus ion, arsenic ion and magnesium ion;

[0033] The negative ion includes at least one of fluoride ion, hydrogen ion and oxygen ion.

[0034] In an implementable embodiment, the insulating isolation region penetrates through the second doped semiconductor layer and the active layer and is located in the first doped semiconductor layer.

[0035] In an implementable embodiment, the LED chip structure further includes:

[0036] A mask layer located on the semiconductor layer, a plurality of injection region patterns are formed on the mask layer, and the injection region patterns expose the insulating isolation regions; wherein, the injection region patterns are in a polygonal serrated shape.

[0037] In an implementable embodiment, the distance between the insulating isolation region and the injection region pattern is 1 - 3 μm.

[0038] In an implementable embodiment, the LED chip structure further includes:

[0039] A groove located in the insulating isolation region;

[0040] A passivation layer covering the bottom and side walls of the groove;

[0041] A metal reflective layer covering the passivation layer;

[0042] The photonic crystal structure covers the metal reflective layer and fills the groove.

[0043] In an implementable embodiment, the LED chip structure further includes:

[0044] A first insulating layer located between the substrate and the semiconductor layer, wherein the material of the first insulating layer includes AlN, AlGaN or BN.

[0045] In the preparation method of the LED chip structure and the LED chip structure of the present disclosure, by performing periodic alternating implantation of positive ions and negative ions on the semiconductor layer, a plurality of insulating isolation regions are formed in the semiconductor layer. Among them, the positive ions prevent carrier penetration while forming a low-mobility defect region, and the negative ions can create deep-level traps to cause carrier localization. The alternating implantation of positive and negative ions enhances the carrier capture ability, thereby further improving the insulation effect of the insulating isolation region. As a result, a good electrical isolation effect can be achieved through a smaller isolation region, which can not only greatly reduce the isolation distance between micro-LED chips and increase the chip density, but also form good electrical insulation between high-density micro-LED chips.

[0046] At the same time, a photonic crystal structure is formed in the insulating isolation region to match the emission wavelength of the active layer with the photonic bandgap of the photonic crystal, restricting the lateral propagation of photons in the quantum well of the active layer, thereby significantly improving the light extraction intensity of the planar micro-LED in the vertical direction.

[0047] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] By referring to the accompanying drawings and reading the following detailed description, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become easily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, wherein:

[0049] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0050] Figure 1 It is a flowchart of the preparation method of the LED chip structure provided by the embodiment of the present disclosure;

[0051] Figure 2 It shows the implementation process schematic of the preparation method of the LED chip structure provided by the embodiment of the present disclosure Figure 1 ;

[0052] Figure 3 Shows the implementation process schematic of the preparation method of the LED chip structure provided by the embodiments of the present disclosure Figure 2 ;

[0053] Figure 4 Shows the implementation process schematic of the preparation method of the LED chip structure provided by the embodiments of the present disclosure Figure 3 ;

[0054] Figure 5 Shows the implementation process schematic of the preparation method of the LED chip structure provided by the embodiments of the present disclosure Figure 4 ;

[0055] Figure 6 Shows the implementation process schematic of the preparation method of the LED chip structure provided by the embodiments of the present disclosure Figure 5 ;

[0056] Figure 7 Shows the implementation process schematic of the preparation method of the LED chip structure provided by the embodiments of the present disclosure Figure 6 ;

[0057] Figure 8 Shows the implementation process schematic of the preparation method of the LED chip structure provided by the embodiments of the present disclosure Figure 7 ;

[0058] Figure 9 Is a top view of the mask layer in the embodiments of the present disclosure;

[0059] Figure 10 Is a structural schematic diagram of the LED chip structure provided by the embodiments of the present disclosure.

[0060] Reference numerals:

[0061] 10. Substrate;

[0062] 20. Second insulating layer;

[0063] 30. First insulating layer;

[0064] 40. Semiconductor layer; 41. First doped semiconductor layer; 42. Active layer; 43. Second doped semiconductor layer; 400. LED unit structure;

[0065] 50. Mask layer; 501. Injection area pattern;

[0066] 60. Insulating isolation area; 601. Groove;

[0067] 71. Passivation layer; 72. Metal reflection layer;

[0068] 80. Photonic crystal structure;

[0069] 91. First electrode; 92. Second electrode; 93. Microlens. Detailed implementation manners

[0070] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present disclosure.

[0071] The embodiments of the present disclosure provide a preparation method for an LED chip structure. Figure 1 It is a flowchart of the preparation method for the LED chip structure provided by the embodiments of the present disclosure. As Figure 1 shown, the method includes:

[0072] Step 101: Provide a substrate.

[0073] Step 102: Form a semiconductor layer on the substrate, where the semiconductor layer includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked in sequence from bottom to top.

[0074] Step 103: Periodically and alternately inject a first ion and a second ion into the semiconductor layer to form a plurality of insulating isolation regions in the semiconductor layer, and the plurality of insulating isolation regions divide the semiconductor layer into a plurality of LED unit structures; wherein, the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion.

[0075] Step 104: Form a photonic crystal structure in the insulating isolation region to inhibit the lateral diffusion of light.

[0076] The preparation method for the LED chip structure provided by the embodiments of the present disclosure will be further described in detail below with reference to specific embodiments. Figures 2 to 8 It is a schematic diagram of the implementation process of the preparation method for the LED chip structure provided by the embodiments of the present disclosure.

[0077] First, refer to Figure 2 , and execute Step 101 to provide a substrate 10.

[0078] In one embodiment, the substrate 10 can be a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (such as a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a sapphire substrate, etc. In a preferred embodiment, the substrate 10 can be a sapphire substrate.

[0079] The epitaxial wafer of the embodiments of the present disclosure adopts a full-structure epitaxial wafer of a blue LED with an emission wavelength of about 450 nm. Since this full-structure epitaxial wafer is used for the preparation of micro-LEDs, it is necessary to ensure the uniformity of the emission wavelength, and its wavelength drift should be less than 1 nm. Therefore, it is necessary to first measure the emission wavelength position, internal quantum efficiency, wavelength uniformity, and emission efficiency of the epitaxial wafer through room-temperature photoluminescence (PL), low-temperature photoluminescence, PL mapping (photoluminescence scanning system), and chemiluminescence (CL) spectra to observe whether the epitaxial wafer meets the LED requirements.

[0080] Next, continue to refer to Figure 2 , the method further includes: forming a second insulating layer 20 on the substrate 10.

[0081] In actual operation, the second insulating layer 20 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.

[0082] In a preferred embodiment, the second insulating layer 20 can be deposited by atomic layer deposition technology.

[0083] The material of the second insulating layer 20 includes but is not limited to silicon dioxide (SiO2), silicon nitride (SiN x ) and aluminum oxide (Al2O3).

[0084] The role of these materials in the LED chip structure is to provide effective isolation and protection, and improve the performance and reliability of the chip. By selecting a suitable insulating layer material, the electrical performance and thermal stability of the LED chip can be improved.

[0085] When selecting the insulating layer material, one or a combination of materials such as silicon dioxide, silicon nitride, or aluminum oxide can be chosen according to specific application requirements. Silicon dioxide has good electrical insulation performance and thermal stability and is suitable for applications in high-temperature environments; silicon nitride has a low dielectric constant and can be used as an ideal isolation layer in microwave and radio frequency applications to achieve electrical isolation between devices and reduce noise interference; aluminum oxide has excellent mechanical strength and corrosion resistance and is suitable for applications that require high strength and durability. In addition, the performance of the insulating layer material can be optimized by adjusting the proportions of silicon dioxide, silicon nitride, and aluminum oxide to meet the requirements of different application scenarios.

[0086] Next, continue to refer to Figure 2 , the method further includes: forming a first insulating layer 30 on the substrate 10 before forming the semiconductor layer, wherein the material of the first insulating layer 30 includes AlN (aluminum nitride), AlGaN (aluminum gallium nitride), or BN (boron nitride). However, it should be explained that the material of the first insulating layer 30 is not limited to this.

[0087] Specifically, the first insulating layer 30 is located on the second insulating layer 20. The thickness range of the first insulating layer 30 is 10 - 30 nm.

[0088] In actual operation, the first insulating layer 30 can be formed by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), magnetron sputtering, atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition methods.

[0089] In a preferred embodiment, the first insulating layer 30 can be deposited by atomic layer deposition technology or low-temperature sputtering method.

[0090] The first insulating layer 30 not only enhances the carrier blocking ability but also prevents the injected ions from undergoing asymmetric diffusion in the lateral direction, enhancing the insulation effect of the subsequently formed insulating isolation region.

[0091] Next, continue to refer to Figure 2 , perform step 102 to form a semiconductor layer 40 on the substrate 10, where the semiconductor layer 40 includes a first doped semiconductor layer 41, an active layer 42, and a second doped semiconductor layer 43 stacked in sequence from bottom to top.

[0092] In actual operation, the first doped semiconductor layer 41, the active layer 42, and the second doped semiconductor layer 43 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.

[0093] The first doped semiconductor layer 41 can be an n-type semiconductor layer, and the second doped semiconductor layer 43 can be a p-type semiconductor layer. More specifically, the first doped semiconductor layer 41 can be an n-type GaN layer, and the second doped semiconductor layer 43 can be a p-type GaN layer.

[0094] The active layer 42 is the key part for the LED chip structure to emit light and is responsible for generating light. It is composed of periodically arranged In x Ga 1-x N quantum well layers and GaN quantum barrier layers. The In x Ga 1-x N quantum well layer has a thickness of 1.5 - 3.5 nm, the GaN quantum barrier layer has a thickness of 9 - 15 nm, and the period number of the In x Ga 1-x N quantum well and the GaN quantum barrier is 3 - 7.

[0095] Next, referring to Figure 3 , a mask layer 50 is formed on the semiconductor layer 40.

[0096] In actual operation, the mask layer 50 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.

[0097] In a preferred embodiment, the mask layer 50 can be formed by evaporation coating.

[0098] The materials of the mask layer 50 include but are not limited to silicon oxide (SiO2), silicon nitride (SiN), aluminum nitride (AlN), aluminum oxide (Al2O3), gallium oxide (Ga2O3), titanium oxide (TiO2), hafnium oxide (HfO2), etc.

[0099] Next, referring to Figure 4, the mask layer 50 is patterned to form a plurality of implantation region patterns on the mask layer 50, and the implantation region patterns expose a part of the semiconductor layer 40; wherein, the implantation region patterns are in a multi-sided sawtooth shape.

[0100] Specifically, the implantation region patterns can be formed by lithography or electron beam exposure.

[0101] The implantation region patterns are used to distinguish the boundary between the ion implantation region and the non-ion implantation region.

[0102] Figure 9 It is a top view of the mask layer in the embodiment of the present disclosure. As Figure 9 shown, the implantation region pattern 501 is in a multi-sided sawtooth shape.

[0103] The implantation region pattern 501 is designed in a multi-sided sawtooth shape, effectively preventing the abnormal expansion of the electric field and the accumulation of edge charges, and significantly improving the overall electrical consistency of the device.

[0104] Next, referring to Figure 5 , step 103 is executed to periodically and alternately implant the first ions and the second ions into the semiconductor layer 40 to form a plurality of insulating isolation regions 60 in the semiconductor layer 40, and the plurality of insulating isolation regions 60 divide the semiconductor layer 40 into a plurality of LED unit structures 400; wherein, the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion.

[0105] The semiconductor layer 40 includes a plurality of ion implantation regions and a plurality of non-ion implantation regions distributed in the plane direction. The ion implantation regions are the insulating isolation regions 60, and any two non-ion implantation regions are electrically isolated by the insulating isolation regions 60. One LED unit structure 400 is fabricated in each non-ion implantation region.

[0106] Specifically, referring to Figure 5 , the first ions and the second ions are periodically and alternately implanted into the part of the semiconductor layer 40 exposed by the implantation region pattern 501 to form a plurality of the insulating isolation regions 60.

[0107] It should be explained that, as Figure 9 shown, not all of the semiconductor layer 40 exposed by the implantation region pattern 501 is implanted with ions, but a part of the semiconductor layer 40 is implanted with ions to form the insulating isolation regions 60. Therefore, there is a certain distance between the insulating isolation regions 60 and the implantation region pattern 501.

[0108] In one embodiment, the distance between the insulating isolation region 60 and the implantation region pattern 501 is 1 - 3 μm. Here, there is still a certain distance between the insulating isolation region 60 and the implantation region pattern 501, so that a part of the second doped semiconductor layer 43 is still exposed, so that electrodes can be formed thereon subsequently. At the same time, the remaining mask layer 50 does not need to be etched away, and the remaining mask layer 50 can be used as an isolation layer between adjacent electrodes located on the second doped semiconductor layer 43 to prevent crosstalk between adjacent electrodes.

[0109] In actual operation, when performing ion implantation, a Spin-Aligned Substrate Rotator (SASR) can be embedded in the LED chip structure. The spin-aligned substrate rotator can rotate the LED chip structure, making the implanted ions always incident at different crystal orientations, further improving the uniformity of the implantation distribution and expanding the spatial width of the defect band, and avoiding the influence of the channel effect on the lattice perturbation consistency. The spin-aligned substrate rotator keeps the LED chip structure rotating at a constant speed, and the rotation rate can be determined according to actual needs.

[0110] In one embodiment, the first ions and the second ions are alternately implanted into the semiconductor layer 40 periodically, including: the range of the implantation period is 3 - 5 times. The first ions and the second ions are implanted into the semiconductor layer 40 through multiple periods, which can improve the uniformity of the formed insulating isolation region 60, and further improve the insulation performance of the insulating isolation region 60. At the same time, it is optimal to control the implantation period within 3 - 5 times, because if the implantation period is too small, the uniformity of the formed insulating isolation region is poor, and if the implantation period is too large, the cost will increase.

[0111] In one embodiment, within each implantation period, the first ions and the second ions are alternately implanted into the semiconductor layer 40 multiple times at a first angle, a second angle, and a third angle.

[0112] Among them, the range of the first angle is 30° - 45°, the range of the second angle is 50° - 65°, and the range of the third angle is 75° - 90°. In a preferred embodiment, the first angle is 45°, the second angle is , and the third angle is 90°. It should be noted that the first angle, the second angle, and the third angle here are all the angles between the ion implantation direction and the plane of the semiconductor layer 40.

[0113] Specifically, for example, first, there is a first ion implantation. The first ions are first implanted into the semiconductor layer 40 at an angle of 45°. After implanting for a certain period of time, they are then implanted into the semiconductor layer 40 at an angle of 60°. After implanting for the same certain period of time, they are then implanted into the semiconductor layer 40 at an angle of 90°. After implanting for a certain period of time, then the first ions are implanted into the semiconductor layer 40 at an angle of 45° again. After cycling several times according to this rule, the implantation of the first ions ends; after the first ion implantation ends, then there is a second ion implantation. The second ions are also first implanted into the semiconductor layer 40 at an angle of 45°. After implanting for a certain period of time, they are then implanted into the semiconductor layer 40 at an angle of 60°. After implanting for the same certain period of time, they are then implanted into the semiconductor layer 40 at an angle of 90°. After implanting for a certain period of time, then the second ions are implanted into the semiconductor layer 40 at an angle of 45° again. After cycling several times according to this rule, the implantation of the second ions ends.

[0114] During one implantation cycle, the first ions and the second ions are alternately implanted at multiple angles, which can achieve the establishment of a highly uniform electrical isolation region and improve the insulation performance of the insulation isolation region.

[0115] In one embodiment, the implantation doses of the first ions and the second ions are greater than or equal to , and the implantation energy range is 70 - 150 keV. In a preferred embodiment, the implantation doses of the first ions and the second ions are , and the implantation energy is 100 keV.

[0116] In a specific embodiment, under the conditions of an implantation dose of and an implantation energy of 100 keV, by using the periodic alternating implantation of the first ions and the second ions, and the multi - angle implantation of the first ions and the second ions, the surface resistivity of the insulation isolation region formed can reach or more, the implantation depth is greater than 2 μm, and the damaged layer thickness is less than 15 nm, forming a high - resistance region for device isolation and effectively avoiding the influence on non - ion - implanted regions.

[0117] In one embodiment, the first ions are one of positive ions and negative ions, and the second ions are the other of positive ions and negative ions. For example, if the first ions are positive ions, then the second ions are negative ions.

[0118] The positive ions include at least one of silicon ions, boron ions, phosphorus ions, arsenic ions, and magnesium ions;

[0119] The negative ions include at least one of fluorine ions, hydrogen ions, and oxygen ions.

[0120] In the present disclosure, by performing periodic alternating implantation of positive ions and negative ions on a semiconductor layer, a plurality of insulating isolation regions are formed within the semiconductor layer. Among them, the positive ions prevent carrier penetration while forming low-mobility defect regions, and the negative ions can create deep-level traps to cause carrier localization. The alternating implantation of positive and negative ions enhances the carrier capture ability, thereby further improving the insulation effect of the insulating isolation regions. Thus, a good electrical isolation effect can be achieved through a smaller isolation region, which can not only greatly reduce the isolation distance between micro-LED chips and increase the chip density, but also form good electrical insulation between high-density micro-LED chips.

[0121] In one embodiment, as Figure 5 shown, the insulating isolation region 60 penetrates through the second doped semiconductor layer 43 and the active layer 42 and is located within the first doped semiconductor layer 41.

[0122] The depth of the insulating isolation region 60 should at least penetrate through the second doped semiconductor layer 43 to disconnect the second doped semiconductor layer 43, so as to form an independent LED unit structure.

[0123] Next, referring to Figures 6 to 7 , perform step 104 to form a photonic crystal structure 80 within the insulating isolation region 60 to suppress the lateral diffusion of light.

[0124] In one embodiment, forming the photonic crystal structure 80 within the insulating isolation region 60 includes:

[0125] Etch the insulating isolation region 60 to form a groove 601 within the insulating isolation region 60;

[0126] Form a passivation layer 71 covering the bottom and side walls of the groove 601;

[0127] Form a metal reflection layer 72 covering the passivation layer 71;

[0128] Form a photonic crystal structure 80 covering the metal reflection layer 72 and filling the groove 601.

[0129] Specifically, first refer to Figure 6 , etch the insulating isolation region 60 to form a groove 601 within the insulating isolation region 60.

[0130] In actual operation, a photoresist layer about 1 μm thick is spin-coated evenly on the surface of the epitaxial wafer and placed on a hot plate for pre-baking to evaporate the moisture inside the photoresist and complete the shaping. Then, a mask plate designed specifically for the photonic crystal structure is used to precisely transfer the periodic pattern through ultraviolet exposure and development processes. After development, the epitaxial wafer is cleaned with deionized water and then cleaned with a plasma asher after hard baking. The above-mentioned epitaxial wafer is subjected to a reaction ion etching (RIE) or inductively coupled plasma (ICP) etching step, and a mixed gas system is selected. The etching power is set at 300 W, the gas flow ratio is 10:5:20 sccm, the chamber pressure is maintained at 10 mTorr, and the etching time is controlled at about 60 seconds to meet the etching requirement of a depth of 60 nm. Immediately after etching, the residual photoresist is removed by ashing cleaning ( plasma + solvent cleaning).

[0131] Next, referring to Figure 7 , a passivation layer 71 covering the bottom and sidewalls of the groove 601 is formed; a metal reflective layer 72 covering the passivation layer 71 is formed.

[0132] In actual operation, the passivation layer 71 and the metal reflective layer 72 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.

[0133] In a preferred embodiment, the passivation layer 71 can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process to reduce the non-radiative recombination probability. The metal reflective layer 72 can be formed using electron beam evaporation or magnetron sputtering technology, so that under the action of the spin sample rotation system, it can evenly cover the entire lattice region.

[0134] In the embodiments of the present disclosure, in order to reduce the sidewall damage caused by dry etching during the preparation of the photonic crystal structure, a passivation layer 71 can be deposited in the groove 601 used for preparing the photonic crystal structure. The material of the passivation layer 71 includes but is not limited to silicon dioxide (SiO2), silicon nitride (SiN x)(and aluminum oxide (Al2O3)), with a thickness range of 20 - 30 nm. The main function of the passivation layer 71 is to passivate the inner wall of the groove 601 and isolate the metal reflective layer 72 from the inner wall of the groove 601.

[0135] When selecting the passivation layer material, one or a combination of materials such as silicon dioxide, silicon nitride, or aluminum oxide can be selected according to specific application requirements. Silicon dioxide has good electrical insulation properties and thermal stability, and is suitable for applications in high-temperature environments; silicon nitride has a low dielectric constant and can be used as an ideal isolation layer in microwave and radio frequency applications to achieve electrical isolation between devices and reduce noise interference; aluminum oxide has excellent mechanical strength and corrosion resistance, and is suitable for applications requiring high strength and durability. In addition, the performance of the passivation layer material can be optimized by adjusting the ratio of silicon dioxide, silicon nitride, and aluminum oxide to meet the requirements of different application scenarios.

[0136] To further enhance the reflection effect of the photonic crystal structure, a metal reflective layer 72 can be selected to be deposited on the surface of the passivation layer 71. The material of the metal reflective layer 72 includes silver (Ag), aluminum (Al), gold (Au), titanium (Ti), nickel (Ni), chromium (Cr), molybdenum (Mo), copper (Cu), etc. or their alloys, with a thickness range of 20 - 30 nm.

[0137] Next, continue to refer to Figure 7 , to form a photonic crystal structure 80 that covers the metal reflective layer 72 and fills the groove 601.

[0138] In the planar LED process, due to the dielectric constant difference between GaN and air, the maximum light-emitting angle of the quantum well is about , and the remaining photons will form a waveguide in the GaN layer for lateral transmission, thereby greatly reducing the light extraction efficiency of the planar LED. In order to effectively suppress the light propagating laterally in the planar micro-LED device and improve its vertical light extraction efficiency (Light Extraction Efficiency, LEE) in the embodiments of the present disclosure, a photonic crystal structure is formed in the insulating isolation region. A photonic crystal is an artificial microstructured material with a periodic refractive index distribution in space. By controlling its periodic structure, strong reflection or prohibited propagation of light in a specific wavelength range can be generated, thereby forming a photonic bandgap effect.

[0139] In the embodiments of the present disclosure, before forming a photonic crystal structure in the groove, it is necessary to first determine a photonic crystal structure that matches the emission wavelength of the LED chip structure in the present disclosure. For example, a blue light LED chip structure is selected, and the central wavelength of the blue light LED chip structure is about 450 nm. Taking the blue light LED as an example in the embodiments of the present disclosure, simulation is carried out by the Finite-Difference Time-Domain (FDTD) method. First, a two-dimensional GaN waveguide model is established. The upper part of the waveguide is air, the thickness of the waveguide is set to 1 μm, and the bottom substrate is set to Al2O3, which is a typical structure of a blue light LED. The photonic crystal structure is designed to introduce periodic air holes on the top layer of the waveguide. The simulation domain is 10×10 μm², and the boundary condition adopts the PML (Perfectly Matched Layer) absorbing boundary to avoid interference of reflection on the simulation results. The excitation source is a short pulse electromagnetic wave with vertical incidence, and its spectrum covers the wavelength range of 400~500 nm, aiming to observe the response behavior of the structure at the central wavelength of 450 nm. The design principle is based on Bragg scattering and interference effects to construct a photonic bandgap, restricting the propagation of light with a specific frequency in a specific direction. In a two-dimensional periodic structure, the periodic change of the refractive index leads to strong scattering of light, forming a quasi-bandgap, resulting in a bandgap suppression effect of photons in the transverse propagation direction (i.e., within the GaN layer), while forming enhanced emission in the vertical direction. The simulation results show that the photonic crystal structure with a period of 280 nm, an aperture of 140 nm, and a depth of 60 nm has the widest bandgap and the strongest reflection intensity in the 450 nm band, and the formed photonic crystal structure is more conducive to the vertical emission of blue light LED light.

[0140] After obtaining the period, aperture, and depth of the photonic crystal structure that matches the emission wavelength of the LED chip structure, a photonic crystal structure 80 is formed on the surface of the metal reflection layer 72.

[0141] In the embodiments of the present disclosure, by introducing a two-dimensional photonic crystal structure and optimizing the period, aperture, and depth of the photonic crystal structure, the bottleneck in the light extraction efficiency of traditional planar light-emitting devices is effectively broken, and it also provides a solid foundation for subsequent integrated optical microstructures, array packaging, etc., making the entire structure have good process compatibility and structural stability, and being suitable for the integrated manufacturing of large-scale micron LED arrays.

[0142] In the present disclosure, a photonic crystal structure is formed in the insulating isolation region to match the emission wavelength of the active layer with the photonic bandgap of the photonic crystal, restricting the transverse propagation of photons in the quantum well in the active layer, thereby significantly improving the light extraction intensity of the planar micron LED in the vertical direction.

[0143] Next, refer to Figure 8, etch away part of the second doped semiconductor layer 43 and the active layer 42 to expose part of the first doped semiconductor layer 41; form a first electrode 91 on the exposed first doped semiconductor layer 41; form a second electrode 92 on the second doped semiconductor layer 43 not covered by the mask layer 50.

[0144] In actual operation, electron beam evaporation technology can be used to sputter metal electrodes to form the first electrode 91 and the second electrode 92.

[0145] The conduction types of the first electrode 91 and the second electrode 92 are different, and the conduction types of the first electrode 91 and the second electrode 92 are the same as the conduction types of the first doped semiconductor layer 41 and the second doped semiconductor layer 43 respectively. For example, if the conduction type of the first doped semiconductor layer 41 is n-type and the conduction type of the second doped semiconductor layer 43 is p-type, then the conduction type of the first electrode 91 is n-type and the conduction type of the second electrode 92 is p-type.

[0146] The materials of the first electrode 91 and the second electrode 92 may include at least one of Cr, Au, Ti, Ag, and Pt.

[0147] The LED chip structure of the embodiment of the present disclosure shares a first electrode 91, which simplifies the electrode preparation process and reduces the manufacturing cost.

[0148] Next, continue to refer to Figure 8 , and form a microlens 93 on the above-mentioned epitaxial wafer. It should be noted that although only one microlens 93 is shown in the figure, multiple microlenses can be formed to form a microlens array.

[0149] Specifically, hot embossing or ultraviolet (UV) lithography technology can be used to form a microlens array aligned with the chip on the light-emitting surface. The diameter of each microlens is about 10 μm, and the radius of curvature is about 25 μm.

[0150] In the preparation method of the LED chip structure proposed by the present disclosure, not only the damage and thermal mismatch problems existing in the traditional etching electrical isolation process are fundamentally solved, but also the overall consistency and reliability of the device are improved. Through the integration of spatial carrier control and defect tunable mechanism, this structure provides a new solution for the construction of the next-generation high-density micron LED array, with broad engineering value and industrial transformation prospects.

[0151] The embodiment of the present disclosure also provides an LED chip structure. Figure 10 It is a schematic structural diagram of the LED chip structure provided by the embodiment of the present disclosure. As Figure 10 shown, the structure includes:

[0152] Substrate 10;

[0153] A semiconductor layer 40 located on the substrate 10, the semiconductor layer 40 including a first doped semiconductor layer 41, an active layer 42, and a second doped semiconductor layer 43 stacked in sequence from bottom to top;

[0154] A plurality of insulating isolation regions 60 located within the semiconductor layer 40, the insulating isolation regions 60 including a first ion and a second ion, the plurality of insulating isolation regions 60 dividing the semiconductor layer into a plurality of LED unit structures; wherein, the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion;

[0155] A photonic crystal structure 80 located within the insulating isolation region 60 to inhibit lateral diffusion of light.

[0156] In one embodiment, the substrate 10 may be a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (such as a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a sapphire substrate, etc. In a preferred embodiment, the substrate 10 may be a sapphire substrate.

[0157] In one embodiment, the LED chip structure further includes: a second insulating layer 20 located on the substrate 10.

[0158] The material of the second insulating layer 20 includes but is not limited to silicon dioxide (SiO2), silicon nitride (SiN x ) and aluminum oxide (Al2O3).

[0159] The functions of these materials in the LED chip structure are to provide effective isolation and protection, and to improve the performance and reliability of the chip. By selecting a suitable insulating layer material, the electrical performance and thermal stability of the LED chip can be improved.

[0160] When selecting the insulating layer material, one or a combination of materials such as silicon dioxide, silicon nitride, or aluminum oxide can be selected according to specific application requirements. Silicon dioxide has good electrical insulation performance and thermal stability and is suitable for applications in high-temperature environments; silicon nitride has a low dielectric constant and can be used as an ideal isolation layer in microwave and radio frequency applications to achieve electrical isolation between devices and reduce noise interference; aluminum oxide has excellent mechanical strength and corrosion resistance and is suitable for applications requiring high strength and durability. In addition, the performance of the insulating layer material can be optimized by adjusting the ratios of silicon dioxide, silicon nitride, and aluminum oxide to meet the requirements of different application scenarios.

[0161] In one embodiment, the LED chip structure further includes: a first insulating layer 30 located between the substrate 10 and the semiconductor layer 40, wherein the material of the first insulating layer 30 includes AlN (aluminum nitride), AlGaN (aluminum gallium nitride), or BN (boron nitride). However, it should be noted that the material of the first insulating layer 30 is not limited thereto.

[0162] Specifically, the first insulating layer 30 is located on the second insulating layer 20. The thickness range of the first insulating layer 30 is 10 - 30 nm.

[0163] The first insulating layer 30 not only enhances the carrier blocking ability but also prevents the injected ions from asymmetrically diffusing in the lateral direction, enhancing the insulation effect of the insulation isolation region 60.

[0164] The semiconductor layer 40 is located on the first insulating layer 30, and the semiconductor layer 40 includes a first doped semiconductor layer 41, an active layer 42, and a second doped semiconductor layer 43 that are stacked in sequence from bottom to top.

[0165] The first doped semiconductor layer 41 can be an n - type semiconductor layer, and the second doped semiconductor layer 43 can be a p - type semiconductor layer. More specifically, the first doped semiconductor layer 41 can be an n - type GaN layer, and the second doped semiconductor layer 43 can be a p - type GaN layer.

[0166] The active layer 42 is the key part for the LED chip to emit light, responsible for generating light, and is composed of periodically arranged In x Ga 1-x N quantum well layers and GaN quantum barrier layers. The thickness of the In x Ga 1-x N quantum well layer is 1.5 - 3.5 nm, the thickness of the GaN quantum barrier layer is 9 - 15 nm, and the number of periods of the In x Ga 1-x N quantum well and GaN quantum barrier is 3 - 7.

[0167] Referring to Figure 9 and Figure 10 , the LED chip structure further includes: a mask layer 50 located on the semiconductor layer 40, and a plurality of injection region patterns 501 are formed on the mask layer 50, and the injection region patterns 501 expose the insulation isolation region 60; wherein, the injection region patterns 501 are in a multi - sided saw - tooth shape.

[0168] The injection region patterns 501 are designed in a multi - sided saw - tooth shape, effectively preventing the abnormal expansion of the electric field and the accumulation of edge charges, and significantly improving the overall electrical consistency of the device.

[0169] The semiconductor layer 40 includes a plurality of ion implantation regions and a plurality of non-ion implantation regions distributed in a planar direction. The ion implantation regions are the insulating isolation regions 60, and any two non-ion implantation regions are electrically isolated by the insulating isolation regions 60. An LED unit structure is fabricated in each non-ion implantation region.

[0170] It should be noted that, as Figure 9 shown, the implantation region pattern 501 not only exposes the insulating isolation region 60, but also exposes a part of the semiconductor layer 40. Therefore, there is a certain distance between the insulating isolation region 60 and the implantation region pattern 501.

[0171] In one embodiment, the distance between the insulating isolation region 60 and the implantation region pattern 501 is 1 - 3 μm. Here, there is a certain distance between the insulating isolation region 60 and the implantation region pattern 501 so that a part of the second doped semiconductor layer 43 is also exposed, and thus an electrode can be formed thereon. At the same time, the mask layer 50 can serve as an isolation layer between adjacent electrodes located on the second doped semiconductor layer 43 to prevent crosstalk between adjacent electrodes.

[0172] In one embodiment, the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion. For example, if the first ion is a positive ion, then the second ion is a negative ion.

[0173] The positive ions include at least one of silicon ions, boron ions, phosphorus ions, arsenic ions, and magnesium ions;

[0174] The negative ions include at least one of fluorine ions, hydrogen ions, and oxygen ions.

[0175] In the present disclosure, the insulating isolation region includes positive ions and negative ions. Among them, the positive ions prevent carrier penetration while forming a low-mobility defect region, and the negative ions can create deep-level traps to cause carrier localization. The presence of positive and negative ions enhances the carrier capture ability, thereby further improving the insulation effect of the insulating isolation region. Thus, a good electrical isolation effect can be achieved through a smaller isolation region, which can not only greatly reduce the isolation distance between micro-LED chips and increase the chip density, but also form good electrical insulation between high-density micro-LED chips.

[0176] In one embodiment, as Figure 10 shown, the insulating isolation region 60 penetrates through the second doped semiconductor layer 43 and the active layer 42 and is located within the first doped semiconductor layer 41.

[0177] The depth of the insulation isolation region 60 should at least penetrate through the second doped semiconductor layer 43 to disconnect the second doped semiconductor layer 43, so as to form an independent LED unit structure.

[0178] In an embodiment, the LED chip structure further includes: a groove 601 located in the insulation isolation region 60;

[0179] A passivation layer 71 covering the bottom and side walls of the groove 601;

[0180] A metal reflective layer 72 covering the passivation layer 71;

[0181] The photonic crystal structure 80 covers the metal reflective layer 72 and fills the groove 601.

[0182] In the embodiments of the present disclosure, in order to reduce the sidewall damage caused by dry etching during the preparation of the photonic crystal structure, a passivation layer can be deposited in the groove used for preparing the photonic crystal structure. The material of the passivation layer 71 includes but is not limited to silicon dioxide (SiO2), silicon nitride (SiN x ), and aluminum oxide (Al2O3), and the thickness range is 20 - 30 nm. The main function of the passivation layer 71 is to passivate the inner wall of the groove 601 and isolate the metal reflective layer 72 from the inner wall of the groove 601.

[0183] When selecting the material of the passivation layer, one or a combination of materials such as silicon dioxide, silicon nitride, or aluminum oxide can be selected according to specific application requirements. Silicon dioxide has good electrical insulation performance and thermal stability and is suitable for applications in high-temperature environments; silicon nitride has a low dielectric constant and can be used as an ideal isolation layer in microwave and radio frequency applications to achieve electrical isolation between devices and reduce noise interference; aluminum oxide has excellent mechanical strength and corrosion resistance and is suitable for applications requiring high strength and durability. In addition, the performance of the passivation layer material can be optimized by adjusting the ratio of silicon dioxide, silicon nitride, and aluminum oxide to meet the requirements of different application scenarios.

[0184] To further enhance the reflection effect of the photonic crystal structure, a metal reflective layer 72 can be selected to be formed on the surface of the passivation layer 71. The material of the metal reflective layer 72 includes silver (Ag), aluminum (Al), gold (Au), titanium (Ti), nickel (Ni), chromium (Cr), molybdenum (Mo), copper (Cu), etc. or their alloys, and the thickness range is 20 - 30 nm.

[0185] The metal reflective layer 72 is mainly used to block and reflect the light reflected in the active layer and block the transmission path of light between adjacent LED unit structures.

[0186] In the planar LED process, due to the difference in dielectric constants between GaN and air, the maximum light-emitting angle of the quantum well is about , and the remaining photons will form a waveguide in the GaN layer for transverse transmission, thereby greatly reducing the light extraction efficiency of the planar LED. In order to effectively suppress the light propagating laterally in the planar micro-LED device and improve its vertical light extraction efficiency (Light Extraction Efficiency, LEE) in the embodiments of the present disclosure, a photonic crystal structure is formed in the insulating isolation region. A photonic crystal is an artificial microstructured material with a periodic refractive index distribution in space. By controlling its periodic structure, strong reflection or prohibited propagation of light in a specific wavelength range can be generated, thereby forming a photonic bandgap effect.

[0187] In the embodiments of the present disclosure, before forming the photonic crystal structure in the groove, it is necessary to first determine the photonic crystal structure that matches the emission wavelength of the LED chip structure in the present disclosure. For example, a blue light LED chip structure is selected, and the central wavelength of the blue light LED chip structure is about 450 nm. Taking the blue light LED as an example, through the Finite-Difference Time-Domain (FDTD) method for simulation, first establish a two-dimensional GaN waveguide model, with air above the waveguide, the waveguide thickness is set to 1 μm, and the bottom substrate is set to Al2O3, as a typical structure of the blue light LED. The photonic crystal structure is designed to introduce periodic air holes on the top layer of the waveguide, the simulation domain is 10×10 μm², and the boundary condition uses the PML (Perfectly Matched Layer) absorbing boundary to avoid interference of reflection on the simulation results. The excitation source is a vertically incident short pulse electromagnetic wave, and its spectrum covers the wavelength range of 400~500 nm, aiming to observe the response behavior of the structure at the central wavelength of 450 nm. The design principle is based on Bragg scattering and interference effects to construct a photonic bandgap, restricting the propagation of light with a specific frequency in a specific direction. In the two-dimensional periodic structure, the periodic change of the refractive index causes strong scattering of light, forming a quasi-bandgap, resulting in a bandgap suppression effect for photons in the transverse propagation direction (i.e., within the GaN layer), while forming enhanced emission in the vertical direction. The simulation results show that the photonic crystal structure with a period of 280 nm, an aperture of 140 nm, and a depth of 60 nm has the widest bandgap and the strongest reflection intensity in the 450 nm band, and the formed photonic crystal structure is more conducive to the vertical emission of blue light LED light.

[0188] After obtaining the period, aperture, and depth of the photonic crystal structure that matches the emission wavelength of the LED chip structure, a photonic crystal structure 80 is formed on the surface of the metal reflection layer 72.

[0189] In the embodiments of the present disclosure, by introducing a two-dimensional photonic crystal structure and optimizing the period, aperture, and depth of the photonic crystal structure, the bottleneck in the light extraction efficiency of traditional planar light-emitting devices is effectively broken, and a solid foundation is also provided for subsequent integrated optical microstructures, array packaging, etc., enabling the entire structure to have good process compatibility and structural stability, and being suitable for the integrated manufacturing of large-scale micron LED arrays.

[0190] In the present disclosure, a photonic crystal structure is formed in the insulating isolation region, the emission wavelength of the active layer is matched with the photonic bandgap of the photonic crystal, and the lateral propagation of photons in the quantum wells in the active layer is restricted, thereby significantly increasing the light extraction intensity of the planar micron LED in the vertical direction.

[0191] In one embodiment, the LED chip structure further includes: a first electrode 91 located on the first doped semiconductor layer 41; a second electrode 92 located on the second doped semiconductor layer 43.

[0192] The first electrode 91 and the second electrode 92 have different conduction types, and the conduction types of the first electrode 91 and the second electrode 92 are the same as the conduction types of the first doped semiconductor layer 41 and the second doped semiconductor layer 43, respectively. For example, if the conduction type of the first doped semiconductor layer 41 is n-type and the conduction type of the second doped semiconductor layer 43 is p-type, then the conduction type of the first electrode 91 is n-type and the conduction type of the second electrode 92 is p-type.

[0193] The materials of the first electrode 91 and the second electrode 92 may include at least one of Cr, Au, Ti, Ag, and Pt.

[0194] The LED chip structure of the embodiments of the present disclosure shares a first electrode 91, which simplifies the electrode preparation process and reduces the manufacturing cost.

[0195] In one embodiment, the LED chip structure further includes: a microlens 93 located on the above-mentioned epitaxial wafer. It should be noted that although only one microlens 93 is shown in the figure, multiple microlenses can be formed to form a microlens array.

[0196] Specifically, a microlens array aligned with the chip can be formed on the light-emitting surface using hot embossing or ultraviolet (UV) lithography technology. The diameter of each microlens is about 10 μm, and the radius of curvature is about 25 μm.

[0197] It should be understood that the various forms of processes shown above can be used, with steps reordered, added or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this is not limited herein.

[0198] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this disclosure, "a plurality" means two or more, unless otherwise specifically defined.

[0199] As described above, the above are only specific embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed in this disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be subject to the protection scope of the claims.

Claims

1. A preparation method of an LED chip structure, characterized in that, The method includes: providing a substrate; forming a semiconductor layer on the substrate, the semiconductor layer including a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked in sequence from bottom to top; periodically and alternately injecting a first ion and a second ion into the semiconductor layer to form a plurality of insulating isolation regions in the semiconductor layer, the plurality of insulating isolation regions dividing the semiconductor layer into a plurality of LED unit structures; the insulating isolation regions penetrate through the second doped semiconductor layer and the active layer and are located in the first doped semiconductor layer; wherein, the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion; forming a photonic crystal structure in the insulating isolation region to suppress lateral diffusion of light; The periodically and alternately injecting the first ion and the second ion into the semiconductor layer includes: forming a mask layer on the semiconductor layer; performing a patterning process on the mask layer to form a plurality of injection region patterns on the mask layer, the injection region patterns exposing a part of the semiconductor layer; wherein, the injection region patterns are in a multi-sided sawtooth shape; periodically and alternately injecting the first ion and the second ion into the exposed part of the semiconductor layer to form a plurality of insulating isolation regions.

2. The method for preparing an LED chip structure according to claim 1, wherein in each injection cycle, the first ion and the second ion are both injected into the semiconductor layer multiple times at a first angle, a second angle, and a third angle.

3. The method for preparing an LED chip structure according to claim 2, wherein the range of the first angle is 30° to 45°, the range of the second angle is 50° to 65°, and the range of the third angle is 75° to 90°.

4. The method for preparing an LED chip structure according to claim 1, wherein the positive ion includes at least one of silicon ion, boron ion, phosphorus ion, arsenic ion, and magnesium ion; the negative ion includes at least one of fluorine ion, hydrogen ion, and oxygen ion.

5. The method for preparing an LED chip structure according to claim 1, wherein the distance between the insulating isolation region and the injection region pattern is 1 to 3 μm.

6. The method for preparing an LED chip structure according to claim 1, wherein forming the photonic crystal structure in the insulating isolation region includes: etching the insulating isolation region to form a groove in the insulating isolation region; forming a passivation layer covering the bottom and side walls of the groove; forming a metal reflection layer covering the passivation layer; forming a photonic crystal structure covering the metal reflection layer and filling the groove.

7. The manufacturing method of the LED chip structure according to claim 1, characterized in that, The method further includes: forming a first insulating layer on the substrate before forming the semiconductor layer, wherein the material of the first insulating layer includes AlN, AlGaN, or BN.

8. An LED chip structure, characterized in that, The LED chip structure includes: a substrate; a semiconductor layer located on the substrate, the semiconductor layer including a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked in sequence from bottom to top; A plurality of insulating isolation regions located within the semiconductor layer, the insulating isolation regions including a first ion and a second ion, the plurality of insulating isolation regions dividing the semiconductor layer into a plurality of LED unit structures; the insulating isolation regions penetrate through the second doped semiconductor layer and the active layer and are located within the first doped semiconductor layer; wherein, the first ion is one of a positive ion and a negative ion, and the second ion is the other of the positive ion and the negative ion; A photonic crystal structure located within the insulating isolation region to suppress lateral diffusion of light; A mask layer located on the semiconductor layer, a plurality of implantation region patterns are formed on the mask layer, and the implantation region patterns expose the insulating isolation regions; wherein, the implantation region patterns are in a multi-sided serrated shape.

9. The LED chip structure according to claim 8, wherein, The positive ion includes at least one of silicon ion, boron ion, phosphorus ion, arsenic ion, and magnesium ion; The negative ion includes at least one of fluorine ion, hydrogen ion, and oxygen ion.

10. The LED chip structure according to claim 8, wherein, The distance between the insulating isolation region and the implantation region pattern is 1 to 3 μm.

11. The LED chip structure according to claim 8, wherein, The LED chip structure further includes: A groove located within the insulating isolation region; A passivation layer covering the bottom and side walls of the groove; A metal reflective layer covering the passivation layer; The photonic crystal structure covers the metal reflective layer and fills the groove.

12. The LED chip structure according to claim 8, wherein, The LED chip structure further includes: A first insulating layer, the first insulating layer is located between the substrate and the semiconductor layer, wherein, the material of the first insulating layer includes AlN, AlGaN, or BN.

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