Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device that is easy to miniaturize. A semiconductor device in which parasitic capacitance is reduced is provided. The semiconductor device includes a transistor, first and second insulating layers, and a wiring. The transistor includes first to third conductive layers, a semiconductor layer, and a third insulating layer. The first insulating layer has a first opening to the first conductive layer. The semiconductor layer contacts the second conductive layer on the first insulating layer, a side surface of the first insulating layer of the first opening, and a top surface of the first conductive layer. The second insulating layer has a second opening reaching the semiconductor layer at a position overlapping the first opening. The third insulating layer contacts a side surface of the second insulating layer of the second opening and the semiconductor layer in the first opening. The third conductive layer is embedded in the second and first openings. The wiring is on the second insulating layer, contacts the third conductive layer, and has a portion overlapping the semiconductor layer or the second conductive layer via the second insulating layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a storage device, a display device, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As examples of the technical field of one aspect of the present invention disclosed in this specification and the like, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input / output devices, driving methods of these devices, or manufacturing methods of these devices can be cited. A semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. Background Art

[0003] In recent years, semiconductor devices have been developed, and CPUs, memories, or LSIs other than these are mainly used for semiconductor devices. A CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit formed by processing a semiconductor wafer to form a chip (including at least a transistor and a memory) and having electrodes as connection terminals formed thereon.

[0004] The semiconductor circuits (IC chips) of CPUs, memories, or LSIs other than these are mounted on a circuit board, for example, a printed wiring board, and are used as one of the components of various electronic devices.

[0005] In addition, a technique of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as integrated circuits and image display devices (simply referred to as display devices). As semiconductor thin films that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0006] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU and the like that utilize the characteristic of a small leakage current. In addition, for example, Patent Document 2 discloses a storage device and the like that achieve long-term retention of stored contents.

[0007] In recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for further high-density integration of integrated circuits. In addition, it is required to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Documents 3 and Non-Patent Document 1 disclose a technique in which a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film are stacked, and a plurality of storage units are overlapped to increase the density of the integrated circuit. For example, Patent Document 4 discloses a vertical transistor in which a gate electrode covers the side surface of an oxide semiconductor with a gate insulator interposed therebetween.

[0008] [Prior Art Documents]

[0009] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187

[0011] [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383

[0012] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0013] [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-211537

[0014] [Non-Patent Documents]

[0015] [Non-Patent Document 1] M.Oota et.al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech.Dig., 2019, pp.50-53 Summary of the Invention

[0016] Technical Problem to be Solved by the Invention

[0017] One of the objects of one aspect of the present invention is to provide a semiconductor device that is easy to miniaturize. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device that can achieve high integration. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device that reduces parasitic capacitance. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device that reduces wiring load. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device with a high operating speed.

[0018] One of the objects of one aspect of the present invention is to provide a semiconductor device, a storage device, a display device, or an electronic device having a novel structure. One of the objects of one aspect of the present invention is to at least alleviate at least one of the problems of the prior art.

[0019] Note that the description of these objects does not preclude the existence of other objects. Note that one aspect of the present invention does not need to achieve all of the above objects. In addition, objects other than the above can be extracted from the descriptions of the specification, drawings, claims, etc.

[0020] Means for Solving the Technical Problem

[0021] One aspect of the present invention is a semiconductor device including a transistor, a first insulating layer, a second insulating layer, and wiring. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is located above the first conductive layer and has a first opening reaching the first conductive layer. The second conductive layer is located above the first insulating layer. The semiconductor layer is in contact with the second conductive layer, the side surface of the first insulating layer in the first opening, and the top surface of the first conductive layer. The second insulating layer is located above the semiconductor layer and has a second opening reaching the semiconductor layer at a position overlapping the first opening. The third insulating layer is in contact with the side surface of the second insulating layer in the second opening and the semiconductor layer in the first opening. The third conductive layer is provided so as to be embedded in the second opening and the first opening. The wiring is in contact with the top surface of the third conductive layer and has a portion overlapping the semiconductor layer or the second conductive layer with the second insulating layer interposed therebetween.

[0022] In addition, in the above aspect, the second insulating layer preferably has a portion thicker than the third insulating layer.

[0023] In addition, in the above aspect, it preferably includes a fourth insulating layer between the second conductive layer and the second insulating layer. At this time, the composition of the fourth insulating layer is preferably different from the composition of the second insulating layer. Furthermore, at this time, the fourth insulating layer preferably covers the end portion of the semiconductor layer.

[0024] In addition, in the above aspect, the opening diameter at the upper end of the first opening is preferably larger than the opening diameter at the lower end of the first opening.

[0025] Another aspect of the present invention is a method of manufacturing a semiconductor device, including the following steps: forming a first insulating layer having a first opening; forming a semiconductor layer in contact with the side surface in the first opening of the first insulating layer; forming a second insulating layer so as to cover the first insulating layer and the semiconductor layer; forming a second opening in the second insulating layer that overlaps the first opening and reaches the semiconductor layer; sequentially forming a third insulating layer and a conductive layer in the second opening and the first opening; and forming wiring in contact with the conductive layer on the second insulating layer.

[0026] Another aspect of the present invention is a method of manufacturing a semiconductor device, including the following steps: forming a first insulating layer having a first opening; forming a semiconductor layer in contact with the side surface in the first opening of the first insulating layer; forming a protective layer covering the semiconductor layer; forming a second insulating layer so as to cover the first insulating layer and the protective layer; forming a second opening in the second insulating layer that overlaps the first opening and reaches the protective layer; etching the protective layer overlapping the second opening so that the semiconductor layer is exposed; sequentially forming a third insulating layer and a conductive layer in the second opening and the first opening; and forming wiring in contact with the conductive layer on the second insulating layer.

[0027] Advantages of the Invention

[0028] According to one aspect of the present invention, a semiconductor device that is easy to miniaturize can be provided. In addition, according to one aspect of the present invention, a semiconductor device capable of achieving high integration can be provided. In addition, according to one aspect of the present invention, a semiconductor device with reduced parasitic capacitance can be provided. In addition, according to one aspect of the present invention, a semiconductor device with reduced wiring load can be provided. In addition, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a high operating speed can be provided.

[0029] According to one aspect of the present invention, a semiconductor device, a storage device, a display device, or an electronic device having a novel structure can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be alleviated.

[0030] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have all of the above effects. In addition, effects other than the above can be extracted from the descriptions in the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A and Figure 1B is an example of the structure of a semiconductor device.

[0032] Figures 2A to 2C is an example of the structure of a semiconductor device.

[0033] Figure 3A and Figure 3B is an example of the structure of a semiconductor device.

[0034] Figures 4A to 4D is an example of the structure of a semiconductor device.

[0035] Figures 5A to 5D is an example of the structure of a semiconductor device.

[0036] Figures 6A to 6D is an example of the structure of a semiconductor device.

[0037] Figures 7A to 7D is an example of the structure of a semiconductor device.

[0038] Figures 8A to 8D is a diagram illustrating an example of a method for manufacturing a semiconductor device.

[0039] Figures 9A to 9C is a diagram illustrating an example of a method for manufacturing a semiconductor device.

[0040] Figure 10A and Figure 10B is a diagram illustrating an example of a method for manufacturing a semiconductor device.

[0041] Figure 11A and Figure 11B are diagrams illustrating examples of manufacturing methods of semiconductor devices.

[0042] Figures 12A to 12C are diagrams illustrating examples of manufacturing methods of semiconductor devices.

[0043] Figure 13A and Figure 13B are diagrams illustrating examples of manufacturing methods of semiconductor devices.

[0044] Figures 14A to 14C are examples of the structure of a storage device.

[0045] Figure 15A and Figure 15B are examples of the structure of a storage device.

[0046] Figure 16A and Figure 16B are examples of the structure of a storage device.

[0047] Figure 17A and Figure 17B are examples of the structure of a storage device.

[0048] Figure 18 are examples of the structure of a storage device.

[0049] Figure 19 are examples of the structure of a storage device.

[0050] Figure 20A and Figure 20B are examples of the structure of a storage device.

[0051] Figures 21A to 21D are examples of the structure of a storage device.

[0052] Figure 22 are examples of the structure of a storage device.

[0053] Figure 23A and Figure 23B are examples of the structure of a display device.

[0054] Figure 24 are examples of the structure of a display device.

[0055] Figure 25 are examples of the structure of a display device.

[0056] Figure 26 are examples of the structure of a display device.

[0057] Figures 27A to 27C are examples of the structure of a display device.

[0058] Figure 28A and Figure 28B is an example of the structure of a display device.

[0059] Figures 29A to 29D is an example of the structure of an electronic device.

[0060] Figures 30A to 30F is an example of the structure of an electronic device.

[0061] Figures 31A to 31G is an example of the structure of an electronic device.

[0062] Figure 32A and Figure 32B is an example of the structure of an electronic component.

[0063] Figures 33A to 33C is an example of the structure of a mainframe computer.

[0064] Figure 34A is an example of the structure of space equipment, Figure 34B is an example of the structure of a storage system. Detailed implementation manners

[0065] Next, the implementation manners will be described with reference to the accompanying drawings. However, those of ordinary skill in the art can easily understand the fact that the implementation manners can be implemented in multiple different forms, and the ways and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following implementation manners.

[0066] Note that in the structure of the invention described below, the same reference numerals are used in common between different drawings to denote the same parts or parts having the same functions, and the repeated description thereof is omitted. In addition, when denoting parts having the same functions, the same hatching is sometimes used without particularly attaching reference numerals.

[0067] Note that in each of the drawings described in this specification, for the sake of clarity, the sizes of the respective components, the thicknesses of the layers, and the areas are sometimes exaggerated. Therefore, the present invention is not limited to the dimensions in the drawings.

[0068] The ordinal numbers such as "first" and "second" used in this specification and the like are attached to avoid confusion of the components, and are not for limiting in terms of the number.

[0069] A transistor is a type of semiconductor device and can perform functions such as amplifying current or voltage, and controlling on / off switching operations. The transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs: Thin Film Transistors).

[0070] In addition, in cases where transistors with different polarities are used or the direction of current flow in a circuit changes, etc., the functions of the "source electrode" and "drain electrode" may sometimes be swapped with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be used interchangeably.

[0071] In addition, in this specification, etc., "electrically connected" includes cases where connection is made through "elements having a certain electrical function". Here, there are no particular restrictions on the "elements having a certain electrical function" as long as they can transmit and receive electrical signals between the connection objects. For example, the "elements having a certain electrical function" include switching elements such as transistors, resistors, coils, capacitors, and other elements having various functions in addition to electrodes or wirings.

[0072] Note that in this specification, etc., the top surface shape of a component refers to the contour shape of the component when viewed from a plane. In addition, viewing from a plane means viewing from the normal direction of the surface of the formed surface of the component or the support (e.g., substrate) on which the component is formed.

[0073] Note that in this specification, etc., "the top surface shapes are substantially the same" means that at least a part of the edges of each layer in the stack overlap. For example, it includes cases where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, strictly speaking, there are cases where the edges do not overlap. For example, the upper layer is located inside the lower layer or the upper layer is located outside the lower layer, and such cases can sometimes be said to have "substantially the same top surface shapes".

[0074] Note that hereinafter, expressions of directions such as "upper" and "lower" are basically used according to the directions in the drawings. However, for simplicity, the directions indicated by "upper" or "lower" in the specification may sometimes be inconsistent with the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface (formed surface, support surface, bonding surface, flat surface, etc.) on the side where the laminate is provided in the drawing is located on the upper side of the laminate, the direction may sometimes be described as "lower", or the opposite direction may be described as "upper", etc.

[0075] In addition, in this specification, etc., "film" and "layer" can be swapped with each other. For example, sometimes "insulating layer" and "insulating film" can be swapped with each other.

[0076] (Embodiment 1)

[0077] In this embodiment, an example of the structure and manufacturing method of a semiconductor device according to one aspect of the present invention will be described. Hereinafter, a transistor will be described as an example of a semiconductor device.

[0078] In a transistor according to one aspect of the present invention, the source electrode and the drain electrode are located at different heights (for example, the height in a direction perpendicular to the substrate surface or the insulating plane on which the transistor is provided). Therefore, the current flowing through the semiconductor layer flows in the height direction. That is to say, the channel length direction has a height (vertical) component. Therefore, a transistor according to one aspect of the present invention can be referred to as a vertical transistor, a vertical channel transistor, etc.

[0079] More specifically, an insulating layer serving as a first spacer is provided between the lower electrode of one of the source electrode and the drain electrode of the transistor and the upper electrode of the other. Inside the first opening provided in the insulating layer, a semiconductor layer forming a channel is provided in a manner of connecting the lower electrode and the upper electrode. A gate insulating layer and a gate electrode overlapping the semiconductor layer are provided inside the first opening. Since the source electrode, the semiconductor layer, and the drain electrode can be overlapped and arranged, the occupied area can be significantly reduced compared with a so-called planar transistor in which the semiconductor layer is arranged in a plane.

[0080] Furthermore, a gate wiring electrically connected to the gate electrode is provided. At this time, an insulating layer serving as a second spacer is provided between the gate wiring and the upper electrode. For example, the second spacer is preferably thicker than the gate insulating layer. In addition, the second spacer preferably uses a low dielectric constant material such as silicon oxide or silicon oxynitride. Thereby, the parasitic capacitance between the gate wiring and the upper electrode can be effectively reduced.

[0081] The gate electrode and the gate insulating layer are provided inside the second opening and the first opening, respectively, and the second opening and the first opening are provided in the second spacer and the first spacer, respectively. The top surface of the gate electrode may be in contact with the gate wiring provided on the second spacer.

[0082] Here, the channel length of the transistor can be precisely controlled according to the thickness of the insulating layer used as the first spacer, so the channel length non-uniformity can be significantly reduced compared with the planar transistor. Furthermore, by thinning the insulating layer, transistors with extremely short channel lengths can also be fabricated. For example, transistors with a channel length of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less and 5 nm or more, 7 nm or more, or 10 nm or more can be fabricated. Thus, transistors with extremely small channel lengths that cannot be achieved by mass-production exposure apparatuses can be realized. In addition, transistors with a channel length of less than 10 nm can be realized without using the very expensive exposure apparatuses used in the state-of-the-art LSI technology.

[0083] The transistor according to one embodiment of the present invention can have an extremely small channel length, reduce the occupied area, allow a large current to flow, reduce the parasitic capacitance, and operate at high speed. The transistor according to one embodiment of the present invention can be applied to various semiconductor devices. For example, it can be applied to storage devices, arithmetic devices, display devices, imaging devices, and the like.

[0084] Hereinafter, specific examples will be described with reference to the drawings.

[0085] [Structural Example]

[0086] Figure 1A and Figure 1B are perspective views of the transistor 10, respectively. Figure 1B is a perspective view of a part of Figure 1A removed. In addition, in Figure 1A and Figure 1B , regarding some constituent elements (interlayer insulating layers, etc.), only the outlines indicated by dotted lines are shown.

[0087] Figure 1A and Figure 1B show the X direction, Y direction, and Z direction with arrows. Note that in Figure 1A and Figure 1B , the same symbols of X, Y, and Z are used to represent the directions, but it is not necessary for the directions to be consistent among these drawings.

[0088] Figure 2A is a plan view of the transistor 10, Figure 2B , Figure 2C are cross-sectional schematic views along the cut lines A1 - A2 and B1 - B2 in Figure 2A , respectively. Note that some constituent elements (insulating layers, etc.) are omitted in Figure 2A .

[0089] The transistor 10 is provided on an insulating layer 11, and the insulating layer 11 is provided on a substrate (not shown). The transistor 10 includes a conductive layer 31 serving as one of a source electrode and a drain electrode, a semiconductor layer 21, an insulating layer 22 serving as a gate insulating layer, a conductive layer 23 serving as a gate electrode, and a conductive layer 32 serving as the other of the source electrode and the drain electrode. The conductive layer 31 and the conductive layer 32 are also used as wirings.

[0090] The conductive layer 31 is provided on the insulating layer 11, and an insulating layer 41 is provided on the conductive layer 31. The conductive layer 32 is provided on the insulating layer 41. The insulating layer 41 has an opening 20a reaching the conductive layer 31. The semiconductor layer 21 is provided in contact with the inner wall (also referred to as a side surface, sidewall) of the opening 20a of the insulating layer 41, and is in contact with the top surface of the conductive layer 31, the top surface and the side surface of the conductive layer 32, respectively.

[0091] An insulating layer 42 is provided on the semiconductor layer 21 and the conductive layer 32. The insulating layer 42 has an opening 20b reaching the semiconductor layer 21. The insulating layer 22 is located inside the opening 20a and the opening 20b. The portion of the insulating layer 22 inside the opening 20a is provided along the top surface of the semiconductor layer 21. In addition, the portion of the insulating layer 22 inside the opening 20b is provided along the inner wall of the opening 20b of the insulating layer 42. Furthermore, the conductive layer 23 is provided in a manner of being embedded in the opening 20a and the opening 20b.

[0092] The top surfaces of the insulating layer 42, the insulating layer 22, and the conductive layer 23 are planarized, and the heights of the top surfaces are substantially the same. A conductive layer 33 used as a wiring is provided on the insulating layer 42. The conductive layer 33 is provided in contact with the top surface of the conductive layer 23. The conductive layer 33 is used as a gate wiring, for example.

[0093] Here, the conductive layer 31 is embedded in an insulating layer 44, the conductive layer 32 is embedded in an insulating layer 45, and the conductive layer 33 is embedded in an insulating layer 46. Furthermore, their top surfaces are planarized, and the heights of the top surfaces of the conductive layers and the insulating layers are substantially the same. By adopting such a structure, it is not affected by steps, and thus is preferable. The insulating layer 44, the insulating layer 45, and the insulating layer 46 are used as interlayer insulating layers. For example, it is preferable to use a low dielectric constant inorganic insulating material such as silicon oxide or silicon oxynitride.

[0094] The source electrode and the drain electrode of the transistor 10 having the above structure are located at different heights, so the current flowing through the semiconductor flows in the height direction. That is to say, the channel length direction can have a component in the height direction (vertical direction), so the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc. In the above transistor 10, the source electrode, the semiconductor, and the drain electrode can be overlapped, so the occupied area can be significantly reduced compared with a so-called planar transistor (which can also be called a lateral transistor, an LFET (Lateral FET), etc.) in which the semiconductor is arranged on a plane.

[0095] In addition, the channel length of the transistor 10 can be precisely controlled according to the thickness of the insulating layer 41 used as a spacer, so the channel length non-uniformity can be significantly reduced compared with a planar transistor. Furthermore, by thinning the insulating layer 41, a transistor with an extremely short channel length can also be manufactured. For example, a transistor with a channel length of 50 nm or less, 30 nm or less, or 20 nm or less and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured. Therefore, even by using an existing mass-production exposure apparatus instead of a very expensive exposure apparatus used in the most advanced LSI technology, a transistor with a channel length less than 10 nm can be realized.

[0096] The semiconductor layer 21 can use various semiconductor materials, and it is particularly preferable to use an oxide semiconductor including a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor with both a high on-state current and an extremely low off-state current can be realized at low cost. Hereinafter, without special emphasis, a preferred structural example of the case where an oxide semiconductor is used as the semiconductor layer 21 will be described.

[0097] The top surfaces of the conductive layer 31 and the conductive layer 32 are in contact with the semiconductor layer 21. Therefore, when an oxide semiconductor is used as the semiconductor layer 21, due to the influence of the deposition process of the semiconductor film that will become the semiconductor layer 21 or subsequent heating, etc., the surfaces near the exposed surfaces of the conductive layer 31 and the conductive layer 32 are oxidized, and an insulating oxide film is formed between the semiconductor layer 21, and sometimes the contact resistance increases. Then, at least the uppermost part of the conductive layer 31 and the conductive layer 32 preferably uses an oxide conductor containing a conductive oxide. Thereby, an increase in the contact resistance due to the surface oxidation of the conductive layer 31 and the conductive layer 32 can be prevented. The conductive layer 31 and the conductive layer 32 can also be called an oxide layer, a metal oxide layer, an oxide conductor layer, etc.

[0098] Conductive layer 31 can be used as one of source wiring and drain wiring. In addition, conductive layer 32 can be used as the other of source wiring and drain wiring. In this way, when one or both of conductive layer 31 and conductive layer 32 are used as wiring, it is preferred that the resistance is low. For this reason, it is preferred to use a material having a higher conductivity than an oxide conductor, such as a metal, an alloy or their nitride. In particular, one or both of conductive layer 31 and conductive layer 32 preferably has a stacked structure including a layer composed of the material having a high conductivity, wherein at least the uppermost portion uses the above-mentioned oxide conductor.

[0099] Here, the transistor 10 is provided at the intersection of the conductive layer 33 used as the gate wiring and the conductive layer 32 used as the source wiring or the drain wiring. Therefore, at the intersection of the conductive layer 33 and the conductive layer 32, a parasitic capacitance is generated in the overlapping portion thereof. However, in one embodiment of the present invention, an insulating layer 42 is provided between the conductive layer 33 and the conductive layer 32, thereby significantly reducing the parasitic capacitance compared to a case where there is no insulating layer 42 (for example, a case where the conductive layer 33 and the conductive layer 32 overlap with the insulating layer 22).

[0100] Furthermore, by increasing the thickness of the insulating layer 42, the parasitic capacitance between the conductive layer 33 and the conductive layer 32 can be reduced. For example, the insulating layer 42 can be thicker than the insulating layer 22. In addition, the insulating layer 42 is more preferably thicker than at least one of the insulating layer 44, the insulating layer 45, and the insulating layer 46. The thicker the insulating layer 42 is, the more preferably it is, thereby reducing the parasitic capacitance between the conductive layer 33 and the conductive layer 32, as long as productivity is considered. For example, the thickness of the insulating layer 42 can be less than 2 times or less than 3 times the thickness of the insulating layer 41.

[0101] exist Figure 2B and Figure 2C In FIG. 1 , a laminated film including an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c is shown as Figure 1A and Figure 1B In the case of the insulating layer 41. In addition, Figure 3A yes Figure 2B Magnified image of .

[0102] The semiconductor layer 21 is arranged in a manner in contact with the side (also referred to as the inner wall) of the insulating layer 41b in the opening 20a. The insulating layer 41b preferably uses an oxide insulating film. In particular, it is preferred to use an oxide insulating film that releases oxygen by heating. In addition, it is preferred to adopt a structure in which the insulating layer 41b is sandwiched by the insulating layer 41a and the insulating layer 41c that have a barrier property to oxygen. As a result, the oxygen contained in the insulating layer 41b can be enclosed in the area surrounded by the insulating layer 41a, the insulating layer 41c and the semiconductor layer 21, and the oxygen in the insulating layer 41b can be prevented from detaching and decreasing during the process, so that oxygen can be supplied from the insulating layer 41b to the semiconductor layer 21 more efficiently.

[0103] The portion of the semiconductor layer 21 that contacts the insulating layer 41b is a region where oxygen vacancies are reduced, and can be said to be an i-type region. On the other hand, the portion that does not contact the insulating layer 41b is preferably an n-type region containing a plurality of carriers. That is, the portion of the semiconductor layer 21 that contacts the insulating layer 41b can be referred to as a channel formation region, and the outer region thereof can be referred to as a low resistance region (also referred to as a source region or a drain region). Figure 3A In FIG. 1 , the channel formation region 21 i and the low resistance region 21 n of the semiconductor layer 21 are given different hatchings.

[0104] At this time, if Figure 3A As shown, the channel length L of the transistor 10 can be said to be the length of the portion that contacts the insulating layer 41b and is located on the shortest distance path connecting the portion that contacts the conductive layer 31 and the portion that contacts the conductive layer 32 in the semiconductor layer 21. When the angle (θ) of the side wall of the opening 20a of the insulating layer 41b is 90 degrees, the channel length L is consistent with the thickness of the insulating layer 41b. By making θ less than (or greater than) 90 degrees, the channel length L can be increased.

[0105] On the other hand, the channel width W of the transistor 10 depends on the shape of the opening 20 a . Figure 3B From the Z direction, along Figure 3A A plan view of the truncated surface when the truncation line C1-C2 at the height where the insulating layer 41b is provided is truncated. Here, the case where the opening 20a has a cylindrical shape is shown. When the outline of the opening 20a is a circle with a diameter R, the channel width W can be regarded as the circumference of the opening 20a (that is, W=π×R). Here, when the angle θ of the side wall of the opening 20a of the insulating layer 41b is offset from 90 degrees, the circumference of the opening 20a is different according to the height. At this time, the circumference of the height where the diameter of the opening 20a is the smallest can be regarded as the channel width W, or the circumference of the height of the upper end of the opening 20a can be regarded as the channel width W.

[0106] Since the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20a of the insulating layer 41b, the thickness of this part is sometimes thinned depending on the deposition method. For example, in deposition methods such as sputtering or plasma CVD, the thickness of the film deposited on a surface inclined or perpendicular to the substrate surface tends to be thinner than the thickness of the film deposited on a surface parallel to the substrate surface. On the other hand, when a deposition method such as atomic layer deposition (ALD) or thermal CVD is used, a film of uniform thickness can be deposited regardless of the angle of the formed surface. For example, when the angle θ of the side wall of the opening 20a of the insulating layer 41b is greater than 75 degrees, greater than 80 degrees, or greater than 85 degrees, it is preferred to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0107] The diameter of the opening 20b provided in the insulating layer 42 is preferably equal to or greater than the diameter of the opening 20a provided in the insulating layer 41b. By making the opening 20b larger than the opening 20a, it is possible to prevent the opening 20a from being clogged due to the non - overlap of the opening 20a and the opening 20b caused by a misalignment in the position when forming the opening 20b.

[0108] Here, the thickness of the insulating layer 42 can also be equal to or greater than the channel length L. For example, by setting the thickness of the insulating layer 42 to be greater than the thickness of the insulating layer 41b, the parasitic capacitance can be more effectively reduced.

[0109] [Constituent elements]

[0110] [Substrate]

[0111] As the substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria - stabilized zirconia substrate), a resin substrate, etc. can be cited. In addition, as the semiconductor substrate, for example, a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be cited. Also, a semiconductor substrate having an insulator region inside the above - mentioned semiconductor substrate, such as a SOI (Silicon On Insulator) substrate, etc. can be cited. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can also be used. In addition, an insulator substrate provided with a conductive layer or a semiconductor layer, a semiconductor substrate provided with a conductive layer or an insulating layer, a conductor substrate provided with a semiconductor layer or an insulating layer, etc. can be cited. Alternatively, a substrate provided with elements on these substrates can also be used. As the elements provided on the substrate, a capacitor, a resistor, a switching element, a light - emitting element, a storage element, etc. can be cited.

[0112] [Semiconductor layer]

[0113] The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0114] As the metal oxide that can be used for the semiconductor layer 21, for example, In oxide, Ga oxide, and Zn oxide can be cited. The metal oxide preferably contains at least In or Zn. In addition, the metal oxide preferably contains two or three selected from In, element M, and Zn. Note that element M is a metal element or a semi-metal element with a high bond energy with oxygen, for example, a metal element or a semi-metal element with a higher bond energy with oxygen than In. As element M, specifically, Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb, etc. can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, and more preferably Ga. Note that hereinafter, the metal oxide containing In, M, and Zn is sometimes referred to as In-M-Zn oxide. Note that in this specification, etc., the metal element and the semi-metal element are sometimes collectively referred to as "metal element", and the "metal element" described in this specification, etc. sometimes includes the semi-metal element.

[0115] When using In-M-Zn oxide as the metal oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or higher than the atomic ratio of M. For example, as the atomic ratio of the metal elements of such In-M-Zn oxide, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions near them, etc. can be cited. Note that the compositions near them include the range of ±30% of the desired atomic ratio. By increasing the atomic ratio of In in the metal oxide, the on-state current or field-effect mobility of the transistor can be improved.

[0116] The atomic ratio of In in the In-M-Zn oxide can also be less than the atomic ratio of element M. For example, as the atomic ratio of the metal elements of such In-M-Zn oxide, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions near them, etc. can be cited. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0117] The semiconductor layer 21 can be, for example, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. In addition, Ga-Zn oxide can also be used.

[0118] The metal oxide can also replace In or contain one or more metal elements with a large period number in addition to In. There is a tendency that the larger the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, when a metal element with a large period number is included, the field-effect mobility of the transistor can sometimes be improved. As the metal element with a large period number, a metal element belonging to the 5th period and a metal element belonging to the 6th period, etc. can be cited. As this metal element, specifically, Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu, etc. can be cited. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0119] In addition, the metal oxide can also contain one or more non-metal elements. When the metal oxide contains a non-metal element, the field-effect mobility of the transistor can sometimes be improved. As the non-metal element, for example, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen, etc. can be cited.

[0120] The metal oxide can be formed by appropriately using a sputtering method or an atomic layer deposition method. Note that in the case of forming a metal oxide by a sputtering method, the composition of the deposited metal oxide is sometimes different from the composition of the target. In particular, the content rate of zinc in the deposited metal oxide sometimes decreases to about 50% of the content rate of zinc in the target.

[0121] In this specification, etc., the content rate of a certain metal element in the metal oxide means the ratio of the number of atoms of this element to the total number of atoms of the metal elements contained in the metal oxide. For example, when the metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in this metal oxide are A X , A Y , A Z respectively, the content rate of metal element X can be expressed as A X / (A X + A Y + A Z)。In addition, when the atomic number ratio (atomic ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is expressed as B X : B Y : B Z ), the content rate of metal element X can be expressed as B X / (B X +B Y +B Z ).

[0122] For example, when using a metal oxide containing In, a transistor with a large on-state current can be realized by increasing the content rate of In.

[0123] By using a metal oxide that does not contain Ga or has a low Ga content rate in the semiconductor layer 21, a transistor with high reliability for positive bias application can be realized. That is, a transistor with a small variation in threshold voltage in the PBTS (Positive Bias Temperature Stress) test can be realized. In addition, when using a metal oxide containing Ga, the Ga content rate is preferably lower than the In content rate. Thereby, a transistor with high mobility and high reliability can be realized.

[0124] On the other hand, by increasing the Ga content rate, a transistor with high reliability for light can be realized. That is, a transistor with a small variation in threshold voltage in the NBTIS (Negative Bias Temperature Illumination Stress) test can be realized. Specifically, the bandgap of a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In is larger, and the variation in threshold voltage in the NBTIS test of the transistor can be reduced.

[0125] In addition, by increasing the content rate of zinc, a metal oxide with high crystallinity can be obtained, and the diffusion of impurities in the metal oxide can be suppressed. Thereby, the variation in the electrical characteristics of the transistor is suppressed, and the reliability can be improved.

[0126] The semiconductor layer 21 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 21 may be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers having the same composition, for example, it can be formed using the same sputtering target, so that the manufacturing cost can be reduced. Note that a stacked structure of two or more oxide semiconductor layers having different compositions may also be adopted. In addition, by using the ALD method, a metal oxide layer having a continuously varying composition in the thickness direction can be formed. Thereby, compared with the case of using a film having a predetermined composition, not only the design selection range can be expanded, but also the generation of interface states and the like generated between two layers having different compositions can be prevented, so that the electrical characteristics and reliability can be improved.

[0127] In the case where the semiconductor layer 21 has a two-layer structure, it is preferable to use a material (a material having high conductivity) having a higher mobility than that of the first layer in the second layer, that is, the layer closer to the gate electrode side. Thereby, a normally-off transistor with a large on-state current can be formed. Therefore, low power consumption and high performance can be achieved at the same time. In addition, a material having a higher mobility than that of the second layer may also be used in the first layer, that is, the layer in contact with the source electrode and the drain electrode. Thereby, the contact resistance between the semiconductor layer 21 and the source electrode or the drain electrode can be reduced, so that the parasitic resistance can be reduced, and a transistor with a large on-state current can be formed.

[0128] In addition, in the case where the semiconductor layer 21 has a three-layer structure, it is preferable to use a material having a higher mobility than those of the first and third layers in the second layer. Thereby, a transistor with a high on-state current and high reliability can be realized.

[0129] For example, the above-mentioned high or low mobility or high or low conductivity may be replaced with high or low indium content. In addition to this, the following factors also affect the mobility and conductivity: the presence or absence of an element other than indium that contributes to improving conductivity or the content of this element, etc. As an example of a high-mobility material, for example, materials around In:Ga:Zn = 4:3:2 [atomic ratio], materials around In:Zn = 1:1 [atomic ratio], materials around In:Zn = 4:1 [atomic ratio], materials around In:Sn:Zn = 40:X:10 [atomic ratio] (X is 0.1 or more and 5 or less, typically X = 1), etc. can be cited. On the other hand, as materials having a lower mobility or conductivity than the above materials, materials around In:Ga:Zn = 1:3:2 [atomic ratio], materials around In:Ga:Zn = 1:3:4 [atomic ratio], materials around In:Ga:Zn = 2:2:1 [atomic ratio], materials around In:Ga:Zn = 1:1:1 [atomic ratio], materials around In:Ga:Zn = 1:1:2 [atomic ratio], etc. can be cited.

[0130] As the semiconductor layer 21, a metal oxide layer having crystallinity is preferably used. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (nc: nano-crystal) structure, etc., which will be described later, can be used. By using a metal oxide layer having crystallinity for the semiconductor layer 21, the density of defect states in the semiconductor layer 21 can be reduced, and thus a highly reliable semiconductor device can be realized.

[0131] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of flowing a large current can be realized.

[0132] Compared with a transistor using amorphous silicon, the field-effect mobility of a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) is very high. In addition, the leakage current between the source and the drain in the off state of the OS transistor (hereinafter, also referred to as the off-state current) is extremely low, and the charge stored in a capacitor connected in series with the transistor can be maintained for a long period. In addition, by using an OS transistor, the power consumption of the semiconductor device can be reduced.

[0133] A semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device. When increasing the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. For this purpose, it is necessary to increase the source-drain voltage of the driving transistor included in the pixel circuit. Since the breakdown voltage between the source and the drain of the OS transistor is higher than that of a transistor using silicon (hereinafter referred to as an Si transistor), a high voltage can be applied between the source and the drain of the OS transistor. Thus, by using an OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be increased, and the emission luminance of the light-emitting device can be increased.

[0134] When the transistor operates in the saturation region, compared with the Si transistor, the OS transistor can make the change in the source-drain current with respect to the change in the gate-source voltage small. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. Thereby, the number of gray levels of the pixel circuit can be increased. In addition, even if there are variations in the electrical characteristics (e.g., resistance) or non-uniformity in the electrical characteristics of the light-emitting device, a stable current can flow.

[0135] As described above, by using an OS transistor as the driving transistor included in the pixel circuit, "suppression of black smear", "increase in emission luminance", "multi-gradation", "suppression of the influence of manufacturing non-uniformity of the light-emitting device", etc. can be realized.

[0136] The OS transistor has small changes in electrical characteristics caused by irradiated rays, that is, it has high tolerance to rays. Therefore, it can be appropriately used in an environment where incident rays may exist. The OS transistor can also be said to have high reliability for rays. For example, the OS transistor can be appropriately used as a pixel circuit of an X-ray flat panel detector. In addition, the OS transistor can be appropriately used for semiconductor devices used in outer space. As rays, electromagnetic radiation rays (for example, X-rays and γ-rays) and particle rays (for example, α-rays, β-rays, proton radiation, and neutron rays) can be cited.

[0137] Note that the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, a semiconductor composed of a single element or a compound semiconductor can be used. As the semiconductor composed of a single element, silicon (including single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon) or germanium, etc. can be cited. As the compound semiconductor, for example, gallium arsenide, silicon germanium can be cited. As the compound semiconductor, for example, an organic semiconductor, a nitride semiconductor, or an oxide semiconductor, etc. can be cited. Note that these semiconductor materials can also contain impurities as dopants.

[0138] Alternatively, the semiconductor layer 21 can also have a layered material used as a semiconductor. The layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by a bonding weaker than covalent bonds and ionic bonds such as van der Waals bonding. The layered material has high conductivity in a unit layer, that is, it has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

[0139] As the above-mentioned layered material, for example, graphene, silicene, chalcogenide, etc. can be cited. Chalcogenide is a compound containing a chalcogen element (an element belonging to Group 16). In addition, as chalcogenide, transition metal chalcogenide, Group 13 chalcogenide, etc. can be cited. As the transition metal chalcogenide that can be used as the semiconductor layer of the transistor, specifically, molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum telluride (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten telluride (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2)), zirconium selenide (typically ZrSe 2 ), etc.

[0140] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 21, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (polycrystalline semiconductor, microcrystalline semiconductor, or a semiconductor having a crystal region in a part thereof) can be used. When using a semiconductor having crystallinity, deterioration of the transistor characteristics can be suppressed, so it is preferable.

[0141] <Gate insulating layer>

[0142] The insulating layer 22 is used as the gate insulating layer of the transistor and also as the dielectric layer of the capacitor. When an oxide semiconductor is used for the semiconductor layer 21, an oxide insulating film is preferably used as at least the film in the insulating layer 22 that contacts the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used. In addition to this, nitride insulating films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride can also be used as the insulating layer 22. Furthermore, the insulating layer 22 can also have a stacked structure, for example, it can also have a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0143] In this specification, etc., oxynitride refers to a material having a higher oxygen content than nitrogen content. Nitrogen oxide refers to a material having a higher nitrogen content than oxygen content.

[0144] Furthermore, the insulating layer 22 is preferably used by laminating an insulating material made of a high-k material, and a stacked structure of a material having a high relative permittivity (high-k) and a material having a dielectric strength greater than that of the high-k material is preferably used. For example, as the insulating layer 22, an insulating film (also called ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in sequence can be used. In addition, for example, an insulating film (also called ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in sequence can be used. By laminating an insulator having a larger dielectric strength such as aluminum oxide and using it, the dielectric strength can be increased and electrostatic breakdown of the capacitor can be suppressed.

[0145] Furthermore, a material exhibiting ferroelectricity can also be used as the insulating layer 22. As the material exhibiting ferroelectricity, metal oxides such as hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0), etc. can be cited.

[0146] <Conductive layer>

[0147] The top surfaces of the conductive layer 31 and the conductive layer 32 are in contact with the semiconductor layer 21. Here, when an oxide semiconductor is used as the semiconductor layer 21, if a metal that is easily oxidized such as aluminum is used for the upper part of the conductive layer 31 or the conductive layer 32, an insulating oxide (such as aluminum oxide) may be formed between the conductive layer 31 or the conductive layer 32 and the semiconductor layer 21, hindering conduction between them. Therefore, at least the uppermost part of the conductive layer 31 and the conductive layer 32 is preferably made of a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, or an oxide conductive material.

[0148] As the conductive layer 31 and the conductive layer 32, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. They are conductive materials that are not easily oxidized or materials that maintain conductivity even when oxidized, so they are preferable.

[0149] Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, Ga-Zn oxide, etc. can be used. In particular, a conductive oxide containing indium is preferably used because of its high conductivity. In addition, oxide materials such as In-Ga-Zn oxide that can be applied to the above-mentioned semiconductor layer 21 can also be used for the conductive layer by increasing the carrier concentration.

[0150] The conductive layer 23 serves as a gate electrode, and various conductive materials can be used. As the conductive layer 23, for example, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., and an alloy composed of the metal element. In addition, nitrides of the above metals or alloys or oxides of the above metals or alloys can also be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, highly conductive semiconductors represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0151] In addition, the conductive layer 23 can also use the nitrides and oxides that can be used for the conductive layer 31 and the conductive layer 32 described above.

[0152] Since the conductive layer 31 and the conductive layer 32 are also used as wirings, a conductive material with a low resistance can also be used in a stacked manner. In addition, the lower the resistance of the conductive layer 33, the more preferable. As the conductive layer 31, the conductive layer 32, and the conductive layer 33, the same conductive materials as those of the above-mentioned conductive layer 23 can be used.

[0153] <Insulating layer>

[0154] The insulating layer 41 (or insulating layer 41b) has a portion in contact with the semiconductor layer 21. When an oxide semiconductor is used for the semiconductor layer 21, in order to improve the interface characteristics between the semiconductor layer 21 and the insulating layer 41, preferably, at least the portion of the insulating layer 41 in contact with the semiconductor layer 21 is made of an oxide. For example, silicon oxide or silicon oxynitride can be appropriately used.

[0155] In addition, the insulating layer 41 is more preferably a film that releases oxygen by heating. Thereby, oxygen can be supplied to the semiconductor layer 21 by the heat applied in the manufacturing process of the transistor 10, oxygen vacancies in the semiconductor layer 21 can be reduced, and the reliability can be improved. As a method of supplying oxygen to the insulating layer 41, heat treatment in an oxygen atmosphere, plasma treatment in an oxygen atmosphere, etc. can be cited. In addition, oxygen can also be supplied to the insulating layer 41 by depositing an oxide film on the top surface of the insulating layer 41 in an oxygen atmosphere using a sputtering method. Then, this oxide film can also be removed.

[0156] The insulating layer 41 is preferably formed by a deposition method such as a sputtering method or a plasma CVD method. In particular, by depositing using a deposition method that does not use hydrogen gas as a deposition gas by the sputtering method, a film with extremely low hydrogen content can be formed. Thereby, the supply of hydrogen to the semiconductor layer 21 can be suppressed and the electrical characteristics of the transistor 10 can be stabilized.

[0157] As the insulating layer 41a and the insulating layer 41c, a film that does not easily diffuse oxygen is preferably used. Thereby, oxygen in the insulating layer 41b can be prevented from permeating through the insulating layer 41a to the insulating layer 11 side and through the insulating layer 41c to the insulating layer 45 side due to heating. In other words, by sandwiching the insulating layer 41b with the insulating layer 41a and the insulating layer 41c that do not easily diffuse oxygen above and below, the oxygen in the insulating layer 41b can be sealed. Thereby, oxygen can be effectively supplied to the semiconductor layer 21.

[0158] As the insulating layer 41a and the insulating layer 41c, for example, one or more of silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. In particular, silicon nitride and silicon oxynitride have the characteristics of rarely releasing impurities (such as water and hydrogen) and not easily allowing oxygen and hydrogen to permeate, so they can be appropriately used as the insulating layer 41a and the insulating layer 41c.

[0159] [Modification example]

[0160] Examples in which a part is different from the above structural example will be described below. Note that the description of parts that overlap with the above content may sometimes be omitted.

[0161] <Modification example 1>

[0162] Figure 4A and Figure 4B is a cross-sectional schematic view of the transistor 10a. The difference between the transistor 10a and the above-mentioned transistor 10 mainly lies in the shape of the opening 20b.

[0163] In the transistor 10a, the end of the semiconductor layer 21 is located inside the opening 20b. In addition, the opening 20b reaches not only the semiconductor layer 21 but also a part of the conductive layer 32 and a part of the insulating layer 45. Thus, a part of the insulating layer 22 is disposed in contact with the conductive layer 32 and the insulating layer 45.

[0164] In this way, by increasing the diameter of the opening 20b, the contact area between the conductive layer 23 and the conductive layer 33 can be increased, and thus the contact resistance between the conductive layer 23 and the conductive layer 33 can be reduced.

[0165] <Modification Example 2>

[0166] Figure 4C and Figure 4D is a cross-sectional schematic view of the transistor 10b. The difference between the transistor 10b and the above-mentioned transistor 10 mainly lies in that the transistor 10b includes an insulating layer 47.

[0167] The insulating layer 47 is located between the conductive layer 32 and the insulating layer 42 and between the insulating layer 45 and the insulating layer 42. In addition, the insulating layer 47 is disposed so as to cover the end of the semiconductor layer 21.

[0168] The insulating layer 47 can be used as an etch stop layer when forming the opening 20b in the insulating layer 42. By providing the insulating layer 47, damage to the semiconductor layer 21 can be reduced when forming the opening 20b.

[0169] As the insulating layer 47, an insulating material that can increase the selectivity ratio with respect to the etching rate of the insulating layer 42 can be used. The insulating layer 47 uses at least an insulating film having a different composition or density from that of the insulating layer 42. The following structure can be adopted: the insulating layer 47 contains constituent elements different from those of the insulating layer 42; the insulating layer 42 contains constituent elements different from those of the insulating layer 47; the insulating layer 47 and the insulating layer 42 contain the same constituent elements.

[0170] For example, the insulating layer 42 can use a silicon oxide film or a silicon oxynitride film, and the insulating layer 47 can use an insulating film having at least one of its composition and constituent elements different from those of the insulating layer 42, such as a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a hafnium oxide film, etc. In addition, by using an insulating film formed by a sputtering method as the insulating layer 42 and using a dense insulating film formed by a deposition method such as a CVD method or an ALD method as the insulating layer 47, an insulating film (for example, a silicon oxide film) containing the same constituent elements can also be adopted.

[0171] <Modified Example 3>

[0172] Figure 5A and Figure 5B The transistor 10c shown is an example of the case where the side wall of the opening 20a has a tapered shape. In the transistor 10c, the diameter (opening diameter) of the upper end of the opening 20a is larger than the diameter (opening diameter) of the lower end.

[0173] Since the side wall of the opening 20a has a tapered shape, the coverage of the semiconductor layer 21, the insulating layer 22, etc. is improved, and even when a deposition method such as a sputtering method is used, generation of defects such as a low-density region in the film can be suppressed. For example, the angle θ can be 45 degrees or more and 90 degrees or less, 60 degrees or more and less than 90 degrees, or 70 degrees or more and less than 90 degrees. In addition, when a deposition method with extremely high coverage such as the ALD method is used, the angle θ can also be greater than 90 degrees.

[0174] When the side wall of the opening 20a has a tapered shape, the diameter of the opening 20a corresponding to the channel width of the transistor 10c becomes larger from the side of the conductive layer 31 toward the side of the conductive layer 32. At this time, the magnitude of the current flowing through the transistor 10c is limited by the portion with the smallest diameter. Therefore, the channel width of the transistor 10c can be regarded as the perimeter of the portion with the smallest diameter. Therefore, by having the side wall of the opening 20a have a tapered shape, a transistor having a channel width smaller than the diameter of the upper end of the opening 20a can be manufactured.

[0175] In addition, Figure 5C and Figure 5D The transistor 10d shown is an example of the case where both the opening 20a and the opening 20b have a tapered shape. Furthermore, the transistor 10d includes an insulating layer 46.

[0176] As Figure 5C and Figure 5D shown, the diameter of the upper end of the opening 20b is preferably larger than the diameter of the lower end of the opening 20b, whereby the contact area between the conductive layer 23 and the conductive layer 33 can be increased.

[0177] <Modified Example 4>

[0178] Figure 6A and Figure 6B The main difference between the transistor 10e shown and the above-mentioned transistors 10, 10a, etc. is that the transistor 10e includes a conductive layer 26 and an insulating layer 27.

[0179] The conductive layer 26 is used as the second gate electrode (or back gate electrode). In addition, the insulating layer 27 is located between the conductive layer 26 and the semiconductor layer 21 and is used as the second gate insulating layer (or back gate insulating layer). The conductive layer 26 can be supplied with a fixed potential or any signal. By providing the conductive layer 26 and supplying an appropriate potential to the conductive layer 26, the potential of the back-channel side of the semiconductor layer 21 can be fixed, thereby reducing the non-uniformity of the electrical characteristics. In addition, the conductive layer 26 can also be electrically connected to any one of the conductive layer 31, the conductive layer 32, and the conductive layer 23 to be supplied with the same potential.

[0180] The conductive layer 26 is embedded in the insulating layer 41b. Therefore, the conductive layer 26 is disposed between the insulating layer 41a and the insulating layer 41c. The insulating layer 27 is disposed along the sides of the conductive layer 32, the insulating layer 41c, the conductive layer 26, and the insulating layer 41a. For example, openings are formed in the conductive layer 32, the insulating layer 41c, the conductive layer 26, and the insulating layer 41a, an insulating film covering the openings is formed using a deposition method with high coverage, and then anisotropic etching is performed, whereby the insulating layer 27 can be formed.

[0181] <Modification Example 5>

[0182] Figure 6C and Figure 6D The transistor 10f shown is mainly different from the transistors 10 and 10a, etc. in the shape of the conductive layer 31.

[0183] A recess is provided in the conductive layer 31, and the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are provided along the recess. At this time, the height of the lower end of the conductive layer 23 is preferably lower than the height of the top surface of the conductive layer 31.

[0184] In the transistor 10f, the portion of the semiconductor layer 21 in contact with the conductive layer 31 is a region having a lower resistance than the channel formation region. Therefore, by making the height of the lower end of the conductive layer 23 lower than the top surface of the conductive layer 31, the gate electric field can be uniformly applied to the entire channel formation region of the semiconductor layer 21, thereby preventing the formation of a high-resistance region (bias region) due to the difficulty of applying the gate electric field in the semiconductor layer 21. Therefore, a transistor with an increased on-state current can be realized. To achieve such a structure, for example, the thickness of the conductive layer 31 is preferably at least thicker than the sum of the thickness of the semiconductor layer 21 and the thickness of the insulating layer 22.

[0185] <Modification Example 6>

[0186] Figure 7A and Figure 7B The transistor 10g shown is mainly different from the transistor 10, etc. in the structure of the insulating layer 22.

[0187] The insulating layer 22 covers not only the semiconductor layer 21 but also the conductive layer 32 and the insulating layer 45. A part of the insulating layer 22 is located between the conductive layer 32 and the insulating layer 42, and another part is located between the insulating layer 45 and the insulating layer 42. An opening 20b reaching the insulating layer 22 is provided in the insulating layer 42, and the conductive layer 23 is provided in such a way as to be embedded in the opening 20b. A part of the conductive layer 23 is provided in contact with the side surface in the opening 20b of the insulating layer 42.

[0188] In the case of adopting the structure of the transistor 10g, there is a concern as follows: when the opening 20b of the insulating layer 42 is formed, the insulating layer 22 is etched and disappears. Therefore, as at least the uppermost part of the insulating layer 22, it is preferable to use a material that can increase the selectivity ratio with respect to the etching rate of the insulating layer 42. Specifically, the same insulating material as the above-mentioned insulating layer 47 can be used. For example, the insulating layer 22 can have either a single-layer structure including this insulating material or a laminated structure in which this insulating material is used for the uppermost film.

[0189] In addition, since the insulating layer 22 is sometimes partially etched and thinned when the opening 20b is formed, it is also possible to pre-form a thicker film for use.

[0190] Figure 7C and Figure 7D The transistor 10h shown is an example in the case where the insulating layer 22 shown in this modification example is applied to the transistor 10c shown in the above-mentioned modification example 3. In addition, without being limited thereto, the insulating layer 22 shown in this modification example can also be applied to each of the structures shown above.

[0191] The above is the description of the modification example.

[0192] [Manufacturing Method Example 1]

[0193] Next, a manufacturing method of a semiconductor device according to one aspect of the present invention will be described. Here, an example of the manufacturing method of the above-mentioned transistor 10 will be described.

[0194] Figures 8A to 11B are cross-sectional schematic views in each process of the manufacturing method of the semiconductor device shown below. In each drawing, the cross-sections corresponding to Figure 2B and Figure 2C are shown side by side on the left and right.

[0195] Hereinafter, for the insulating material for forming the insulating layer, the conductive material for forming the conductive layer, or the semiconductor material for forming the semiconductor layer, deposition such as sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be appropriately used.

[0196] As the sputtering method, there can be mentioned an RF sputtering method using a high-frequency power source as a sputtering power source, a DC sputtering method using a DC power source, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal conductive film. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides by a reactive sputtering method.

[0197] Note that the CVD method can be classified into a plasma CVD method (PECVD) using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0198] By using the plasma enhanced CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used in the thermal CVD method, plasma damage to the object to be processed can be reduced. In addition, in the thermal CVD method, plasma damage during deposition does not occur, so a film with fewer defects can be obtained.

[0199] As the ALD method, there are a thermal ALD method in which only heat energy is used to react a precursor and a reactant, a PEALD method using a reactant excited by plasma, etc.

[0200] The CVD method and the ALD method are different from the sputtering method. The CVD method and the ALD method are deposition methods with good step coverage and are not easily affected by the shape of the object to be processed. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for forming a film covering the surface of an opening with a high aspect ratio. However, since the deposition rate of the ALD method is relatively slow, it is sometimes preferably used in combination with other deposition methods such as the CVD method with a high deposition rate.

[0201] In addition, when using the CVD method, a film with an arbitrary composition can be deposited according to the flow rate ratio of the source gas. For example, when using the CVD method, a film with a continuously changing composition can be deposited by changing the flow rate ratio of the source gas while performing deposition. When depositing while changing the flow rate ratio of the source gas, since the time required for transferring or adjusting the pressure is not required, the deposition time can be shortened compared to the case of depositing using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0202] When using the ALD method, a film with an arbitrary composition can be deposited by simultaneously introducing a plurality of different precursors. Alternatively, when introducing a plurality of different precursors, a film with an arbitrary composition can be deposited by controlling the number of cycles of each precursor. In addition, similar to the CVD method, a film with a continuously changing composition can be deposited.

[0203] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate. As the insulating layer 11, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. The deposition of the insulating layer 11 can utilize a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. When the surface of the insulating layer 11 to be formed is uneven, it is preferable to perform a planarization process after depositing the insulating layer 11 so that the top surface of the insulating layer 11 becomes flat.

[0204] Next, a conductive film that will become the conductive layer 31 is formed on the insulating layer 11. Next, a resist mask is formed on the conductive film by a photolithography method or the like, and the portion of the conductive film not covered by the resist mask is removed by etching, and then the resist mask is removed. Thus, the conductive layer 31 can be formed. Next, by depositing an insulating film that will become the insulating layer 44 and removing the portion overlapping with the conductive layer 31, the insulating layer 44 and the conductive layer 31 embedded in the insulating layer 44 can be formed ( Figure 8A ). The processing of the insulating film that will become the insulating layer 44 is preferably performed by a CMP (Chemical Mechanical Polishing) method. For example, by processing the insulating film until the top surface of the conductive layer 31 is exposed, the Figure 8A insulating layer 44 shown can be formed.

[0205] In addition, it is also possible to first form an insulating film that will become the insulating layer 44, then form an opening in the insulating film, and form a conductive film in the opening so as to be embedded therein, and perform a polishing process (planarization process) by the CMP method until the top surface of the insulating film is exposed, thereby forming the insulating layer 44 and the conductive layer 31.

[0206] By performing a planarization process so that the heights of the top surfaces of the insulating layer 44 and the conductive layer 31 are the same, the top surface of the insulating layer 41 formed later can be made flat. Note that the insulating layer 41 can be provided to cover the conductive layer 31 without providing the insulating layer 44. In this case, it is preferable to perform a planarization process on the top surface of the insulating layer 41 by the CMP method to make the top surface flat.

[0207] Next, an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c (hereinafter sometimes collectively referred to as the insulating layer 41) are formed on the conductive layer 31 and the insulating layer 44 ( Figure 8B ). The insulating layer 41a, the insulating layer 41b, and the insulating layer 41c can be appropriately formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.

[0208] Here, since the thickness of the insulating layer 41 affects the channel length of the transistor, it is important that the thickness of the insulating layer 41 does not become non-uniform.

[0209] By depositing the insulating layer 41b by sputtering in an oxygen-containing atmosphere, an insulating layer 41b containing a plurality of oxygen atoms can be formed. Further, by using a sputtering method that does not require the use of a hydrogen-containing molecule as a deposition gas, the hydrogen concentration in the insulating layer 41b can be reduced. Thus, by depositing the insulating layer 41b, oxygen is supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, whereby oxygen vacancies can be reduced.

[0210] Next, a conductive layer 32 and an insulating layer 45 are formed on the insulating layer 41( Figure 8C ). The conductive layer 32 and the insulating layer 45 can be formed by the same method as the above-described conductive layer 31 and insulating layer 44.

[0211] Next, an opening 20a reaching the conductive layer 31 is formed in the conductive layer 32 and the insulating layer 41( Figure 8D ).

[0212] The side wall of the opening 20a is preferably perpendicular to the top surface of the conductive layer 31. By adopting such a structure, a transistor with a small occupied area can be manufactured. Alternatively, the side wall of the opening 20a may have a tapered shape. By having a tapered shape, the coverage of the film formed inside the opening 20a can be improved.

[0213] The maximum width of the opening 20a (the maximum diameter of the opening 20a when the opening 20a is circular when viewed from the plane) is preferably as fine as possible. For example, the maximum width of the opening 20a is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more. Thus, in order to perform fine processing of the opening 20a, a lithography method using light with a short wavelength such as EUV light or an electron beam is preferably used.

[0214] Since the aspect ratio of the opening 20a is large, it is preferably formed using anisotropic etching. Since processing using a dry etching method is suitable for fine processing, it is particularly preferred. Further, this processing can also be performed under different etching conditions in each of the conductive layer 32, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a. Further, the angles of the side walls of the opening 20a in each of the conductive layer 32, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a can also be different.

[0215] When etching the insulating layer 41, sometimes a part of the upper portion of the conductive layer 31 is etched, and the thickness of the conductive layer 31 at the bottom of the opening 20a becomes thinner. Alternatively, after forming the opening 20a, a part of the upper portion of the conductive layer 31 can be etched to thin the thickness of the conductive layer 31.

[0216] Next, a heat treatment can also be performed. The heat treatment is carried out at 250°C or higher and 650°C or lower, preferably at 300°C or higher and 500°C or lower, and more preferably at 320°C or higher and 450°C or lower. In addition, the heat treatment is carried out in an atmosphere of nitrogen gas or inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas can be set to about 20%. The heat treatment can also be carried out under reduced pressure. Alternatively, the heat treatment can be carried out in an atmosphere of nitrogen gas or inert gas, and then, in order to fill the escaped oxygen, the heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above heat treatment, impurities such as water contained in the insulating layer 41 and the like can be reduced before the deposition of the oxide semiconductor film that will become the semiconductor layer.

[0217] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the moisture content of the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed by the insulating layer 41 and the like as much as possible.

[0218] Next, a semiconductor film that will become the semiconductor layer 21 is formed so as to cover the insulating layer 41, the conductive layer 32, the opening 20a, the insulating layer 45, etc., and unnecessary portions are removed by etching to form the semiconductor layer 21( Figure 9A )

[0219] An oxide semiconductor film can be used as the semiconductor film. The oxide semiconductor film can be deposited by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. Here, the oxide semiconductor film is preferably formed in contact with the bottom and side walls of the opening 20a having a high aspect ratio. Therefore, when depositing the oxide semiconductor film, a deposition method with good coverage is preferably used, and more preferably a CVD method or an ALD method, etc. For example, In-Ga-Zn oxide can be deposited as the oxide semiconductor film by the ALD method. In addition, when the opening 20a has a tapered shape, the oxide semiconductor film can be deposited by the sputtering method.

[0220] In addition, preferably, microwave treatment is performed in an oxygen-containing atmosphere during or after deposition of the oxide semiconductor film to reduce the impurity concentration in the oxide semiconductor film. Examples of the impurities include hydrogen and carbon. In addition, by performing microwave treatment, the crystallinity of the oxide semiconductor film can sometimes be improved. Here, the microwave treatment refers to, for example, a treatment using a device including a power source that generates high-density plasma using microwaves.

[0221] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high frequencies such as RF, and the oxygen plasma can act. In addition, as the oxygen acting on the oxide semiconductor, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having unpaired electrons, also referred to as O radicals). In addition, the oxygen acting on the oxide semiconductor can be any one or more of the above forms, and oxygen radicals are particularly preferred.

[0222] In addition, by heating the substrate during the above-described microwave treatment in an oxygen-containing atmosphere, the impurity concentration in the oxide semiconductor film can be further reduced, which is preferable. The heating of the substrate may be performed at 100°C or higher and 650°C or lower, preferably at 200°C or higher and 600°C or lower, and more preferably at 300°C or higher and 450°C or lower.

[0223] By heating the substrate during the above-described microwave treatment in an oxygen-containing atmosphere, the carbon concentration in the oxide semiconductor film measured by SIMS can be made lower than 1×10 20 atoms / cm 3 , preferably lower than 1×10 19 atoms / cm 3 , and further preferably lower than 1×10 18 atoms / cm 3 .

[0224] Note that the above shows a structure in which microwave treatment is performed on the oxide semiconductor film in an oxygen-containing atmosphere, but it is not limited thereto. For example, microwave treatment can also be performed on an insulating film located near the oxide semiconductor film in an oxygen-containing atmosphere. More specifically, microwave treatment can also be performed on a silicon oxide film. Thereby, hydrogen contained in the silicon oxide film can be released to the outside as H 2 O. By releasing hydrogen from the silicon oxide film located near the oxide semiconductor film, a highly reliable semiconductor device can be provided.

[0225] In addition, when the semiconductor layer 21 has a stacked structure, the deposition methods of the respective layers may be the same or different. For example, when the semiconductor layer 21 has a two-layer stacked structure, the underlying oxide semiconductor film may be deposited by sputtering and the upper oxide semiconductor film may be deposited by ALD. The oxide semiconductor film deposited by sputtering can easily have crystallinity. Then, by providing an oxide semiconductor film with crystallinity as the underlying oxide semiconductor film, the crystallinity of the upper oxide semiconductor film can be improved. In addition, even if pinholes or disconnections are formed in the underlying oxide semiconductor film deposited by sputtering, the portions overlapping with the pinholes or disconnections can be blocked by the upper oxide semiconductor film deposited by ALD with good coverage.

[0226] Here, the oxide semiconductor film is preferably formed in contact with the top surface of the conductive layer 31 in the opening 20a, the side surface of the insulating layer 41 in the opening 20a, and the side surface and the top surface of the conductive layer 32 on the insulating layer 41.

[0227] After the oxide semiconductor film is formed, a heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the above oxide semiconductor film does not undergo polycrystallization, and may be performed at 250°C or higher and 650°C or lower, preferably at 400°C or higher and 600°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas may be set to about 20%. The heat treatment may also be performed under a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then, in order to replenish the oxygen that has escaped, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more.

[0228] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed by the above oxide semiconductor film and the like as much as possible.

[0229] Here, the above heat treatment is preferably performed in a state where the semiconductor film is in contact with the insulating layer 41b containing a plurality of oxygen atoms. Thereby, oxygen can be supplied from the insulating layer 41b to the portion of the semiconductor film that will become the channel formation region to reduce oxygen vacancies.

[0230] Note that the heat treatment is performed after depositing the above oxide semiconductor film as described above, but the present invention is not limited thereto. Furthermore, the heat treatment may also be performed in a subsequent process.

[0231] Next, an insulating layer 42 is formed so as to cover the conductive layer 32, the semiconductor layer 21, and the insulating layer 45( Figure 9B ). The insulating layer 42 can be formed in the same manner as the insulating layer 41b or the like.

[0232] The insulating layer 42 is formed so as to be embedded in the opening 20a. Here, when irregularities are formed on the top surface of the insulating layer 42, the top surface of the insulating layer 42 can also be planarized.

[0233] Next, an opening 20b reaching the semiconductor layer 21 is formed in the insulating layer 42( Figure 9C ). At this time, the insulating layer 42 embedded in the interior of the opening 20a is also removed by etching so that the side surface and the bottom surface of the semiconductor layer 21 located inside the opening 20a are exposed.

[0234] When the opening 20b is formed, the semiconductor layer 21 is sometimes damaged by etching. Therefore, after the opening 20b is formed, a part of the damaged surface layer portion in the semiconductor layer 21 can also be removed by etching. Although dry etching can be used as this etching, wet etching is preferably used. For example, it is preferable to etch the surface layer portion (for example, a range having a thickness of 1 nm or more and 10 nm or less including the surface) of the semiconductor layer 21 by wet etching using an acid such as phosphoric acid, oxalic acid, or nitric acid that is sufficiently diluted. In addition, after wet etching, a heat treatment can also be performed to remove the water adsorbed on the surface. This heat treatment can be performed under the above conditions.

[0235] Here, although the opening diameter of the opening 20b is shown to be smaller than the width of the semiconductor layer 21 and larger than the opening 20a in Figure 9C or the like, it is not limited thereto. For example, by making the opening diameter of the opening 20b larger than the width of the semiconductor layer 21, the structure shown in Figure 4A and Figure 4B can be realized. The opening diameter of the opening 20b can also be smaller than the opening 20a, but by making the opening diameter of the opening 20b larger than the opening 20a, the coverage of the layers (the insulating layer 22, the conductive layer 23, etc.) provided inside the opening 20b and the opening 20a can be improved, so it is preferable.

[0236] Next, an insulating film 22f is formed so as to cover the semiconductor layer 21 and the insulating layer 42( Figure 10A ). The insulating film 22f is an insulating film that will later become the insulating layer 22. The insulating film 22f can be appropriately formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0237] Preferably, the insulating film 22f is provided on the side surface of the semiconductor layer 21 within the opening 20a in a manner such that the thickness is as uniform as possible. Therefore, it is particularly preferable to form the insulating film 22f using the ALD method, which is a deposition method with extremely excellent coverage. In the case where the side walls of the opening 20a and the opening 20b have a tapered shape, deposition methods such as the sputtering method can be used to form the insulating film 22f.

[0238] Next, a conductive film 23f ( Figure 10B ) is formed on the insulating film 22f. The conductive film 23f is the conductive film that will later become the conductive layer 23. The conductive film 23f is provided in such a manner that a part of it is embedded in the opening 20a and the opening 20b.

[0239] The conductive film 23f is preferably deposited using a deposition method with high coverage or embedment, for example, more preferably using the CVD method or the ALD method, etc. In addition, when the side walls of the opening 20a and the opening 20b have a tapered shape, the conductive film can be deposited using the sputtering method.

[0240] Next, by using the CMP method or the dry etching method, etc., the upper portions of the conductive film 23f and the insulating film 22f are etched until the top surface of the insulating layer 42 is exposed, to form the insulating layer 22 and the conductive layer 23 embedded in the opening 20a and the opening 20b ( Figure 11A ).

[0241] In addition, by etching the upper portion of the conductive film 23f until the top surface of the insulating film 22f is exposed, a part of the insulating layer 22 (insulating film 22f) covering the upper portion of the insulating layer 42 can also be left remaining.

[0242] Next, a conductive layer 33 and an insulating layer 46 are formed on the insulating layer 42, the insulating layer 22, and the conductive layer 23 ( Figure 11B ). The conductive layer 33 and the insulating layer 46 can be formed using the same method as the conductive layer 31 and the insulating layer 44.

[0243] Through the above processes, the transistor 10 can be manufactured.

[0244] [Example of manufacturing method 2]

[0245] Next, an example of a manufacturing method of a semiconductor device, a part of which is different from the above Example of manufacturing method 1, will be described. More specifically, an example of the manufacturing method of the transistor 10b shown in Figure 4C and Figure 4D will be described. The description of the parts that overlap with the above Example of manufacturing method 1 will be omitted.

[0246] First, similar to the above Example of manufacturing method 1, the semiconductor layer 21 is formed until then. The cross-sectional schematic diagram at this time corresponds to Figure 9A .

[0247] Next, an insulating film 47f is formed so as to cover the conductive layer 32, the insulating layer 45, and the semiconductor layer 21( Figure 12A ). The insulating film 47f preferably covers the side surfaces in the opening 20a of the semiconductor layer 21 and is preferably formed by a deposition method such as ALD method with excellent step coverage. In the case where the opening 20a has a tapered shape, deposition methods such as sputtering method and CVD method can also be used.

[0248] The insulating film 47f is used as a protective layer that protects the semiconductor layer 21 from damage caused by etching of the insulating layer 42 when forming the opening 20b later. The insulating film 47f can also be referred to as an etch stop layer, and a material with a large etch selectivity to the insulating layer 42 can be used. That is, the insulating film 47f preferably uses a film having a different composition from the insulating layer 42. More specifically, the insulating film 47f can use a film containing constituent elements different from those of the insulating layer 42, a film containing the same constituent elements as the insulating layer 42 but having a different composition from the insulating layer 42, a film having a different density from the insulating layer 42, etc.

[0249] Next, an insulating layer 42 is formed on the insulating film 47f( Figure 12B ).

[0250] Next, an opening 20b reaching the insulating film 47f is formed in the insulating layer 42( Figure 12C ). At this time, since the semiconductor layer 21 is covered and protected by the insulating film 47f, it is not damaged by etching of the insulating layer 42.

[0251] Next, the insulating film 47f in the portion overlapping with the opening 20b is removed so that the top surface and side surfaces of the semiconductor layer 21 are exposed( Figure 13A ). Thus, an insulating layer 47 located between the conductive layer 32 and the insulating layer 42 and covering the end portion of the semiconductor layer 21 is formed.

[0252] It is important to etch the insulating film 47f in such a way that the semiconductor layer 21 is damaged as little as possible. For example, the insulating film 47f can be removed by wet etching. In addition, the insulating film 47f can also be etched by dry etching. In the case of etching the insulating film 47f by dry etching, conditions with less damage (low power conditions) compared to the etching conditions of the insulating layer 42 are preferably employed.

[0253] In addition, after etching the insulating film 47f, a heat treatment can also be performed. This heat treatment can be performed under the above conditions.

[0254] Next, an insulating film 22f that will become the insulating layer 22 is formed so as to cover the insulating layer 42, the insulating layer 47, and the semiconductor layer 21( Figure 13B ). The insulating film 22f can be formed in the same manner as in Manufacturing Method Example 1 described above.

[0255] In the case where the gate insulating layer is used as an etch stop layer, such as the transistor 10g shown in the above deformation example, the insulating film 47f can also be used as the gate insulating layer (insulating layer 22) without etching the insulating film 47f. That is to say, after forming the opening 20b, the conductive film 23f that will become the conductive layer 23 can be continuously formed. By using this method, the process can be simplified. On the other hand, when the insulating film 47f is deteriorated due to etch damage when forming the opening 20b, the gate insulating layer contains defects, so it is preferable to form the insulating film 47f and the insulating layer 22 separately as described above.

[0256] For the subsequent processes, reference can be made to the above Example 1 of the manufacturing method.

[0257] Through the above processes, the transistor 10b can be manufactured. By using this method, defects in the semiconductor layer 21 where the channel is formed can be reduced, so that non-uniformity of electrical characteristics is suppressed and a highly reliable transistor can be realized.

[0258] The above is the description of the manufacturing method example.

[0259] [Application Example]

[0260] The structure of a memory device using a transistor and a capacitor will be described below.

[0261] Figure 14A It is the circuit diagram of the memory cell 30. The memory cell 30 is composed of a transistor Tr1 and a capacitor C, and can also be denoted as 1Tr1C. The gate of the transistor Tr1 is connected to the wiring WL, one of the source and the drain is connected to the wiring BL, and the other is connected to one electrode of the capacitor C. The other electrode of the capacitor C is connected to the wiring PL.

[0262] The memory cell 30 holds the data potential input from the wiring BL through the transistor Tr1 in the capacitor C, and thus can store data. In addition, by making the transistor Tr1 non-conductive, the data can be held. In addition, by making the transistor Tr1 conductive, the potential corresponding to the held data is output to the wiring BL, and thus the data can be read out. The wiring WL is supplied with a signal for controlling the conduction and non-conduction of the transistor Tr1. In addition, the wiring PL is supplied with a specified potential (for example, a fixed potential).

[0263] Figure 14B and Figure 14C It is the cross-sectional view of the memory cell 30. The memory cell 30 has a structure in which a transistor 10 is stacked on a capacitor 50. The transistor 10 and the capacitor 50 respectively correspond to the above transistor Tr1 and the above capacitor C.

[0264] The structure of the transistor 10 can be referred to the above description, and thus the description is omitted here. Here, an example of using the transistor 10 is shown, but it is not limited to the transistor 10 and can be replaced with various transistors described above.

[0265] The capacitor 50 includes a conductive layer 51, a conductive layer 52, and an insulating layer 53 sandwiched therebetween. The capacitor 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.

[0266] The capacitor 50 is provided on the insulating layer 11. On the insulating layer 11, a conductive layer 34 and an insulating layer 47 on the conductive layer 34 are provided. The insulating layer 47 is provided with an opening 20c reaching the conductive layer 34. Inside the opening 20c, the conductive layer 51 is provided in contact with the side surface of the insulating layer 47 and the top surface of the conductive layer 34. In addition, the insulating layer 53 is provided to cover the insulating layer 47 and the conductive layer 51. An insulating layer 48 is provided on the insulating layer 53, and an opening 20d overlapping the opening 20c is provided in the insulating layer 48. The conductive layer 52 is provided so as to be embedded in the opening 20d and the opening 20c.

[0267] The top surfaces of the conductive layer 52 and the insulating layer 48 are planarized, and their top surface heights are substantially the same. An insulating layer 44 and a conductive layer 31 are provided on the conductive layer 52 and the insulating layer 48. The conductive layer 31 is provided in contact with the top surface of the conductive layer 52.

[0268] In Figure 14B and Figure 14C the conductive layer 32 corresponds to the wiring BL, the conductive layer 33 corresponds to the wiring WL, and the conductive layer 34 corresponds to the above-mentioned wiring PL.

[0269] As the conductive layer 34, the conductive layer 51, and the conductive layer 52, a low-resistance conductive material can be used. For example, the material that can be used for the above-mentioned conductive layer 23 can be used.

[0270] The insulating layer 53 is used as the dielectric layer of the capacitor 50. Thus, the thinner the thickness and the higher the relative dielectric constant, the more the capacitance of the capacitor 50 increases. For example, it is preferable to use a high-k material that can be used for the above-mentioned insulating layer 22.

[0271] Figure 15A and Figure 15B An example of a storage device in which two storage units 30 are connected to the same wiring is shown. Figure 15A is a top view schematic diagram of the storage device, Figure 15B is along Figure 15A The cross-sectional schematic diagram of the cut line A3 - A4 in

[0272] The conductive layer 33 used as the wiring WL is respectively provided in two storage units 30. The conductive layer 32 used as the wiring BL is provided in a manner shared by two storage units 30.

[0273] In addition, the conductive layer 32 used as the wiring BL is embedded in each interlayer insulating layer and is electrically connected to the conductive layers 61 and 62 used as plugs (also referred to as connection electrodes). The conductive layer 61 can also be electrically connected to a sense amplifier (not shown) provided below the insulating layer 11. In addition, the conductive layer 61 can also be electrically connected to the conductive layer 32 of the storage unit laminated above the insulating layer 65.

[0274] The insulating layer 65 is used as a barrier layer and has the function of preventing impurities such as water and hydrogen from diffusing into the storage device from the outside.

[0275] In addition, by arranging the storage units 30 in a three-dimensional and matrix manner, a storage unit array can be formed. As an example of the storage unit array, Figure 16A and Figure 16B an example of a storage device in which 4 × 2 × 4 storage units 30 are arranged in the X direction, Y direction, and Z direction is shown.

[0276] A group composed of four storage units 30 can be referred to as a memory unit 60. FIG. 16 shows eight memory units (memory units 60[1,1] to memory units 60[2,4]). In the memory unit 60[a, b] (where a and b are positive integers respectively), a represents the address in the Y direction and b represents the address in the Z direction.

[0277] The memory units 60 are centered on the conductive layer 61 or the conductive layer 62, and every two storage units 30 are respectively arranged at symmetric positions. The conductive layers 32 of the memory units 60 laminated in the Z direction are electrically connected to each other through the conductive layer 62. In this way, by laminating a plurality of memory units 60, the storage capacity per unit area can be increased, and a storage device capable of realizing miniaturization or high integration can be provided.

[0278] Figure 17A and Figure 17B An example showing the case where the connection part is arranged at the end of the memory unit is shown. Here, as an example of the storage unit array, an example of a storage device in which 3 × 3 × m (m is an integer of 2 or more) storage units 30 are arranged is shown. In the layer including the storage unit 30, the first layer is denoted as layer 70[1], and the mth layer (the uppermost layer) is denoted as layer 70[m].

[0279] The conductive layer 63 is disposed outside the storage unit. The conductive layer 63 can also be connected to the wiring in the layer above the layer 70 including the conductive layer 63. For example, the conductive layer 63 disposed in the layer 70[1] is electrically connected to the wiring disposed in the layer 70[2]. In addition, without being limited thereto, the conductive layer 63 can also be electrically connected to the wiring in the layer 70 below the layer 70 including the conductive layer 63.

[0280] Figure 18 Fig. shows an example of a cross-sectional structure of a storage device in which the layer including the storage cell 30 is stacked on the layer provided with the drive circuit including the sense amplifier.

[0281] Figure 18 Fig. shows an example in which a capacitor 50 and a transistor 10 thereon are stacked above a transistor 90. The transistor 90 is one of the transistors in the sense amplifier.

[0282] By arranging the sense amplifier so as to overlap with the storage cell 30, the bit line can be shortened. As a result, the load on the bit line can be reduced, and thus the read sensitivity of the sense amplifier can be improved. Therefore, the holding capacitance of the storage cell can be reduced.

[0283] The transistor 90 is disposed on a substrate 91 and includes a conductive layer 94 serving as a gate, an insulating layer 93 serving as a gate insulating layer, a semiconductor region 92 formed of a part of the substrate 91, and low-resistance regions 95a and 95b serving as a source region or a drain region. The transistor 90 can be a p-channel type or an n-channel type.

[0284] Here, in Figure 18 In the transistor 90 shown, the semiconductor region 92 (a part of the substrate 91) forming the channel has a convex shape. In addition, the conductive layer 94 is disposed so as to cover the side surface and the top surface of the semiconductor region 92 with the insulating layer 93 interposed therebetween. Since the convex portion of the semiconductor substrate is utilized, this transistor 90 is also referred to as a FIN type transistor.

[0285] Preferably, an interlayer insulating layer and a wiring layer (also referred to as a multilayer wiring layer) are alternately stacked between the layer provided with the transistor 90 and the layer provided with the storage cell 30. Figure 18 Fig. shows an example in which the low-resistance region 95b of the transistor 90 is electrically connected to the conductive layer 32 serving as the bit line of the storage cell 30 through wiring and a plug.

[0286] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0287] (Embodiment 2)

[0288] In this embodiment, with reference to Figures 19 to 22A storage device according to one embodiment of the present invention is described. In this embodiment, a structural example of a storage device in which a layer including a driving circuit with a sense amplifier is stacked on a layer including memory cells is described.

[0289] <Structural example of a storage device>

[0290] Figure 19 FIG. is a block diagram showing a structural example of a storage device 480 according to one embodiment of the present invention. Figure 19 The storage device 480 shown includes a layer 420 and a stacked layer 470.

[0291] The layer 420 is a layer including Si transistors. In the layer 470, element layers 430[1] to 430[m] (m is an integer of 2 or more) are stacked. The element layers 430[1] to 430[m] are layers including OS transistors. The layer 470 in which layers including OS transistors are stacked can be stacked on the layer 420.

[0292] Elements such as OS transistors and capacitors included in the element layers 430[1] to 430[m] constitute memory cells. Figure 19 An example is shown in which the element layers 430[1] to 430[m] include a plurality of memory cells 432 arranged in a matrix of m rows and n columns (n is an integer of 2 or more).

[0293] In Figure 19 , the memory cell 432 in the first row and the first column is denoted as the memory cell 432[1, 1], and the memory cell 432 in the m-th row and the n-th column is denoted as the memory cell 432[m, n]. In addition, in this embodiment and the like, an arbitrary row may be denoted as "the i-th row". In addition, an arbitrary column may be denoted as "the j-th column". Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. In addition, in this embodiment and the like, the memory cell 432 in the i-th row and the j-th column is denoted as the memory cell 432[i, j]. Note that in this embodiment and the like, when expressed as "i + α" (α is a positive integer or a negative integer), "i + α" is not less than 1 and not greater than m. Similarly, when expressed as "j + α", "j + α" is not less than 1 and not greater than n.

[0294] In addition, as an example, Figure 19Shown are m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the wiring WL provided in the first (first row) is denoted as wiring WL[1], and the wiring WL provided in the m-th (m-th row) is denoted as wiring WL[m]. Similarly, the wiring PL provided in the first (first row) is denoted as wiring PL[1], and the wiring PL provided in the m-th (m-th row) is denoted as wiring PL[m]. Similarly, the wiring BL provided in the first (first column) is denoted as wiring BL[1], and the wiring BL provided in the n-th (n-th column) is denoted as wiring BL[n]. Note that the number of layers of the element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) may also be different.

[0295] The plurality of memory cells 432 provided in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 432 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0296] The wiring BL is used as a bit line for writing and reading data. The wiring WL is used as a word line for controlling the on or off (conductive state or non-conductive state) of an access transistor serving as a switch. The wiring PL is used as a constant potential line connected to a capacitor. In addition, a wiring for transmitting the back gate potential may be provided separately.

[0297] The memory cells 432 included in the element layers 430[1] to 430[m] are connected to the sense amplifier 446 through the wiring BL. The wiring BL can be arranged in a direction parallel to or perpendicular to the substrate surface on which the layer 420 is provided. By forming the wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] with wirings arranged in a direction parallel to the substrate surface and wirings arranged in a direction perpendicular to the substrate surface, the wiring length between the element layer 430 and the sense amplifier 446 can be shortened. Since the signal transmission distance between the memory cell and the sense amplifier can be shortened and the resistance and parasitic capacitance of the bit line can be significantly reduced, power consumption and signal delay can be reduced. Thus, reduction of power consumption and signal delay of the storage device 480 can be achieved. In addition, it can operate even when the capacitance of the capacitor included in the memory cell 432 is reduced. Thus, miniaturization of the storage device 480 can be achieved.

[0298] The layer 420 includes a PSW471 (power switch), a PSW472, and a peripheral circuit 422. The peripheral circuit 422 includes a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Note that each circuit included in the layer 420 is a circuit including Si transistors.

[0299] In the storage device 480, each circuit, each signal, and each voltage can be appropriately selected or discarded as needed. Alternatively, other circuits or other signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

[0300] In addition, the signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are signals for power gating control. In addition, the signals PON1 and PON2 can also be generated in the control circuit 473.

[0301] The control circuit 473 is a logic circuit having a function of controlling the overall operation of the storage device 480. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode of the storage device 480 (e.g., write operation, read operation). Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 to execute the above operation mode.

[0302] The voltage generation circuit 474 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when a signal of H level is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0303] The drive circuit 440 is a circuit for writing and reading data to and from the memory cell 432. The drive circuit 440 includes the above-mentioned sense amplifier 446 in addition to the row decoder 442, column decoder 444, row driver 443, column driver 445, input circuit 447, and output circuit 448.

[0304] The row decoder 442 and the column decoder 444 have a function of decoding the signal ADDR. The row decoder 442 is a circuit for specifying the row to be accessed, and the column decoder 444 is a circuit for specifying the column to be accessed. The row driver 443 has a function of selecting the wiring WL specified by the row decoder 442. The column driver 445 has the following functions: a function of writing data to the memory cell 432; a function of reading data from the memory cell 432; a function of holding the read data, etc.

[0305] The input circuit 447 has the function of holding the signal WDA. The data held in the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is the data (Din) written into the memory cell 432. The data (Dout) read out from the memory cell 432 by the column driver 445 is output to the output circuit 448. The output circuit 448 has the function of holding Dout. In addition, the output circuit 448 has the function of outputting Dout to the outside of the storage device 480. The data output from the output circuit 448 is the signal RDA.

[0306] The PSW471 has the function of controlling the supply of VDD to the peripheral circuit 422. The PSW472 has the function of controlling the supply of VHM to the row driver 443. Here, the high power supply voltage of the storage device 480 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage used to make the word line high level, which is higher than VDD. The on / off of the PSW471 is controlled by the signal PON1, and the on / off of the PSW472 is controlled by the signal PON2. In Figure 19 , the number of power supply domains supplied with VDD in the peripheral circuit 422 is 1, but it can also be multiple. At this time, power switches can be set for each power supply domain.

[0307] The element layers 430[1] to 430[m] can be overlapped and provided on the layer 420. Figure 20A FIG. is a perspective view of the storage device 480 showing a case where the five-layer (m = 5) element layers 430[1] to 430[5] are stacked on the layer 420.

[0308] In Figure 20A , the element layer 430 provided in the first layer is denoted as the element layer 430[1], the element layer 430 provided in the second layer is denoted as the element layer 430[2], and the element layer 430 provided in the fifth layer is denoted as the element layer 430[5]. In addition, Figure 20A FIG. shows the wiring WL and the wiring PL extending in the X direction and the wiring BL and the wiring BLB extending in the Y direction and the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). The wiring BLB is the inverted bit line. Note that, in order to make the drawings easier to understand, the description of a part of the wiring WL and the wiring PL included in each of the element layers 430 is omitted.

[0309] Figure 20B It is to explain Figure 20ASchematic diagram of the structure example of the sense amplifier 446 connected to the wirings BL and BLB and the memory cells 432 included in the element layers 430[1] to 430[5] connected to the wirings BL and BLB. In addition, the structure in which a plurality of memory cells (memory cells 432) are electrically connected to one wiring BL and BLB is also referred to as a "memory string".

[0310] Figure 20B An example of the circuit structure of the memory cell 432 connected to the wiring BLB is shown. The memory cell 432 includes a transistor 437 and a capacitor 438. Regarding the transistor 437, the capacitor 438, and each wiring (BL and WL, etc.), for example, the wirings BL[1] and WL[1] may be referred to as the wiring BL and the wiring WL, etc. As the memory cell 432, for example, the memory cell 30 shown in the above embodiment can be used. That is, the transistor 10 can be used as the transistor 437, and the capacitor 50 can be used as the capacitor 438. In addition, the transistor included in the sense amplifier 446 can be the transistor 90 (refer to Figure 18 ).

[0311] In the memory cell 432, one of the source and drain of the transistor 437 is connected to the wiring BL. The other of the source and drain of the transistor 437 is connected to one electrode of the capacitor 438. The other electrode of the capacitor 438 is connected to the wiring PL. The gate of the transistor 437 is connected to the wiring WL.

[0312] The wiring PL is a wiring for supplying a constant potential for maintaining the potential of the capacitor 438. By connecting a plurality of wirings PL to be used as one wiring, the number of wirings can be reduced.

[0313] In one aspect of the present invention, while the OS transistors are stacked, the wiring serving as the bit line is arranged in a direction perpendicular to the substrate surface on which the layer 420 is provided. And the transistor 437 and the capacitor 438 included in the memory cell 432 are arranged in a row in a direction perpendicular to the substrate surface on which the layer 420 is provided. By arranging each element and each wiring in a direction perpendicular to the substrate surface, the wiring length between the element layers can be shortened, and the element density provided per unit area can be increased. Thereby, a storage device excellent in terms of reducing the storage capacity and power consumption can be realized.

[0314] [Structural examples of memory cell 432 and sense amplifier 446]

[0315] Figure 21A and Figure 21B are the circuit diagram corresponding to the above memory cell 432 and the diagram of the circuit block corresponding to the circuit diagram. As Figure 21A and Figure 21BAs shown, the storage unit 432 is sometimes represented as a block in the drawings and the like. In addition, in the case where the wirings BL shown in Figure 21A and Figure 21B are replaced with the wiring BLB, the same representation can be used.

[0316] In addition, Figure 21C and Figure 21D are a circuit diagram corresponding to the above-described sense amplifier 446 and a diagram of a circuit block corresponding to the circuit diagram. In the sense amplifier 446, a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485 are shown. In addition, wirings SA_OUT and SA_OUTB for outputting the read signal are shown in addition to the wirings BL and BLB.

[0317] As Figure 21C shown, the switch circuit 482 includes, for example, n-channel transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conduction states of the wiring pair of the wirings SA_OUT and SA_OUTB and the wiring pair of the wirings BL and BLB according to the signal CSEL.

[0318] As Figure 21C shown, the precharge circuit 483 is composed of n-channel transistors 483_1 to 483_3. The precharge circuit 483 is a circuit for precharging the wirings BL and BLB to an intermediate potential VPRE equivalent to VDD / 2 according to the signal EQ.

[0319] As Figure 21C shown, the precharge circuit 484 is composed of p-channel transistors 484_1 to 484_3. The precharge circuit 484 is a circuit for precharging the wirings BL and BLB to an intermediate potential VPRE equivalent to VDD / 2 according to the signal EQB.

[0320] As Figure 21C shown, the amplifier circuit 485 is composed of p-channel transistors 485_1 and 485_2 and n-channel transistors 485_3 and 485_4 connected to the wiring SAP or the wiring SAN. The wiring SAP or the wiring SAN is a wiring having a function of supplying VDD or VSS. The transistors 485_1 to 485_4 are transistors constituting an inverter loop.

[0321] In addition, Figure 21D is a diagram of a circuit block corresponding to the sense amplifier 446 described in Figure 21C and the like. As Figure 21D shown, the sense amplifier 446 is sometimes represented as a block in the drawings and the like.

[0322] Figure 22 is Figure 19Circuit diagram of the storage device 480. In Figure 22 used in Figures 21A to 21D the circuit block described in

[0323] As Figure 22 shown, the layer 470 having the element layer 430[m] includes the storage cells 432. As an example, Figure 22 the storage cells 432 shown are connected to the paired wirings BL[1] and BLB[1] or the wirings BL[2] and BLB[2]. The storage cells 432 connected to the wiring BL are the storage cells for writing or reading data.

[0324] The wiring BL[1] and the wiring BLB[1] are connected to the sense amplifier 446[1], and the wiring BL[2] and the wiring BLB[2] are connected to the sense amplifier 446[2]. The sense amplifiers 446[1] and 446[2] can read data according to Figure 21C the various signals described in

[0325] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0326] (Embodiment 3)

[0327] In this embodiment, a structural example of a display device using a transistor according to one aspect of the present invention will be described.

[0328] A transistor according to one aspect of the present invention can be formed to be extremely micro, so a display device using a transistor according to one aspect of the present invention can be a very high-definition display device. For example, a display device according to one aspect of the present invention can be used for the display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type, and the display unit of VR devices such as head-mounted displays and head-mounted devices (HMD: Head Mounted Display) such as glasses-type AR devices.

[0329] [Display Module]

[0330] Figure 23A A perspective view showing the display module 280 is shown. The display module 280 includes the display device 200A and the FPC 290. Note that the display device included in the display module 280 is not limited to the display device 200A, and may also be the display device 200B or the display device 200C described later.

[0331] The display module 280 includes the substrate 291 and the substrate 292. The display module 280 includes the display unit 281. The display unit 281 is an area for displaying an image.

[0332] Figure 23BA perspective schematic diagram showing the structure on one side of the substrate 291. A circuit section 282 is laminated on the substrate 291, a pixel circuit section 283 is on the circuit section 282, and a pixel section 284 is on the pixel circuit section 283. In addition, a terminal section 285 for connecting to the FPC 290 is provided on a portion of the substrate 291 that does not overlap with the pixel section 284. The terminal section 285 and the circuit section 282 are electrically connected through a wiring section 286 composed of a plurality of wirings.

[0333] The pixel section 284 includes a plurality of pixels 284a arranged periodically. Figure 23B An enlarged view of one pixel 284a is shown on the right side. The pixel 284a includes a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0334] The pixel circuit section 283 includes a plurality of pixel circuits 283a arranged periodically. One pixel circuit 283a controls the light emission of the three light-emitting elements included in one pixel 284a. One pixel circuit 283a may include three circuits that control the light emission of one light-emitting element. For example, the pixel circuit 283a may adopt a structure having at least one selection transistor, one current control transistor (driving transistor), and a capacitor for one light-emitting element. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. Thus, an active matrix type display panel can be realized.

[0335] The circuit section 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit section 283. For example, it preferably includes one or both of a gate line driving circuit and a source line driving circuit. In addition, it may also have at least one of an arithmetic circuit, a storage circuit, and a power supply circuit, etc. In addition, the transistors provided in the circuit section 282 may also form a part of the pixel circuit 283a. That is to say, the pixel circuit 283a may be composed of the transistors included in the pixel circuit section 283 and the transistors included in the circuit section 282.

[0336] The FPC 290 serves as a wiring for supplying a video signal, a power supply potential, etc. from the outside to the circuit section 282. In addition, an IC may also be mounted on the FPC 290.

[0337] The display module 280 may adopt a structure in which one or both of the pixel circuit portion 283 and the circuit portion 282 are overlapped below the pixel portion 284, so that the display portion 281 can have an extremely high aperture ratio (effective display area ratio). For example, the aperture ratio of the display portion 281 may be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. In addition, the pixels 284a can be arranged with extremely high density, whereby the display portion 281 can have extremely high definition. For example, the pixels 284a of the display portion 281 are preferably arranged with a definition of 2000 ppi or more, more preferably 3000 ppi or more, further preferably 5000 ppi or more, still more preferably 6000 ppi or more and 20000 ppi or less or 30000 ppi or less.

[0338] Such a display module 280 is very clear, so it is suitable for VR devices such as head-mounted displays or glasses-type AR devices. For example, because the display module 280 has a display portion 281 with extremely high definition, in the structure of viewing the display portion of the display module 280 through a lens, even if the display portion is magnified by the lens, the user cannot see the pixels, whereby a display with a high sense of immersion can be achieved. In addition, the display module 280 is not limited thereto, and can also be applied to electronic devices having a relatively small display portion. For example, it is suitable for the display portion of wearable electronic devices such as watch-type devices.

[0339] [Display device 200A]

[0340] Figure 24 The shown display device 200A includes a substrate 331, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 240, and a transistor 320.

[0341] The substrate 331 corresponds to Figure 23A the substrate 291 in

[0342] The transistor 320 is a vertical channel type transistor using an oxide semiconductor in a semiconductor layer forming a channel. The transistor 320 includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a conductive layer 325, a conductive layer 326, etc.

[0343] The transistor 320 can use various transistors shown in Embodiment 1.

[0344] An insulating layer 332 is provided on a substrate 331. The insulating layer 332 serves as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 into the transistor 320 and prevents oxygen from escaping from the semiconductor layer 321 to the side of the insulating layer 332. As the insulating layer 332, for example, a film such as an alumina film, a hafnium oxide film, or a silicon nitride film, in which hydrogen or oxygen is less likely to diffuse compared to a silicon oxide film, can be used.

[0345] A conductive layer 327 is provided on the insulating layer 332, and a conductive layer 325 is provided on the conductive layer 327. A conductive layer 326 is provided on the conductive layer 325. An insulating layer 334 is provided on the conductive layer 326, and an opening is provided in the insulating layer 334 and the conductive layer 326, and a semiconductor layer 321 is provided in the opening. An insulating layer 264 is provided to cover the semiconductor layer 321 and the conductive layer 326, and an insulating layer 323 and a conductive layer 324 are stacked in sequence in the opening provided in the insulating layer 264. In addition, an insulating layer 265 and a conductive layer 328 are provided on the insulating layer 264 and the conductive layer 324. In addition, an insulating layer 266 is provided on the insulating layer 265 and the conductive layer 328.

[0346] The insulating layer 264, the insulating layer 265, and the insulating layer 266 serve as interlayer insulating layers. A barrier layer that prevents impurities such as water or hydrogen in the insulating layer 266, etc., from diffusing into the transistor 320 may also be provided between the insulating layer 266 and the insulating layer 265. As the barrier layer, the same insulating film as the insulating layer 332 can be used.

[0347] A plug 274 electrically connected to one of the conductive layers 326 is embedded in the insulating layer 266, the insulating layer 265, and the insulating layer 264. Here, the plug 274 preferably has a conductive layer 274a that covers the side surfaces of the openings of the insulating layer 266, the insulating layer 265, and the insulating layer 264 and a part of the top surface of the conductive layer 326, and a conductive layer 274b that contacts the top surface of the conductive layer 274a. At this time, as the conductive layer 274a, a conductive material in which hydrogen and oxygen are less likely to diffuse is preferably used.

[0348] In addition, a capacitor 240 is provided on the insulating layer 266. The capacitor 240 includes a conductive layer 241, a conductive layer 245, and an insulating layer 243 located between them. The conductive layer 241 serves as one electrode of the capacitor 240, the conductive layer 245 serves as the other electrode of the capacitor 240, and the insulating layer 243 serves as the dielectric of the capacitor 240.

[0349] The conductive layer 241 is provided on the insulating layer 266 and is embedded in the insulating layer 254. The conductive layer 241 is electrically connected to the conductive layer 326 of the transistor 320 through the plug 274. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0350] The covering capacitor 240 is provided with an insulating layer 255a, on which an insulating layer 255b is provided, and on which an insulating layer 255c is provided.

[0351] As the insulating layers 255a, 255b, and 255c, inorganic insulating films can be suitably used. For example, preferably, a silicon oxide film is used as the insulating layers 255a and 255c, and a silicon nitride film is used as the insulating layer 255b. Thus, the insulating layer 255b can be used as an etching protection film. Although an example in which a part of the insulating layer 255c is etched to form a recess is shown in this embodiment, a recess may not be provided in the insulating layer 255c.

[0352] On the insulating layer 255c, a light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided. Details of the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B will be described in Embodiment 3.

[0353] The light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are commonly provided in the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0354] The organic layer 112R included in the light-emitting element 110R contains at least a light-emitting organic compound that emits red light. The organic layer 112G included in the light-emitting element 110G contains at least a light-emitting organic compound that emits green light. The organic layer 112B included in the light-emitting element 110B contains at least a light-emitting organic compound that emits blue light. Each of the organic layers 112R, 112G, and 112B may also be referred to as an EL layer and at least includes a layer having a light-emitting organic compound (light-emitting layer).

[0355] Since the display device 200A forms light-emitting devices for each light-emitting color, the chromaticity change between low-brightness light emission and high-brightness light emission is small. In addition, since the organic layers 112R, 112G, and 112B are separated from each other, crosstalk between adjacent sub-pixels can be suppressed even in a high-definition display device. Therefore, a high-definition and high-quality display device can be realized.

[0356] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0357] The pixel electrodes 111R, 111G, and 111B of the light-emitting elements are electrically connected to the conductive layer 326 of the transistor 320 through plugs 256 embedded in the insulating layers 255a, 255b, and 255c, a conductive layer 241 embedded in the insulating layer 254, and plugs 274. The height of the top surface of the insulating layer 255c is the same as or substantially the same as the height of the top surface of the plug 256. Various conductive materials can be used as the plugs.

[0358] In addition, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. A substrate 170 is attached to the protective layer 121 by an adhesive layer 171.

[0359] No insulating layer covering the top end portion of the pixel electrode 111 is provided between two adjacent pixel electrodes 111. Therefore, the interval between adjacent light-emitting elements can be made very small. Therefore, a high-definition or high-resolution display device can be realized.

[0360] [Display device 200B]

[0361] Hereinafter, a display device having a partial structure different from the above example will be described. Note that the same parts as the above are referred to the above description, and the description may be omitted sometimes.

[0362] Figure 25 The illustrated display device 200B shows an example in which a transistor 320A, which is a planar transistor having a semiconductor layer formed on a plane, and a transistor 320B, which is a vertical-channel transistor, are stacked. The transistor 320B has the same structure as the transistor 320 in the above display device 200A.

[0363] The transistor 320A includes a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 356, and a conductive layer 357.

[0364] An insulating layer 352 is provided on the substrate 331. The insulating layer 352 serves as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from escaping from the semiconductor layer 351 to the insulating layer 352 side. As the insulating layer 352, for example, a film such as an alumina film, a hafnium oxide film, or a silicon nitride film, in which hydrogen or oxygen is less likely to diffuse compared to a silicon oxide film, can be used.

[0365] A conductive layer 357 is provided on the insulating layer 352, and an insulating layer 356 is provided so as to cover the conductive layer 357. The conductive layer 357 serves as the first gate electrode of the transistor 320A, and a part of the insulating layer 356 serves as the first gate insulating layer. At least a part of the insulating layer 356 that contacts the semiconductor layer 351 is preferably an oxide insulating film such as a silicon oxide film. The top surface of the insulating layer 356 is preferably planarized.

[0366] A semiconductor layer 351 is provided on an insulating layer 356. The semiconductor layer 351 preferably contains a metal oxide film (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. A pair of conductive layers 355 are in contact with the semiconductor layer 351 and serve as a source electrode and a drain electrode.

[0367] An insulating layer 358 and an insulating layer 350 are provided to cover the top surface and side surfaces of the pair of conductive layers 355 and the side surface of the semiconductor layer 351, etc. The insulating layer 358 serves as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and oxygen from escaping from the semiconductor layer 351. As the insulating layer 358, the same insulating film as the above-mentioned insulating layer 352 can be used.

[0368] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 that contacts the top surface of the semiconductor layer 351 and a conductive layer 354 are embedded inside the opening. The conductive layer 354 serves as a second gate electrode, and the insulating layer 353 serves as a second gate insulating layer.

[0369] Flattening is performed so that the top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are at the same height or approximately the same height, and an insulating layer 359 is provided to cover them. The insulating layer 359 serves as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can use the same insulating film as the above-mentioned insulating layer 352.

[0370] As the transistor 320, a structure in which a semiconductor layer forming a channel is clamped by two gates is adopted. In addition, the two gates can be connected, and the transistor can be driven by supplying the same signal to the two gates. Alternatively, the threshold voltage of the transistor can be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0371] [Display device 200C]

[0372] Figure 26 The shown display device 200C includes a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a transistor 320 that is a vertical channel type transistor.

[0373] The transistor 310 is a transistor having a channel formation region in a substrate 301. As the substrate 301, for example, a semiconductor substrate such as a single crystal silicon substrate can be used. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 is used as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and is used as a gate insulating layer. The low-resistance region 312 is a region in the substrate 301 doped with impurities and is used as one of a source and a drain. The insulating layer 314 covers the side surface of the conductive layer 311.

[0374] In addition, between two adjacent transistors 310, an element isolation layer 315 is provided in a manner of being embedded in the substrate 301.

[0375] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0376] (Embodiment 4)

[0377] In this embodiment, a structural example of a display device applicable to the manufacture of a transistor for use in one mode of the present invention is described. The display device shown below can be used for the pixel portion 284 and the like of the above-described Embodiment 3.

[0378] One mode of the present invention is a display device including a light-emitting element (also referred to as a light-emitting device). The display device includes two or more pixels having different light-emitting colors. Each pixel includes a light-emitting element. Each light-emitting element includes a pair of electrodes and an EL layer therebetween. The light-emitting element is preferably an organic EL element (organic electroluminescent element). Two or more light-emitting elements emitting different colors each include an EL layer containing different light-emitting materials. For example, by including three light-emitting elements that respectively emit red (R), green (G), or blue (B) light, a full-color display device can be realized.

[0379] When manufacturing a display device including a plurality of light-emitting elements having different emission colors, it is necessary to form at least a layer containing a light-emitting material (light-emitting layer) into an island shape respectively. Here, a method of forming an island-shaped organic film by vapor deposition using a mask such as a metal mask is known when forming part or all of the EL layer respectively. However, due to various influences such as the accuracy of the metal mask, the misalignment between the metal mask and the substrate, the flexure of the metal mask, and the vapor scattering, which cause the contour of the deposited film to become larger, the shape and position of the island-shaped organic film deviate from the shape and position at the time of design, and it is difficult to achieve high definition and high aperture ratio of the display device. In addition, during vapor deposition, sometimes the thickness of the end portion becomes smaller due to the blurred contour of the layer. That is, sometimes the thickness of the island-shaped light-emitting layer varies depending on the position. In addition, when manufacturing a large-sized, high-resolution or high-definition display device, there is a concern that the manufacturing yield decreases due to the low dimensional accuracy of the metal mask and the deformation caused by heat or the like. Therefore, measures have been taken to simulate an increase in clarity (also referred to as pixel density) by adopting a special pixel arrangement such as a Pentile arrangement.

[0380] Note that in this specification and the like, the island shape means a state in which two or more layers made of the same material formed in the same process are physically separated. For example, the island-shaped light-emitting layer means a state in which the light-emitting layer is physically separated from the adjacent light-emitting layer.

[0381] In one aspect of the present invention, the EL layer is processed into a fine pattern by photolithography without using a mask such as a high-precision metal mask (FMM). Therefore, a display device having high definition and high aperture ratio, which has been difficult to achieve at present, can be realized. In addition, since the EL layer can be manufactured separately, a display device having a very vivid and high-contrast display quality can be realized. In addition, for example, the EL layer can also be processed into a fine pattern using both a metal mask and photolithography.

[0382] In addition, part or all of the EL layer can be physically separated. Thereby, leakage current between light-emitting elements via a layer (also referred to as a common layer) commonly used by adjacent light-emitting elements can be suppressed. Therefore, crosstalk caused by unintentional light emission can be suppressed, and a display device having a very high contrast can be realized. In particular, a display device having high current efficiency at low brightness can be realized.

[0383] One aspect of the present invention can also implement a display device that combines a light-emitting element that emits white light and a color filter. In this case, light-emitting elements having the same structure can be used for each light-emitting element in pixels (sub-pixels) that emit different colors of light, and all layers in each light-emitting element can be used as a common layer. Furthermore, a part or all of each EL layer can be cut off by using photolithography. Thereby, leakage current via the common layer can be suppressed, and a display device with high contrast can be achieved. In particular, in an element having a tandem structure in which a plurality of light-emitting layers are stacked with an intermediate layer having high conductivity interposed therebetween, leakage current via the intermediate layer can be effectively prevented, so a display device having high brightness, high definition, and high contrast can be achieved.

[0384] When processing the EL layer by photolithography, sometimes deterioration occurs due to a part of the light-emitting layer being exposed. Therefore, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layer. The insulating layer can also cover a part of the top surface of the island-shaped EL layer. The insulating layer preferably uses a material that has a barrier property against water and oxygen. For example, an inorganic insulating film that does not easily allow water or oxygen to diffuse can be used. Thereby, deterioration of the EL layer can be suppressed, and a display device with high reliability can be achieved.

[0385] In addition, there is a region (recess) between two adjacent light-emitting elements where the EL layer of each light-emitting element is not provided. When forming a common electrode or a common electrode and a common layer so as to cover the recess, sometimes the common electrode is disconnected due to a step at the end of the EL layer (also referred to as disconnection), resulting in insulation of the common electrode on the EL layer. Thus, it is preferable to adopt a structure in which a resin layer used as a planarization film fills the local steps located between two adjacent light-emitting elements (also referred to as LFP: Local Filling Planarization). The resin layer is used as a planarization film. Thereby, disconnection of the common layer or the common electrode can be suppressed, and a display device with high reliability can be achieved.

[0386] Hereinafter, a more specific structural example of the display device according to one aspect of the present invention will be described with reference to the drawings.

[0387] [Structural Example 1]

[0388] Figure 27A A plan view schematically showing a display device 100 according to one aspect of the present invention. The display device 100 includes a plurality of light-emitting elements 110R that emit red, a plurality of light-emitting elements 110G that emit green, and a plurality of light-emitting elements 110B that emit blue on a substrate 101. In Figure 27A in order to facilitate distinction between the respective light-emitting elements, symbols "R", "G", and "B" are attached to the light-emitting regions of the respective light-emitting elements.

[0389] The light emitting elements 110R, the light emitting elements 110G, and the light emitting elements 110B are arranged in a matrix. Figure 27A The so-called stripe arrangement is shown in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited to this, and an S-stripe arrangement, a Delta arrangement, a Bayer arrangement, a zigzag arrangement, a Pentile arrangement, a Diamond arrangement, etc. can also be used.

[0390] As the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, it is preferable to use an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode). As the light-emitting substance contained in the EL element, there can be cited substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), and substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials). As the light-emitting substance contained in the EL element, in addition to organic compounds, inorganic compounds (quantum dot materials, etc.) can also be used.

[0391] also, Figure 27A The connection electrode 111C is shown to be electrically connected to the common electrode 113. The connection electrode 111C is supplied with a potential (for example, an anode potential or a cathode potential) for supplying the common electrode 113. The connection electrode 111C is provided outside the display region where the light emitting elements 110R and the like are arranged.

[0392] The connection electrode 111C may be disposed along the periphery of the display region. For example, it may be disposed along one side of the periphery of the display region, or may be disposed across two or more sides of the periphery of the display region. That is, when the top surface of the display region is rectangular, the top surface of the connection electrode 111C may be in a strip shape (rectangle), L shape, "冂" shape (square bracket shape), or quadrangle shape, etc.

[0393] Figure 27B , Figure 27C They correspond to Figure 27A Schematic cross-sectional view of the dot-dashed line A1-A2 and the dot-dashed line A3-A4. Figure 27B Schematic cross-sectional view showing the light emitting element 110R, the light emitting element 110G and the light emitting element 110B, Figure 27C A schematic cross-sectional view of the connection portion 140 connecting the connection electrode 111C to the common electrode 113 is shown.

[0394] The light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The light-emitting elements 110R, 110G, and 110B commonly use the common layer 114 and the common electrode 113.

[0395] The organic layer 112R included in the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G included in the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B included in the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B may each also be referred to as an EL layer and at least include a layer (light-emitting layer) having a light-emitting organic compound.

[0396] Hereinafter, when explaining the common content among the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, it will sometimes be referred to as the light-emitting element 110 for explanation. Similarly, when explaining the common content among the constituent elements distinguished by letters such as the organic layer 112R, the organic layer 112G, and the organic layer 112B, it will sometimes be explained using symbols omitting the letters.

[0397] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 has a stacked structure in which a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer are stacked from the pixel electrode 111 side, and the common layer 114 includes an electron injection layer.

[0398] The pixel electrodes 111R, 111G, and 111B are all provided in each light-emitting element. In addition, the common electrode 113 and the common layer 114 are provided as a layer commonly used by the respective light-emitting elements. A conductive film having light transmittance to visible light is used for either the pixel electrodes or the common electrode 113, and a reflective conductive film is used for the other. By making each pixel electrode have light transmittance and making the common electrode 113 have reflectivity, a bottom-emission type (bottom emission structure) display device can be realized. On the contrary, by making each pixel electrode have reflectivity and making the common electrode 113 have light transmittance, a top-emission type (top emission structure) display device can be realized. In addition, by making both the pixel electrodes and the common electrode 113 have light transmittance, a double-sided emission type (double-sided emission structure) display device can also be realized.

[0399] A protective layer 121 is provided on the common electrode 113 so as to cover the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above to each light-emitting element.

[0400] The end portion of the pixel electrode 111 preferably has a tapered shape. When the end portion of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the end portion of the pixel electrode 111 may also have a tapered shape. By making the side surface of the pixel electrode 111 have a tapered shape, the coverage of the organic layer 112 provided across the end portion of the pixel electrode 111 can be improved. In addition, by making the side surface of the pixel electrode 111 have a tapered shape, foreign matters (for example, dust or fine particles, etc.) in the manufacturing process can be easily removed by a washing process or the like, so it is preferable.

[0401] Note that in this specification and the like, the tapered shape means a shape in which at least a part of the side surface of the constituent element is inclined with respect to the substrate surface. For example, it preferably has a region where the angle (also referred to as the taper angle) formed by the inclined side surface and the substrate surface is less than 90°.

[0402] The organic layer 112 is processed into an island shape by photolithography. Therefore, the organic layer 112 has a shape in which the angle formed by the top surface and the side surface at its end portion is nearly 90°. On the other hand, the thickness of the organic film formed using an FMM (Fine Metal Mask, high-precision metal mask) or the like tends to decrease as it approaches the end portion. For example, in the range of 1 μm or more and 10 μm or less from the end portion, the top surface is formed in a sloped shape, so it is difficult to distinguish the top surface from the side surface.

[0403] An insulating layer 125, a resin layer 126, and a layer 128 are provided between two adjacent light-emitting elements.

[0404] Between two adjacent light-emitting elements, the side surfaces of the respective organic layers 112 face each other across the resin layer 126. The resin layer 126 is located between two adjacent light-emitting elements and is provided so as to fill the region between the end portions of the respective organic layers 112 and between the two organic layers 112. The top surface of the resin layer 126 has a smooth convex shape, and the common layer 114 and the common electrode 113 are provided so as to cover the top surface of the resin layer 126.

[0405] The resin layer 126 is used as a planarization film for filling the steps located between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent the common electrode 113 from being insulated on the organic layer 112 due to the phenomenon (also referred to as disconnection) in which the common electrode 113 is broken by the steps at the end portion of the organic layer 112. The resin layer 126 may also be referred to as an LFP (Local Filling Planarization) layer.

[0406] As the resin layer 126, an insulating layer containing an organic material can be suitably used. For example, as the resin layer 126, an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimide amide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenolic resin, or a precursor of the above resins can be used. In addition, as the resin layer 126, an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used.

[0407] In addition, as the resin layer 126, a photosensitive resin can also be used. As the photosensitive resin, a photoresist can also be used. The photosensitive resin can be a positive-type material or a negative-type material.

[0408] The resin layer 126 can also contain a material that absorbs visible light. For example, the resin layer 126 itself can be composed of a material that absorbs visible light, and the resin layer 126 can also contain a pigment that absorbs visible light. As the resin layer 126, for example, the following resins can be used: a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light; or a resin that contains carbon black as a pigment and is used as a black matrix; etc.

[0409] The insulating layer 125 is in side contact with the organic layer 112. In addition, the insulating layer 125 covers the upper end portion of the organic layer 112. In addition, a part of the insulating layer 125 is in contact with the top surface of the substrate 101.

[0410] The insulating layer 125 is located between the resin layer 126 and the organic layer 112 and is used as a protective film that prevents the resin layer 126 from contacting the organic layer 112. When the organic layer 112 and the resin layer 126 are in contact, there is a possibility that the organic layer 112 is dissolved due to an organic solvent or the like used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, the side surface of the organic layer 112 can be protected.

[0411] The insulating layer 125 can be an insulating layer containing an inorganic material. As the insulating layer 125, inorganic insulating films such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitrogen oxide insulating film can be used. The insulating layer 125 can have a single-layer structure or a laminated structure. As the oxide insulating film, examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. As the nitride insulating film, examples include a silicon nitride film and an aluminum nitride film. As the oxynitride insulating film, examples include a silicon oxynitride film and an aluminum oxynitride film. As the nitrogen oxide insulating film, examples include a silicon nitrogen oxide film and an aluminum nitrogen oxide film. In particular, by using a metal oxide film such as an aluminum oxide film or a hafnium oxide film formed by ALD method, or an inorganic insulating film such as a silicon oxide film for the insulating layer 125, an insulating layer 125 with fewer pinholes and excellent EL layer protection function can be formed.

[0412] In this specification and the like, "oxynitride" refers to a material in which the oxygen content is more than the nitrogen content in its composition, and "nitrogen oxide" refers to a material in which the nitrogen content is more than the oxygen content in its composition. For example, when it is described as "silicon oxynitride", it refers to a material in which the oxygen content is more than the nitrogen content in its composition, and when it is described as "silicon nitrogen oxide", it refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0413] The insulating layer 125 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, etc. The insulating layer 125 is preferably formed by the ALD method with good coverage.

[0414] In addition, the light emitted by the light-emitting layer can also be reflected by providing a reflective film (for example, a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.) between the insulating layer 125 and the resin layer 126. Thereby, the light extraction efficiency can be further improved.

[0415] The layer 128 is a part of the protective layer (also called a mask layer, a sacrificial layer) that remains to protect the organic layer 112 during the etching of the organic layer 112. The layer 128 can use the materials that can be used for the above-mentioned insulating layer 125. In particular, it is preferable that both the layer 128 and the insulating layer 125 use the same material, so that the same processing devices and the like can be used.

[0416] In particular, since metal oxide films such as an aluminum oxide film or a hafnium oxide film formed by ALD method, and inorganic insulating films such as a silicon oxide film have fewer pinholes and excellent EL layer protection function, they can be suitably used for the insulating layer 125 and the layer 128.

[0417] The protective layer 121 may, for example, have a single-layer structure or a laminated structure including at least an inorganic insulating film. As the inorganic insulating film, for example, oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film can be cited. Alternatively, semiconductor materials or conductive materials such as indium gallium oxide, indium zinc oxide, indium tin oxide, and indium gallium zinc oxide can also be used as the protective layer 121.

[0418] As the protective layer 121, a laminated film of an inorganic insulating film and an organic insulating film can also be used. For example, it is preferable to sandwich an organic insulating film between a pair of inorganic insulating films. In addition, the organic insulating film is preferably used as a planarizing film. Therefore, the top surface of the organic insulating film can be made flat, so the coverage of the inorganic insulating film thereon is improved, and thus the barrier property can be improved. In addition, the top surface of the protective layer 121 becomes flat, so when a structure (for example, a color filter, an electrode of a touch sensor, or a lens array, etc.) is provided above the protective layer 121, the influence caused by the uneven shape of the underlying structure can be reduced, which is preferable.

[0419] Figure 27C A connection portion 140 that electrically connects the connection electrode 111C and the common electrode 113 is shown. In the connection portion 140, openings are provided in the insulating layer 125 and the resin layer 126 on the connection electrode 111C. In this opening, the connection electrode 111C and the common electrode 113 are electrically connected.

[0420] Note that Figure 27C A connection portion 140 that electrically connects the connection electrode 111C and the common electrode 113 is shown, but the common electrode 113 can also be provided on the connection electrode 111C with the common layer 114 interposed therebetween. In particular, in the case where a carrier injection layer is used as the common layer 114, etc., the resistivity of the material for the common layer 114 is sufficiently low and its thickness is also very thin, so in many cases there is no problem even if the common layer 114 is located in the connection portion 140. Thus, the common electrode 113 and the common layer 114 can be formed using the same masking mask, so the manufacturing cost can be reduced.

[0421] [Structural Example 2]

[0422] Hereinafter, a display device in which some structures are different from those in the above Structural Example 1 will be described. Note that the description of the parts that are the same as those in the above Structural Example 1 may be omitted with reference to the above Structural Example 1.

[0423] Figure 28A It is a cross-sectional schematic view of the display device 100a. The main differences between the display device 100a and the display device 100 are: the structure of the light-emitting element; and the former includes a coloring layer.

[0424] The display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may include two or more light-emitting materials whose emission colors are in a complementary color relationship. For example, the organic layer 112W may include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. In addition, it may also include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0425] Between two adjacent light-emitting elements 110W, the respective organic layers 112W are separated. Thereby, leakage current flowing between adjacent light-emitting elements 110W through the organic layer 112W can be suppressed, and crosstalk due to the leakage current can be suppressed. Therefore, a display device with high contrast and color reproducibility can be achieved.

[0426] An insulating layer 122 serving as a planarization film is provided on the protective layer 121, and a coloring layer 116R, a coloring layer 116G, and a coloring layer 116B are provided on the insulating layer 122.

[0427] As the insulating layer 122, an organic resin film or an inorganic insulating film whose top surface is planarized can be used. Since the insulating layer 122 is the formation surface of the coloring layer 116R, the coloring layer 116G, and the coloring layer 116B, the thickness of the coloring layer 116R etc. can be made uniform when the top surface of the insulating layer 122 is planar, thereby improving color purity. Note that when the thickness of the coloring layer 116R etc. is non-uniform, the light absorption amount varies according to the region in the coloring layer 116R, which may cause a decrease in color purity.

[0428] [Structural Example 3]

[0429] Figure 28B is a cross-sectional schematic view of the display device 100b.

[0430] The light-emitting element 110R includes a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. The light-emitting element 110B includes a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. The conductive layer 115R, the conductive layer 115G, and the conductive layer 115B all have light transmissivity and are used as optical adjustment layers.

[0431] A microcavity resonator (microcavity) structure can be realized by using a film that reflects visible light as the pixel electrode 111 and a film that has both reflectivity and transmissivity to visible light as the common electrode 113. At this time, by adjusting the thicknesses of the conductive layer 115R, the conductive layer 115G, and the conductive layer 115B in such a way as to achieve the most suitable optical path length, even when using the organic layer 112 that emits white light, light of different wavelengths can be extracted from the light-emitting elements 110R, the light-emitting element 110G, and the light-emitting element 110B, and the enhanced light can be obtained.

[0432] Moreover, by respectively providing the color filter layers 116R, the color filter layer 116G, and the color filter layer 116B on the optical paths of the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, light with high color purity can be extracted.

[0433] In addition, an insulating layer 123 is provided to cover the ends of the pixel electrode 111 and the optical adjustment layer 115. The end of the insulating layer 123 preferably has a tapered shape. By providing the insulating layer 123, the coverage of the organic layer 112W, the common electrode 113, the protective layer 121, etc. formed thereon can be improved.

[0434] The organic layer 112W and the common electrode 113 are respectively provided as a continuous film in each light-emitting element. By adopting this structure, the manufacturing process of the display device can be greatly simplified, so it is preferred.

[0435] Here, the end of the pixel electrode 111 preferably has an almost vertical shape. Thereby, a steeply inclined portion can be formed on the surface of the insulating layer 123, and a thin portion can be formed in a part of the organic layer 112W covering this portion, or a part of the organic layer 112W can be separated. Thereby, leakage current generated between adjacent light-emitting elements through the organic layer 112W can be suppressed without performing processing of the organic layer 112W using photolithography or the like.

[0436] The above describes an example of the structure of the display device.

[0437] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0438] (Embodiment 5)

[0439] In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to FIGS. 29 to 31.

[0440] The electronic device of the present embodiment includes, in a display unit, a display panel (display device) using a transistor according to one aspect of the present invention. A display device according to one aspect of the present invention can easily achieve high definition and high resolution, and in addition, can achieve high display quality. Therefore, it can be used for the display units of various electronic devices.

[0441] Examples of the electronic device include, in addition to electronic devices having a relatively large screen such as a television device, a desktop or notebook personal computer, a monitor for a computer or the like, a digital signage, a pachinko machine or other large game machines, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproduction device, and the like.

[0442] In particular, since a display panel according to one aspect of the present invention can improve clarity, it can be suitably used for an electronic device including a relatively small display unit. Examples of such an electronic device include a watch-type and bracelet-type information terminal device (wearable device), a wearable device that can be worn on the head such as a VR device such as a head-mounted display, a glasses-type AR device, and an MR device.

[0443] A display panel according to one aspect of the present invention preferably has an extremely high resolution such as HD (number of pixels: 1280×720), FHD (number of pixels: 1920×1080), WQHD (number of pixels: 2560×1440), WQXGA (number of pixels: 2560×1600), 4K (number of pixels: 3840×2160), 8K (number of pixels: 7680×4320), or the like. In particular, it is preferably set to a resolution of 4K, 8K, or higher. In addition, the pixel density (clarity) in a display panel according to one aspect of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, further preferably 1000 ppi or more, still further preferably 2000 ppi or more, still further preferably 3000 ppi or more, yet further preferably 5000 ppi or more, and further preferably 7000 ppi or more. By using the above display panel having one or both of high resolution and high clarity, the sense of reality, the sense of depth, and the like can be further improved. In addition, there is no particular limitation on the screen ratio (aspect ratio) of a display panel according to one aspect of the present invention. For example, the display panel can be adapted to various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, and the like.

[0444] The electronic device according to this embodiment may also include a sensor that has the function of sensing, detecting, and measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays.

[0445] The electronic device according to this embodiment may have various functions. For example, it may have functions such as displaying various information (static images, moving images, text images, etc.) on a display unit; the function of a touch panel; the function of displaying a calendar, date, or time; the function of executing various software (programs); the function of performing wireless communication; the function of reading programs or data stored in a storage medium; and so on.

[0446] Use Figures 29A to 29D An example of a wearable device that can be worn on the head will be described. These wearable devices have one or both of the functions of displaying AR content and displaying VR content. In addition, these wearable devices may also have the function of displaying content of SR or MR in addition to AR and VR. When the electronic device has the function of displaying at least one of the content such as AR, VR, SR, and MR, the immersion feeling of the user can be enhanced.

[0447] Figure 29A The illustrated electronic device 700A and Figure 29B the illustrated electronic device 700B both include a pair of display panels 751, a pair of frames 721, a communication unit (not illustrated), a pair of mounting portions 723, a control unit (not illustrated), an imaging unit (not illustrated), a pair of optical members 753, a bezel 757, and a pair of nose pads 758.

[0448] The display panel 751 may apply the display panel of one aspect of the present invention. Therefore, an electronic device capable of extremely high-definition display can be realized.

[0449] Both the electronic device 700A and the electronic device 700B can project the image displayed by the display panel 751 onto the display area 756 in the optical member 753. Since the optical member 753 has translucency, the user can see the image displayed in the display area overlapping with the transmitted image seen through the optical member 753. Therefore, both the electronic device 700A and the electronic device 700B are electronic devices capable of AR display.

[0450] On the electronic device 700A and the electronic device 700B, a camera capable of photographing the front can also be provided as an imaging unit. In addition, by providing an acceleration sensor such as a gyro sensor in the electronic device 700A and the electronic device 700B, the user's head orientation can be detected and an image corresponding to the direction can be displayed on the display area 756.

[0451] The communication unit has a wireless communication device, and an image signal or the like can be supplied through the wireless communication device. In addition, instead of or in addition to the wireless communication device, a connector capable of connecting a cable for supplying an image signal and a power potential may be included.

[0452] In addition, the electronic device 700A and the electronic device 700B are provided with a battery and can be charged in one or both of a wireless manner and a wired manner.

[0453] The housing 721 may also be provided with a touch sensor module. The touch sensor module has a function of detecting whether the outer surface of the housing 721 is touched. Through the touch sensor module, various processes can be executed by detecting a tap operation or a swipe operation of the user. For example, through a tap operation, processes such as temporarily stopping or playing a moving image can be executed, and through a swipe operation, processes such as fast forward and rewind can be executed. In addition, by providing a touch sensor module on each of the two housings 721, the operation range can be expanded.

[0454] As the touch sensor module, various touch sensors can be used. For example, various methods such as a capacitive method, a resistive film method, an infrared method, an electromagnetic induction method, a surface acoustic wave method, and an optical method can be adopted. In particular, it is preferable to apply a capacitive method or an optical method sensor to the touch sensor module.

[0455] When using an optical touch sensor, a photoelectric conversion device (also referred to as a photoelectric conversion element) can be used as a light receiving device (also referred to as a light receiving element). In the active layer of the photoelectric conversion device, one or both of an inorganic semiconductor and an organic semiconductor can be used.

[0456] Figure 29C The illustrated electronic device 800A and Figure 29D the illustrated electronic device 800B each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0457] The display unit 820 can apply a display panel according to one aspect of the present invention. Therefore, an electronic device capable of performing extremely clear display can be realized. As a result, the user can experience a high sense of immersion.

[0458] The display unit 820 is disposed at a position visible through the lens 832 inside the housing 821. Further, by displaying different images on each of the pair of display units 820, three-dimensional display using parallax can be performed.

[0459] Both the electronic device 800A and the electronic device 800B can be referred to as VR-oriented electronic devices. A user wearing the electronic device 800A or the electronic device 800B can see the image displayed on the display unit 820 through the lens 832.

[0460] The electronic device 800A and the electronic device 800B preferably have a mechanism capable of adjusting the left and right positions of the lens 832 and the display unit 820 so that the lens 832 and the display unit 820 are located at the most appropriate positions according to the position of the user's eyes. Further, it preferably has a mechanism for adjusting the focus by changing the distance between the lens 832 and the display unit 820.

[0461] The user can mount the electronic device 800A or the electronic device 800B on the head using the mounting unit 823. In Figure 29C etc., the mounting unit 823 is illustrated as having a shape such as the temple of glasses (also referred to as a wire, etc.), but is not limited thereto. As long as the user can mount it, the mounting unit 823 can have, for example, a helmet type or a band type shape.

[0462] The imaging unit 825 has a function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. Further, a plurality of cameras can be provided to be able to correspond to various perspectives such as telephoto and wide angle.

[0463] Note that an example including the imaging unit 825 is shown here, and a distance measurement sensor (hereinafter, also referred to as a detection unit) capable of measuring the distance to an object may be provided. In other words, the imaging unit 825 is one form of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as a lidar (Light Detection and Ranging) can be used. By using the image acquired by the camera and the image acquired by the distance image sensor, more information can be acquired, and more accurate attitude operation can be achieved.

[0464] The electronic device 800A may also include a vibration mechanism used as a bone conduction headphone. For example, any one or more of the display unit 820, the housing 821, and the mounting unit 823 may adopt a structure including the vibration mechanism. Thereby, it is not necessary to separately provide audio devices such as a headset, headphones, or speakers, and the user can enjoy images and sounds only by mounting the electronic device 800A.

[0465] The electronic device 800A and the electronic device 800B may also both include input terminals. Cables for supplying video signals from a video output device or the like and power for charging a battery provided in the electronic device may be connected to the input terminals.

[0466] An electronic device according to one embodiment of the present invention may also have a function of wirelessly communicating with the earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (such as audio data) from the electronic device through the wireless communication function. For example, Figure 29A The illustrated electronic device 700A has a function of transmitting information to the earphone 750 through the wireless communication function. In addition, for example, Figure 29C The illustrated electronic device 800A has a function of transmitting information to the earphone 750 through the wireless communication function.

[0467] In addition, the electronic device may also include an earphone unit. Figure 29B The illustrated electronic device 700B includes an earphone unit 727. For example, a structure in which the earphone unit 727 and the control unit are connected in a wired manner may be adopted. A part of the wiring connecting the earphone unit 727 and the control unit may also be disposed inside the housing 721 or the mounting portion 723.

[0468] Similarly, Figure 29D The illustrated electronic device 800B includes an earphone unit 827. For example, a structure in which the earphone unit 827 and the control unit 824 are connected in a wired manner may be adopted. A part of the wiring connecting the earphone unit 827 and the control unit 824 may also be disposed inside the housing 821 or the mounting portion 823. In addition, the earphone unit 827 and the mounting portion 823 may also include magnets. Thus, the earphone unit 827 can be fixed to the mounting portion 823 by magnetic force, which makes storage easier, so it is preferable.

[0469] The electronic device may also include a sound output terminal capable of connecting to an earphone or a headset. In addition, the electronic device may also include one or both of a sound input terminal and a sound input mechanism. As the sound input mechanism, for example, a sound collection device such as a microphone may be used. By providing the sound input mechanism in the electronic device, the electronic device can have the function of a so-called headset.

[0470] Thus, as an electronic device according to one embodiment of the present invention, both the glasses type (such as the electronic device 700A and the electronic device 700B) and the goggles type (such as the electronic device 800A and the electronic device 800B) are preferable.

[0471] Figure 30A The illustrated electronic device 6500 is a portable information terminal device that can be used as a smartphone.

[0472] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, etc. The display unit 6502 has a touch panel function. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one embodiment of the present invention can be used for the display unit 6502, the control device 6509, etc. By using a semiconductor device according to one embodiment of the present invention for the control device 6509, power consumption can be reduced, which is therefore preferable.

[0473] The display unit 6502 can use a display panel according to one embodiment of the present invention.

[0474] Figure 30B It is a schematic cross-sectional view of an end on the microphone 6506 side including the housing 6501.

[0475] A protective member 6510 having translucency is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are provided in a space surrounded by the housing 6501 and the protective member 6510.

[0476] The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 using an adhesive layer (not shown).

[0477] In a region outside the display unit 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded-back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

[0478] The display panel 6511 can use a flexible display according to one embodiment of the present invention. Thereby, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. In addition, by folding a part of the display panel 6511 to provide a connection portion with the FPC 6515 on the back surface of the pixel portion, a narrow-bezel electronic device can be realized.

[0479] Figure 30C An example of a television device is shown. In the television device 7100, the display unit 7000 is assembled in the housing 7101. A structure in which the housing 7101 is supported by a bracket 7103 is shown here.

[0480] It can be performed by using the operation switch provided in the housing 7101 and the separately provided remote operation machine 7111Figure 30C The operation of the television apparatus 7100 shown. Alternatively, a touch sensor may be provided in the display unit 7000, and the television apparatus 7100 may be operated by touching the display unit 7000 with a finger or the like. In addition, a display unit for displaying data output from the remote controller 7111 may be provided in the remote controller 7111. By using the operation keys or the touch panel provided in the remote controller 7111, channel and volume operations can be performed, and the image displayed on the display unit 7000 can be operated on.

[0481] In addition, the television apparatus 7100 includes a receiver, a modem, etc. General television broadcasts can be received by using the receiver. Furthermore, by connecting to a communication network in a wired or wireless manner through the modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver or between the receivers, etc.) information communication can be performed.

[0482] Figure 30D An example of a notebook personal computer is shown. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. The display unit 7000 is assembled in the housing 7211. The control device 7216 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used for the display unit 7000, the control device 7216, etc. By using a semiconductor device according to one aspect of the present invention for the control device 7216, power consumption can be reduced, which is therefore preferable.

[0483] Figure 30E and Figure 30F An example of a digital sign is shown.

[0484] Figure 30E The digital sign 7300 shown includes a housing 7301, a display unit 7000, a speaker 7303, etc. In addition, it may also include an LED lamp, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0485] Figure 30F A digital sign 7400 provided on a cylindrical column 7401 is shown. The digital sign 7400 includes a display unit 7000 provided along the curved surface of the column 7401.

[0486] The larger the display unit 7000 is, the more information can be provided at one time. The larger the display unit 7000 is, the more likely it is to attract people's attention. For example, the advertising effect can be improved.

[0487] By using the touch panel for the display unit 7000, not only can static images or dynamic images be displayed on the display unit 7000, but also the user can operate intuitively, so it is preferable. In addition, when used for providing information such as route information or traffic information, the usability can be improved by intuitive operations.

[0488] As Figure 30E and Figure 30F shown, the digital signage 7300 or the digital signage 7400 preferably can be linked with an information terminal device 7311 such as a smart phone carried by the user or the information terminal device 7411 through wireless communication. For example, the advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal device 7311 or the information terminal device 7411. In addition, by operating the information terminal device 7311 or the information terminal device 7411, the display of the display unit 7000 can be switched.

[0489] In addition, a game can be executed on the digital signage 7300 or the digital signage 7400 with the screen of the information terminal device 7311 or the information terminal device 7411 as an operation unit (controller). Thus, an unspecified number of users can participate in the game simultaneously and enjoy the fun of the game.

[0490] In Figures 30C to 30F it, the display panel of one mode of the present invention can be used for the display unit 7000.

[0491] Figures 31A to 31G The electronic device shown includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (the sensor has the function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared ray), a microphone 9008, etc.

[0492] Figures 31A to 31GThe electronic device shown has various functions. For example, it can have the following functions: the function of displaying various information (such as still images, moving images, and text images) on the display unit; the function of a touch panel; the function of displaying a calendar, date, or time, etc.; the function of controlling processing by using various software (programs); the function of performing wireless communication; the function of reading programs or data stored in a storage medium and processing them; etc. Note that the functions of the electronic device are not limited to the above functions, but can have various functions. The electronic device may include a plurality of display units. In addition, a camera or the like may be provided in the electronic device so that it has the following functions: the function of taking a still image or a moving image and storing the taken image in a storage medium (an external storage medium or a storage medium built in the camera); the function of displaying the taken image on the display unit; etc.

[0493] Next, the Figures 31A to 31G electronic device shown will be described in detail.

[0494] Figure 31A is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as a smart phone, for example. Note that in the portable information terminal 9101, a speaker 9003, a connection terminal 9006, a sensor 9007, etc. may also be provided. In addition, as the portable information terminal 9101, text or image information can be displayed on its multiple faces. In Figure 31A an example of displaying three icons 9050 is shown. In addition, information 9051 shown by a dotted rectangle can be displayed on other faces of the display unit 9001. As an example of the information 9051, information indicating receipt of an e-mail, SNS, or phone call, etc.; the title of an e-mail or SNS, etc.; the sender's name of an e-mail or SNS, etc.; date; time; battery level; and radio wave intensity, etc. can be cited. Alternatively, icons 9050, etc. can be displayed at the position where the information 9051 is displayed.

[0495] Figure 31B is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on more than three faces of the display unit 9001. Here, an example in which information 9052, information 9053, and information 9054 are respectively displayed on different faces is shown. For example, in a state where the portable information terminal 9102 is placed in an upper pocket, the user can confirm the information 9053 displayed at a position seen from above the portable information terminal 9102. For example, the user can confirm this display without taking out the portable information terminal 9102 from the pocket, and thus can determine whether to answer a call.

[0496] Figure 31CFIG. 0 is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 can execute various application software such as a mobile phone, reading and editing of e-mails and articles, playing music, network communication, computer games, etc. The tablet terminal 9103 includes a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front surface of the housing 9000, an operation key 9005 serving as an operation button on the left side surface of the housing 9000, and connection terminals 9006 on the bottom surface.

[0497] Figure 31D FIG. 1 is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can be used as, for example, a smart watch (registered trademark). Further, the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. Further, the portable information terminal 9200 can perform hands-free calling, for example, by communicating with a headset capable of wireless communication. Further, by using the connection terminals 9006, the portable information terminal 9200 can perform data transmission with other information terminals or can be charged. Charging can also be performed by wireless power supply.

[0498] Figures 31E to 31G FIG. 2 is a perspective view showing a foldable portable information terminal 9201. Further, Figure 31E FIG. 3 is a perspective view of a state in which the portable information terminal 9201 is unfolded, Figure 31G FIG. 4 is a perspective view of a folded state, Figure 31F FIG. 5 is a perspective view of an intermediate state when converting from Figure 31E one of the states of Figure 31G to the other. The portable information terminal 9201 has good portability in the folded state, and has strong display browsability in the unfolded state because it has a seamless and spliced large display area. The display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. The display unit 9001 can be curved, for example, in a range of a curvature radius of 0.1 mm or more and 150 mm or less.

[0499] At least a part of the present embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0500] (Embodiment 6)

[0501] In this embodiment, an application example of a semiconductor device according to one aspect of the present invention will be described. For example, a semiconductor device according to one aspect of the present invention can be used in electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DCs). Electronic components, electronic devices, mainframe computers, space equipment, and data centers using a semiconductor device according to one aspect of the present invention are effective for achieving high performance such as low power consumption.

[0502] Electronic components and the like using a semiconductor device according to one aspect of the present invention can be applied to the electronic device shown in Embodiment 5.

[0503] [Electronic component]

[0504] Figure 32A A perspective view of a substrate (circuit board 704) on which an electronic component 700 is mounted is shown. Figure 32A The illustrated electronic component 700 includes a semiconductor device 710 within a mold 711. In Figure 32A , a part of the electronic component 700 is omitted from the description to show its interior. The electronic component 700 includes a land 712 outside the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through a lead 714. The electronic component 700 is mounted on a printed circuit board 702, for example. By combining a plurality of such electronic components and electrically connecting them to the printed circuit board 702 respectively, the circuit board 704 is completed.

[0505] In addition, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The stacked structure of the drive circuit layer 715 and the storage layer 716 can be a monolithic stacked structure. In the monolithic stacked structure, through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding are not required to connect between the layers. When the drive circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0506] In addition, by adopting the on-chip memory structure, compared with technologies using through-electrodes such as TSV, the size of connection wirings and the like can be reduced, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, and thus the bandwidth of the memory (also referred to as memory bandwidth) can be improved.

[0507] In addition, preferably, multiple memory cell arrays in the memory layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When the multiple memory cell arrays are monolithically stacked, one or both of the bandwidth of the memory and the access latency of the memory can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between access and the start of data exchange. When Si transistors are used in the memory layer 716, it is more difficult to stack them in a monolithic manner than OS transistors. Therefore, in a structure stacked in a monolithic manner, OS transistors are superior to Si transistors.

[0508] In addition, the semiconductor device 710 can be referred to as a die. In this specification and the like, a die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip and cutting it into rectangular small pieces. Examples of semiconductor materials that can be used for a die include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon die.

[0509] Next, Figure 32B A perspective view of the electronic component 730 is shown. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 are provided on the interposer 731.

[0510] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM: High Bandwidth Memory). In addition, the semiconductor device 735 can be used for integrated circuits such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0511] The package substrate 732 can use, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can use, for example, a silicon interposer or a resin interposer.

[0512] The interposer 731 has multiple wirings and functions of electrically connecting multiple integrated circuits with different terminal pitches. The multiple wirings are composed of a single layer or multiple layers. In addition, the interposer 731 has a function of electrically connecting the integrated circuits provided on the interposer 731 with the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also called a "rewiring substrate" or an "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through this through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as the through electrode.

[0513] In HBM, in order to achieve a wide memory bandwidth, many wirings need to be connected. For this purpose, it is required that fine wirings can be formed at a high density on the interposer on which HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer for mounting HBM.

[0514] In addition, in SiP, MCM, etc. that use a silicon interposer, it is not easy to cause a decrease in reliability due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer. In addition, due to the high surface flatness of the silicon interposer, it is not easy to generate a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer. It is particularly preferable to use a silicon interposer for 2.5D packaging (2.5D mounting), in which multiple integrated circuits are arranged horizontally and configured on the interposer.

[0515] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when trying to reduce the size of the electronic component 730, the width of the above-mentioned terminal pitch becomes a problem, and it is sometimes difficult to set a sufficient number of wirings required to achieve a wide memory bandwidth. Thus, as described above, a structure that is stacked monolithically using OS transistors is preferable. In addition, a composite structure that combines a memory cell array stacked using TSV and a memory cell array stacked monolithically can also be adopted.

[0516] In addition, a heat sink (heat dissipation plate) can also be provided overlapping the electronic component 730. In the case of providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 731 the same. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 the same.

[0517] In order to mount the electronic component 730 on another substrate, electrodes 733 can also be provided at the bottom of the package substrate 732. Figure 32BAn example of forming the electrode 733 with solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, the installation of BGA (Ball Grid Array) can be achieved. In addition, the electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, the installation of PGA (Pin Grid Array) can be achieved.

[0518] The electronic component 730 can be installed on other substrates by various installation methods, not limited to BGA and PGA. As installation methods, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package) can be cited.

[0519] [Mainframe computer]

[0520] Next, Figure 33A A perspective view of the mainframe computer 5600 is shown. In the mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in the rack 5610. In addition, the mainframe computer 5600 can also be referred to as a supercomputer.

[0521] Figure 33B A perspective view showing an example of the computer 5620 is shown. The computer 5620 includes a motherboard 5630, and a plurality of slots 5631 and a plurality of connection terminals are provided on the motherboard 5630. A personal computer card 5621 is inserted into the slot 5631. And, the personal computer card 5621 includes connection terminals 5623, connection terminals 5624, connection terminals 5625, which are connected to the motherboard 5630.

[0522] Figure 33C An example of the personal computer card 5621 is shown. The personal computer card 5621 is, for example, a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 includes a board 5622 and connection terminals 5623, connection terminals 5624, connection terminals 5625, electronic components 5626, electronic components 5627, electronic components 5628, and connection terminals 5629, etc., which are mounted on the board 5622. Figure 33C Components other than the electronic components 5626, the electronic components 5627, and the electronic components 5628 are also shown.

[0523] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. For example, the specification of the connection terminal 5629 can be PCIe or the like.

[0524] The connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to the personal computer card 5621 or inputting signals. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621. For example, the specifications of the connection terminals 5623, 5624, and 5625 can be USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. In addition, when outputting a video signal from the connection terminals 5623, 5624, and 5625, the specifications can be HDMI (registered trademark), etc.

[0525] The electronic component 5626 includes terminals (not shown) for inputting and outputting signals. By inserting these terminals into the sockets (not shown) included in the board 5622, the electronic component 5626 and the board 5622 can be electrically connected.

[0526] The electronic components 5627 and 5628 include a plurality of terminals. For example, by soldering these terminals to the wiring included in the board 5622 by reflow soldering, the electronic components 5627 and 5628 can be installed. For example, as the electronic component 5627, an FPGA, a GPU, a CPU, etc. can be cited. For example, the electronic component 730 can be used as the electronic component 5627. For example, as the electronic component 5628, a storage device, etc. can be cited. For example, the electronic component 700 can be used as the electronic component 5628.

[0527] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0528] [Space equipment]

[0529] One embodiment of the semiconductor device of the present invention can be applied to space equipment.

[0530] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The electrical characteristics of the OS transistor change little due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used even in an environment where incident radiation may be present. For example, the OS transistor can be appropriately used when used in space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, a satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that space generally refers to an altitude of 100 km or more, but the space described in this specification may also include one or more of the thermosphere, mesosphere, and stratosphere.

[0531] In Figure 34A as an example of a space device, a satellite 6800 is shown. The satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In addition, Figure 34A an example where there is a planet 6804 in space is shown.

[0532] In addition, although Figure 34A not shown in the figure, a battery management system (also referred to as BMS) or a battery control circuit may be provided in the secondary battery 6805. When the OS transistor is used for the above battery management system or battery control circuit, the power consumption is low, and high reliability is achieved even in space, so it is preferable.

[0533] In addition, space is an environment where the radiation dose is 100 times or more that of the ground. Examples of radiation include electromagnetic waves (electromagnetic radiation) typified by X-rays and γ-rays; and particle radiation typified by α-rays, β-rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0534] When sunlight shines on the solar panel 6802, the power required for the satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar panel or when the amount of sunlight shining on the solar panel is small, the amount of generated power decreases. Therefore, it may not be possible to generate the power required for the satellite 6800 to operate. In order to make the satellite 6800 operate even when the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. In addition, the solar panel is sometimes referred to as a solar cell module.

[0535] The artificial satellite 6800 can generate signals. The signals are transmitted through the antenna 6803 and can be received by, for example, a receiver on the ground or other artificial satellites. By receiving the signals transmitted by the artificial satellite 6800, the position of the receiver that receives the signals can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0536] In addition, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is constituted by, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device including an OS transistor according to one aspect of the present invention is preferably used. Compared with Si transistors, the OS transistor has less change in electrical characteristics due to being irradiated with radiation. Therefore, the OS transistor has high reliability and can be appropriately used even in an environment where incident radiation may occur.

[0537] In addition, the artificial satellite 6800 may include sensors. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected by an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays released from the earth's surface. Thus, the artificial satellite 6800 can be used as, for example, an earth observation satellite.

[0538] Note that in this embodiment, an artificial satellite is shown as an example of a space device, but it is not limited thereto. For example, a semiconductor device according to one aspect of the present invention can be appropriately applied to space devices such as spacecrafts, space capsules, and space probes.

[0539] As described above, compared with Si transistors, the OS transistor has excellent effects such as enabling a wider memory bandwidth and high radiation resistance.

[0540] [Data Center]

[0541] For example, a semiconductor device according to one aspect of the present invention can be applied to a storage system adopted in a data center or the like. The data center is required to ensure data immutability and perform long-term management of data. When performing long-term management of data, it is necessary to make the facility large-scale, such as setting up storage and servers for storing huge amounts of data, ensuring stable power to maintain the data, or ensuring cooling equipment required during data retention.

[0542] By using a semiconductor device according to one aspect of the present invention for the storage system adopted in the data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the scale of the cooling equipment. Thus, it is possible to save space in the data center.

[0543] In addition, the power consumption of the semiconductor device according to one embodiment of the present invention is low, so that the circuit heating can be reduced. As a result, the negative impacts on the circuit itself, peripheral circuits, and modules caused by such heating can be reduced. In addition, by using the semiconductor device according to one embodiment of the present invention, a data center that can operate stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0544] Figure 34B A storage system applicable to a data center is shown. Figure 34B The storage system 6000 shown includes a plurality of servers 6001sb as a host 6001 (illustrated as a main computer). In addition, a plurality of storage devices 6003md are included as storage 6003 (illustrated as storage). A form in which the host 6001 and the storage 6003 are connected through a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as a storage controller) is shown.

[0545] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 can also be connected to each other through a network.

[0546] In the storage 6003, by using a flash memory, the access speed of data is shortened, that is, the time required for data storage and output is shortened. However, this time is much longer than the time required for DRAM that can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 6003, a cache memory is generally provided in the storage to shorten the time required for data storage and output.

[0547] The above cache memory is used in the storage control circuit 6002 and the storage 6003. The data exchanged between the host 6001 and the storage 6003 is output to the host 6001 or the storage 6003 after being stored in the cache memory in the storage control circuit 6002 and the storage 6003.

[0548] When an OS transistor is used as a transistor for storing the data of the above cache memory to hold the potential corresponding to the data, the refresh frequency can be reduced to lower the power consumption. In addition, miniaturization can be achieved by stacking the memory cell arrays.

[0549] Note that by using the semiconductor device according to one embodiment of the present invention for any one or more selected from electronic components, electronic devices, mainframes, space devices, and data centers, an effect of reducing power consumption can be expected. Therefore, although it is currently considered that the energy demand increases with the high performance or high integration of semiconductor devices, by using the semiconductor device according to one embodiment of the present invention, it is also possible to reduce carbon dioxide (CO 2) Emissions of greenhouse gases represented thereby. In addition, the semiconductor device according to one aspect of the present invention has low power consumption and is thus also effective as a measure against global warming.

[0550] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0551] [Symbol Explanation]

[0552] 10a: transistor, 10b: transistor, 10c: transistor, 10d: transistor, 10e: transistor, 10f: transistor, 10g: transistor, 10h: transistor, 10: transistor, 11: insulating layer, 20a: opening, 20b: opening, 20c: opening, 20d: opening, 21i: channel formation region, 21n: low-resistance region, 21: semiconductor layer, 22f: insulating film, 22: insulating layer, 23f: conductive film, 23: conductive layer, 26: conductive layer, 27: insulating layer, 30: memory cell, 31: conductive layer, 32: conductive layer, 33: conductive layer, 34: conductive layer, 41a: insulating layer, 41b: insulating layer, 41c: insulating layer, 41: insulating layer, 42: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 47f: insulating film, 47: insulating layer, 48: insulating layer, 50: capacitor, 51: conductive layer, 52: conductive layer, 53: insulating layer, 60: memory unit, 61: conductive layer, 62: conductive layer, 63: conductive layer, 65: insulating layer, 70: layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low-resistance region, 95b: low-resistance region.

Claims

1. A semiconductor device, comprising: a transistor; a first insulating layer; a second insulating layer; and a wiring, wherein the transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer, the first insulating layer is located above the first conductive layer and has a first opening reaching the first conductive layer, the second conductive layer is located above the first insulating layer, the semiconductor layer is in contact with the second conductive layer, the side surface of the first insulating layer in the first opening, and the top surface of the first conductive layer, the second insulating layer is located above the semiconductor layer and has a second opening reaching the semiconductor layer at a position overlapping with the first opening, the third insulating layer is in contact with the side surface of the second insulating layer in the second opening and the semiconductor layer in the first opening, the third conductive layer is disposed so as to be embedded in the second opening and the first opening, and the wiring is in contact with the top surface of the third conductive layer and has a portion overlapping with the semiconductor layer or the second conductive layer with the second insulating layer therebetween.

2. The semiconductor device according to claim 1, wherein the second insulating layer has a portion thicker than the third insulating layer.

3. The semiconductor device according to claim 1, further comprising a fourth insulating layer between the second conductive layer and the second insulating layer, wherein the composition of the fourth insulating layer is different from that of the second insulating layer.

4. The semiconductor device according to claim 3, wherein the fourth insulating layer covers an end portion of the semiconductor layer.

5. The semiconductor device according to claim 1, wherein the opening diameter at the upper end of the first opening is larger than the opening diameter at the lower end of the first opening.

6. A method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating layer having a first opening; forming a semiconductor layer in contact with the side surface in the first opening of the first insulating layer; forming a second insulating layer to cover the first insulating layer and the semiconductor layer; forming a second opening in the second insulating layer that overlaps with the first opening and reaches the semiconductor layer; successively forming a third insulating layer and a conductive layer in the second opening and the first opening; and forming a wiring on the second insulating layer in contact with the conductive layer.

7. A method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating layer having a first opening; forming a semiconductor layer in contact with the side surface in the first opening of the first insulating layer; forming a protective layer covering the semiconductor layer; forming a second insulating layer to cover the first insulating layer and the protective layer; forming a second opening in the second insulating layer that overlaps with the first opening and reaches the protective layer; etching the protective layer overlapping with the second opening so that the semiconductor layer is exposed; successively forming a third insulating layer and a conductive layer in the second opening and the first opening; and forming a wiring on the second insulating layer in contact with the conductive layer.

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