Backside BPR / BSPDN integration with backside local interconnect

Abstract

A semiconductor device includes: a backside power rail between an N-channel field effect transistor to N-channel field effect transistor space and between at least one P-channel field effect transistor to P-channel field effect transistor space; and back local signal lines located between the back power rails.

Description

Background Art

[0001] The exemplary embodiments described herein generally relate to semiconductor device design and integrated circuit design, and more particularly, to the integration of a back power rail (BPR) and a back supply power distribution network (BSPDN) with backside local interconnects.

[0002] The examples described herein provide not only a back source / drain power supply voltage (VDD) and a source / drain power supply voltage (VSS), but also local signal lines for gate connections and source / drain (S / D) connections. Summary of the Invention

[0003] In one aspect, a semiconductor device includes a back power rail located between N-channel field-effect transistor to N-channel field-effect transistor spaces and between at least one P-channel field-effect transistor to P-channel field-effect transistor spaces; and backside local signal lines located between the back power rails.

[0004] In another aspect, a method of forming a semiconductor device includes forming transistors having at least one gate and at least one source / drain on at least a portion of a substrate of a wafer; forming front contacts to some of the gates and source / drains; forming a back end of line and a carrier wafer; flipping the wafer and removing at least a portion of the substrate; forming back contacts to some of the gates and source / drains; forming a back power rail to the back contacts connected to the source / drains; wherein the back power rail is formed between N-channel field-effect transistor to N-channel field-effect transistor spaces and between at least one P-channel field-effect transistor to P-channel field-effect transistor spaces; and forming backside local signal lines between the back power rails.

[0005] In another aspect, a semiconductor device includes two adjacent N-channel transistors; two adjacent P-channel transistors, wherein an N-channel transistor of the two adjacent N-channel transistors is adjacent to a P-channel transistor of the two adjacent P-channel transistors; and wherein a back N-channel power rail for the two adjacent N-channel transistors is located between the two adjacent N-channel transistors, and wherein a back P-channel power rail for the two adjacent P-channel transistors is located between the two adjacent P-channel transistors, and wherein backside local signal lines for the N-channel transistors and P-channel transistors are located between the adjacent N-channel transistors and P-channel transistors. Brief Description of the Drawings

[0006] The foregoing and other aspects of the exemplary embodiments become more apparent in the following detailed description when read in conjunction with the accompanying drawings, in which:

[0007] Figure 1Depicts a semiconductor device formed based on the examples described herein;

[0008] Figure 2 Depicts vertical and horizontal metal pitches;

[0009] Figure 3 Depicts the height of an n - track cell with backside routing (INV_X2 example);

[0010] Figure 4 Depicts the height of an n - track cell with backside routing (NAND2_X1 example);

[0011] Figure 5A Depicts a cross - sectional view of the starting wafer of an integrated circuit, Figure 5B Depicts a top - down view including a cut - plane of the integrated circuit;

[0012] Figure 6A Depicts a cross - sectional view of the integrated circuit after nanoplate (NS) patterning and shallow trench isolation (STI) formation, and Figure 6B Depicts a top - down view including a cut - plane of the integrated circuit;

[0013] Figure 7A 、 Figure 7B and Figure 7C Each depicts a cross - sectional view of the integrated circuit after gate formation, and Figure 7D Shows a top - down view of the integrated circuit including cut - lines (Y, X1, and X2 respectively) that relate the top - down view to the Figure 7A 、 7B and cross - sectional views shown in 7C;

[0014] Figure 8A 、 Figure 8B and Figure 8C Each depicts a cross - sectional view of the integrated circuit after SiGe (e.g., SiGe60) removal, spacer formation, and bottom dielectric isolation (BDI) formation, and Figure 8D Shows a top - down view of the integrated circuit including cut - lines (Y, X1, and X2 respectively) that relate the top - down view to the Figure 8A 、 8B and cross - sectional views shown in 8C;

[0015] Figure 9A 、 Figure 9B and Figure 9C Each depicts a cross - sectional view of the integrated circuit after nanoplate (NS) recess, inner spacer formation, source / drain epitaxy formation, inter - layer dielectric deposition, and chemical mechanical polishing (CMP), and Figure 9DA top view of an integrated circuit showing cut lines (Y, X1, and X2 respectively) that relate the top view to the cross-sectional views shown in Figure 9A and 9B and 9C;

[0016] Figure 10A and Figure 10B and Figure 10C each depict a cross-sectional view of an integrated circuit after gate cut formation, gate removal, SiGe release, and high-k metal gate (HKMG) formation, and Figure 10D A top view of an integrated circuit showing cut lines (Y, X1, and X2 respectively) that relate the top view to the cross-sectional views shown in Figure 10A and 10B and 10C;

[0017] Figure 11A and Figure 11B and Figure 11C each depict a cross-sectional view of an integrated circuit after middle-of-line (MOL) contact formation, back-end-of-line (BEOL) formation, and carrier wafer bonding, and Figure 11D A top view of an integrated circuit showing cut lines (Y, X1, and X2 respectively) that relate the top view to the cross-sectional views shown in Figure 11A and 11B and 11C;

[0018] Figure 12A and Figure 12B and Figure 12C each depict a cross-sectional view of an integrated circuit after wafer flip, substrate removal, and stopping on an etch stop layer, and Figure 12D A top view of an integrated circuit showing cut lines (Y, X1, and X2 respectively) that relate the top view to the cross-sectional views shown in Figure 12A and 12B and 12C;

[0019] Figure 13A and Figure 13B and Figure 13C each depict a cross-sectional view of an integrated circuit after etch stop layer removal and remaining Si removal, and Figure 13D A top view of an integrated circuit showing cut lines (Y, X1, and X2 respectively) that relate the top view to the cross-sectional views shown in Figure 13A and 13B and 13C;

[0020] Figure 14A and Figure 14B and Figure 14CEach depicts a cross - sectional view of an integrated circuit after back - end - of - line (ILD) filling and planarization, and Figure 14D shows a top - view of an integrated circuit including scribe lines (Y, X1, and X2 respectively), which relate the top - view to the Figure 14A , 14B cross - sectional views shown in 14C;

[0021] Figure 15A , Figure 15B and Figure 15C each depict a cross - sectional view of an integrated circuit after forming a back - contact, and Figure 15D shows a top - view of an integrated circuit including scribe lines (Y, X1, and X2 respectively), which relate the top - view to the Figure 15A , 15B cross - sectional views shown in 15C;

[0022] Figure 16A , Figure 16B and Figure 16C each depict a cross - sectional view of an integrated circuit after forming a back - power rail and local signal lines, and Figure 16D shows a top - view of an integrated circuit including scribe lines (Y, X1, and X2 respectively), which relate the top - view to the Figure 16A , 16B cross - sectional views shown in 16C;

[0023] Figure 17A , Figure 17B and Figure 17C each depict a cross - sectional view of an integrated circuit after forming a back - side power - delivery network (BSPDN), and Figure 17D shows a top - view of an integrated circuit including scribe lines (Y, X1, and X2 respectively), which relate the top - view to the Figure 17A , 17B cross - sectional views shown in 17C;

[0024] Figure 18A , Figure 18B and Figure 18C each depict a cross - section of an integrated circuit, where Figure 18C depicts cross - section X3, Figure 18D shows a top - view of an integrated circuit including scribe lines (Y, X1, and X3 respectively), which relate the top - view to the Figure 18A , 18B cross - sectional views shown in 18C; and

[0025] Figure 19 is a logic flow - chart for fabricating a device based on the examples described herein. Detailed Description

[0026] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described in this detailed description are exemplary embodiments provided to enable those skilled in the art to make or use the invention, and not to limit the scope of the invention as defined by the claims.

[0027] This document describes the integration of a back power rail (BPR) and a back-side power delivery network (BSPDN) with back-side local interconnects. The structures described herein have not only a back-side source / drain power supply voltage (VDD) and a source / drain power supply voltage (VSS), but also local signal lines for gate connections and source / drain (S / D) connections. For the current structures, there is no coexistence of a back power rail (BPR) and a back-side power delivery network (BSPDN) with local interconnects.

[0028] Based on the examples described herein, a method of forming a semiconductor device includes forming a transistor having a gate and source / drain (S / D), forming front-side contacts to some of the gates and S / Ds (source / drains), forming a back-end structure and a carrier wafer, flipping the wafer, and removing the substrate, forming back-side contacts to some of the gates and S / Ds, forming a back power rail to those back-side contacts connected to the S / Ds at an N2N or P2P space, and forming back-side local signal lines to the back-side contacts between the back power rails or at an N2P space.

[0029] Based on the examples described herein, a semiconductor device includes two adjacent N-channel transistors; two adjacent P-channel transistors, wherein an N-channel transistor among the two adjacent N-channel transistors is adjacent to a P-channel transistor among the two adjacent P-channel transistors; and wherein a back-side N-channel power rail for the two adjacent N-channel transistors is located between the two adjacent N-channel transistors, and wherein a back-side P-channel power rail for the two adjacent P-channel transistors is located between the two adjacent P-channel transistors, and wherein back-side local signal lines for the N-channel and P-channel transistors are located between the adjacent N-channel and P-channel transistors.

[0030] Reference Figure 1, described herein is a semiconductor device 100 that includes backside power rails (106, 108, 110) located between an N2N space (102) and a P2P space (104). The semiconductor device 100 includes backside local signal lines (112, 114) located between the backside power rails (106, 108, 110). The backside power rails (106, 108, 110) of the semiconductor device 100 are connected to the S / D epitaxy through backside contacts. The backside local signal lines (112, 114, 116) of the semiconductor device 100 are connected to the source / drain epitaxy or the gate (124) through backside contacts (126). The semiconductor device 100 includes a standard cell architecture that has local signal lines (112, 114, 116, 117) that horizontally extend on the backside and a first front-side metal that vertically extends. Figure 1 Also shown are transistors 113, an N2P space (105), N-channel field-effect transistor regions or spaces (504, 506, 512, 514), and P-channel field-effect transistor regions or spaces (508, 510).

[0031] When the cell height is shortened while maintaining the same number of metal layer 0 (M0) signal traces, the M0 pitch is reduced, i.e., from 28 to 24 to 18 to 16. A tighter M0 pitch has narrower metal and smaller vias, which have higher resistance. Since the circuit output nodes are connected through these higher-resistance metals and vias, the circuit delay is affected. The structures described herein relate to a standard cell architecture that utilizes backside metal to reduce this high-resistance bottleneck.

[0032] Figure 2 A high-performance cell architecture with backside metal is depicted. In particular, Figure 2 a vertical metal pitch (202) of a given dimension (e.g., in nm) and a horizontal metal pitch (204) of a given dimension (e.g., in nm) are described. The vertical metal pitch 202 includes at least signal 206. The horizontal metal pitch 204 includes at least source / drain power voltage 208, signal 210, signal 212, signal 214, and source / drain power voltage 216. As an example, given Figure 2 the configuration shown, where metal layer 220 is connected to metal layer 222 through via 221, metal layer 222 is connected to source / drain 226 through via 224, M0P is a given dimension (e.g., in nm), and M1P is a given dimension (e.g., in nm). If the voltage between metal layer 220 and metal layer 222 is a given value M (e.g., in Ω), and the voltage between metal layer 222 and source / drain 226 is a given value N (e.g., in Ω), where via 224 has a size of a×b for values a and b, there is high resistance and limited performance.

[0033] Figure 3 depicts a high-performance cell architecture with backside metal. Specifically, Figure 3 depicts an n-trace cell height (INV_X2 example) with backside wiring. Vertical signal traces (302, 304, 306, 308, 310) on the front side 301 are shown, and output Y 312 is along the vertical signal trace 306. The wafer 300 includes p-channel 314 and n-channel 316. The backside 303 of the wafer 300 includes horizontal power and signal traces (322, 324, 326, 328, 330) for adding, for example, backside wiring to the backside power supply network. Source / drain power voltages (332, 334) are also shown. Figure 3 A configuration is further shown in which output Y312 is coupled to source / drain 342 through via 340. In this case, a larger via 340 results in lower resistance and improved performance. If the size of via 340 is s×t for values s and t, a resistance with a value (e.g., in Ω) is given.

[0034] Figure 4 depicts an n-trace cell height (NAND2_X1 example) with backside wiring. Vertical signal traces (402, 404, 406, 408, 410) on the front side 401 are shown, and output Y 412 is along the vertical signal trace 410. The wafer 400 includes p-channel 414 and n-channel 416. Signal lines 420 and vias 440 are along signal trace 408, and signal lines 418 and vias 442 are along trace 404. The backside 403 of the wafer 400 includes horizontal power and signal traces (422, 424, 426, 428, 430) for adding, for example, backside wiring to the backside power supply network. Signal line 436 is along trace 422. Source / drain power voltages (432, 434) are also shown. Figure 4 A configuration is further shown in which output Y 412 is coupled to source / drain 444 through via 442. In this case, a larger via 442 results in lower resistance and improved performance. If the size of via 442 is i×j for values i and j, a resistance with a value (e.g., in Ω) is given.

[0035] Figures 5 to 17 depict example process flows for forming a semiconductor device or integrated circuit based on the examples described herein.

[0036] Figure 5ADepicts the starting wafer 500 of an integrated circuit, particularly the Y cross-section 501. If the SiGe30 layer 502 (also known as the etch stop layer 502) fails to stop substrate removal, the SiGe30 layer 502 can also (e.g., optionally) be BOX SiO2. The Y cross-section 501 includes a hard mask 520, a silicon layer 522, SiGe30 layers (502, 526, 528, 530) within the silicon layer 522, and a SiGe55 layer (524) within the silicon layer 522. The layer 524 can also be a SiGe60 layer.

[0037] Figure 5B Shows a top view of the integrated circuit, including cutting lines for the Y cross-section 501, the X1 cross-section 503, and the X2 cross-section 505. Figure 5B Also shows N-channel field-effect transistor regions (504, 506, 512, 514), P-channel field-effect transistor regions (508, 510), and gates (516). In Figure 5B , X1 and X2 are the cutting lines that correlate the Figure 5B top view with the Figure 5A cross-sectional view. In Figure 5B , Y represents the cutting line for the cross-section.

[0038] Figure 6A Depicts the Y cross-section 501 of the integrated circuit after nanoplate (NS) patterning and shallow trench isolation (STI) formation. Figure 6B Depicts a top view of the integrated circuit including cutting lines for the cross-sections Y 501, X1 503, and X2 505 of the integrated circuit. Nanoplate patterning includes removing the hard mask 520 and forming an etch 602 within the silicon layer 522, the SiGe30 layers (526, 528, 530), and the SiGe55 layer 524. Shallow trench isolation 604 is formed within the silicon layer 522 below the etch 602 and above the SiGe30 layer 502. In Figure 6B , X1 and X2 are the cutting lines that correlate the Figure 6B top view with the Figure 6A cross-sectional view. In Figure 6B , Y represents the cutting line for the cross-section.

[0039] Figure 7A Depicts a cross-sectional view of the Y cross-section 501 of the integrated circuit after gate formation. Figure 7B Depicts a cross-sectional view of the X1 cross-section 503 of the integrated circuit after gate formation. Figure 7C Depicts a cross-sectional view of the X2 cross-section 505 of the integrated circuit after gate formation. In the Y cross-section 501, the gate 516 is formed within and above the etch 602 and contacts the shallow trench isolation layer 604. The nanoplate layer 702 is formed above the gate 516. Figure 7BIt is shown that in the X1 cross-section 503, the gate (516) is formed above the shallow trench isolation layer 604, and the nanosheet layer 702 is formed above the gate (516). Figure 7C It is shown that in the X2 cross-section 505, the gate (516) is formed above the silicon layer 522, and the nanosheet layer 702 is formed above the gate (516). Figure 7D It is shown including Figure 7A 、 Figure 7B and Figure 7C A top view of an integrated circuit showing the cutting lines of the cross-sections Y 501, X1 503, and X2 505 shown in. In Figure 7D , X1 and X2 are the cutting lines that correlate the top view of Figure 7D with the cross-sectional views of Figure 7A 、 Figure 7B and Figure 7C . In Figure 7D , Y shows the cutting line of the cross-section.

[0040] Figure 8A 、 Figure 8B and Figure 8C Each depicts a cross-section (Y 501, X1 503, X2 505 respectively) of the integrated circuit after removing the SiGe60 layer 524, spacer formation, and bottom dielectric isolation (BDI) 802 formation. In the Y cross-section 501, bottom dielectric isolation 802 is formed to replace the removed SiGe60 layer 524. In the X1 cross-section 503, spacers 804 are formed along the sides of the gate (516) and the nanosheet layer 702. In the X2 cross-section 503, bottom dielectric isolation 802 is formed to replace the removed SiGe60 layer 524, and spacers are formed along the sides of the gate (516) and the nanosheet layer 702. Figure 8D It is shown Figure 8A 、 Figure 8B and Figure 8C The views of the cross-sections (Y 501, X1 503, and X2 505 respectively) shown in. In Figure 8D , X1 and X2 are the cutting lines that correlate the top view of Figure 8D with the cross-sectional views of Figure 8A 、 Figure 8B and Figure 8C . In Figure 8D , Y shows the cutting line of the cross-section.

[0041] Figure 9A Depicts the Y cross-section 501 after the nanosheet layer 702 (shown as 902) is recessed and chemically mechanically polished. Figure 9B Depicts the X1 cross-section 503 after depositing the interlayer dielectric 904 and after chemical and mechanical polishing, where the interlayer dielectric 904 is deposited along the sides of the spacers 804 and above the shallow trench isolation 604.Figure 9C Shows the X2 cross-section 505 after forming the interlayer dielectric 904 above the bottom dielectric isolation 802 and on the sides of the spacer 804, and forming the source / drain epitaxy 906 within the interlayer dielectric 904 above the bottom dielectric isolation 802 and on the sides of the spacer 804. Figure 9C Further shows the formation of the inner spacer 908 between the source / drain epitaxies 906 above the bottom dielectric isolation 802, below the spacer 804 and the gate (516), between portions of the silicon layer 522, and along the sides of portions of the SiGe30 layers (526, 528, 530). The operations performed in the Figure 9C context may also include chemical and mechanical polishing. Figure 9D Shows Figure 9A , 9B and views of the cross-sections shown in 9C (Y 501, X1 503, and X2 505, respectively). In Figure 9D , X1 and X2 are the cutting lines that correlate the top view of Figure 9D with the cross-sectional views of Figure 9A , Figure 9B and Figure 9C . In Figure 9D , Y shows the cutting line of the cross-section.

[0042] Figure 10A , Figure 10B and Figure 10C each depict cross-sections of an integrated circuit after gate cutting formation, gate removal, SiGe release, and high-k metal gate formation. In particular, Figure 10A shows the gate cut 1002 formed in the Y cross-section 501, where the gate 516 is removed and is on the shallow trench isolation 604. Figure 10A Also shows that the high-k metal gate 124 is formed between the gate cuts 1002 and on at least a portion of the shallow trench isolation 604 and the silicon layer 522, and within the region where the SiGe30 layers (526, 528, 530) are released. Figure 10B Shows the high-k metal gate 124 formed in the region where the gate (516) is removed in the X1 cut 503. Figure 10C Shows the high-k metal gate 124 formed in the region where the gate (516) is removed in the X2 cut 505, and the SiGe30 layers (526, 528, 530) are released between the silicon layers 522 and between the inner spacers 908, between the spacers 804, and above the bottom dielectric isolation 802. Figure 10D Shows Figure 10A , Figure 10B and Figure 10C views of the cross-sections shown in (Y501, X1503, and X2505, respectively). Figure 10DA gate cut 1002 is formed between N-channel field effect transistor regions 504 and 506, P-channel field effect transistor regions 508 and 510, and N-channel field effect transistor regions 512 and 514. In Figure 10D X1 and X2 are cut lines that correlate the top view of Figure 10D with the cross-sectional views of Figure 10A , Figure 10B and Figure 10C . In Figure 10D , Y shows the cut line for the cross-section.

[0043] Figure 11A , Figure 11B and Figure 11C each depict a cross-section of the integrated circuit after the formation of MOL contacts, BEOL formation, and carrier wafer bonding.

[0044] Figure 11A Shows that for the Y cross-section 501, an interlayer dielectric layer 1102 is applied over the high-k metal gate 124 and the gate cut 1002. A mid-gate contact 1104 is formed within the interlayer dielectric 1102 to connect the high-k metal gate 124 to the formed back-end interlayer dielectric 1108. Additionally, for the Y cross-section 501, more BEOL layers 1110 are formed over the back-end interlayer dielectric 1108, and a carrier wafer 1112 is formed over the more BEOL layers 1110.

[0045] Figure 11B Shows that for the X1 cross-section 503, an interlayer dielectric 1102 is formed over the interlayer dielectric 904, the high-k metal gate 124, and the spacer 804. A mid-gate contact 1104 connects one of the high-k metal gates 124 and the corresponding spacer 804 to a via 1114 within the back-end interlayer dielectric 1108, the via 1114 is connected to a metal layer 1116, the metal layer 1116 is connected to the back-end layer 1110, and the back-end layer 1110 is connected to the carrier wafer 1112. As Figure 11B shown, for the X1 cross-section 503, there are multiple metal layers 1116 that are connected to the back-end layer 1110.

[0046] Figure 11CFor the X2 cross-section 505, the interlayer dielectric 1102 is formed over the source / drain epitaxy 906, the high-k metal gate 124, and the corresponding spacers 804. The mid-end source / drain contact 1106 connects the source / drain epitaxy (906) to the via 1114 in the back-end interlayer dielectric 1108 over the interlayer dielectric 1102. The via 1114 is connected to the metal layer 1116, and the metal layer 1116 is connected to the back-end layer 1110. For the X2 cross-section 505, multiple metal layers 1116 are formed in the interlayer dielectric 1108, and the metal layers 1116 are connected to the back-end layer 1110. In the X2 cross-section 505, the carrier wafer 1112 is formed over the back-end layer 1110.

[0047] Figure 11D Shows Figure 11A , Figure 11B and Figure 11C views of the cross-sections (Y 501, X1 503, and X2 505, respectively) shown in Figure 11D Shows that the mid-end source / drain contact 1106 is formed in the N-channel field-effect transistor region 504, the mid-end source / drain contact 1106 is formed in the N-channel field-effect transistor region 506, the mid-end gate contact 1104 is formed between the N-channel field-effect transistor region 506 and the P-channel field-effect transistor region 508 and together with the gate 516, the mid-end source / drain contact 1106 is formed in the P-channel field-effect transistor region 508, the mid-end source / drain contact is formed in the P-channel field-effect transistor region 510, two mid-end gate contacts (1104) are formed between the P-channel field-effect transistor region 510 and the N-channel field-effect transistor region 512 and on the gate (516), the mid-end source / drain contact 1106 is formed in the N-channel field-effect transistor region 512, and the mid-end source / drain contact 1106 is formed in the N-channel field-effect transistor region 514. In Figure 11D , X1 and X2 are the cutting lines that correlate the Figure 11D top view of Figure 11A , Figure 11B and Figure 11C with the cross-sectional views of Figure 11D . In

[0048] Figure 12A , Figure 12B and Figure 12C each depict a cross-section of an integrated circuit after wafer flipping, substrate removal, and stopping at the etch stop layer. Figure 12A Shows that for the Y cross-section 501, after the wafer is flipped (1202), the carrier wafer 1112 is at the bottom and the etch stop layer 502 is at the top. For the Y cross-section 501, a portion of the substrate 522 is removed and stopped at the etch stop layer 502, as shown in item 1208.Figure 12B It shows that for the X1 cross-section 503, after flipping the wafer (1204), the carrier wafer 1112 is at the bottom and the etch stop layer 502 is at the top. For the X1 cross-section 503, a portion of the substrate 522 is removed, stopping at the etch stop layer 502, as shown in item 1208. Figure 12C It shows that for the X2 cross-section 505, after flipping the wafer (1206), the carrier wafer 1112 is at the bottom and the etch stop layer 502 is at the top. For the X2 cross-section 505, a portion of the substrate 522 is removed, stopping at the etch stop layer 502, as shown in item 1208. Figure 12D It shows Figure 12A 、 Figure 12B and Figure 12C views of the cross-sections shown in Figure 12D (Y 501, X1 503, and X2 505 respectively). In Figure 12D , X1 and X2 are the cutting lines related to aligning the top view of Figure 12A 、 Figure 12B and Figure 12C with the cross-sectional views of Figure 12D . In Figure 12D , Y shows the cutting line for the cross-section.

[0049] Figure 13A 、 Figure 13B and Figure 13C each depict a cross-section of the integrated circuit after removing the etch stop layer and the remaining Si. Figure 13A It shows that in the Y cross-section 501, the silicon of the silicon layer 522 is removed (as shown in item 1302), including between the shallow trench isolation 604 and above the bottom dielectric isolation 802. In the Y cross-section 501, the etch stop layer 502 is removed (as shown in item 1304). Figure 13B It shows that for the X1 cross-section 503, the silicon of the silicon layer 522 is removed on the shallow trench isolation 604 (as shown in item 1302). The etch stop layer 502 is also shown to be removed in the X1 cross-section 503 (as shown in item 1304). Figure 13C It shows that for the X2 cross-section 505, the silicon 522 is removed above the bottom dielectric isolation 802 (as shown in item 1302). The etch stop layer 502 is also shown to be removed in the X2 cross-section 505 (as shown in item 1304). Figure 13D It shows Figure 13A 、 Figure 13B and Figure 13C views of the cross-sections shown in Figure 13D (Y 501, X1 503, and X2 505 respectively). In Figure 13D , X1 and X2 are the cutting lines related to aligning the top view of Figure 13D with the cross-sectional views of Figure 13A 、 Figure 13B and Figure 13C . InFigure 13D In it, Y shows the cutting line of the cross-section.

[0050] Figure 14A , Figure 14B and Figure 14C each depict a cross-section of the integrated circuit after back-end-of-line dielectric filling and planarization. Figure 14A Shows that for the Y cross-section 501, the back-end-of-line dielectric 1402 is filled at the position where silicon 522 is removed (1302) between the shallow trench isolations 604 adjacent to the bottom dielectric isolation 802. Figure 14C Shows that for the X2 cross-section 505, the back-end-of-line dielectric 1402 is formed at the position where silicon 522 is removed (1302) adjacent to the bottom dielectric isolation 802. Figure 14D Shows Figure 14A , Figure 14B and Figure 14C views of the cross-sections shown in Figure 14D In Figure 14D the top view of Figure 14A , Figure 14B and Figure 14C are related to the cutting lines of the cross-sectional views. In Figure 14D Y shows the cutting line of the cross-section.

[0051] Figure 15A , Figure 15B and Figure 15C each depict a cross-section of the integrated circuit after forming the back contact. Figure 15A Shows that for the Y cross-section 501, a back-to-gate contact 126 is formed between the back-end-of-line dielectrics 1402 within the shallow trench isolation 604 to contact the high-k metal gate 124. Figure 15B Shows that for the X1 cross-section 503, a back-to-gate contact (126) is formed within the shallow trench isolation 604 to contact the high-k metal gate 124 and the spacer 804. Figure 15C Shows that a back-to-source / drain contact (1504) is formed within the back-end-of-line dielectric 1402 and the bottom dielectric isolation 802 to contact the source / drain (906). Figure 15D Shows Figure 15A , Figure 15B and Figure 15C views of the cross-sections shown in Figure 15D Shows that a back-to-source / drain contact (1504) is formed within the N-channel field-effect transistor regions (504, 506, 512, 514), and a back-to-gate contact (126) is formed between the N-channel field-effect transistor region 506 on the gate (516) and the P-channel field-effect transistor region 508. InFigure 15D In, X1 and X2 are the cutting lines related to the top view of Figure 15D and the sectional views of Figure 15A , Figure 15B and Figure 15C . In Figure 15D , Y shows the cutting line of the cross-section.

[0052] Figure 16A , Figure 16B and Figure 16C each depict a cross-section of the integrated circuit after forming the back power rails and local signal lines. Figure 16A shows that for the Y cross-section 501, an additional back interlayer dielectric 1602 is formed over the shallow trench isolation 604 and the back contact 126. The back power rails (106, 108, 110) and the local signal lines (112, 114) are formed within the back interlayer dielectric 1602. The back power rails (106, 108, 110) and the local signal line 114 are coupled to the shallow trench isolation 604, and the local signal line 112 is coupled to the back contact 126. The back power rails are at least partially formed above the back interlayer dielectric (1402).

[0053] Figure 16B shows that for the X1 cross-section 503, an additional back interlayer dielectric 1602 is formed over the shallow trench isolation 604 and the back contact (126). The local signal line 116 is formed within the additional back interlayer dielectric 1602 and is coupled to the back contact (125) and the shallow trench isolation 604. Figure 16C shows that for the X2 cross-section 505, an additional back interlayer dielectric 1602 is formed over the back-to-source / drain contact (1504) and the back interlayer dielectric 1402. Figure 16D shows Figure 16A , Figure 16B and Figure 16C views of the cross-sections shown in Figure 16D shows the N2N space (102), the P2P space (104), and the N2P space (105). The power rails (106, 108, 110) are located between the N2N space (102) and the P2P space 104. The local signal lines (112, 114, 116) are between the N2P spaces (105). Also refer to Figure 1 , in Figure 16D , X1 and X2 are the cutting lines related to the top view of Figure 16D and the sectional views of Figure 16A , Figure 16B and Figure 16C . In Figure 16D , Y shows the cutting line of the cross-section.

[0054] Figure 17A , Figure 17B and Figure 17C each depict a cross-section of an integrated circuit after formation of a backside power supply network. Figure 17A Shows that in the Y cross-section 501, an additional backside interlayer dielectric 1702 is formed over the backside interlayer dielectric 1602, power rails (106, 108, 110), and local signal lines (112, 114). Through-holes (1706) are formed within the backside interlayer dielectric 1702 to couple the power rails (106, 110) to the formed backside power supply network (1704). As shown, the backside power supply network 1704 is formed to be partially coupled to the backside interlayer dielectric 1702.

[0055] Figure 17B Shows that for the X1 cross-section 503, the backside interlayer dielectric 1702 is formed over the backside interlayer dielectric 1602 and the local signal line 116, and immediately following the backside interlayer dielectric 1702, the backside power supply network 1704 is formed. Figure 17C Shows that for the X2 cross-section 505, the backside interlayer dielectric 1702 is formed over the backside interlayer dielectric 1602, and immediately following the backside interlayer dielectric 1702, the backside power supply network 1704 is formed. Figure 17D Shows Figure 17A , Figure 17B and Figure 17C views of the cross-sections (Y 501, X1 503, and X2 505 respectively) shown in Figure 17D In Figure 17D , X1 and X2 are the cut lines that correlate the top view of Figure 17A , Figure 17B and Figure 17C with the cross-sectional views of Figure 17D In

[0056] Figure 18A , [[ID=2 and ​ each depict a cross-section of an integrated circuit, where ​ depicts the cross-section X3 507. ​ Shows ​ , ​ and ​ views of the cross-sections (Y 501, X1 503, and X3 507 respectively) shown in Figure 18D Also shows the INV_X21802 and NAND2_X1 1804 of the cross-section X3 507. In Figure 18D In Figure 18D , X1 and X3 are the cut lines that correlate the top view of Figure 18A , Figure 18B and Figure 18C with the cross-sectional views ofFigure 18D In this figure, Y shows the cutting line of the cross-section.

[0057] Figure 19 is a logic flow diagram of manufacturing a device based on the examples described herein. In 1910, the method includes forming a transistor (113) having at least one gate (124) and at least one source / drain (906) on at least a portion of a substrate (522) of a wafer (500). In 1920, the method includes forming front contacts (1104, 1106) to some of the gates (124) and source / drains (906). In 1930, the method includes forming a back-end structure (1108, 1110) and a carrier wafer (1112). In 1940, the method includes flipping the wafer (500) and removing at least a portion of the substrate (522). In 1950, the method includes forming back contacts (126, 1504) to some of the gates (124) and source / drains (906). In 1960, the method includes forming back power rails (106, 108, 110) to the back contacts (1504) connected to the source / drains (906). In 1970, the method includes, wherein the back power rails (106, 108, 110) are formed between N-channel field-effect transistor to N-channel field-effect transistor spaces (102) and between at least one P-channel field-effect transistor to P-channel field-effect transistor spaces (104). In 1980, the method includes forming back local signal lines (112, 114) between the back power rails (106, 108, 110).

[0058] Now referring to all the figures, in one exemplary embodiment, a semiconductor device includes back power rails located between N-channel field-effect transistor to N-channel field-effect transistor spaces and between at least one P-channel field-effect transistor to P-channel field-effect transistor spaces; and back local signal lines located between the back power rails.

[0059] The backside power rail can be connected to the source / drain epitaxy through backside contacts. The backside local signal lines can be connected to the source / drain epitaxy or the gate through backside contacts. The semiconductor device can include a cell architecture having backside local signal lines horizontally extending on the backside and front-side metals vertically extending. The semiconductor device can include at least a pair of adjacent N-channel transistors. The backside power rail can include at least one backside N-channel power rail for at least a pair of adjacent N-channel transistors, and the at least one backside N-channel power rail is located between the at least a pair of adjacent N-channel transistors. The semiconductor device can include two adjacent P-channel transistors, and at least one N-channel transistor among the at least a pair of adjacent N-channel transistors is adjacent to the P-channel transistor among the two adjacent P-channel transistors. The semiconductor device can include at least one backside P-channel power rail for the two adjacent P-channel transistors, and the at least one backside P-channel power rail is located between the two adjacent P-channel transistors. The semiconductor device can include backside local signal lines for the N-channel transistors and the P-channel transistors, and the backside local signal lines are located between at least one of the N-channel transistors and at least one of the P-channel transistors.

[0060] In one embodiment, a method of forming a semiconductor device includes: forming transistors having at least one gate and at least one source / drain on at least a portion of a substrate of a wafer; forming front-side contacts to some of the gates and source / drains; forming a backend structure and a carrier wafer; flipping the wafer and removing at least a portion of the substrate; forming backside contacts to some of the gates and source / drains; forming a backside power rail to the backside contacts connected to the source / drain; wherein the backside power rail is formed between N-channel field effect transistor to N-channel field effect transistor spaces and between at least one P-channel field effect transistor to P-channel field effect transistor spaces; and forming backside local signal lines between the backside power rails.

[0061] The method may include forming backside local signal lines to connect to at least one source / drain or gate through at least one backside contact. The method may include forming a cell architecture having backside local signal lines horizontally extending on the backside and front-side metal vertically extending. The method may include forming backside signal lines at the N-channel field-effect transistor to P-channel field-effect transistor space. The method may include forming at least a pair of adjacent N-channel transistors, wherein the backside power rail includes at least one backside N-channel power rail for the at least a pair of adjacent N-channel transistors, and the at least one backside N-channel power rail is located between the at least a pair of adjacent N-channel transistors; forming two adjacent P-channel transistors, wherein at least one N-channel transistor of the at least a pair of adjacent N-channel transistors is adjacent to the P-channel transistor of the two adjacent P-channel transistors. The backside power rail may include at least one backside P-channel power rail for the two adjacent P-channel transistors, the at least one backside P-channel power rail is located between the two adjacent P-channel transistors, and the backside local signal lines are for the N-channel transistors and the P-channel transistors, and the backside local signal lines are located between at least one of the N-channel transistors and at least one of the P-channel transistors.

[0062] In another embodiment, a semiconductor device includes two adjacent N-channel transistors; two adjacent P-channel transistors, wherein the N-channel transistor of the two adjacent N-channel transistors is adjacent to the P-channel transistor of the two adjacent P-channel transistors; and wherein the backside N-channel power rail for the two adjacent N-channel transistors is located between the two adjacent N-channel transistors, and wherein the backside P-channel power rail for the two adjacent P-channel transistors is located between the two adjacent P-channel transistors, and wherein the backside local signal lines for the N-channel transistors and the P-channel transistors are located between the adjacent N-channel transistors and P-channel transistors.

[0063] The semiconductor device may further include at least one backside contact to connect to at least one source / drain or at least one gate. The backside N-channel power rail may be connected to at least one source / drain using at least one backside contact. The backside local signal lines may be connected to at least one source / drain or at least one gate using at least one backside contact. The semiconductor device may further include a cell architecture having backside local signal lines horizontally extending on the backside and front-side metal vertically extending.

[0064] References to "computers", "processors", etc. should be understood to cover not only computers with different architectures (such as single / multi-processor architectures and sequential or parallel architectures), but also dedicated circuits (such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), signal processing devices, and other processing circuits). References to computer programs, instructions, code, etc. should be understood to cover software or firmware for programmable processors, such as the programmable content of a hardware device, whether instructions for a processor or configuration settings for a fixed function device, gate array, or programmable logic device, etc.

[0065] The memory as described herein can be implemented using any suitable data storage technology, such as semiconductor-based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, non-transitory memory, transitory memory, fixed memory, and removable memory. The memory can include a database for storing data.

[0066] As used herein, a circuit can refer to the following: (a) a hardware circuit implementation, such as an implementation in analog and / or digital circuits, and (b) a combination of a circuit and software (and / or firmware), such as (as applicable): (i) a combination of processors or (ii) portions of a processor / software, including a digital signal processor, software, and memory that work together to cause a device to perform various functions, and (c) a circuit, such as a microprocessor or a portion of a microprocessor, that requires software or firmware for operation, even if the software or firmware is not physically present. As a further example, as used herein, a circuit will also cover an implementation of only a processor (or processors) or a portion of a processor and its accompanying software and / or firmware. For example, if applicable to a particular element, a circuit will also cover a baseband integrated circuit for a mobile phone or an application processor integrated circuit or a similar integrated circuit in a server, cellular network device, or another network device.

[0067] List of abbreviations that can be appended to each other or to other characters using, for example, a dash or hyphen ("-"):

[0068] An input pin of circuit (inverter) (e.g. Figure 4 )

[0069] ASIC Application Specific Integrated Circuit

[0070] A second input pin in circuit B (e.g. Figure 4 )

[0071] BDI Bottom Dielectric Isolation

[0072] BEOL Back End of Line

[0073] BOX Buried Oxide

[0074] BPR Back Power Rail

[0075] BSPDN Back Power Delivery / Supply in Network

[0076] CA Contact to Source / Drain

[0077] CB Contact to Gate

[0078] CMP Chemical Mechanical Planarization / Polishing

[0079] epi Epitaxy

[0080] FPGA Field Programmable Gate Array

[0081] HKMG High-k Metal Gate

[0082] HM Hard Mask

[0083] ILD Interlayer Dielectric

[0084] INV_X2 Inverter X2 Circuit

[0085] M0 Metal Layer 0

[0086] M0P M0 Pitch

[0087] M1 Metal Layer 1

[0088] M1P M1 Pitch

[0089] MOL Middle-of-Line

[0090] N N-Channel

[0091] NAND NAND

[0092] NAND2_X1 NAND2 X1 Logic Circuit

[0093] N2N N-Channel FET to N-Channel FET Space

[0094] N2P N-Channel FET to P-Channel FET Space

[0095] nCA Back Contact to Source / Drain

[0096] nCB Back Contact to Gate

[0097] NFET N-Channel Field-Effect Transistor

[0098] NS Nanowire

[0099] n-Trace n Traces

[0100] P-channel

[0101] P2P P-channel MOSFET to P-channel MOSFET space

[0102] PC gate

[0103] PFET P-channel MOSFET

[0104] Si Silicon

[0105] SiGe Silicon Germanium (e.g., SiGe30, SiGe55, SiGe60)

[0106] SiO2 Silicon Dioxide

[0107] STI Shallow Trench Isolation

[0108] S / D Source / Drain

[0109] V0 Via 0

[0110] VA or Va Via to Source / Drain Contact

[0111] VDD Source / Drain supply voltage, typically a positive voltage VSS Source / Drain supply voltage, typically 0V or ground

[0112] In the above description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the exemplary embodiments disclosed herein. However, one of ordinary skill in the art will understand that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, to avoid obscuring the presented embodiments, details of well-known structures or processing steps may have been omitted or may not be described.

[0113] The description of the invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the form disclosed. Many modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, and to enable others of ordinary skill in the art to understand the invention with various modifications suited to the particular use contemplated.

Claims

1. A semiconductor device, comprising: a back power rail located between N-channel field-effect transistor to N-channel field-effect transistor spaces and between at least one P-channel field-effect transistor to P-channel field-effect transistor spaces; and a back local signal line located between the back power rails.

2. The semiconductor device according to claim 1, wherein the back power rail is connected to the source / drain epitaxy through a back contact.

3. The semiconductor device according to claim 1, wherein the back local signal line is connected to the source / drain epitaxy or the gate through a back contact.

4. The semiconductor device according to claim 1, further comprising a cell architecture having the back local signal line horizontally extending on the back surface and front-side metal vertically extending.

5. The semiconductor device according to claim 1, further comprising at least a pair of adjacent N-channel transistors.

6. The semiconductor device according to claim 5, wherein the back power rail includes at least one back N-channel power rail for the at least a pair of adjacent N-channel transistors, and the at least one back N-channel power rail is located between the at least a pair of adjacent N-channel transistors.

7. The semiconductor device according to claim 5, further comprising two adjacent P-channel transistors, wherein at least one N-channel transistor in the at least a pair of adjacent N-channel transistors is adjacent to one P-channel transistor in the two adjacent P-channel transistors.

8. The semiconductor device according to claim 7, further comprising at least one back P-channel power rail for the two adjacent P-channel transistors, and the at least one back P-channel power rail is located between the two adjacent P-channel transistors.

9. The semiconductor device according to claim 7, further comprising a back local signal line for the N-channel transistors and the P-channel transistors, and the back local signal line is located between at least one of the N-channel transistors and at least one of the P-channel transistors.

10. A method of forming a semiconductor device, comprising: forming transistors having at least one gate and at least one source / drain on at least a portion of a substrate of a wafer; forming front contacts to some of the gates and source / drains; forming a backend structure and a carrier wafer; flipping the wafer and removing at least a portion of the substrate; forming back contacts to some of the gates and source / drains; forming a back power rail to the back contacts connected to the source / drain; wherein the back power rail is formed between N-channel field-effect transistor to N-channel field-effect transistor spaces and between at least one P-channel field-effect transistor to P-channel field-effect transistor spaces; and forming a back local signal line between the back power rails.

11. The method according to claim 10, further comprising forming the back local signal line to be connected to at least one source / drain or connected to the gate through at least one back contact.

12. The method according to claim 10 further includes forming a cell architecture having the backside local signal lines horizontally extending on the backside and front-side metal vertically extending.

13. The method according to claim 10 further includes forming the backside signal line at the space between the N-channel field-effect transistor and the P-channel field-effect transistor.

14. The method according to claim 10 further includes: forming at least a pair of adjacent N-channel transistors, wherein the backside power rail includes at least one backside N-channel power rail for the at least a pair of adjacent N-channel transistors, and the at least one backside N-channel power rail is located between the at least a pair of adjacent N-channel transistors; forming two adjacent P-channel transistors, wherein at least one N-channel transistor of the at least a pair of adjacent N-channel transistors is adjacent to one P-channel transistor of the two adjacent P-channel transistors.

15. The method according to claim 14, wherein the backside power rail includes at least one backside P-channel power rail for the two adjacent P-channel transistors, the at least one backside P-channel power rail is located between the two adjacent P-channel transistors, and the backside local signal lines are for the N-channel transistors and the P-channel transistors, and the backside local signal lines are located between at least one of the N-channel transistors and at least one of the P-channel transistors.

16. A semiconductor device, comprising: two adjacent N-channel transistors; two adjacent P-channel transistors, wherein one N-channel transistor of the two adjacent N-channel transistors is adjacent to one P-channel transistor of the two adjacent P-channel transistors; and wherein a backside N-channel power rail for the two adjacent N-channel transistors is located between the two adjacent N-channel transistors, and wherein a backside P-channel power rail for the two adjacent P-channel transistors is located between the two adjacent P-channel transistors, and wherein backside local signal lines for the N-channel transistors and the P-channel transistors are located between the adjacent N-channel transistors and P-channel transistors.

17. The semiconductor device according to claim 16 further includes at least one backside contact to connect to at least one source / drain or at least one gate.

18. The semiconductor device according to claim 17, wherein the backside N-channel power rail is connected to the at least one source / drain through the at least one backside contact.

19. The semiconductor device according to claim 17, wherein the backside local signal lines are connected to the at least one source / drain or the at least one gate by using the at least one backside contact.

20. The semiconductor device according to claim 16 further includes a cell architecture having the backside local signal lines horizontally extending on the backside and front-side metal vertically extending.

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