Optical detection device and electronic equipment

Abstract

The invention realizes miniaturization of a photoelectric conversion region. In the present invention, an optical detection device comprises: a semiconductor layer having a first surface and a second surface on opposite sides from each other and having photoelectric conversion regions divided by isolation regions; a photoelectric conversion unit provided in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the semiconductor layer into a signal charge; a transfer transistor having a gate electrode provided adjacent to the photoelectric conversion region via a gate insulating film extending in the thickness direction of the semiconductor layer, the transfer transistor transferring a signal charge photoelectrically converted by the photoelectric conversion unit; and a charge holding unit disposed outside the first surface of the semiconductor layer and holding the signal charge transferred from the transfer transistor. In addition, the charge holding unit includes a contact electrode disposed outside the first surface of the semiconductor layer and connected to the photoelectric conversion region.

Description

Technical Field

[0001] The present technology (the technology according to the present disclosure) relates to an optical detection device and an electronic device, and more particularly to a technology effective when applied to an optical detection device having a three-dimensional structure and an electronic device including the optical detection device. Background Art

[0002] Optical detection devices such as solid-state imaging devices and ranging devices include a photoelectric conversion unit that photoelectrically converts light into signal charges, a transfer transistor that transfers the signal charges photoelectrically converted by the photoelectric conversion unit, and a charge holding unit that holds the signal charges transferred by the transfer transistor. In addition, the above-described photoelectric conversion unit, transfer transistor, and charge holding unit are provided in a photoelectric conversion region of a semiconductor layer. The charge holding unit is constituted by a floating diffusion region serving as an FD capacitor (Floating Diffusion Capacitance).

[0003] Patent Document 1 discloses a vertical stacked type image sensor that includes a photodiode chip 170 and a transistor array chip 172 stacked on each other. In addition, Patent Document 1 discloses a transfer transistor that includes a semiconductor transfer channel 180 provided on a photodiode 154, a transfer gate 158 provided around the semiconductor transfer channel 180 with an oxide 182 interposed therebetween, and a drain region 183 provided in the semiconductor transfer channel 180. [Citation List] [Patent Document]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2019-193305 Summary of the Invention Summary of the Invention [Technical Problem to be Solved by the Invention]

[0005] Meanwhile, with the recent market demand for high-resolution image sensors, the development of image sensors including miniaturized sensor pixels has been promoted. The miniaturization of each sensor pixel requires reducing the size of the photoelectric conversion region of the semiconductor layer.

[0006] However, the conventional photoelectric conversion region includes a floating diffusion region serving as a charge holding unit and a transfer transistor. The floating diffusion region requires a sufficient size to generate a floating diffusion capacitance (FD capacitance: Floating Diffusion Capacitance) that the pixel circuit can use to read the signal charge held in the floating diffusion region. On the other hand, the transfer transistor needs to maintain a sufficient gate electrode size according to the size of the floating diffusion region to control the transfer of signal charge from the photoelectric conversion unit to the floating diffusion region. Therefore, the floating diffusion region and the transfer transistor are as difficult to miniaturize as the photoelectric conversion region, which becomes a factor hindering the reduction in the size of the photoelectric conversion region.

[0007] An object of the present technology is to provide a technology capable of reducing the size of the photoelectric conversion region. [Solution to the Problem]

[0008] (1) The optical detection device according to one aspect of the present technology includes: a semiconductor layer having a first surface and a second surface located on opposite sides of each other, and having a photoelectric conversion region divided by isolation regions; a photoelectric conversion unit provided in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the semiconductor layer into signal charges; a transfer transistor having a gate electrode disposed adjacent to the photoelectric conversion region with a gate insulating film extending in the thickness direction of the semiconductor layer, and transferring the signal charges photoelectrically converted by the photoelectric conversion unit; and a charge holding unit provided outside the photoelectric conversion region and holding the signal charges transferred from the transfer transistor. In addition, the charge holding unit includes a contact electrode connected to the photoelectric conversion region.

[0009] (2) The optical detection device according to another aspect of the present technology includes: a first semiconductor portion having a first surface and a second surface located on opposite sides of each other, and having a photoelectric conversion region; a second semiconductor portion protruding from the first semiconductor portion toward the first surface side; a third semiconductor portion provided on the first surface side of the first semiconductor portion and joined to the distal end of the second semiconductor portion; a photoelectric conversion unit provided in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the first semiconductor portion into signal charges; a charge holding unit provided in the third semiconductor portion; and a transfer transistor transferring the signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit. In addition, the transfer transistor includes: a first gate electrode adjacent to the second semiconductor portion with a first gate insulating film therebetween, the first gate insulating film extending in the protruding direction of the second semiconductor portion; and a second gate electrode disposed side by side with the first gate electrode and spaced apart from the first gate electrode in the protruding direction of the second semiconductor portion, and adjacent to the third semiconductor portion with a second gate insulating film therebetween.

[0010] (3) An electronic device according to another aspect of the present technology includes: the above-described optical detection device; an optical system that forms an image of image light received from a subject on the optical detection device; and a signal processing circuit that performs signal processing on a signal output from the optical detection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a chip layout diagram schematically showing an example of a solid-state imaging device according to a first embodiment of the present technology. Figure 2 is an exploded view schematically showing an example of a solid-state imaging device according to a first embodiment of the present technology. Figure 3 is an equivalent circuit diagram showing a configuration example of a sensor pixel unit mounted on a solid-state imaging device according to a first embodiment of the present technology. Figure 4A shows Figure 3 an equivalent circuit diagram of another example of a pixel circuit in Figure 4B shows Figure 3 an equivalent circuit diagram of another example of a pixel circuit in Figure 4C shows Figure 3 an equivalent circuit diagram of another example of a pixel circuit in Figure 5 is a plan view schematically showing an arrangement pattern of pixel transistors included in a pixel circuit of a solid-state imaging device according to a first embodiment of the present technology. Figure 6 is a plan view schematically showing an arrangement pattern of a transfer transistor and a contact electrode in a photoelectric conversion region of a solid-state imaging device according to a first embodiment of the present technology. Figure 7 is a vertical cross-sectional view showing a vertical cross-sectional structure of a solid-state imaging device according to a first embodiment of the present technology, and is a vertical cross-sectional view schematically showing a vertical cross-sectional structure at the same position as the a5-a5 cross-sectional line in Figure 5 Figure 8 shows Figure 7 an enlarged vertical cross-sectional view of an enlarged portion of ​ Fig.9A is a vertical cross-sectional view schematically showing Modification 1-A of the first embodiment according to the present technology. Fig. 9B is a vertical cross-section schematically showing Modification 1-B of the first embodiment according to the present technology. Fig. 10A is a vertical cross-sectional view schematically showing Modification 2-A of the first embodiment according to the present technology. Fig. 10B is a vertical cross-section schematically showing Modification 2-B of the first embodiment according to the present technology. Fig. 10C is a vertical cross-section schematically showing Modification 2-C of the first embodiment according to the present technology. Fig.11 is a vertical cross-section schematically showing Modification 3 of the first embodiment according to the present technology. Fig.12 is an equivalent circuit diagram showing a configuration example of a sensor pixel unit mounted on a solid-state imaging device according to the second embodiment of the present technology. Fig.13 is a plan view schematically showing an arrangement pattern of pixel transistors included in a pixel circuit of a solid-state imaging device according to the second embodiment of the present technology. Fig.14 is a plan view schematically showing an arrangement pattern of transfer transistors and contact electrodes in four photoelectric conversion regions included in one sensor pixel group of a solid-state imaging device according to the second embodiment of the present technology. Fig.15 is an equivalent circuit diagram showing a configuration example of a sensor pixel unit mounted on a solid-state imaging device according to the third embodiment of the present technology. Fig.16 is a plan view schematically showing an arrangement pattern of pixel transistors included in a pixel circuit of a solid-state imaging device according to the third embodiment of the present technology. Fig.17 is a plan view schematically showing an arrangement pattern of transfer transistors and contact electrodes in four photoelectric conversion regions included in one sensor pixel group of a solid-state imaging device according to the third embodiment of the present technology. Fig.18 is an exploded view schematically showing an example of a solid-state imaging device according to the fourth embodiment of the present technology. Fig.19 is an equivalent circuit diagram showing a configuration example of a sensor pixel unit mounted on a solid-state imaging device according to the fourth embodiment of the present technology. Fig. 20It is a plan view schematically showing the layout pattern of pixel transistors included in a pixel circuit of a solid-state imaging device according to a fourth embodiment of the present technology and second gate electrodes included in transfer transistors. Fig.21 It is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of a solid-state imaging device according to a fourth embodiment of the present technology. Fig. 22 It shows Fig.21 An enlarged vertical cross-sectional view of an enlarged portion. Fig.23A It is a vertical cross-sectional view schematically showing the transfer direction of signal charges by transfer transistors. Fig. 23B It is a diagram showing an example of potentials during charge transfer by transfer transistors. Fig.24A It is a vertical cross-sectional view schematically showing steps of a manufacturing method of a solid-state imaging device according to a fourth embodiment of the present technology. Fig. 24B It schematically shows Fig.24A A vertical cross-sectional view of a step after. Fig.24C It schematically shows Fig. 24B A vertical cross-sectional view of a step after. Fig.24D It schematically shows Fig.24C A vertical cross-sectional view of a step after. Fig.24E It schematically shows Fig.24D A vertical cross-sectional view of a step after. Fig.24F It schematically shows Fig.24E A vertical cross-sectional view of a step after. Figure 24G It schematically shows Fig.24F A vertical cross-sectional view of a step after. Fig.24H It schematically shows Figure 24G A vertical cross-sectional view of a step after. Fig.24I It schematically shows Fig.24H A vertical cross-sectional view of a step after. Fig.24J It schematically shows Fig.24I A vertical cross-sectional view of a step after. Figure 24K It schematically shows Fig.24J A vertical cross-sectional view of a step after. Figure 24L It schematically shows Figure 24K Vertical cross-sectional view of a subsequent step. Figure 24M Schematically shows Figure 24L Vertical cross-sectional view of a subsequent step. Fig.24N Schematically shows Figure 24M Vertical cross-sectional view of a subsequent step. Fig.24O Schematically shows Fig.24N Vertical cross-sectional view of a subsequent step. Figure 24P Schematically shows Fig.24O Vertical cross-sectional view of a subsequent step. Figure 24Q Schematically shows Figure 24P Vertical cross-sectional view of a subsequent step. Figure 24R Schematically shows Figure 24Q Vertical cross-sectional view of a subsequent step. Figure 24S Schematically shows Figure 24R Vertical cross-sectional view of a subsequent step. Fig.25 Equivalent circuit diagram showing a modification of the fourth embodiment. Fig.26 Equivalent circuit diagram showing a configuration example of a sensor unit mounted on a solid-state imaging device according to the fifth embodiment of the present technology. Fig. 27 Vertical cross-sectional view schematically showing a configuration example of a solid-state imaging device according to the fifth embodiment of the present technology. Fig.28 Diagram showing a configuration example of an electronic device according to the sixth embodiment of the present technology. Detailed description of specific embodiments

[0012] Hereinafter, embodiments of the present technology will be described in detail with reference to the accompanying drawings. Note that the same or similar parts included in the accompanying drawings referred to in the following description will be given the same or similar reference numerals. However, it should be considered that these drawings are merely schematic diagrams, which may include relationships between thickness and planar dimensions, ratios of thicknesses of respective layers, and other conditions different from the actual situation. Therefore, specific thicknesses and dimensions should be determined in combination with the following description.

[0013] In addition, it goes without saying that the dimensional relationships and ratios included in some of the drawings may be different from those in other drawings. Moreover, the beneficial effects brought about are not limited to those described only as examples in this specification, and other beneficial effects may also be brought about.

[0014] In addition, the following embodiments are merely examples of devices and methods for implementing the technical idea of the present technology, and it is not necessary to adopt the specific configurations described below. Therefore, the technical idea of the present technology can be variously modified within the technical scope defined by the claims.

[0015] Furthermore, the definitions of directions such as the up-down direction included in the following description are only given for convenience of explanation, and thus the technical idea of the present technology is not limited by these definitions. For example, it goes without saying that when observing an object rotated by 90 degrees, the up-down direction of the object is switched to the left-right direction, or when observing an object rotated by 180 degrees, the up-down direction of the object is inverted up and down.

[0016] In addition, in the following embodiments, the case where the first-conductivity-type semiconductor and the second-conductivity-type semiconductor are a p-type semiconductor and an n-type semiconductor, respectively, will be described as an example, but the selected conductivity types can be reversed, that is, the first-conductivity-type semiconductor and the second-conductivity-type semiconductor can be an n-type semiconductor and a p-type semiconductor, respectively.

[0017] In addition, among the three directions perpendicular to each other in space, in the following embodiments, it is assumed that the first direction and the second direction perpendicular to each other in the same plane are the X direction and the Y direction, respectively, and the third direction perpendicular to the first direction and the second direction is the Z direction.

[0018] [First Embodiment] Here, in the first embodiment, an optical detection device to which the present technology is applied will be described, that is, an example of a solid-state imaging device called a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor. In addition, the first embodiment to the third embodiment here will be described based on the following assumption: the thickness direction of the semiconductor layer 101 described below corresponds to the Z direction.

[0019] <<Overall Configuration of Solid-State Imaging Device>> First, the overall configuration of the solid-state imaging device 1A will be described. As Figure 1 shown, the solid-state imaging device 1A according to the first embodiment of the present technology mainly includes a semiconductor chip 2, and the semiconductor chip 2 has a square as a two-dimensional planar shape in a plan view. Specifically, since the solid-state imaging device 1A is mounted on the semiconductor chip 2, the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. As Fig.28As shown, the solid-state imaging device 1A (601) introduces image light (incident light 606) from a subject through an optical lens 602, converts the amount of incident light 606 that forms an image on the imaging surface into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal (image signal).

[0020] As Figure 1 shown, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes, in a two-dimensional plane including the X direction and the Y direction that are perpendicular to each other, a square pixel array portion 2A provided at the central portion and a peripheral portion 2B provided outside the pixel array portion 2A and surrounding the pixel array portion 2A. The semiconductor chip 2 is formed as a small piece divided from a semiconductor wafer in which a plurality of semiconductor layers are stacked. Therefore, the solid-state imaging device 1A described below has a substantially similar configuration even when in the state of a wafer before being divided into small pieces.

[0021] For example, the pixel array portion 2A is a light-receiving surface that receives light converged by the Fig.28 shown optical lens (optical system) 602. In addition, a plurality of sensor pixels 12 are arranged in a matrix in the pixel array portion 2A in a two-dimensional plane including the X direction and the Y direction. In other words, the sensor pixels 12 are repeatedly arranged in each of the X direction and the Y direction that are perpendicular to each other in the two-dimensional plane.

[0022] As Figure 1 shown, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. For example, the plurality of bonding pads 14 are arranged along each of the four sides of the two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 serves as an input / output terminal for electrically connecting the semiconductor chip 2 to an external device.

[0023] <Semiconductor Chip> As Figure 2 shown, the solid-state imaging device 1A (semiconductor chip 2) according to the first embodiment includes a first substrate (first layer) 10, a second substrate (second layer) 20, and a third substrate (third layer) 30. In addition, the solid-state imaging device 1A has a three-dimensional structure in which the first substrate 10, the second substrate 20, and the third substrate 30 are stacked in sequence. In addition, the solid-state imaging device 1A according to the first embodiment further includes a sensor pixel unit PU1 as Figure 3 shown. As Figure 2 shown, the first substrate 10 has a plurality of sensor pixels 12 provided in the semiconductor layer 101 and performing photoelectric conversion. Each of the plurality of sensor pixels 12 is arranged in a matrix in the pixel array portion 2A of the first substrate 10 in a plan view.

[0024] As Figure 2 As shown, the second substrate 20 includes pixel circuits (read circuits) 22, and each pixel circuit 22 outputs a pixel signal based on the signal charge output from the corresponding sensor pixel 12. In addition, the second substrate 20 includes a plurality of pixel driving lines 23 extending in the row direction (X direction) and a plurality of vertical signal lines 24 extending in the column direction (Y direction). Therefore, the solid-state imaging device 1A of the first embodiment herein is configured such that the sensor pixels 12 are provided in the first substrate 10 and the pixel circuits 22 are provided in the second substrate 20.

[0025] Here, note that the third substrate 30, the second substrate 20, and the first substrate 10 may also be referred to as the Bottom substrate, the Middle substrate, and the Top substrate, respectively, in some cases.

[0026] <Logic circuit> As Figure 2 shown, the third substrate 30 includes a logic circuit 32 that processes pixel signals. For example, the logic circuit 32 includes a vertical driving circuit 33, a column signal processing circuit 34, a horizontal driving circuit 35, and a system control circuit 36, and also includes an output circuit (not shown). The logic circuit 32 (specifically, the horizontal driving circuit 35) outputs the output voltage Vout of each sensor pixel 12 to the outside. For example, the logic circuit 32 includes a complementary MOS (CMOS: Complementary MOS) circuit having n-channel conductive type metal oxide semiconductor field effect transistors (MOSFETs: Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductive type MOSFETs as field effect transistors. Alternatively, each field effect transistor may be a metal insulator semiconductor field effect transistor (MISFET: Metal Insulator Semiconductor FET) that includes a silicon nitride film as a gate insulating film or a laminated film (composite film) of a laminated body including a silicon nitride (Si 3 N 4 ) film and a silicon oxide film, etc.

[0027] For example, Figure 2The vertical driving circuit 33 shown includes a shift register. The vertical driving circuit 33 sequentially selects a desired pixel driving line 23 and supplies a pulse for driving the sensor pixel 12 to the selected pixel driving line 23 to drive each sensor pixel 12 row by row. Specifically, the vertical driving circuit 33 sequentially scans each sensor pixel 12 of the pixel array unit 2A row by row in the vertical direction, and supplies the pixel signal received from each sensor pixel 12 as a signal corresponding to the signal charge generated by the photoelectric conversion unit (photoelectric conversion element) of the corresponding sensor pixel 12 based on the light reception amount to the column signal processing circuit 34 via the vertical signal line 24.

[0028] For example, Figure 2 The column signal processing circuit 34 shown is arranged in one-to-one correspondence with the columns of the sensor pixels 12, and performs signal processing such as noise removal on the signals output from the sensor pixels 12 in one row for each pixel column. For example, each column signal processing circuit 34 performs signal processing such as correlated double sampling (CDS: Correlated Double Sampling) and analog-to-digital (AD: Analog Digital) conversion to remove fixed pattern noise inherent in the pixels.

[0029] For example, Figure 2 The horizontal driving circuit 35 shown includes a shift register. The horizontal driving circuit 35 sequentially selects each column signal processing circuit 34 by sequentially outputting horizontal scan pulses to the column signal processing circuit 34, and causes each column signal processing circuit 34 to output the processed pixel signal to a horizontal signal line (not shown).

[0030] Figure 2 The system control circuit 36 shown generates a clock signal and a control signal as operation references for the vertical driving circuit 33, the column signal processing circuit 34, the horizontal driving circuit 35, etc. based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock signal. Thereafter, the system control circuit 36 outputs the generated clock signal and control signal to the vertical driving circuit 33, the column signal processing circuit 34, the horizontal driving circuit 35, etc.

[0031] Although not shown in Figure 2 the output circuit included in the logic circuit 32 performs signal processing on the pixel signals sequentially supplied from each column signal processing circuit 34 via a horizontal signal line (not shown) and outputs the processed pixel signals. For example, the signal processing may include buffering, black level adjustment, column change correction, various digital signal processes, etc.

[0032] <Sensor Pixel Unit> As Figure 3As shown, the sensor pixel unit PU1 includes a photoelectric conversion unit 105, a transfer transistor TR, a charge holding unit 15, and a pixel circuit (read circuit) 22. The photoelectric conversion unit 105 and the transfer transistor TR are provided in Figure 7 the photoelectric conversion region 102 shown. Additionally, for each sensor pixel 12, the photoelectric conversion region 102 including the photoelectric conversion unit 105 and the transfer transistor TR is provided in Figure 7 the semiconductor layer 101 shown.

[0033] (Photoelectric conversion unit) For example, Figure 3 the photoelectric conversion unit 105 shown includes a pn junction type photodiode (PD) as a photoelectric conversion element and generates signal charges corresponding to the received light amount. The photoelectric conversion unit 105 is configured such that the cathode side is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground).

[0034] (Charge holding unit) Figure 3 The charge holding unit 15 shown mainly holds (accumulates) the signal charges transferred from the photoelectric conversion unit 105 via the transfer transistor TR, that is, the signal charges transferred from the transfer transistor TR. The charge holding unit 15 includes, but is not limited to, a floating contact electrode 208 and a floating diffusion region 206 that are respectively the FD capacitor (floating diffusion capacitor) of the charge holding unit 15. The floating contact electrode 208 is electrically connected to the transfer transistor TR and is also electrically connected to the floating contact electrode 208 via a conduction path 213. Here, the conduction path 213 also serves as the FD capacitor of the charge holding unit 15.

[0035] (Transfer transistor) Figure 3 The transfer transistor TR shown transfers the signal charges photoelectrically converted by the photoelectric conversion unit 105 to the charge holding unit 15. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 105, while the drain region of the transfer transistor TR is electrically connected to the charge holding unit 15. Additionally, the gate electrode of the transfer transistor TR is electrically connected to Figure 2 the transfer transistor drive line in the pixel drive line 23 shown.

[0036] <Pixel circuit> As Figure 3As shown, the input side of the pixel circuit 22 is electrically connected to the output side of the charge holding unit 15. The first embodiment given here as an example has the following circuit configuration: Each pixel circuit 22 is assigned to a corresponding one of the sensor pixels 12 (photoelectric conversion region 102) one by one. However, it is not necessary to adopt this configuration of the first embodiment. For example, the following circuit configuration can be adopted: Each pixel circuit 22 is shared by a plurality of sensor pixels 12 (photoelectric conversion region 102). In addition, the following circuit configuration can also be adopted: Each pixel circuit 22 is shared by a sensor pixel group (photoelectric conversion group) that is a single unit and is composed of four sensor pixels 12 arranged in a 2×2 array with two sensor pixels 12 arranged in each of the X direction and the Y direction. In addition, the following circuit configuration can also be adopted: Each pixel circuit 22 is shared by a sensor pixel group (photoelectric conversion group) composed of two sensor pixels 12 that is a single unit. Additionally, the following circuit configuration can also be adopted: Each pixel circuit 22 is shared by a sensor pixel group (photoelectric conversion group) composed of four or more sensor pixels 12 that is a single unit.

[0037] Figure 3 The pixel circuit 22 shown reads the signal charge held in the charge holding unit 15, converts the read signal charge into a pixel signal, and outputs the pixel signal. In other words, the pixel circuit 22 converts the signal charge photoelectrically converted by the photoelectric conversion unit 105 (photodiode PD) into a pixel signal based on the signal charge and outputs the pixel signal.

[0038] For example, the pixel circuit 22 includes, but is not limited to, an amplifying transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors. For example, each of these pixel transistors (AMP, SEL, and RST) and the above-mentioned transfer transistor TR are composed of MOSFETs that are field effect transistors. Alternatively, each of these transistors can also be composed of MISFETs.

[0039] Among the pixel transistors included in the pixel circuit 22, each of the selection transistor SEL and the reset transistor RST serves as a switching element, while the remaining amplifying transistor AMP serves as an amplifying element.

[0040] As Figure 3 shown, the amplifying transistor AMP is configured such that the source region is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line VDD and the drain region of the reset transistor RST. In addition, the gate electrode of the amplifying transistor AMP is electrically connected to the charge holding unit 15 and the source region of the reset transistor RST.

[0041] As Figure 3As shown, the selection transistor SEL is configured such that the source region is electrically connected to the vertical signal line 24 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP. Additionally, the gate electrode of the selection transistor SEL is electrically connected to Figure 2 the selection transistor drive line in the pixel drive line 23 shown.

[0042] As Figure 3 shown, the reset transistor RST is configured such that the source region is electrically connected to the charge holding unit 15 and the gate electrode of the amplification transistor AMP, and the drain region is electrically connected to the power supply line VDD and the drain region of the amplification transistor AMP. Additionally, the gate electrode of the reset transistor RST is electrically connected to Figure 2 the reset transistor drive line of the pixel drive line 23 shown.

[0043] Figure 3 As shown, when the transfer transistor TR is in the on state, the transfer transistor TR transfers the signal charge generated by the photoelectric conversion unit 105 to the charge holding unit 15.

[0044] Figure 3 As shown, when the reset transistor RST is in the on state, the reset transistor RST resets the potential (signal charge) of the charge holding unit 15 to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal received from the pixel circuit 22.

[0045] Figure 3 As shown, the amplification transistor AMP generates a signal representing a voltage corresponding to the level of the signal charge held in the charge holding unit 15 as a pixel signal. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal representing a voltage corresponding to the level of the signal charge generated by the photoelectric conversion unit 105. When the selection transistor SEL is in the on state, the amplification transistor AMP amplifies the potential of the charge holding unit 15 and outputs a voltage corresponding to that potential to the column signal processing circuit 34 via the vertical signal line 24 (VSL).

[0046] Here, reference is made to Figure 3To explain, during the operation of the solid-state imaging device 1A according to the first embodiment of the present invention, the signal charges generated by the photoelectric conversion unit 105 of the sensor pixel 12 are transferred via the transfer transistor TR of the sensor pixel 12 and held (accumulated) in the charge holding unit 15. Thereafter, the signal charges held in the charge holding unit 15 are read by the pixel circuit 22 and applied to the gate electrode of the amplification transistor AMP of the pixel circuit 22. The selection control signal in the horizontal line is supplied from the vertical shift register to the gate electrode of the selection transistor SEL of the pixel circuit 22. Thereafter, the selection transistor SEL is turned on in response to the selection control signal set to the high (H) level, and causes a current corresponding to the potential of the charge holding unit 15 amplified by the amplification transistor AMP to flow in the vertical signal line 24. In addition, the reset transistor RT is turned on in response to the reset control signal set to the high (H) level and applied to the gate electrode of the reset transistor RST of the pixel circuit 22, and resets the signal charges accumulated in the charge holding unit 15.

[0047] For example, the pixel transistors (AMP, SEL, and RST) included in the pixel circuit 22 are provided in Figure 7 the semiconductor layer 201 shown, but it is not necessarily provided in this way.

[0048] <Other pixel circuits> Note that the pixel circuit 22 may have a different configuration. For example, as Figure 4A shown, the selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain region of the reset transistor RST is electrically connected to the power supply line VDD and the drain region of the selection transistor SEL. In addition, the source region of the selection transistor SEL is electrically connected to the drain region of the amplification transistor AMP, and the gate electrode of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 2 ). The source region (output terminal of the pixel circuit 22) of the amplification transistor AMP is electrically connected to the vertical signal line 24, and the gate electrode of the amplification transistor AMP is electrically connected to the source region of the reset transistor RST.

[0049] In addition, the pixel circuit 22 may have other different configurations. For example, as Figure 4B and Figure 4C shown, the switching transistor FDG may be provided between the source region of the reset transistor RST and the gate electrode of the amplification transistor AMP. The switching transistor FDG is used to switch the conversion efficiency. Generally, the pixel signal is low when imaging in a dark place. If the FD capacitance C (floating diffusion capacitance C) of the charge holding unit 15 is high during the charge-voltage conversion based on Q = CV, the voltage V will decrease when converted to a voltage by the amplifying transistor AMP. On the other hand, the pixel signal is high in a bright place. Therefore, unless the FD capacitance C of the charge holding unit 15 is high, it is difficult for the charge of the photoelectric conversion unit 105 (photodiode PD) to be received by the charge holding unit 15. In addition, the FD capacitance C of the charge holding unit 15 needs to be high to avoid an excessive increase in the voltage V (i.e., to reduce the voltage V) when converted to a voltage by the amplifying transistor AMP. Considering these situations, when the switching transistor FDG is turned on, the gate capacitance increases the capacitance of the switching transistor FDG. Therefore, the total FD capacitance C increases. On the other hand, when the switching transistor FDG is turned off, the total FD capacitance C decreases. It can be clearly seen from the above that the FD capacitance C is variable, so the conversion efficiency can be switched according to the on / off switching of the switching transistor FDG.

[0050] <<Specific Configuration of Solid-State Imaging Device>> Next, the specific configuration of the solid-state imaging device 1A according to the first embodiment of the present invention will be described with reference to Figures 5 to 8 the following. Figure 5 is a plan view schematically showing the layout pattern of pixel transistors (AMP, SEL, and RST) included in the pixel circuit 22. Figure 6 is a plan view schematically showing the layout pattern of the transfer transistor TR and the floating contact electrode 208 in the photoelectric conversion region 102. Figure 7 is schematically showing the Figure 5 vertical cross-sectional structure at the same position as the a5-a5 cross-sectional line in Note that Figure 5 and Figure 6 each show a plan view of the semiconductor chip 2 when viewed from the side opposite to the light incident surface side. At the same time, Figure 1 and Figure 7 each are views upside down with respect to Figure 8 Figure 1

[0051] As shown in Figure 7 ​​As shown, the semiconductor chip 2 includes a first substrate 10, a second substrate 20, and a third substrate 30 that are stacked relative to each other. The pixel array portion 2A, the peripheral portion 2B, the bonding pad 14, the photoelectric conversion region 102, etc. are mainly provided in the first substrate 10. The pixel transistors (AMP, SEL, and RST) included in the pixel circuit 22 are mainly provided in the second substrate 20. The logic circuit 32, etc. are mainly provided in the third substrate 30.

[0052] <First substrate> As Figure 7 shown, the first substrate 10 includes a semiconductor layer 101, a multilayer wiring layer 120 provided on the first surface S1 side of the semiconductor layer 101, and an optical layer 130 provided on the second surface S2 side of the semiconductor layer 101. The semiconductor layer 101 has a first surface S1 and a second surface S2 located on opposite sides in the thickness direction (Z direction) of the first substrate 10. The first substrate 10 further includes the charge holding unit 15. The charge holding unit 15 is provided outside the first surface S1 of the semiconductor layer 101. Note here that the semiconductor layer 101 according to the first embodiment of the present document corresponds to a specific example of the "semiconductor layer" or "first semiconductor layer" of the present technology.

[0053] (Semiconductor layer) As Figure 7 shown, the semiconductor layer 101 includes an isolation region 106 extending in the thickness direction (Z direction) of the semiconductor layer 101 and a photoelectric conversion region 102 divided by the isolation region 106. Therefore, the semiconductor layer 101 includes a first surface S1 and a second surface S2 located on opposite sides and the photoelectric conversion region 102 divided by the isolation region 106. In addition, as Figure 6 and Figure 7 shown, in the photoelectric conversion region 102 of the semiconductor layer 101, the transfer transistor TR is provided in the surface layer portion (upper part) on the first surface S1 side of the semiconductor layer 101.

[0054] The semiconductor layer 101 may be composed of a semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide (GaAs) substrate, and an indium phosphide (InP) substrate. According to the first embodiment of the present document, for example, the semiconductor layer 101 is an i-type semiconductor substrate made of single crystal silicon.

[0055] Note here that, in some cases, the first surface S1 of the semiconductor layer 101 will be referred to as the element formation surface or the main surface, and the second surface S2 will be referred to as the light incident surface or the back surface. The solid-state imaging device 1A according to the first embodiment of the present disclosure receives light from the second surface (light incident surface, back surface) S2 side of the semiconductor layer 101, and photoelectrically converts the light in the photoelectric conversion region 102 (specifically, the photoelectric conversion unit 105) of the semiconductor layer 101.

[0056] In addition, the plan view refers to a view in the direction along the thickness direction (Z direction) of the semiconductor chip 2. In addition, the cross-sectional view refers to a cross-section taken in the thickness direction (Z direction) of the semiconductor chip 2 and observed in a direction perpendicular to the thickness direction (Z direction) of the semiconductor chip 2 (X direction or Y direction). Additionally, the photoelectric conversion region 102 may also be referred to as the photoelectric conversion unit.

[0057] (Isolation region) As Figure 7 shown, the isolation region 106 extends between the first surface S1 side and the second surface S2 side of the semiconductor layer 101 to electrically and optically isolate the photoelectric conversion regions 102 adjacent to each other in the two-dimensional plane. For example, the isolation region 106 has, but is not limited to, a groove-type isolation structure that includes an insulating film in a groove extending in the thickness direction (Z direction) of the semiconductor layer 101. Although not shown in detail in the figure, referring to Figure 6 it can be understood that the isolation region 106 has a lattice-like planar pattern in which a plurality of first portions extending in the X direction and a plurality of second portions extending in the Y direction cross each other in the plan view.

[0058] (Photoelectric conversion region) Although not shown in detail in Figures 5 to 7 , the photoelectric conversion region 102 is provided in the semiconductor layer 101 for each sensor pixel 12, and is repeatedly arranged with the isolation region 106 interposed therebetween in each of the X direction and the Y direction. Specifically, the semiconductor layer 101 includes a plurality of photoelectric conversion regions 102 that are provided adjacent to each other with the isolation region 106 extending in the thickness direction (Z direction) of the semiconductor layer 101 interposed therebetween.

[0059] As Figure 7 shown, the photoelectric conversion region 102 includes a p-type semiconductor region 103 extending between the first surface S1 side and the second surface S2 side of the semiconductor layer 101 and an n-type semiconductor region 104 formed within the above p-type semiconductor region 103. In addition, the photoelectric conversion region 102 includes the above-described transfer transistor TR.

[0060] The n-type semiconductor region 104 extends in the p-type semiconductor region 103 between the first face S1 side and the second face S2 side of the semiconductor layer 101 while being separated from each of the first face S1 of the semiconductor layer 101 and the isolation region 106. In addition, the p-type semiconductor region 103 is provided in the semiconductor layer 101 between the first face S1 and the n-type semiconductor region 104 and between the isolation region 106 and the n-type semiconductor region 104.

[0061] (Photoelectric conversion unit) Figure 7 The photoelectric conversion unit 105 shown mainly includes an n-type semiconductor region 104, and constitutes a pn junction type photodiode (PD) formed by a pn junction between a p-type semiconductor region 103 and an n-type semiconductor region 104. The photoelectric conversion unit 105 photoelectrically converts light incident from the second surface S2 side of the semiconductor layer 101 into a signal charge, and temporarily holds (accumulates) the photoelectrically converted signal charge. The photoelectric conversion unit 105 is provided for each photoelectric conversion region 102 (sensor pixel 12).

[0062] (Pass transistor) like Figure 7 and Figure 8 As shown, the transfer transistor TR is provided at the surface layer portion of the photoelectric conversion region 102 on the first surface S1 side of the semiconductor layer 101. In addition, the transfer transistor TR is provided for each photoelectric conversion region 102 (sensor pixel 12).

[0063] The transfer transistor TR includes a gate recess portion 110 formed in the surface portion (upper portion) on the first surface S1 side of the semiconductor layer 101, an insulating film 111 formed on the bottom wall (bottom surface) in the above-mentioned gate recess portion 110, a gate insulating film 112 formed on the side wall in the gate recess portion 110, and a gate electrode 113 provided in the gate recess portion 110 via the insulating film 111 and the gate insulating film 112 provided in this manner. The transfer transistor TR also includes a channel forming portion 114 formed in the semiconductor layer 101 and adjacent to the gate insulating film 112 in a plan view, and a photoelectric conversion unit 105 and a charge holding unit 15 serving as a source region and a drain region, respectively.

[0064] The gate electrode 113 extends in the thickness direction (depth direction (Z direction)) of the semiconductor layer 101. In addition, in a plan view, the gate electrode 113 is adjacent to the channel forming portion 114 via the gate insulating film 112. Specifically, the transfer transistor TR includes a gate electrode 115 provided in the photoelectric conversion region 102 via the gate insulating film 112 extending in the thickness direction of the semiconductor layer 101, and transfers the signal charge photoelectrically converted by the photoelectric conversion unit 105 to the charge holding unit 15.

[0065] The insulating film 111 is interposed between the bottom wall of the gate electrode 113 and the semiconductor layer 101 to insulate the gate electrode 113 from the semiconductor layer 101. The film thickness of the insulating film 111 is greater than the film thickness of the gate insulating film 112.

[0066] The gate insulating film 112 extends along the thickness (depth direction) of the semiconductor layer 101. Additionally, although not shown in detail in the figure, the gate insulating film 112 is provided on the sidewalls of the gate electrode 113 so as to surround the gate electrode 113 in a plan view. For example, each of the gate insulating film 112 and the insulating film 111 is composed of a silicon oxide film.

[0067] For example, the gate electrode 113 is disposed in the gate groove portion 110 such that the upper surface portion thereof is substantially flush with the first surface S1 of the semiconductor layer 101, but is not limited thereto. In addition, for example, as Figure 6 shown, the gate electrode 113 has the following planar pattern: in a plan view, the gate electrode 113 includes at least one side 113s adjacent to the floating contact electrode 208. The gate electrode 113 according to the first embodiment herein has an L-shaped planar pattern, and in a plan view, the gate electrode 113 includes two sides 113s respectively adjacent to the floating contact electrode 208. For example, the gate electrode 113 is composed of a polysilicon film into which impurities for reducing resistance are introduced.

[0068] (Multilayer wiring layer) As Figure 7 and Figure 8 shown, the multilayer wiring layer 120 is provided on the first surface S1 side of the semiconductor layer 101. Although not shown in detail in the figure, the multilayer wiring layer 120 has a stacked structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked. For example, each insulating layer may be composed of silicon oxide. For example, each wiring layer may be composed of a metal such as aluminum (Al) and copper (Cu), an alloy mainly composed of Al or Cu, etc.

[0069] Note that Figure 7 and Figure 8 each show a contact electrode 121 provided in the insulating layer of the multilayer wiring layer 120 and a wiring 122 provided in the wiring layer of the multilayer wiring layer 120. The wiring 122 is electrically connected to the gate electrode 113 of the transfer transistor TR via the contact electrode 121. In addition, the photoelectric conversion region 102 in the semiconductor layer 101 and the gate electrode 113 of the transfer transistor TR are covered by the lowermost insulating layer of the multilayer wiring layer 120.

[0070] (Optical layer) As Figure 7As shown, the optical layer 130 is disposed on the second surface S2 side of the semiconductor layer 101. The optical layer 130 includes a planarization film 131, a light-shielding film 132, an optical filter 133, and a microlens (on-chip lens) 134 that are sequentially formed on the second surface S2 side of the semiconductor layer 101 starting from the second surface S2 side.

[0071] The planarization film 131 is disposed on the second surface S2 side of the semiconductor layer 101 so as to cover the semiconductor layer 101, and planarizes the second surface S2 side of the semiconductor layer 101.

[0072] The light-shielding film 132 has a lattice-shaped planar pattern in a plan view to divide the adjacent sensor pixels 12 from each other.

[0073] The optical filter 133 and the microlens 134 are provided for each photoelectric conversion region 102 (sensor pixel 12). The optical filter 133 separates the color of the incident light incident from the light incident surface side of the semiconductor chip 2. The microlens 134 converges the incident light and effectively introduces the converged light into the photoelectric conversion region 102 (sensor pixel 12).

[0074] <Second substrate> As Figure 7 shown, the second substrate 20 is disposed on the multilayer wiring layer 120 side of the first substrate 10. The second substrate 20 includes a semiconductor layer 201 having a first surface and a second surface on opposite sides thereof, a multilayer wiring layer 210 disposed on the first surface side of the semiconductor layer 201 and on the side opposite to the first substrate 10 side, and a bonding film 219 disposed on the second surface side of the semiconductor layer 201 and on the first substrate 10 side. In addition, the semiconductor layer 201 side of the second substrate 20 is bonded to the multilayer wiring layer 120 of the first substrate 10 with the bonding film 219 interposed therebetween.

[0075] (Semiconductor layer) As Figure 5 and Figure 7 shown, the semiconductor layer 201 includes an element isolation region 203 provided in the surface layer portion on the multilayer wiring layer 210 side (the first surface side of the semiconductor layer 201) of the semiconductor layer 201, and element formation regions (active regions) 201a, 201b, 201c, and 201d divided by the element isolation region 203 thus provided. In addition, as Figure 7As shown, a p-type well region 202 formed of a p-type semiconductor region is provided in a semiconductor layer 201 including respective element formation regions 201a, 201b, 201c, and 201d. The semiconductor layer 201 may be formed of a semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide (GaAs) substrate, and an indium phosphide (InP) substrate. According to the first embodiment of the present disclosure, for example, the semiconductor layer 201 is formed of a p-type semiconductor substrate made of single-crystalline silicon. Here, note that the semiconductor layer 201 in the first embodiment of the present disclosure corresponds to a specific example of the "second semiconductor layer" of the present technology.

[0076] (Element isolation region) For example, Figure 5 and Figure 7 As shown, the element isolation region 203 has, but is not limited to, a shallow trench isolation (STI) structure having an insulating film (field insulating film) selectively embedded in a shallow trench portion (field trench portion) recessed from a first surface (side surface of the multilayer wiring layer 210) of the semiconductor layer 201 toward a second surface side (bonding film 219 side). For example, the insulating film may be formed of a silicon oxide film.

[0077] (Element formation region and pixel transistor) As Figure 5 and Figure 7 shown, a selection transistor SEL is provided in an element formation region 201b partitioned by the element isolation region 203. The selection transistor SEL thus provided includes a gate insulating film 204 formed in the element formation region 201b, a gate electrode 205s crossing the element isolation region 203 with the gate insulating film 204 interposed therebetween, and a pair of main electrode regions (not shown) provided in the element formation region 201b on both sides of the gate electrode 205s in the gate length direction (X direction). Each of the pair of main electrode regions thus formed is formed of an n-type semiconductor region. Although not shown in the figure, the selection transistor SEL thus provided includes a channel formation portion in the semiconductor layer 201 opposite to the gate electrode 205s with the gate insulating film 204 interposed therebetween.

[0078] As Figure 5As shown, an amplifying transistor AMP having a gate electrode 205a is provided in an element formation region 201a divided by an element isolation region 203. Further, a reset transistor RST having a gate electrode 205r is provided in an element formation region 201c divided by the element isolation region 203. Although not shown in detail in the figure, similar to the selection transistor SEL, each of the amplifying transistor AMP and the reset transistor RST thus provided includes a gate insulating film 204, gate electrodes (205a and 205r), and a pair of main electrode regions.

[0079] (Floating diffusion region) As Figure 5 and Figure 7 shown, the above-described floating diffusion region 206 is provided in an element formation region 201d divided by the element isolation region 203. The floating diffusion region 206 thus provided is composed of an n-type semiconductor region.

[0080] (Multilayer wiring layer) As Figure 7 shown, the multilayer wiring layer 210 is provided on the side (second surface side) of the semiconductor layer 201 opposite to the side of the bonding film 219 (first surface side). Although not shown in detail in the figure, the multilayer wiring layer 210 has a stacked structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked. Further, the multilayer wiring layer 210 includes wirings provided in each wiring layer and bonding metal pads 215. For example, each insulating layer of the multilayer wiring layer 210 may be composed of a silicon oxide film. For example, each wiring layer and the bonding metal pads 215 in the multilayer wiring layer 210 may be composed of a metal such as aluminum (Al) and copper (Cu), an alloy mainly composed of Al or Cu, or the like.

[0081] <Third substrate> As Figure 7 shown, the third substrate 30 is provided on the side of the second substrate 20 opposite to the side of the first substrate 10. The third substrate 30 includes a semiconductor layer 301 and a multilayer wiring layer 310 formed on the first surface side of the semiconductor layer 301, and the semiconductor layer 301 has a first surface and a second surface located on opposite sides of each other.

[0082] (Semiconductor layer) As Figure 7 shown, for example, as field effect transistors constituting the above-described logic circuit 32, an n-channel conductivity type MOSFET-Qn and a p-channel conductivity type MO transistor-Qp are provided in the surface layer portion on the first surface side of the semiconductor layer 301. Similar to the above-described semiconductor layer 201, for example, the semiconductor layer 301 is composed of a p-type semiconductor substrate made of single crystal silicon.

[0083] (Multilayer wiring layer) As Figure 7 As shown, the multilayer wiring layer 310 is provided on the first surface side (the first substrate 20 side) of the semiconductor layer 301. Although not shown in detail in the figure, the multilayer wiring layer 310 has a stacked structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked. In addition, the multilayer wiring layer 310 includes wirings provided in each wiring layer and bonding metal pads 315. For example, each insulating layer of the multilayer wiring layer 310 may be formed of a silicon oxide film. For example, each wiring layer and the bonding metal pad 215 in the multilayer wiring layer 310 may be formed of a metal such as aluminum (Al) and copper (Cu), an alloy mainly composed of Al or Cu, or the like.

[0084] (Bonding between the second substrate and the third substrate) As Figure 7 shown, the second substrate 20 includes bonding metal pads 215 in the surface layer portion on the side opposite to the semiconductor layer 201 side of the multilayer wiring layer 210. Each of the thus formed bonding metal pads 215 is provided in the uppermost insulating layer of the multilayer wiring layer 210 in a state where the bonding surface is exposed. As Figure 7 shown, the third substrate 30 includes bonding metal pads 315 in the surface layer portion on the side opposite to the semiconductor layer 301 side of the multilayer wiring layer 310. Each of the thus formed bonding metal pads 315 is provided in the uppermost insulating layer of the multilayer wiring layer 310 in a state where the bonding surface is exposed.

[0085] In addition, the bonding metal pads 215 of the second substrate 20 and the bonding metal pads 315 of the third substrate 30 are electrically and mechanically connected to each other by metal bonding therebetween, so that the respective bonding surfaces face each other. Furthermore, through the metal bonding between the bonding metal pads 215 and the bonding metal pads 315 achieved as described above, the wirings in the multilayer wiring layer 210 of the second substrate 20 and the wirings in the multilayer wiring layer 310 of the third substrate 30 are electrically conducted to each other.

[0086] The respective bonding surfaces of the bonding metal pads 215 of the second substrate 20 and the bonding metal pads 315 of the third substrate 30 are bonded to each other by direct bonding. In addition, the respective bonding surfaces of the uppermost insulating layer of the multilayer wiring layer 210 of the second substrate 20 and the uppermost insulating layer of the multilayer wiring layer 310 of the third substrate 30 are bonded to each other by direct bonding. For example, such direct bonding may be surface activation bonding achieved by plasma bonding.

[0087] <Charge holding unit> Subsequently, the specific configuration of the charge holding unit 15 will be described. As described above, the charge holding unit 15 according to the first embodiment of the present disclosure includes a floating contact electrode 208 and a floating diffusion region 206 that serve as FD capacitors, respectively. In addition, the charge holding unit 15 according to the first embodiment of the present disclosure further includes a conduction path 213 that electrically connects the floating contact electrode 208 and the floating diffusion region 206 and also serves as an FD capacitor.

[0088] (floating contact electrode) As Figure 8 shown, the floating contact electrode 208 extends through the first substrate 10 and the second substrate 20. Specifically, the floating contact electrode 208 penetrates each of the element isolation region 203, the semiconductor layer 201, and the bonding film 219 of the second substrate 20 from the first surface (element formation surface) side of the semiconductor layer 201 of the second substrate 20, further penetrates the multilayer wiring layer 120 of the first substrate 10, and reaches the photoelectric conversion region 102 in the semiconductor layer 101 of the first substrate 10. In addition, the floating contact electrode 208 is configured such that one end side (lower side) of the floating contact electrode 208 is electrically connected to the surface layer portion (specifically, the p-type well region 103) of the photoelectric conversion region 102, and the other end side (upper side) of the floating contact electrode 208 is electrically connected to the floating diffusion region 206 via the conduction path 213.

[0089] In addition, as Figure 6 and Figure 8 shown, the floating contact electrode 208 overlaps with the photoelectric conversion region 102 in the semiconductor layer 101 in a plan view and is also located at a position that does not overlap with the gate electrode 113 of the transfer transistor TR. Therefore, the charge holding unit 15 includes the floating contact electrode 208 disposed outside the first surface S1 of the semiconductor layer 101 (i.e., above the photoelectric conversion region 102) and also connected to the photoelectric conversion region 102.

[0090] As Figure 6 shown, in a two-dimensional plane, the floating contact electrode 208 and the gate electrode 113 of the transfer transistor TR are offset from each other to achieve electrical isolation from each other. As described above, the gate electrode 113 of the transfer transistor TR has an L-shaped planar pattern that includes two sides 113s that are adjacent to the floating contact electrode 208 in a plan view.

[0091] In addition, as Figure 8 shown, an insulating film 207 is disposed between the floating contact electrode 208 and the semiconductor layers 201 and 101 and electrically insulates the floating contact electrode 208 from the semiconductor layers 201 and 101. For example, similar to the floating contact electrode 208, the insulating film 207 extends through the second substrate 20 and the first substrate 10. For example, the insulating film 207 is composed of a silicon oxide film.

[0092] (Impurity Concentration Gradient of the Floating Contact Electrode) For example, Figure 8 the floating contact electrode 208 shown includes, but is not limited to, a semiconductor presenting the following impurity concentration gradient: the impurity concentration on the side (the other end side or the upper side) opposite to the photoelectric conversion region 102 side (one end side or the lower side) of the floating contact electrode 208 is higher than the impurity concentration on the photoelectric conversion region 102 side (one end side) of the floating contact electrode 208. Specifically, for example, the floating contact electrode 208 is composed of a semiconductor with silicon (Si) as the semiconductor material, single crystal as the crystallinity, and n-type as the conductivity. In addition, for example, arsenic (As) or phosphorus (P) is introduced as the n-type impurity. Furthermore, for the floating contact electrode 208 according to the first embodiment herein, the impurity concentration on one end side of the floating contact electrode 208 is, for example, about 1 × 10 17 / cm 3 , while the impurity concentration on the other end side of the floating contact electrode 208 is, for example, about 1 × 10 20 / cm 3 .

[0093] The floating contact electrode 208 configured as above has the following impurity concentration gradient: the impurity concentration on the other end side (the side opposite to the photoelectric conversion region 102 side) of the floating contact electrode 208 is higher than the impurity concentration on one end side (the photoelectric conversion region 102 side). This concentration gradient generates a potential gradient from one end side (the lower side) to the other end side (the upper side) of the floating contact electrode 208.

[0094] As an example of the impurity concentration gradient, for example, the floating contact electrode 208 according to the first embodiment herein presents the following impurity concentration gradient: gradually increasing in a quadratic curve shape or a linear shape from one end side (the photoelectric conversion region 102 side or the lower side) to the other end side (the side opposite to the photoelectric conversion region 102 side or the upper side) of the floating contact electrode 208.

[0095] Alternatively, as another example of the impurity concentration gradient, the following impurity concentration gradient can be adopted: gradually increasing step by step from one end side (the photoelectric conversion region 102 side or the lower side) to the other end side (the side opposite to the photoelectric conversion region 102 side or the upper side) of the floating contact electrode 208.

[0096] In short, as described above, it is only necessary to satisfy that the impurity concentration on the side (the other end side) opposite to the photoelectric conversion region 102 side (one end side or the lower side) of the floating contact electrode 208 is higher than the impurity concentration on the photoelectric conversion region 102 side (one end side) of the floating contact electrode 208.

[0097] (Shape of the Floating Contact Electrode) As Figure 5 and Figure 7 As shown, for example, the floating contact electrode 208 has, but is not limited to, a prismatic shape, and the widths of one end side and the other end side thereof are substantially the same. In another example, the floating contact electrode 208 may have a cylindrical shape, and the widths of one end side and the other end side thereof are substantially the same.

[0098] (Floating diffusion region) As Figure 5 and Figure 8 shown, the floating diffusion region 206 is provided in the element formation region 201d divided by the element isolation region 203. In other words, the floating diffusion region 206 is provided in the semiconductor layer 101 within the window surrounded by the element isolation region 203.

[0099] The floating diffusion region 206 is composed of an n-type semiconductor region. The floating diffusion region 206 is provided within the p-type well region 202 and is pn-junctioned to the p-type well region 202 mentioned here. In addition, the impurity concentration of the floating diffusion region 206 is higher than the impurity concentration of the p-type well region 202. For example, the impurity concentration of the p-type well region 202 is, for example, about 1 × 10 17 / cm 3 , while the impurity concentration of the floating diffusion region 206 is, for example, about 1 × 10 20 / cm 3 .

[0100] (Conductive path) As Figure 5 and Figure 8 shown, the conductive path 213 is provided in the multilayer wiring layer 210 of the second substrate 20. The conductive path 213 includes two contact electrodes 211a and 211b and a wiring 212.

[0101] As Figure 8 shown, the contact electrode 211a is configured such that one end side of the contact electrode 211a is electrically and mechanically connected to the other end side (upper side) of the floating contact electrode 208, and the other end side of the contact electrode 211a opposite to the one end is electrically and mechanically connected to the wiring 212.

[0102] The contact electrode 211b is configured such that one end side of the contact electrode 211b is electrically and mechanically connected to the other end side (upper side) of the floating diffusion region 206 of the semiconductor layer 201, and the other end side of the contact electrode 211b opposite to the one end is electrically and mechanically connected to the wiring 212.

[0103] As Figure 5As shown, the wiring 212 includes a first portion 212a that overlaps each of the floating contact electrode 208 and the floating diffusion region 206 in a plan view, a second portion 212b that is routed upward from the thus - arranged first portion 212a toward one main - electrode region (source region) of the reset transistor RST, and a third portion 212c that is routed upward from the thus - arranged second portion 212b toward the gate electrode 205a of the amplification transistor AMP.

[0104] As Figure 8 shown, the first portion 212a is electrically connected to the floating contact electrode 208 via the contact electrode 211a and is also electrically connected to the floating diffusion region 206 via the contact electrode 211b.

[0105] Although not shown in detail in the figure, referring to Figure 5 it can be understood that the second portion 212b is electrically connected to one main - electrode region of the reset transistor RST via a contact electrode. Additionally, the third portion 212c is electrically connected to the gate electrode 205a of the amplification transistor AMP via a contact electrode.

[0106] <Charge transfer and charge holding> Next, referring to Figure 8 the transfer and holding (accumulation) of the signal charge photoelectrically converted by the photoelectric conversion unit 105 will be described.

[0107] When the transfer transistor TR is in the on - state, an inversion layer (channel) is formed in the channel - forming portion 114. Thereafter, the signal charge photoelectrically converted by the photoelectric conversion unit 205 passes through this inversion layer formed in the channel - forming portion 114 and is transferred to one end (lower side) of the floating contact electrode 208. Specifically, the transfer transistor TR transfers the signal charge photoelectrically converted by the photoelectric conversion unit 105 from the photoelectric conversion unit 205 to one - end side of the floating contact electrode 208, that is, vertically transfers the signal charge along the direction of arrow R in the figure.

[0108] Subsequently, because the floating contact electrode 208 has the above - described impurity - concentration gradient (the impurity - concentration gradient in which the impurity concentration on the other - end side (upper side) of the floating contact electrode 208 is higher than the impurity concentration on one - end side (lower side) of the floating contact electrode 208), the signal charge transferred to one - end side (lower side) of the floating contact electrode 208 moves toward the other - end side (upper side) of the floating contact electrode 208 according to the potential gradient from one - end side (lower - end side) to the other - end side (upper - end side) of the floating contact electrode 208. Thereafter, the signal charge is held (accumulated) on the other - end side (upper side) of the floating contact electrode 208.

[0109] In addition, the impurity concentration gradient of the floating contact electrode 208 is an impurity concentration gradient that gradually increases in a quadratic curve shape or a linear shape from one end side (lower side) of the floating contact electrode 208 toward the other end side (upper side). Therefore, the signal charges transmitted to one end side of the floating contact electrode 208 move smoothly toward the other end side of the floating contact electrode 208.

[0110] In addition, the charge holding unit 15 according to the first embodiment of the present disclosure includes a floating diffusion region 206 electrically connected to the floating contact electrode 208 via a conduction path 213. Therefore, the signal charges transmitted to the other end side (lower side) of the floating contact electrode 208 move to the floating diffusion region 206 via the conduction path 213 and are held (accumulated) in the floating diffusion region 206.

[0111] In addition, the charge holding unit 15 according to the first embodiment of the present disclosure electrically connects the floating contact electrode 208 and the floating diffusion region 206 via the conduction path 213. In this case, the signal charges transmitted to the other end side of the floating contact electrode 208 are held (accumulated) in the conduction path 213.

[0112] Therefore, the charge holding unit 15 of the first embodiment of the present disclosure holds (accumulates) the signal charges transmitted from the photoelectric conversion unit 105 (photodiode PD) via the transfer transistor TR in each of the floating contact electrode 208, the floating diffusion region 206, and the conduction path 213 that are respectively used as FD capacitors.

[0113] Note that, as Figure 5 shown, the charge holding unit 15 is electrically connected to the gate electrode 205a of the amplification transistor AMP and one main electrode region of the reset transistor RST included in the pixel circuit 22 via a wiring 212. In this configuration, the pixel circuit 22 reads the signal charges held in the charge holding unit 15, converts the read signal charges into pixel signals, and outputs the pixel signals.

[0114] <<Main advantageous effects of the first embodiment>> Next, the main advantageous effects of the solid-state imaging device 1A according to the first embodiment given in the present disclosure will be described. The solid-state imaging device 1A according to the first embodiment of the present invention includes a charge holding unit 15 that is disposed outside the first face S1 of the semiconductor layer 101 and holds the signal charge transferred from the transfer transistor TR. In addition, the charge holding unit 15 includes a floating contact electrode 208 that is connected to the photoelectric conversion region 102 and serves as an FD capacitor. Therefore, the solid-state imaging device 1A of the first embodiment of the present invention can remove (cancel) the floating diffusion region that provides the conventional FD capacitor and becomes one of the factors that hinder the size reduction of the photoelectric conversion region 102 from the photoelectric conversion region 102, and thus achieves the size reduction of the photoelectric conversion region 102, that is, the miniaturization of the sensor pixel 12. On the contrary, in the case where the planar size of the photoelectric conversion region 102 is fixed, it is allowed to increase the volume of the photoelectric conversion unit 105 (n-type semiconductor region 104). Therefore, the saturation signal amount Qs can be increased.

[0115] Furthermore, the reduction in size of the photoelectric conversion region 102 (sensor pixel 12) thus achieved can improve the resolution of the provided solid-state imaging device 1A.

[0116] In addition, the solid-state imaging device 1A according to the first embodiment of the present invention includes a transfer transistor TR whose gate electrode 113 is provided in the semiconductor layer 101 (specifically, the photoelectric conversion region 102) via a gate insulating film 112 extending in the thickness (depth direction (Z direction)) of the semiconductor layer 101. Therefore, the gate electrode 113 can extend in the depth direction of the semiconductor layer 101 according to the size of the floating contact electrode 208. Therefore, without increasing the planar size of the gate electrode 113, the size of the gate electrode 113 can be maintained in the depth direction of the semiconductor layer 101 according to the size of the floating contact electrode 208. In this way, further size reduction of the photoelectric conversion region 102, that is, further miniaturization of the sensor pixel 12 can be achieved. On the contrary, in the case where the planar size of the photoelectric conversion region 102 is fixed, the volume of the photoelectric conversion unit 105 (n-type semiconductor region 104) is allowed to be increased. Therefore, the saturation signal amount Qs can be further improved.

[0117] In addition, the floating contact electrode 208 includes a semiconductor whose impurity concentration on the other end side opposite to the one end side (photoelectric conversion region 102 side) is higher than the impurity concentration on the one end side (photoelectric conversion region 102 side). In this case, the signal charge transferred to the one end side (photoelectric conversion region 102 side) of the floating contact electrode 208 smoothly moves toward the other end side of the floating contact electrode 208. Therefore, while miniaturization of the sensor pixel 12 (photoelectric conversion region 102) is achieved, the image processing speed can be improved.

[0118] In addition, the charge holding unit 15 according to the first embodiment of the present disclosure further includes a floating diffusion region 206 provided in the semiconductor layer 201 and electrically connected to the floating contact electrode 208. Therefore, the signal charge transmitted to the other end side (lower side) of the floating contact electrode 208 moves to the floating diffusion region 206 via the conduction path 213 and is held (accumulated) in the floating diffusion region 206. Therefore, the solid-state imaging device 1A according to the first embodiment of the present disclosure can increase the FD capacitance of the charge holding unit 15 while reducing the size of the photoelectric conversion region 102 (sensor pixel 12).

[0119] In addition, the charge holding unit 15 according to the first embodiment of the present disclosure electrically connects the floating contact electrode 208 and the floating diffusion region 206 via the conduction path 213. In this case, the signal charge transmitted to the other end side of the floating contact electrode 208 is held (accumulated) in the conduction path 213. Therefore, the solid-state imaging device 1A according to the first embodiment of the present disclosure can further increase the FD capacitance of the charge holding unit 15 while reducing the size of the photoelectric conversion region 102.

[0120] Here, note that the floating diffusion region of a conventional solid-state imaging device including a photoelectric conversion region constituting the FD capacitance as the photoelectric conversion region includes, for example, an n-type semiconductor region with an impurity concentration of 1 × 10 20 / cm 3 . In this case, in order to reduce the leakage between the floating diffusion region and the photoelectric conversion unit, an isolation potential generated by a p-type isolation region (p-type semiconductor region) is required on the photoelectric conversion unit side of the floating diffusion region. In this case, in order to maintain the above isolation potential, it is difficult to reduce the p-type isolation region to a size close to the size of the photoelectric conversion region when reducing the size of the photoelectric conversion region. Therefore, this configuration compresses the transmission region from the photoelectric conversion unit to the transfer transistor and the floating diffusion region and narrows the transmission path. Therefore, a transmission barrier is generated. In particular, various impurities for assisting the transmission of signal charges are implanted into the surface layer portion (the surface layer portion on the floating diffusion region side) on the side opposite to the light incident surface side of the photoelectric conversion region. These impurities may further affect the generation of the transmission barrier according to process variations. Therefore, in order to reduce the size of the photoelectric conversion region, it is necessary to widen the transmission region between the photoelectric conversion unit and the transfer transistor.

[0121] On the other hand, the solid-state imaging device 1A according to the first embodiment of the present disclosure includes the charge holding unit 15 outside the photoelectric conversion region 102. Therefore, it is not necessary to provide a p-type isolation region (p-type semiconductor region) which is one of the factors hindering the reduction of the size of the photoelectric conversion region 102. In this regard, it is also possible to reduce the size of the photoelectric conversion region 102, that is, miniaturize the sensor pixel 12.

[0122] Note that if sufficient FD capacitance can be generated only by the floating contact electrode 208, the floating diffusion region 206 can be removed. In addition, the floating contact electrode 208 can include metal.

[0123] [Modification of the First Embodiment] [[Modification of the Floating Contact Electrode]] Although the floating contact electrode 208 described in the first embodiment has a prism shape with substantially the same width on one end side and the other end side, the shape of the floating contact electrode 208 is not limited to the shape described in the first embodiment.

[0124] [Modification 1-A] For example, as Fig.9A shown, the floating contact electrode 208 in Modification 1-A can have a frustum of a pyramid shape or a frustum of a cone shape, and the width W2 on the other end side (opposite to the photoelectric conversion region 102 side) is larger than the width W1 on one end side. The floating contact electrode 208 according to Modification 1-A herein can increase more FD capacitance than the floating contact electrode 208 of the first embodiment above without changing the bonding area with the photoelectric conversion region 102.

[0125] [Modification 1-B] In addition, as Fig. 9B shown, the floating contact electrode 208 in Modification 1-B can have a prism shape or a cylinder shape, and its width decreases stepwise such that the width W2 on the other end side (the side opposite to the photoelectric conversion region 102 side) is larger than the width W1 on one end side (the photoelectric conversion region 102 side). The floating contact electrode 208 according to Modification 1-B herein can also increase more FD capacitance than the floating contact electrode 208 of the first embodiment above without changing the bonding area with the photoelectric conversion region 102.

[0126] [[Modification of the Gate Electrode Planar Shape]] In addition, although the gate electrode 113 included in the transfer transistor TR described in the first embodiment has an L-shaped planar shape including two sides 113s adjacent to the contact electrode 208 respectively in a plan view, the planar shape of the gate electrode 113 is not limited to the L-shape in the first embodiment.

[0127] [Modification 2-A] For example, as Fig. 10AAs shown, when the floating contact electrode 208 has a quadrilateral horizontal cross-sectional shape, in the case of Modification Example 2-A, the gate electrode 113 of the transfer transistor TR may have a C-shaped planar shape in a plan view, including three sides 113s adjacent to the floating contact electrode 208 respectively. In the case of the above C-shaped gate electrode 113, the substantial overlapping area of the channel formation portion 114 and the floating contact electrode 208 becomes larger than the overlapping area of the gate electrode 113 having an L shape. Therefore, the transfer efficiency of the transfer transistor TR for transferring the signal charges photoelectrically converted by the photoelectric conversion unit 105 to the floating contact electrode 208 can be improved.

[0128] <Modification Example 2-B> In addition, as Fig. 10B shown, when the floating contact electrode 208 has a quadrilateral horizontal cross-sectional shape, the gate electrode 113 of the transfer transistor TR in Modification Example 2-B may have an I-shaped (linear) planar shape including one side 113s adjacent to the floating contact electrode 208 in a plan view.

[0129] <Modification Example 2-C> In addition, as Fig. 10C shown, when the floating contact electrode 208 has a quadrilateral horizontal cross-sectional shape, the gate electrode 113 of the transfer transistor TR in Modification Example 2-C may have an O-shaped (ring-shaped) planar shape including four linear sides 113s adjacent to the floating contact electrode 208 respectively. In the case of the above O-shaped gate electrode 113, the substantial overlapping area of the channel formation portion 114 and the floating contact electrode 208 also becomes larger than the overlapping area of the gate electrode 113 having an L shape. Therefore, the transfer efficiency of the transfer transistor TR for transferring the signal charges photoelectrically converted by the photoelectric conversion unit 105 to the floating contact electrode 208 can be improved.

[0130] <Modification Example 2-D> According to the above Modification Examples 2-A to 2-C, the floating contact electrode 208 has a quadrilateral horizontal cross-sectional shape. However, when the floating contact electrode 208 has a circular horizontal cross-sectional shape, the gate electrode 113 of the transfer transistor TR has the following planar shape: in a plan view, it includes at least one curved side adjacent to the floating contact electrode 208.

[0131] <<Modification Examples of the Longitudinal Shape of the Gate Electrode>> In addition, regarding the longitudinal shape of the gate electrode 113 of the transfer transistor TR, in the first embodiment, it is described that the gate electrode 113 is disposed in the gate groove portion 110 such that the upper surface portion of the gate electrode 113 is substantially flush with the first surface S1 of the semiconductor layer 101. However, the longitudinal shape of the gate electrode 113 is not limited to this shape in the first embodiment.

[0132] For example, as Fig.11 shown, the gate electrode 113 may have the following longitudinal shape: its upper surface portion protrudes upward from the first surface S1 of the semiconductor layer 101.

[0133] [Second Embodiment] A second embodiment of the present technology will illustrate an example in which the present technology is applied to a charge holding unit 15B that includes a floating contact electrode 208 provided for each of a plurality of photoelectric conversion regions 102 (sensor pixels 12) included in one sensor pixel group 16. The solid-state imaging device 1B according to the second embodiment of the present technology has a configuration substantially similar to that of the solid-state imaging device 1A according to the first embodiment described above, but is different from the solid-state imaging device 1A in the following configuration aspects.

[0134] Specifically, the solid-state imaging device 1B according to the second embodiment of the present technology includes Fig.12 the sensor pixel unit PU2 shown, in place of Figure 3 the sensor pixel unit PU1 of the first embodiment shown. In addition, as Fig.12 shown, the sensor pixel unit PU2 includes one sensor pixel group 16 equipped with four sensor pixels 12 as one unit and one pixel circuit (read circuit) 22 shared by the four sensor pixels 12 included in one sensor pixel group 16. In addition, the sensor pixel unit PU2 also includes a charge holding unit 15B connected between the sensor pixel group 16 and the pixel circuit 22. Other configurations are substantially similar to the corresponding configurations of the first embodiment described above.

[0135] Each of the four sensor pixels 12 included in one sensor pixel group 16 has a photoelectric conversion region 102 similar to that of the first embodiment described above, and the photoelectric conversion region 102 includes a photoelectric conversion unit 105 (PD) and a transfer transistor TR. In other words, one sensor pixel group 16 has four photoelectric conversion regions 102 respectively similar to the photoelectric conversion region 102 of the first embodiment described above.

[0136] As Fig.12As shown, the charge holding unit 15B includes four floating contact electrodes 208 provided in one-to-one correspondence with the four photoelectric conversion regions 102, and a floating diffusion region 206 electrically connected to each of the four floating contact electrodes 208 thus provided via a conductive path 213B. Similar to the first embodiment described above, each of the four floating contact electrodes 208, the floating diffusion region 206, and the conductive path 213B thus provided serves as the FD capacitance of the charge holding unit 15B. Further, similar to the charge holding unit 15 of the first embodiment described above, the charge holding unit 15B also serves as the drain region of the transfer transistor TR.

[0137] One end side of each of the four floating contact electrodes 208 is respectively connected to a corresponding one of the four photoelectric conversion regions 102. Further, the other end side of each of the four floating contact electrodes 208 is electrically connected to a single floating diffusion region 206 via a conductive path 213B.

[0138] As Fig.14 shown, the four photoelectric conversion regions 102 included in one sensor pixel group 16 form a 2×2 planar layout configuration, in which two photoelectric conversion regions 102 are provided in each of the X direction and the Y direction. Further, the two photoelectric conversion regions 102 arranged in the X direction and the Y direction are adjacent to each other with the isolation region 106 therebetween.

[0139] As Fig.14 shown, one sensor pixel group 16 includes an intersection (planar intersection point) 106a at which the isolation region 106 extending in the X direction and the isolation region 106 extending in the Y direction intersect with each other in a plane at the central region where the respective corners of the four photoelectric conversion regions 102 are adjacent to each other. Further, four transfer transistors TR respectively included in a corresponding one of the four photoelectric conversion regions 102 are arranged at positions shifted toward the intersection 106a of the isolation region 106. Further, the gate electrodes 113 of the transfer transistors TR of the four photoelectric conversion regions 102 are arranged at positions shifted toward the intersection 106a of the isolation region 106 so as to surround the intersection 106a of the isolation region 106.

[0140] As Fig.14 shown, each of the four floating contact electrodes 208 included in the charge holding unit 15B overlaps with a corresponding one of the four photoelectric conversion regions 102 in a plan view, and is arranged at a position shifted toward the intersection 106a of the isolation region 106. Further, in the plan view of a corresponding one of the four photoelectric conversion regions 102, each of the four floating contact electrodes 208 is arranged between the gate electrode 113 of the transfer transistor TR and the intersection 106a of the isolation region 106.

[0141] Although not shown in detail, similar to the conductive path 213 of the first embodiment described above, Fig.12 the shown conductive path 213B is provided in the multilayer wiring layer 210 of the second substrate 20. For example, referring to Figure 7 it can be understood that the conductive path 213B includes but is not limited to Figure 7 the four contact electrodes 211a shown, Figure 7 the one contact electrode 211b shown, and the wiring 212X having a wiring pattern different from the pattern of the wiring 212 shown (see Figure 7 ). Fig.13 )

[0142] As Fig.13 shown, the wiring 212X included in the conductive path 213B is wired in a manner that overlaps each of the four floating contact electrodes 208, the floating diffusion region 206, one main electrode region of the reset transistor RST, and the gate electrode 205a of the amplification transistor AMP in a plan view. In addition, the wiring 212X is electrically connected to the other end side of each of the four floating contact electrodes 208 via the contact electrode 211a (see Figure 7 ), and is also electrically connected to the floating diffusion region 206 via another contact electrode 211b (see Figure 7 ). In addition, the wiring 212X is electrically connected to one main electrode region of the reset transistor RST via a contact electrode, and is also electrically connected to the gate electrode 205a of the amplification transistor AMP via another different contact electrode.

[0143] According to the second embodiment herein, the pixel circuit 22 has a configuration similar to that of the pixel circuit 22 of the first embodiment described above. The input side of the pixel circuit 22 is electrically connected to the output side of the charge holding unit 15B. In addition, the four floating contact electrodes 208 and the floating diffusion region 206 have configurations similar to those of the floating contact electrodes 208 and the floating diffusion region 206 of the first embodiment described above, and thus will not be specifically described.

[0144] The solid-state imaging device 1B according to the second embodiment herein also has beneficial effects similar to those of the solid-state imaging device 1A of the first embodiment described above.

[0145] [Third Embodiment] The third embodiment herein will illustrate an example in which the present technology is applied to the charge holding unit 15C including the floating contact electrode 208 shared by a plurality of photoelectric conversion regions 102 (sensor pixels 12) included in one sensor pixel group 16. The solid-state imaging device 1C according to the third embodiment of the present technology has a configuration substantially similar to that of the solid-state imaging device 1B of the second embodiment described above, but is different from the solid-state imaging device 1B in the following configuration aspects. Specifically, the solid-state imaging device 1C according to the third embodiment of the present technology includes Fig.15 the sensor pixel unit PU3 shown, in place of the sensor pixel unit PU2 shown in the second embodiment as Fig.12 shown. In addition, as Fig.15 shown, the sensor pixel unit PU3 includes a sensor pixel group 16 equipped with four sensor pixels 12 as a unit and a pixel circuit (read circuit) 22 shared by the four sensor pixels 12 included in one sensor pixel group 16. Further, the sensor pixel unit PU3 also includes a charge holding unit 15C connected between the sensor pixel group 16 and the pixel circuit 22. Other configurations are substantially similar to the corresponding configurations of the second embodiment.

[0146] Similar to the second embodiment described above, each of the four sensor pixels 12 included in one sensor pixel group 16 has a photoelectric conversion region 102, and the photoelectric conversion region 102 includes a photoelectric conversion unit 105 and a transfer transistor TR. In other words, one sensor pixel group 16 has four photoelectric conversion regions 102, and the photoelectric conversion regions 102 are respectively similar to the photoelectric conversion region 102 of the first embodiment.

[0147] As Fig.15 shown, the charge holding unit 15C includes a floating contact electrode 208C shared by the four photoelectric conversion regions 102 and a floating diffusion region 206 electrically connected to the floating contact electrode 208C via a conduction path 213C. Similar to the second embodiment described above, each of the floating contact electrode 208C, the floating diffusion region 206, and the conduction path 213C thus provided serves as the FD capacitance of the charge holding unit 15C. In addition, similar to the charge holding units 15 and 15B of the first and second embodiments, the charge holding unit 15C also serves as the drain region of the transfer transistor TR.

[0148] One end side of the floating contact electrode 208C is connected to each of the four photoelectric conversion regions 102. In addition, the other end side of the floating contact electrode 208C is electrically connected to a floating diffusion region 206 via a conduction path 213C.

[0149] As Fig.17As shown, four photoelectric conversion regions 102 included in a sensor pixel group 16 form a 2×2 layout configuration, where two photoelectric conversion regions 102 are provided in each of the X direction and the Y direction. In addition, the two photoelectric conversion regions 102 arranged in each of the X direction and the Y direction are adjacent to each other with an isolation region 106 therebetween.

[0150] As Fig.17 shown, a sensor pixel group 16 includes a crossing portion (planar crossing point) 106a, at which an isolation region 106 extending in the X direction and an isolation region 106 extending in the Y direction intersect in a plane at a central region where the respective corners of the four photoelectric conversion regions 102 are adjacent to each other. In addition, four transfer transistors TR respectively included in a corresponding one of the four photoelectric conversion regions 102 are arranged at positions offset toward the crossing portion 106a of the isolation region 106. Further, gate electrodes 113 of the transfer transistors TR of the four photoelectric conversion regions 102 are arranged at positions offset toward the crossing portion 106a of the isolation region 106 in a manner surrounding the crossing portion 106a of the isolation region 106.

[0151] As Fig.17 shown, a floating contact electrode 208C included in a charge holding unit 15B overlaps with the crossing portion 106a of the isolation region 106 in a plan view, also overlaps with the four photoelectric conversion regions 102 near the crossing portion 106a of the isolation region 106, and is further arranged at a position not overlapping with the gate electrodes 113 of the transfer transistors TR of the four photoelectric conversion regions 102. In addition, one end side of the floating contact electrode 208C is connected to each of the four photoelectric conversion regions 102. Specifically, referring to Figure 7 it can be seen that one end side of the floating contact electrode 208C is electrically connected to a p-type well region 103 of each of the four photoelectric conversion regions 102 included in a sensor pixel group 16.

[0152] As Fig.17 shown, a floating contact electrode 208C included in a charge holding unit 15C is adjacent to the gate electrodes 113 of the transfer transistors TR of the four photoelectric conversion regions 102 in a plan view and is also electrically insulated from the gate electrodes 113 of the transfer transistors TR.

[0153] Although not shown in detail in the figure, similar to the conductive path 213 of the first embodiment described above, a conductive path 213C according to the third embodiment of the present disclosure is provided in a multilayer wiring layer 210 of a second substrate 20. Referring to Figure 7 it can be understood that the conductive path 213C includes Figure 7 a contact electrode 211a shown, Figure 7One of the contact electrodes 211b shown and a wiring 212Y having a wiring pattern different from that of the wiring 212 shown Figure 7 shown.

[0154] As Fig.16 shown, the wiring 212Y included in the conduction path 213C is wired so as to overlap each of the floating contact electrode 208C, the floating diffusion region 206, one main electrode region of the reset transistor RST, and the gate electrode 205a of the amplifying transistor AMP in a plan view. Further, the wiring 212Y is electrically connected to the other end side of the floating contact electrode 208C via the contact electrode 211a (see Figure 7 ), and is also electrically connected to the floating diffusion region 206 via the contact electrode 211b (see Figure 7 ). Further, the wiring 212Y is electrically connected to one main electrode region of the reset transistor RST via a different contact electrode, and is also electrically connected to the gate electrode 205a of the amplifying transistor AMP via a different contact electrode.

[0155] According to the third embodiment of the present disclosure, the pixel circuit 22 has a configuration similar to that of the pixel circuit 22 of the first embodiment described above. The input side of the pixel circuit 22 is electrically connected to the output side of the charge holding unit 15C. Further, the floating contact electrode 208C and the floating diffusion region 206 have configurations similar to those of the floating contact electrode 208 and the floating diffusion region 206 of the first embodiment described above, and thus will not be specifically described.

[0156] The solid-state imaging device 1C according to the third embodiment of the present disclosure also has beneficial effects similar to those of the solid-state imaging device 1B of the second embodiment described above.

[0157] [Fourth Embodiment] The fourth embodiment of the present disclosure will describe a solid-state imaging device 1D including a transfer transistor TR4 having two gate electrodes, the transfer transistor TR4 being a transfer transistor for transferring signal charges photoelectrically converted by a photoelectric conversion unit to a charge holding unit. In the fourth embodiment, it is also assumed that the thickness direction of the semiconductor base portion 402 described below corresponds to the Z direction. In addition, the cross-sectional view of the drawing related to the fourth embodiment of the present disclosure partially omits the hatching indicating the cross section for easy understanding of the drawing.

[0158] Further, Fig.21 for easy understanding of the configuration of the solid-state imaging device 1D, the position of the semiconductor protrusion 415b shown Fig. 20 is intentionally changed.

[0159] [Overall Configuration of Solid-State Imaging Device] The solid-state imaging device 1D according to the fourth embodiment of the present technology has a configuration substantially similar to that of the solid-state imaging device 1A of the first embodiment described above, but is different from the solid-state imaging device 1A in the following configurations.

[0160] Specifically, as Fig.18 shown, the solid-state imaging device 1D according to the fourth embodiment of the present technology includes a first substrate 40 and a second substrate 50, in place of the first substrate 10 and the second substrate 20 as Figure 2 shown in the above first embodiment. In addition, the solid-state imaging device 1D according to the fourth embodiment herein includes Fig.19 the sensor pixel unit PU4 as Figure 3 shown, in place of the sensor pixel unit PU1 as Figure 3 shown in the above first embodiment. Other configurations are substantially similar to the corresponding configurations of the first embodiment.

[0161] As Fig.18 shown, similar to the solid-state imaging device 1A of the first embodiment described above, the solid-state imaging device 1D according to the fourth embodiment of the present technology mainly includes Fig.18 the semiconductor chip 3 as Fig.18 shown. Specifically, the solid-state imaging device 1D is mounted on the semiconductor chip 3, and thus the semiconductor chip 3 can be regarded as the solid-state imaging device 1D. Similar to the semiconductor chip 2 described above, the semiconductor chip 3 is formed as a small piece obtained by dividing a semiconductor wafer in which a plurality of semiconductor layers are stacked. Therefore, the solid-state imaging device 1D described below has a substantially similar configuration even in the state of the wafer before being divided into small pieces.

[0162] <Semiconductor Chip> As Fig.18 shown, the solid-state imaging device 1D (semiconductor chip 3) according to the fourth embodiment herein includes a first substrate (first layer) 40, a second substrate (second layer) 50, and a third substrate (third layer) 30. In addition, the solid-state imaging device 1D has a three-dimensional structure in which the first substrate 40, the second substrate 50, and the third substrate 30 are stacked in sequence.

[0163] As Fig.18 shown, the first substrate 40 has a plurality of sensor pixels 12d that respectively perform photoelectric conversion. In a plan view, each of the plurality of sensor pixels 12d is arranged in a matrix shape in the pixel array portion 2A of the first substrate 40 1 therein.

[0164] As Fig.18As shown, the second substrate 50 includes a pixel circuit (read circuit) 22D that outputs pixel signals respectively based on signal charges output from corresponding sensor pixels 12d. In addition, the second substrate 50 includes a plurality of pixel driving lines 23 extending in the row direction (X direction) and a plurality of vertical signal lines 24 extending in the column direction (Y direction). Therefore, the solid-state imaging device 1D of the fourth embodiment herein is configured such that the sensor pixels 12d are provided in the first substrate 40, and the pixel circuits 22 are provided in the second substrate 50.

[0165] Here, note that in the fourth embodiment herein, the third substrate 30, the second substrate 20, and the first substrate 40 may also be referred to as the Bottom substrate, the Middle substrate, and the Top substrate, respectively, in some cases.

[0166] As Fig.18 shown, the third substrate 30 includes a logic circuit 32 that processes pixel signals. The logic circuit 32 according to the fourth embodiment herein has a configuration that is basically similar to the configuration of the logic circuit 32 of the first embodiment described above, and includes a vertical driving circuit 33, a column signal processing circuit 34, a horizontal driving circuit 35, and a system control circuit 36, and also includes an output circuit (not shown). Therefore, the third substrate 30 including the logic circuit 32 will not be described further in the fourth embodiment herein.

[0167] <Sensor Pixel Unit> As Fig.19 shown, the sensor pixel unit PU4 includes a photoelectric conversion unit 105d, a transfer transistor TR4, a charge holding unit 15D, and a pixel circuit (read circuit) 22D.

[0168] (Photoelectric Conversion Unit) The photoelectric conversion unit 105d is provided in Fig.21 the photoelectric conversion region 102d shown. In addition, similar to the first embodiment described above, a photoelectric conversion region 102d including the photoelectric conversion unit 105d is provided for each sensor pixel 12d. Similar to the sensor pixel 12 of the first embodiment described above, the sensor pixels 12d according to the fourth embodiment herein are repeatedly arranged in the X direction and the Y direction perpendicular to each other in a two-dimensional plane, and constitute a pixel array portion 1A similar to Figure 1 the pixel array portion 1A shown 1 .

[0169] For example, Fig.19The photoelectric conversion unit 105d shown includes a pn junction type photodiode (PD) as a photoelectric conversion element, and generates signal charges corresponding to the received light amount. The photoelectric conversion unit 105d is configured such that the cathode side is electrically connected to the source region of the transfer transistor TR4, and the anode side is electrically connected to a reference potential line (for example, a reference potential line having 0V).

[0170] (Transfer transistor) Fig.19 The transfer transistor TR4 shown transfers the signal charges photoelectrically converted by the photoelectric conversion unit 105d to the charge holding unit 15D. The source region of the transfer transistor TR4 is electrically connected to the cathode side of the photoelectric conversion unit 105d, while the drain region of the transfer transistor TR4 is electrically connected to the charge holding unit 15D. In addition, the gate electrode of the transfer transistor TR4 is electrically connected to Fig.18 the transfer transistor drive line in the pixel drive line 23 shown.

[0171] Fig.19 The transfer transistor TR4 shown is provided for each sensor pixel 12d together with the photoelectric conversion region 102d. In addition, as will be described in detail below, the transfer transistor TR4 is different from the transfer transistor TR of the above-described first embodiment in that it has two gate electrodes. In other words, as Fig.19 shown, the transfer transistor TR4 includes a first transfer transistor TG and a second transfer transistor TM connected in series in an equivalent circuit manner. The first transfer transistor TG is provided on the first substrate 40 side, while the second transfer transistor TM is provided on the second substrate 50 side. Therefore, the transfer transistor TR4 is configured to extend through the first substrate 40 and the second substrate 50.

[0172] In addition, different from the transfer transistor TR of the above-described first embodiment, as Fig.21 shown, the transfer transistor TR4 is configured such that the two gate electrodes (the first gate electrode 406a and the second gate electrode 506) of the transfer transistor TR4 overlap the photoelectric conversion region 102d in a plan view and are arranged outside the photoelectric conversion region 102d.

[0173] (Charge holding unit) Fig.19 The charge holding unit 15D shown mainly holds the signal charges transferred from the photoelectric conversion unit 105d via the transfer transistor TR4, that is, the signal charges transferred from the transfer transistor TR4.

[0174] <Pixel circuit> As Fig.19As shown, the input side of the pixel circuit 22D is electrically connected to the output side of the charge holding unit 15D (the drain region of the second transfer transistor TM). Similar to the above-described first embodiment, the fourth embodiment given herein by way of example has the following circuit configuration: Each pixel circuit 22D is assigned to a corresponding sensor pixel 12d (photoelectric conversion region 102d) one-to-one. However, it is not necessary to adopt such a configuration of the fourth embodiment. For example, as described in the above-described first embodiment, the following circuit configuration may be adopted: Each pixel circuit 22D is shared by a plurality of sensor pixels 12d (photoelectric conversion regions 102d). In addition, the following circuit configuration may be adopted: Each pixel circuit 22D is shared by a sensor pixel group (photoelectric conversion group) as a unit, which is composed of four sensor pixels 12d arranged in a 2×2 array with two sensor pixels 12 arranged in each of the X direction and the Y direction. In addition, the following circuit configuration may be adopted: Each pixel circuit 22D is shared by a sensor pixel group (photoelectric conversion group) as a unit, which is composed of two sensor pixels 12d. In addition, the following circuit configuration may be adopted: Each pixel circuit 22D is shared by a sensor pixel group (photoelectric conversion group) as a unit, which is composed of four or more sensor pixels 12d.

[0175] Fig.19 The pixel circuit 22D shown reads the signal charge held in the charge holding unit 15D, converts the read signal charge into a pixel signal, and outputs the pixel signal. In other words, the pixel circuit 22D converts the signal charge photoelectrically converted by the photoelectric conversion unit 105d (photodiode PD) into a pixel signal based on the signal charge, and outputs the pixel signal.

[0176] For example, as Fig.19 shown, the pixel circuit 22d includes, but is not limited to, an amplifying transistor AMP, a selection transistor SEL, a reset transistor RST, and a discharging transistor OFG as pixel transistors. For example, each of the above-described pixel transistors (AMP, SEL, RST, and OFG) is composed of an n-channel conductive MOSFET as a field effect transistor. Each of these pixel transistors may also be composed of an n-channel conductive MISFET.

[0177] Among the pixel transistors included in the pixel circuit 22D, the selection transistor SEL, the reset transistor RST, and the discharging transistor OFG are used as switching elements, and the remaining amplifying transistor AMP is used as an amplifying element.

[0178] As Fig.19As shown, the discharge transistor OFG is configured such that the drain region is electrically connected to the power supply line VDD, and the source region is electrically connected to the charge holding unit 15D, the source region of the reset transistor RST, and the gate electrode of the amplification transistor AMP. In addition, the gate electrode of the discharge transistor is electrically connected to Fig.18 the selection transistor drive line in the pixel drive line 23 shown.

[0179] As Fig.19 shown, the amplification transistor AMP is configured such that the source region is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line VDD. In addition, the gate electrode of the amplification transistor AMP is electrically connected to the charge holding unit 15D and the source region of the reset transistor RST.

[0180] As Fig.19 shown, the selection transistor SEL is configured such that the source region is electrically connected to the vertical signal line 24 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP. In addition, the gate electrode of the selection transistor SEL is electrically connected to Fig.18 the selection transistor drive line in the pixel drive line 23 shown.

[0181] As Fig.19 shown, the reset transistor RST is configured such that the source region is electrically connected to the charge holding unit 15D, the source region of the discharge transistor OFG, and the gate electrode of the amplification transistor AMP, and the drain region is electrically connected to the power supply line VDD. In addition, the gate electrode of the reset transistor RST is electrically connected to Fig.18 the reset transistor drive line in the pixel drive line 23 shown. Specifically, the drain regions of each of the discharge transistor OFG, the reset transistor RST, and the amplification transistor AMP are electrically connected to each other via the power supply line VDD.

[0182] Fig.19 The transfer transistor TR4 shown transfers the signal charge generated by the photoelectric conversion unit 105d to the charge holding unit 15 when the transfer transistor TR is in the on state.

[0183] Fig.19 The discharge transistor OFG shown initializes (resets) the charge holding unit 15D when the discharge transistor OFG is in the on state. For example, when the discharge transistor OFG is in the on state, the potential of the charge holding unit 15D is reset to the potential level of the power supply line VDD.

[0184] Fig.19 The reset transistor RST shown resets the potential (signal charge) of the charge holding unit 15D to the potential of the power supply line VDD when the reset transistor RST is in the on state.

[0185] Fig.19 The illustrated selection transistor SEL controls the output timing of the pixel signal received from the pixel circuit 22.

[0186] Fig.19 The illustrated amplification transistor AMP generates a signal representing a voltage corresponding to the level of the signal charge held in the charge holding unit 15 as a pixel signal. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal representing a voltage corresponding to the level of the signal charge generated by the photoelectric conversion unit 105d. When the selection transistor SEL is in the ON state, the amplification transistor AMP amplifies the potential of the charge holding unit 15 and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 34 via the vertical signal line 24 (VSL).

[0187] Here, with reference to Fig.19 During the operation of the solid-state imaging device 1D according to the fourth embodiment of the present disclosure, the signal charge generated by the photoelectric conversion unit 105d of the sensor pixel 12d is held (accumulated) in the charge holding unit 15D via the transfer transistor TR4 of the sensor pixel 12d. Thereafter, the signal charge held in the charge holding unit 15D is read by the pixel circuit 22D and applied to the gate electrode of the amplification transistor AMP of the pixel circuit 22D. The selection control signal in the horizontal line is supplied from the vertical shift register to the gate electrode of the selection transistor SEL of the pixel circuit 22D. Thereafter, the selection transistor SEL turns on in response to the selection control signal set to the high (H) level and causes a current corresponding to the potential of the charge holding unit 15D amplified by the amplification transistor AMP to flow in the vertical signal line 24. In addition, the reset transistor RST turns on in response to the reset control signal set to the high (H) level and applied to the gate electrode of the reset transistor RST of the pixel circuit 22D and resets the signal charge accumulated in the charge holding unit 15D.

[0188] <<Specific Configuration of Solid-State Imaging Device>> Next, the specific configuration of the solid-state imaging device 1D according to the fourth embodiment will be described with reference to Fig. 20 , Fig.21 , Fig. 22 , Fig.23A and Fig. 23B The specific configuration of the solid-state imaging device 1D according to the fourth embodiment will be described. Fig. 20 is a plan view schematically showing the layout pattern of the pixel transistors (AMP, SEL, RST, and OFG) included in the pixel circuit 22D and the second gate electrode 506 included in the transfer transistor TR4. Fig.21 is a vertical cross-sectional view schematically showing the vertical cross-sectional structure of the solid-state imaging device 1D. Fig. 22 is an enlarged vertical sectional view showing the enlarged portion Fig.21 . Fig.23A is a vertical sectional view schematically showing the transfer direction of signal charges of a transfer transistor. Fig. 23B is a diagram showing an example of potential when charge transfer is performed by transfer transistor TR4. Note that Fig. 20 is a plan view of semiconductor chip 2X in Figure 1 viewed from the side opposite to the light incident surface side. In addition, Fig.21 is a diagram upside down with respect to Figure 1 and Fig.18 . In addition, Fig. 22 the third substrate 30 shown in Fig.18 is not shown.

[0189] As Fig.21 shown, the solid-state imaging device 1D (semiconductor chip 3) includes a first substrate 40, a second substrate 50, and a third substrate 30 (see Fig.18 ) stacked relative to each other. The above-described pixel array section 2A 1 , the peripheral section 2B, the bonding pads 14, the photoelectric conversion region 102d, etc. are mainly provided in the first substrate 40. The pixel transistors (AMP, SEL, RST, and OFG) included in the above-described pixel circuit 22D, the charge holding unit 15D, etc. are mainly provided in the second substrate 50. The above-described logic circuit 32, etc. are mainly provided in the third substrate 30. In addition, the transfer transistor TR4 is provided to pass through the first substrate 40 and the second substrate 50. Each of the two gate electrodes (406a and 506) of the transfer transistor TR4 and the charge holding unit 15D are provided outside the photoelectric conversion region 102d of the first substrate 40 and not in the photoelectric conversion region 102d.

[0190] <First Substrate> As Fig.21 and Fig. 22 shown, the first substrate 10 includes a semiconductor base portion 402 having a first surface S1 and a second surface S2 located on opposite sides in the thickness direction (Z direction) of the first substrate 10, and also includes a photoelectric conversion region 102d constituting the first semiconductor portion, semiconductor protrusion portions 415a respectively protruding from the above-described semiconductor base portion 402 toward the first surface S1 to constitute the second semiconductor portion, and semiconductor protrusion portions 415b respectively protruding from the above-described semiconductor base portion 402 toward the first surface S1. In addition, the first substrate 10 further includes a light-shielding film 409 provided on the first surface side of the semiconductor base portion 402 and an optical layer 420 provided on the second surface S2 side of the semiconductor base portion 402. The optical layer 420 has a configuration that is substantially similar to the configuration of the optical layer 130 of the first embodiment described above, and includes a planarization film 131, a light-shielding film 132, an optical filter 133, and a microlens 134. According to the fourth embodiment of the present disclosure, the semiconductor base portion 402 corresponds to a specific example of the "first semiconductor portion" of the present technology, and each semiconductor protrusion portion 415a corresponds to a specific example of the "second semiconductor portion" of the present technology.

[0191] (Semiconductor base portion) As Fig.21 and Fig. 22 shown, the semiconductor base portion 402 includes an isolation region 106 extending in the thickness direction (Z direction) of the semiconductor base portion 402 and a photoelectric conversion region 102d partitioned by the isolation region 106. Accordingly, the semiconductor base portion 402 includes a first surface S1 and a second surface S2 located on opposite sides of each other and the photoelectric conversion region 102d partitioned by the isolation region 106. The semiconductor base portion 402 extends two-dimensionally over a plurality of photoelectric conversion regions 102d (sensor pixels 12d).

[0192] (Isolation region) Similar to the isolation region 106 of the first embodiment described above, as Fig.21 shown, the isolation region 106d extends between the first surface S1 side and the second surface S2 side of the semiconductor base portion 402 to electrically and optically isolate the photoelectric conversion regions 102d adjacent to each other in a two-dimensional plane. For example, the isolation region 106d has, but is not limited to, the following dug-hole-shaped isolation structure, which includes an insulating film in a dug-hole portion extending in the thickness direction (Z direction) of the semiconductor layer 101. Although not shown in detail in the figure, the isolation region 106d has a lattice-shaped planar pattern in which a plurality of first portions extending in the X direction and a plurality of second portions extending in the Y direction intersect in a plan view.

[0193] (Photoelectric conversion region and photoelectric conversion unit) Although in Fig.21Although not shown in detail, similar to the photoelectric conversion region 102 of the above-described first embodiment, a photoelectric conversion region 102d is provided in the semiconductor base portion 402 for each sensor pixel 12d and is repeatedly arranged at intervals in the isolation region 106 in each of the X direction and the Y direction. Specifically, the semiconductor base portion 402 includes a plurality of photoelectric conversion regions 102d, and these photoelectric conversion regions 102d are provided adjacent to each other with an isolation region 106 extending in the thickness direction (Z direction) of the semiconductor base portion 402 therebetween.

[0194] Similar to the photoelectric conversion region 102 of the above-described first embodiment, as Fig.21 shown, the photoelectric conversion region 102d includes a p-type semiconductor region 103 extending between the first surface S1 side and the second surface S2 side of the semiconductor base portion 402 and an n-type semiconductor region 104 formed within the p-type semiconductor region 103 thus provided.

[0195] The p-type semiconductor region 103 and the n-type semiconductor region 104 of the fourth embodiment herein have a configuration similar to the configuration of the p-type semiconductor region 103 and the n-type semiconductor region 104 of the above-described first embodiment. Therefore, the p-type semiconductor region 103 and the n-type semiconductor region 104 of the fourth embodiment herein will not be specifically described anymore.

[0196] In addition, Fig.21 the photoelectric conversion unit 105d shown also has a configuration similar to the configuration of the photoelectric conversion unit 105 of the above-described first embodiment. Therefore, the photoelectric conversion unit 105d of the fourth embodiment herein will not be specifically described anymore.

[0197] (Semiconductor protrusion) As Fig. 22 shown, semiconductor protrusions 415a and 415b are provided for each photoelectric conversion region 102d (sensor pixel 12d) and are dispersed at positions separated from each other. As Fig. 20 shown, for example, the semiconductor protrusion 415a is composed of two protrusions, but is not limited thereto. In addition, although not shown in Fig. 20 , for example, the semiconductor protrusion 415b is also composed of two protrusions.

[0198] As Fig. 22As shown, each semiconductor protrusion 415a includes a p-type base protrusion 403a integrally formed with the semiconductor base portion 402 and a p-type single crystal layer 413a selectively formed by epitaxial growth at the distal end of the p-type base protrusion 403a. Similarly, each semiconductor protrusion 415b includes a p-type base protrusion 403b integrally formed with the semiconductor base portion 402 and a p-type single crystal layer 413b selectively formed by epitaxial growth at the distal end of the base protrusion 403b.

[0199] The semiconductor base portion 402 has an integral structure with the base protrusions 403a and 403b, and there is no interface portion between the semiconductor base portion 402 and the base protrusions 403a and 403b. Such an integral structure without an interface portion can be formed by selectively etching one surface side of the semiconductor layer 401 in the depth direction (Z direction) of the semiconductor layer 401 to a predetermined depth. The semiconductor layer 401 may be composed of semiconductor substrates such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide (GaAs) substrate, and an indium phosphide (InP) substrate. According to the fourth embodiment herein, for example, the semiconductor layer 401 is composed of a p-type semiconductor substrate made of single crystal silicon. Therefore, for example, each of the semiconductor base portion 402 and the base protrusions 403a and 403b in the fourth embodiment herein is composed of single crystal silicon. Additionally, for example, each of the single crystal layers 413a and 413b is also composed of single crystal silicon.

[0200] The epitaxial growth herein can form single crystal layers 413a and 413b made of single crystal silicon at the distal ends of the base protrusions 403a and 403b made of single crystal silicon according to the crystallinity of the base protrusions 403a and 403b. Additionally, the single crystal layers 413a and 413b formed by epitaxial growth are covalently bonded to the base protrusions 403a and 403b. Therefore, there is no interface portion between the base protrusions 403a and 403b and the single crystal layers 413a and 413b. In other words, the semiconductor protrusion 415a including the base protrusion 403a and the single crystal layer 413a has no interface portion. Similarly, the semiconductor protrusion 415b including the base protrusion 403b and the single crystal layer 413b also has no interface portion.

[0201] In the fourth embodiment herein, for ease of illustration, the base protrusions 403a and 403b and the single crystal layers 413a and 413b are shown separately, but as described above, there is no interface portion between the base protrusions 403a and 403b and the single crystal layers 413a and 413b.

[0202] Each semiconductor protrusion 415a serves as a channel formation portion of the transfer transistor TR4. On the other hand, each semiconductor protrusion 415b is electrically connected to the p-type well region 103 of the photoelectric conversion region 102d and serves as a power supply conduction path for supplying a reference potential to the p-type well region 103. In addition, each semiconductor protrusion 415b also serves as a discharge path for discharging carriers (holes) accumulated in the photoelectric conversion region to the wiring 513b via a through contact electrode 512b described below.

[0203] Here, note that the first surface S1 of the semiconductor base portion 402 may be referred to as an element formation surface or a main surface in some cases, and the second surface S2 may be referred to as a light incident surface or a back surface in some cases. The solid-state imaging device 1D according to the fourth embodiment of the present invention receives light from the second surface (light incident surface, back surface) S2 side of the semiconductor base portion 402 and performs photoelectric conversion on the received light in the photoelectric conversion region 102d (specifically, or the photoelectric conversion unit 105d) of the semiconductor base portion 402.

[0204] In addition, the plan view refers to a view in the direction along the thickness direction (Z direction) of the semiconductor chip 3. In addition, the cross-sectional view refers to a view of a cross-section taken in the thickness direction (Z direction) of the semiconductor chip 3 as observed in a direction perpendicular to the thickness direction (Z direction) of the semiconductor chip 3 (X direction or Y direction). In addition, the photoelectric conversion region 102d may also be referred to as a photoelectric conversion unit.

[0205] (First gate electrode and planarization plate) As Fig. 22 shown, the first gate electrode 406a, the planarization plate 406b, and the light shielding film 409 are provided on the first surface S1 side of the semiconductor base portion 402.

[0206] The first gate electrode 406a is adjacent to the semiconductor protrusion 415a with the first gate insulating film 404 extending in the protruding direction (Z direction) of the semiconductor protrusion 415a. In addition, for example, the gate electrode 406a surrounds the outer periphery of the semiconductor protrusion 415a in the plan view.

[0207] The first gate insulating film 404 is provided on the semiconductor protrusions 415a and 415b and the semiconductor base portion 402. In addition, the first gate insulating film 404 covers the respective circumferential surfaces of the semiconductor protrusions 415a and 415b and the photoelectric conversion region 102d of the semiconductor base portion 402.

[0208] The planarization plate 406b is disposed on the first surface S1 side of the semiconductor substrate 402 with the first gate insulating film 404 therebetween. The planarization plate 406b includes a first portion (flat portion) and a second portion (protruding portion). The first portion overlaps with the photoelectric conversion region 102d of the semiconductor substrate 402 in a plan view, surrounds the outer periphery of the first gate electrode 406a with the insulating film 408 therebetween, and also surrounds the outer periphery of the semiconductor protrusion 415b with the first gate insulating film 404 therebetween. The second portion protrudes from the first portion in the protruding direction (Z direction) of the semiconductor protrusion 415b and surrounds the outer periphery of the semiconductor protrusion 415b with the first gate insulating film 404 therebetween. In addition, the planarization plate 406b extends two-dimensionally over a plurality of photoelectric conversion regions 102d.

[0209] In a plan view, the first gate electrode 406a and the planarization plate 406b are disposed adjacent to each other with the insulating film 408 therebetween, and are electrically and mechanically isolated from each other. The planarization plate 406b reduces the step between the semiconductor substrate 402 and the semiconductor protrusions 415a and 415b to planarize the first surface S1 side of the semiconductor substrate 402. The insulating film 408 is disposed between the gate electrode 406a and the planarization plate 406b and covers each of the first gate electrode 406a and the planarization plate 406b.

[0210] For example, each of the first gate electrode 406a and the planarization plate 406b is made of a polysilicon film doped with impurities for reducing resistance. For example, the first gate insulating film 404 is made of a silicon oxide film formed by thermal oxidation. For example, the insulating film 408 is made of a silicon oxide film formed by deposition.

[0211] (Light-shielding film) As Fig. 22 shown, the light-shielding film 409 is disposed on the side of the planarization plate 406b opposite to the semiconductor substrate 402 with the insulating film 408 therebetween. The light-shielding film 409 surrounds the outer periphery of each of the first gate electrode 406a and the second portion (protruding portion) of the planarization plate 406b with the insulating film 408 therebetween and extends two-dimensionally over a plurality of photoelectric conversion regions 102d.

[0212] The light-shielding film 409 is insulated from the first gate electrode 406a and the planarization plate 406b with the insulating film 408 therebetween. For example, the light-shielding film 409 is made of a tungsten (W) film having a light-shielding property. For example, the insulating film 408 is made of a silicon oxide film.

[0213] As Fig. 22As shown, the light-shielding film 409 is covered by an insulating film 411 disposed on the side of the light-shielding film 409 opposite to the semiconductor base portion 402. The insulating film 411 surrounds the outer periphery of the semiconductor protrusion 415a protruding from the light-shielding film 409 with the first gate insulating film 404, the first gate electrode 406a, the insulating film 408, etc. interposed therebetween, and also surrounds the outer periphery of the semiconductor protrusion 415b protruding from the light-shielding film 409 with the first gate insulating film 404, the second portion (protruding portion) of the planarization plate, the insulating film 408, etc. interposed therebetween. The insulating film 411 has a planarized upper surface portion on the side opposite to the light-shielding film 409. For example, the insulating film 411 is formed of a silicon oxide film.

[0214] (Relay region) As Fig. 22 shown, the photoelectric conversion region 102d includes an n-type semiconductor region 104a protruding from the n-type semiconductor region 104 toward the semiconductor protrusion 415a. The thus formed n-type semiconductor region 104a is a relay region for facilitating the movement of signal charges photoelectrically converted by the photoelectric conversion unit 105d to the semiconductor protrusion 415a. Therefore, the n-type semiconductor region 104a preferably extends over the photoelectric conversion region 102d and the semiconductor protrusion 415a.

[0215] <Second substrate> As Fig. 22 shown, the second substrate 50 is disposed on the side of the first substrate 40 opposite to the semiconductor base portion 402 side.

[0216] As Fig. 22 shown, the second substrate 50 includes a semiconductor island portion 502 and a second gate electrode 506 on the first surface S1 side of the semiconductor base portion 402. The semiconductor island portion 502 is joined to the distal end of the semiconductor protrusion 415a and constitutes a third semiconductor portion. The second gate electrode 506 is arranged side by side with the first gate electrode 406a in a manner leaving a gap in the protruding direction (Z direction) of the semiconductor protrusion 415a, and is adjacent to the semiconductor island portion 502 with the second gate insulating film 504 interposed therebetween.

[0217] In addition, as Fig. 22 shown, the second substrate 50 further includes a charge holding unit 15D disposed on the semiconductor island portion 502. In addition, although not shown in detail in the figure, the second substrate 50 further includes Fig. 20 the semiconductor island portion 503 shown disposed on the first surface S1 side of the semiconductor base portion 402.

[0218] Furthermore, as Fig. 22As shown, the second substrate 50 further includes an insulating layer 508 provided on the side of the first surface S1 of the semiconductor base portion 402, a light-shielding film 509 formed on the side of the insulating layer 508 opposite to the semiconductor base portion 402, and an insulating layer 511 formed on the side of the light-shielding film 509 opposite to the semiconductor base portion 402. In addition, as Fig. 22 shown, the second substrate 50 further includes a p-type polycrystalline layer 414 formed between the insulating film 411 and the semiconductor island portion 502. Although not shown in detail in the figure, the p-type polycrystalline layer 414 thus provided is also formed between the insulating film 411 and the semiconductor island portion 503.

[0219] Here, note that the semiconductor island portion 502 according to the fourth embodiment of the present invention corresponds to a specific example of the "third semiconductor portion" of the present technology.

[0220] (Semiconductor island portion) As Fig. 20 and Fig. 22 shown, each of the semiconductor island portions 502 and 503 is provided for each photoelectric conversion region 102d (sensor pixel 12d) and overlaps with the photoelectric conversion region 102d in the plan view.

[0221] As Fig. 22 shown, the semiconductor island portion 502 is configured such that a part of the back surface on the side of the semiconductor base portion 402 of the semiconductor island portion 502 is joined to the distal end of the semiconductor protrusion portion 415a. In addition, the semiconductor island portion 502 is configured such that another part of the back surface on the side of the semiconductor base portion 402 of the semiconductor island portion 502 is joined to the p-type polycrystalline layer 414. On the other hand, although not shown in the figure, the entire back surface on the side of the semiconductor base portion 402 of the semiconductor island portion 503 is joined to the p-type polycrystalline layer 414.

[0222] As Figure 24M shown, each of the semiconductor island portions 502 and 503 is formed by joining the semiconductor layer 501 to the respective distal ends of the semiconductor protrusion portions 415a and 415b and the p-type polycrystalline layer 414, and then patterning the joined semiconductor layer 501. Therefore, as Fig. 22 shown, in the fourth embodiment of the present invention, there is a bonding interface portion Ja between the semiconductor protrusion portion 415a and the semiconductor island portion 502 1 .

[0223] As Fig. 20As shown, the semiconductor island portion 502 includes a first portion 502a extending in the X direction in the plan view and a second portion 502b protruding in the Y direction from the thus formed first portion 502a. Further, the second gate electrode 506 overlaps with the first portion 502a and the second portion 502b of the semiconductor island portion 502. In addition, the reset transistor RST is provided at the first portion 502a of the semiconductor island portion 502, and the discharge transistor OFG is provided at the second portion 502b of the semiconductor island portion 502.

[0224] As Fig. 20 shown, the semiconductor island portion 503 extends in the X direction and is arranged side by side with the semiconductor island portion 502 in the Y direction. Further, the amplification transistor AMP and the selection transistor SEL are provided side by side with each other in the semiconductor island portion 503.

[0225] For example, each of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the discharge transistor OFG is constituted by an n-channel conductivity type MOSFET which is a field effect transistor.

[0226] (Amplification transistor and selection transistor) As Fig. 20 shown, the amplification transistor AMP includes a gate electrode 506a provided on the semiconductor island portion 503 with a gate insulating film interposed therebetween and a pair of main electrode regions 508a and 508b which are provided in the semiconductor island portion 503 on one side and the other side in the gate length direction of the gate electrode 506a and which also serve as a source region and a drain region, respectively.

[0227] As Fig. 20 shown, the selection transistor SEL includes a gate electrode 506s provided in the semiconductor island portion 503 with a gate insulating film interposed therebetween and a pair of main electrode regions 508c and the main electrode region 508a which are provided in the semiconductor island portion 503 on one side and the other side in the gate length direction of the gate electrode 506s and which also serve as a source region and a drain region, respectively.

[0228] Further, the amplification transistor AMP and the selection transistor SEL share one main electrode region (source region side) 508a of the amplification transistor AMP and the other main electrode region (drain region side) 508a of the selection transistor SEL.

[0229] For example, each of the gate insulating films provided on the amplification transistor AMP and the selection transistor SEL is constituted by a silicon oxide film. For example, each of the gate electrodes 506a and 506s is constituted by a polysilicon film into which impurities for reducing resistance are introduced. For example, each of the main electrode regions 508a, 508b, and 508c is constituted by an impurity concentration ratio Fig. 22The n-type semiconductor region 104 shown is composed of a higher n-type semiconductor region.

[0230] For example, the gate electrodes 506a and 06s provided on the amplification transistor AMP and the selection transistor SEL, respectively, are formed by the same steps as those for forming the second gate electrode 506 of the transfer transistor TR4. In addition, for example, the gate insulating films included in the amplification transistor AMP and the selection transistor SEL are formed by the same steps as those for forming the second gate insulating film of the transfer transistor TR4.

[0231] (Reset transistor and discharge transistor) As Fig. 20 shown, the reset transistor RST includes a gate electrode 506r provided in the first portion 502a of the semiconductor island portion 502 with a gate insulating film interposed therebetween, and a pair of main electrode regions 507a and 507b that are provided on one side and the other side in the gate length direction of the gate electrode 506r and also serve as a source region and a drain region, respectively. As Fig. 20 shown, the discharge transistor OFG includes a gate electrode 506g provided in the second portion 502b of the semiconductor island portion 502 with a second gate insulating film interposed therebetween, and a pair of main electrode regions 507c and 507d that are provided on one side and the other side in the gate length direction of the gate electrode 506g and also serve as a source region and a drain region, respectively.

[0232] For example, each gate insulating film provided on the reset transistor RST and the discharge transistor OFG is composed of a silicon oxide film. For example, each of the gate electrodes 506r and 506g is composed of a polysilicon film into which impurities for reducing resistance are introduced. For example, each of the main electrode regions 507a, 507b, 507c, and 507d is composed of an n-type semiconductor region with an impurity concentration higher than that of Fig. 22 the n-type semiconductor region 104 shown.

[0233] For example, the gate electrodes 506r and 06g provided on the reset transistor RST and the discharge transistor OFG, respectively, are formed by the same steps as those for forming the second gate electrode 506 of the transfer transistor TR4. In addition, for example, each gate insulating film provided on the reset transistor RST and the discharge transistor OFG is formed by the same steps as those for forming the second gate electrode of the transfer transistor TR4.

[0234] (Insulating layer and light-shielding film) As Fig. 22As shown, the insulating layer 508 is joined to the upper surface portion of the insulating film 411 on the side opposite to the semiconductor base portion 402. Although not shown in detail in the figure, in a plan view, the insulating layer 508 is disposed over the plurality of photoelectric conversion regions 102d and covers the semiconductor island portions 502 and 503 provided for each photoelectric conversion region 102d, the second gate electrode 506 of the transfer transistor TR4, pixel transistors (AMP, SEL, RST, and OFG), and the like. For example, the insulating layer 508 is made of a silicon oxide film.

[0235] As Fig. 22 shown, the light-shielding film 509 is provided on the upper surface portion of the insulating layer 508 on the side opposite to the semiconductor base portion 402. In a plan view, the light-shielding film 509 is provided over the plurality of photoelectric conversion regions 102d and is formed, for example, over Fig.18 the entire pixel array portion 2A as 1 shown. For example, the light-shielding film 509 is made of a tungsten (W) film having a light-shielding property. The light-shielding film 509 shields light emitted from the transistors included in the logic circuit 32 of the third substrate 30 during operation to prevent light from entering the pixel transistors (AMP, SEL, RST, and OFG), the transfer transistor TR4, the charge holding unit 15D, and the like from the third substrate 30.

[0236] As Fig. 22 shown, the light-shielding film 509 is covered with the insulating layer 511 provided on the upper surface portion of the insulating layer 508 on the side opposite to the semiconductor base portion 402. In addition, the wirings 513a, 513b, and 513c formed in the first wiring layer are provided on the upper surface portion of the insulating layer 511 on the side opposite to the semiconductor base portion 402. For example, the insulating layer 511 is made of a silicon oxide film. For example, the wiring layer including the wirings 513a, 513b, and 513c is made of a metal film such as aluminum (Al) or copper (Cu), an alloy film mainly composed of Al or Cu, or the like.

[0237] <The First Substrate and the Second Substrate> (Transfer Transistor) As Fig. 22 shown, the transfer transistor TR4 includes the first gate electrode 406a provided in the first substrate 40 as described above and the second gate electrode 506 provided in the second substrate 50 as described above. Therefore, the transfer transistor TR4 of the fourth embodiment is configured to extend over the first substrate 40 and the second substrate 50. In addition, the transfer transistor TR4 further includes a photoelectric conversion unit 105d mainly serving as a source region and a main electrode region 507a mainly serving as a drain region.

[0238] As Fig. 22As shown, the main electrode region 507a of the transfer transistor TR4 shares with one main electrode region (source region side) 705a of the reset transistor RST. In addition, the main electrode region 705a is provided in the semiconductor island portion 502 and is aligned with the gate electrodes 506 and 506r of the transfer transistor TR4 and the reset transistor RST, respectively.

[0239] The first gate electrode 406a is provided around the semiconductor protrusion portion 415a with the first gate insulating film 404 interposed therebetween. On the other hand, the second gate electrode 506 is provided on the upper surface portion and the side surface portion of the semiconductor island portion 502 with the second gate insulating film 504 interposed therebetween. Therefore, unlike the gate electrode 113 of the transfer transistor TR in the first embodiment described above, each of the first gate electrode 406a and the second gate electrode 506 of the transfer transistor TR4 in the fourth embodiment herein is provided outside the first surface S1 of the semiconductor base portion 402, specifically, outside the photoelectric conversion region 102d, and is not provided inside the photoelectric conversion region 102d. In addition, each of the first gate electrode 406a and the second gate electrode 506 of the transfer transistor TR4 in the fourth embodiment herein is separated from the bonding interface portion Ja 1 between the semiconductor protrusion portion 415a and the semiconductor island portion 502, and does not 1 overlap with the bonding interface portion Ja.

[0240] (Charge holding unit) As Fig. 22 shown, the charge holding unit 15D is provided in the semiconductor island portion 502. In addition, the charge holding unit 15D shares with the main electrode region 507a of the transfer transistor TR4 and also shares with one main electrode region 507a of the reset transistor RST. Specifically, the charge holding unit 15D is provided in the semiconductor island portion 502 and is aligned with the respective gate electrodes (the second gate electrode 506 and the gate electrode 506r) of the transfer transistor TR4 and the reset transistor RST. In addition, the charge holding unit 15D is composed of an n-type semiconductor region having an impurity concentration higher than that of Fig. 22 the n-type semiconductor region 104 shown, and serves as an FD capacitor (floating diffusion capacitor). In addition, similar to the charge holding unit 15 in the first embodiment described above, the charge holding unit 15D is provided outside the first surface S1 of the semiconductor base portion 402, specifically, outside the photoelectric conversion region 102d, and is not provided inside the photoelectric conversion region 102d. In addition, in the plan view, the charge holding unit 15D overlaps with the light shielding film 409 and is not affected by the light passing through the photoelectric conversion unit 105d.

[0241] (Bonding interface portion) Fig. 22 The bonding interface portion Ja shown 1 Included in the bonding interface portion Jb between the first substrate 40 and the second substrate 50. In addition, the bonding interface portion Jb between the insulating film 411 of the first substrate 40 and the insulating layer 508 of the second substrate 50 1 It is also included in the joint interface portion Jb between the first substrate 40 and the second substrate 50 .

[0242] like Fig. 22 As shown, the second gate electrode 506 of the transfer transistor TR4 extends along the side surface portion of the semiconductor island portion 502 via the second gate insulating film 504 and is bonded to the insulating film 411 of the first base 40. In addition, the bonding interface portion Jb between the second gate electrode 506 and the insulating film 411 is 2 It is also included in the joint interface portion Jb between the first substrate 40 and the second substrate 50 .

[0243] like Fig. 22 As shown, the second gate electrode 506 of the transfer transistor TR4 is bonded to the insulating film 411 of the first base 40 but does not pass through the bonding interface portion Jb between the first base 40 and the second base 50 . On the other hand, the first gate electrode 406a of the transfer transistor TR4 is spaced apart from the bonding interface portion Jb between the first base 40 and the second base 50. Therefore, similar to the second gate electrode 506, the first gate electrode 406a does not pass through the bonding interface portion Jb between the first base 40 and the second base 50. Therefore, each of the first gate electrode 406 a and the second gate electrode 506 of the transfer transistor TR4 does not pass through the bonding interface portion Jb between the first base body 40 and the second base body 50 in the Z direction.

[0244] (Through contact electrode) like Fig. 22As shown, the wiring 513a is electrically connected to the first gate electrode 406a of the transfer transistor TR4 via the through-contact electrode 512a that extends through the first substrate 40 and the second substrate 50 in the thickness direction (Z direction) of each of the first substrate 40 and the second substrate 50. The through-contact electrode 512a penetrates through the upper surface portion of the insulating layer 511 on the side opposite to the semiconductor base portion 402, the through-hole 510a of the light-shielding film 509, the insulating layer 508, the insulating film 411, the through-hole 410a of the light-shielding film 409, the insulating film 408, etc., and reaches the first gate electrode 406a. Further, the through-contact electrode 512a is electrically insulated from the light-shielding film 509 with the insulating layer 511 provided in the through-hole 510a of the light-shielding film 509 therebetween. Further, the through-contact electrode 512a is electrically insulated from the light-shielding film 409 with the insulating film 411 provided in the through-hole 410a of the light-shielding film 409 therebetween.

[0245] As Fig. 22 shown, the wiring 513b is electrically connected to the distal end of the semiconductor protrusion 415b via the through-contact electrode 512b that extends in the thickness direction (Z direction) of the second substrate 50. The through-contact electrode 512b penetrates through the upper surface portion of the insulating layer 511, the through-hole 510b of the light-shielding film 509, the insulating layer 508, etc., and reaches the distal end of the semiconductor protrusion 415b. Further, the through-contact electrode 512b is electrically insulated from the light-shielding film 509 with the insulating layer 511 provided in the through-hole 510b of the light-shielding film 509 therebetween.

[0246] As Fig. 22 shown, the wiring 513c is electrically connected to the planarization plate 406b via the through-contact electrode 512c that extends through the first substrate 40 and the second substrate 50 in the thickness direction (Z direction) of each of the first substrate 40 and the second substrate 50. The through-contact electrode 512c penetrates through the upper surface portion of the insulating layer 511, the through-hole 510c of the light-shielding film 509, the insulating layer 508, the insulating film 411, the through-hole 410c of the light-shielding film 409, the insulating film 408, etc., and reaches the planarization plate 406b. Further, the through-contact electrode 512c is electrically insulated from the light-shielding film 509 with the insulating layer 511 provided in the through-hole 510c of the light-shielding film 509 therebetween. Further, the through-contact electrode 512c is electrically insulated from the light-shielding film 409 with the insulating film 411 provided in the through-hole 410c of the light-shielding film 409 therebetween.

[0247] For example, each of the through-contact electrodes 512a, 512b, and 512c is formed of a high melting point metal film such as titanium (Ti) or tungsten (W).

[0248] (Position relationship between the semiconductor island portion and the light-shielding film) As Fig. 22As shown, in the plan view, the semiconductor island portion 502 overlaps with the photoelectric conversion region 102d of the semiconductor base portion 402. In addition, a light-shielding film 409 is provided between the semiconductor island portion 502 and the photoelectric conversion region 102d. Preferably, the light-shielding film 409 is provided at least between the charge holding unit 15D and the photoelectric conversion unit 105d.

[0249] <<Charge Transfer and Charge Holding>> Next, reference will be made to Fig.23A and Fig. 23B to describe the signal charge transfer performed by the transfer transistor TR4.

[0250] For example, as types of field effect transistors, there are enhancement-mode (normally-off) field effect transistors and depletion-mode (normally-on) field effect transistors. The enhancement-mode field effect transistor causes a drain current to flow by applying a threshold gate voltage or higher voltage to the gate electrode, and the depletion-mode field effect transistor does not need to apply a voltage to the gate electrode to cause a drain current to flow. For example, the transfer transistor TR4 in the fourth embodiment herein is an enhancement-mode, but is not limited thereto.

[0251] In the case of the enhancement-mode, the transfer transistor TR4 applies a threshold gate voltage or higher voltage to the first gate electrode 406a to form (induce) a first channel (inversion layer) in the semiconductor protrusion portion 415a adjacent to the gate electrode 406a with the first gate insulating film 404 interposed therebetween. In addition, the transfer transistor TR4 applies a threshold gate voltage or higher voltage to the second gate electrode 506 to form a second channel (inversion layer) in the semiconductor island portion 502 adjacent to the gate electrode 506 with the second gate insulating film 504 interposed therebetween.

[0252] Thereafter, by applying a gate voltage to each of the first gate electrode 406a and the second gate electrode 506 through the transfer transistor TR4, the photoelectric conversion unit 105d of the photoelectric conversion region 102d and the charge holding unit 15D are electrically connected through the first channel and the second channel. As a result, the signal charge photoelectrically converted by the photoelectric conversion unit 105d passes through the first channel, then through the second channel, and is transferred to the charge holding unit 15D. In other words, the signal charge sequentially passes through the first channel and the second channel in a relay manner and is transferred to the charge holding unit 15D. Thereafter, the signal charge transferred to the charge holding unit 15D is temporarily held in the charge holding unit 15D. The signal charge held in the charge holding unit 15D is then converted into a pixel signal by the pixel circuit 22D and output.

[0253] As Fig.23A the arrow R in 1 shows, the signal charge transferred from the transfer transistor TR4 passes through the bonding interface portion Ja between the semiconductor protrusion portion 415a and the semiconductor island portion 5021 However, each of the first gate electrode 406a and the second gate electrode 506 is separated from the bonding interface portion Ja 1 and does not directly overlap with the bonding interface portion Ja 1 . In this case, as Fig. 23B shown, the interface state at the bonding interface portion Ja 1 is not easily affected by the electric field. Therefore, even if there is a bonding interface portion Ja between the semiconductor protrusion 415a and the semiconductor island portion 502 1 , that is, even if there is a bonding interface portion Ja in the charge transfer path where the signal charge moves 1 , the signal charge can smoothly move from the semiconductor protrusion 415a to the semiconductor island portion 502.

[0254] <<Method of Manufacturing a Solid-State Imaging Device>> Next, a method of manufacturing the solid-state imaging device 1D according to the above-described fourth embodiment will be described with reference to FIG. 24A to FIG. 24S . The fourth embodiment herein will specifically relate to the manufacture of the transfer transistor TR4 and the charge holding unit 15D included in the method of manufacturing a solid-state imaging device 1D.

[0255] First, as Fig.24A shown, a photoelectric conversion region 102d, a p-type well region 103, a p-type semiconductor region 103a, an n-type semiconductor region 104, an n-type semiconductor region 104a, a photoelectric conversion unit 105d, an isolation region 106, etc. are formed in the semiconductor layer 401. The isolation region 106 divides each unit of the photoelectric conversion region 102d. A p-type well region 103 and semiconductor regions 103a, n-type semiconductor regions 104 and 104a, and a photoelectric conversion unit 105d are formed for each photoelectric conversion region 102d. The n-type semiconductor region 104 is formed to be separated from one surface of the semiconductor layer 401. The p-type semiconductor region 103a extends in the depth direction (Z direction) of the semiconductor layer 401 from one surface side of the semiconductor layer 401 and contacts the n-type semiconductor region 104. The p-type semiconductor region 103a is formed in a region where a substrate protrusion 403a described below is formed and has a higher impurity concentration than the p-type well region 103. The n-type semiconductor region 104 protrudes into the p-type semiconductor region 103a from the n-type semiconductor region 104. For example, the semiconductor layer 401 may be composed of a p-type semiconductor substrate made of single crystal silicon, but is not limited thereto.

[0256] Subsequently, as Fig. 24BAs shown, one surface side of the semiconductor layer 401 in which the photoelectric conversion region 102d, semiconductor regions (103, 103a, 104, and 104a), photoelectric conversion unit 105d, isolation region 106, etc. are formed is etched in the depth direction (Z direction) of the semiconductor layer 401 to form a semiconductor base portion 402 having a first surface S1 and a second surface S2 located on opposite sides of each other and base protrusions 403a and 403b protruding from the semiconductor base portion 402 toward the first surface S1 side of the semiconductor base portion 402. The base protrusions 403a and 403b are spaced apart from each other and are formed for each photoelectric conversion region 102d. The base protrusion 403a includes a p-type semiconductor region 103a and an n-type semiconductor region 104a. The base protrusion 403b includes a p-type well region 103.

[0257] After forming the semiconductor base portion 402 and the base protrusions 403a and 403b, as Fig.24C shown, subsequently, a first gate insulating film 404 is formed on the first surface S1 of the semiconductor base portion 402 and the upper surface portions and side surface portions of each of the base protrusions 403a and 403b. For example, the first gate insulating film 404 can be prepared by thermal oxidation or depositing a silicon oxide film.

[0258] After forming the first gate insulating film 404, as Fig.24D shown, subsequently, a conductive film (first gate material) 405 covering the semiconductor base portion 402 and each of the base protrusions 403a and 403b is formed on the first surface S1 side of the semiconductor base portion 402. For example, the conductive film 405 can be a polysilicon (doped polysilicon) film, and impurities for reducing resistance are introduced into the polysilicon film during or after film formation. For example, the polysilicon film can be formed by a known CVD method.

[0259] Subsequently, as Fig.24E shown, the conductive film 405 on the upper surface portion of each of the base protrusions 403a and 403b is selectively removed and then patterned to form separate first gate electrodes 406a and a planarization plate 406b. For example, the selective removal of the conductive film 405 can be achieved by an anisotropic dry etching technique such as reactive ion etching (RIE: Reactive Ion Etching). The conductive film 405 can be patterned by a known photolithography technique and a known anisotropic dry etching technique. In this step, the first gate electrode 406a is formed in an annular planar pattern that surrounds the outer periphery of the base protrusion 403a with the first gate insulating film 404 interposed therebetween in a plan view.

[0260] In addition, in this step, the planarization plate 406b is formed on the first surface S1 side of the semiconductor substrate 402 with the first gate insulating film 404 therebetween. Further, the planarization plate 406b includes a flat portion (first portion) and a protruding portion (second portion). The flat portion overlaps with the photoelectric conversion region 102d of the semiconductor substrate 402 in a plan view, surrounds the outer periphery of the first gate electrode 406a with a gap therebetween, and also surrounds the outer periphery of the semiconductor protrusion 415b with the first gate insulating film 404 therebetween. The protruding portion protrudes from the flat portion in the protruding direction (Z direction) of the semiconductor protrusion 415b and surrounds the outer periphery of the semiconductor protrusion 415b with the first gate insulating film 404 therebetween. Additionally, the planarization plate 406b extends two-dimensionally over a plurality of photoelectric conversion regions 102d.

[0261] After forming the first gate electrode 406a and the planarization plate 406b, as Fig.24F shown, subsequently, an insulating film 408 is formed. The insulating film 408 fills the gap between the first gate electrode 406a and the planarization plate 406b and covers the first gate electrode 406a and the planarization plate 406b. For example, the insulating film 408 can be prepared by forming a silicon oxide film by CVD. The insulating film 408 is a film for electrically insulating the first gate electrode 406a from the planarization plate 406b, and is also for electrically insulating the first gate electrode 406a and the planarization plate 406b from the light-shielding film 409 described below. Therefore, preferably, the thickness of the insulating film 408 is less than the protruding amount of the protruding portion of the planarization plate 406b. Further, preferably, for example, the insulating film 408 has a sufficient or greater thickness to prevent dielectric breakdown between the first gate electrode 406a and the planarization plate 406b.

[0262] After forming the insulating film 408, as Figure 24G shown, subsequently, a light-shielding film 409 is formed on the entire surface of the insulating film 408 on the side opposite to the semiconductor substrate 402. The light-shielding film 409 covers the first gate electrode 406a and the planarization plate 406b with the insulating film 408 therebetween. For example, the light-shielding film 409 can be prepared by forming a high melting point metal film such as titanium (Ti) or tungsten (W) using a known film-forming technique. The light-shielding film 409 is formed over a plurality of photoelectric conversion regions 102d and overlaps with the photoelectric conversion regions 102d in a plan view.

[0263] After forming the light-shielding film 409, subsequently, the light-shielding film 409 located on the respective upper surface portions of the substrate protrusions 403a and 403b is selectively removed, and then as Fig.24HAs shown, through holes 410a and 410c are formed in the light-shielding film 409. The through hole 410a is formed at a position overlapping with the flat portion of the first gate electrode 406a in the plan view. The through hole 410b is formed at a position overlapping with the first portion (flat portion) of the planarizing plate 406b in the plan view. Each of the through holes 410a and 410c reaches the insulating film 408 overlapping with the light-shielding film 409. For example, selective removal of the light-shielding film 409 can be achieved by an anisotropic dry etching technique such as reactive ion etching (RIE). The through holes 410a and 410b can be formed by known photolithography techniques and known anisotropic dry etching techniques.

[0264] In this step, the light-shielding film 409 is insulated from the first gate electrode 406a and the planarizing plate 406b, and is also formed to surround the outer periphery of each protruding portion of the first gate electrode 406a and the planarizing plate 406b, and extends two-dimensionally over the plurality of photoelectric conversion regions 102d to cover each photoelectric conversion region 102d. Preferably, the light-shielding film 409 is formed to have such a film thickness that the upper surface portion of the light-shielding film 409 is lower than the distal end of the base protruding portion 403a.

[0265] After forming the through holes 410a and 410b, as Fig.24I shown, subsequently, an insulating film 411 is formed on the entire surface on the semiconductor base portion 402 side of the light-shielding film 409. For example, the insulating film 411 can be prepared by forming a silicon oxide film by CVD. Preferably, the insulating film 411 has a thickness sufficient to cover the insulating film 408 on the respective upper surfaces of the base protruding portions 403a and 403b.

[0266] After forming the insulating film 411, as Fig.24J shown, subsequently, openings 412a and 412b are formed, which are openings exposing the distal ends of the base protruding portions 403a and openings exposing the distal ends of the base protruding portions 403b, respectively. By selectively removing the insulating film 411, the insulating film 408, the first gate insulating film 404, etc. on the respective distal ends of the base protruding portions 403 and 403b, the respective openings 412a and 412b are formed. The respective openings 412a and 412b can be formed by known photolithography techniques and known anisotropic dry etching techniques.

[0267] After forming the respective openings 412a and 412b, subsequently, epitaxial growth of single crystal layers 413a and 413a is caused at the distal ends of the base protruding portions 403a and 403b by using the openings 412a and 412a, respectively. In this way, as Figure 24KAs shown, a semiconductor protrusion 415a including a base protrusion 403a and a single crystal layer 413a can be formed, and a semiconductor protrusion 415b including a base protrusion 403b and a single crystal layer 413b can be formed.

[0268] In this step, epitaxial growth can form single crystal layers 413a and 413b made of single crystal silicon at the distal ends of the base protrusions 403a and 403b made of single crystal silicon according to the crystallinity of the base protrusions 403a and 403b described above. Therefore, single crystal layers 413a and 413b of each silicon are formed in the fourth embodiment herein. In addition, the single crystal layers 413a and 413b formed by epitaxial growth are covalently bonded to the base protrusions 403a and 403b. Therefore, there is no interface portion between the base protrusions 403a and 403b and the single crystal layers 413a and 413b. In this step, as Figure 24K shown, a polycrystalline layer 414 of silicon is further formed by epitaxial growth on the upper surface of the insulating film 411 on the side opposite to the semiconductor base portion 402 side.

[0269] After the single crystal layers 413a and 413b are grown, for example, as Figure 24L shown, subsequently, the thicknesses of the single crystal layers 413a and 413b and the polycrystalline layer 414 are reduced by CMP to planarize these layers.

[0270] Subsequently, boron ions (B + ) and boron difluoride (BF 2 + ) are implanted as p-type impurities into each of the planarized single crystal layers 413a and 413b and the planarized polycrystalline layer 414, and then the single crystal layers 413a and 413b and the polycrystalline layer 414 are converted into p-type layers by heat treatment. In this way, a p-type semiconductor protrusion 415a including a p-type base protrusion 403a and a p-type single crystal layer 413a, and a p-type semiconductor protrusion 415b including a p-type base protrusion 403b and a p-type single crystal layer 413b are formed.

[0271] Subsequently, as Figure 24MAs shown, the semiconductor layer 501 is bonded to the respective distal ends (single crystal layers 413a and 413b) of the semiconductor protrusions 415a and 415b and the polycrystalline layer 414 by direct bonding. Specifically, first, plasma is applied to the respective distal ends of the semiconductor protrusions 415a and 415b and the polycrystalline layer 414 to remove oxides and adsorbed substances and generate atomic dangling bonds. Similarly, plasma is applied to the bonding surface of the semiconductor layer 501 to generate atomic dangling bonds. Thereafter, with the bonding surface of the semiconductor layer 501 facing the respective distal ends of the semiconductor protrusions 415a and 415b and the polycrystalline layer 414, the semiconductor layer 501 is pressed against the respective distal ends of the semiconductor protrusions 415a and 415b and the polycrystalline layer 414. In this way, as Figure 24M shown, the semiconductor layer 501 can be bonded to the respective distal ends (single crystal layers 413a and 413b) of the semiconductor protrusions 415a and 415b by direct bonding, and can be bonded to the polycrystalline layer 414. The semiconductor layer 501 can be composed of a semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a gallium arsenide (GaAs) substrate, and an indium phosphide (InP) substrate. According to the fourth embodiment herein, for example, the semiconductor layer 501 is composed of a p-type semiconductor substrate made of single crystal silicon.

[0272] In this step, a bonding interface portion Ja 1 exists between the semiconductor protrusion 415a and the semiconductor layer 501. In addition, a bonding interface portion Ja 2 exists between the semiconductor protrusion 415b and the semiconductor layer 501.

[0273] After bonding the semiconductor layer 501, the semiconductor layer 501 and the polycrystalline layer 414 are then patterned. Thereafter, as Fig.24N shown, semiconductor island portions 502 are formed, which include a part of the back surface on the semiconductor base portion 402 side and bonded to the distal end of the semiconductor protrusion 415a, and another part of the back surface on the semiconductor base portion 402 side and bonded to the insulating film 411 with the polycrystalline layer 414 interposed therebetween. In addition, although Fig.24N not shown, semiconductor island portions 503 as Fig. 20 shown are formed. Each of the semiconductor island portions 502 and 503 is formed for each photoelectric conversion region 102d. The semiconductor layer 501 and the polycrystalline layer 414 are patterned by known photolithography techniques and known anisotropic dry etching techniques.

[0274] In this step, a bonding interface portion Ja 1 exists between the semiconductor protrusion 415a and the semiconductor island portion 503.

[0275] In addition, in this step, the semiconductor layer 501 located on the semiconductor protrusion 415b is removed. Thus, the bonding interface portion Ja 2 disappears.

[0276] After forming the semiconductor island portions 502 and 503, as Fig.24O shown, subsequently, a second gate insulating film 504 is formed on the upper surface portion and the side surface portion of the semiconductor island portion 502. Although Figure 24O not shown in Figure 20 the figure, the second gate insulating film 504 is also formed on the upper surface portion and the side surface portion of the semiconductor island portion 503 shown. For example, the second gate insulating film 504 can be prepared by thermal oxidation or depositing a silicon oxide film.

[0277] After forming the second gate insulating film 504, as Figure 24P shown, subsequently, a conductive film (second gate material) 505 is formed on the side of the insulating film 411 opposite to the semiconductor base portion 402. The conductive film 505 covers the semiconductor island portion 502 with the second gate insulating film 504 interposed therebetween. In addition, although Figure 24P not shown in Figure 20 the figure, the conductive film 505 also covers the semiconductor island portion 503 shown with the second gate insulating film 504 interposed therebetween. For example, the conductive film 505 can be composed of a polysilicon (doped polysilicon) film, and impurities for reducing resistance are introduced into the polysilicon film during or after film formation. For example, the polysilicon film can be formed by a known CVD method.

[0278] After forming the conductive film 505, subsequently, the conductive film 505 is patterned to form a second gate electrode 506 and gate electrodes 506g and 506r on the semiconductor island portion 502 shown in Figure 24Q and Figure 2 the figure, and also form gate electrodes 506a and 506s on the semiconductor island portion 503 described in Figure 2 the figure. The conductive film 505 can be patterned by a known photolithography technique and a known anisotropic dry etching technique. In this step, as Figure 24Q and Figure 20 shown, the second gate electrode 506 is formed on the upper surface portion and the side surface portion of the semiconductor island portion 502 with the second gate insulating film 504 interposed therebetween. In addition, the second gate electrode 506 is spaced apart from the first gate electrode 406a in the protruding direction (Z direction) of the semiconductor protrusion 415a, and is also arranged side by side with the first gate electrode 406a. In addition, in this step, the gate electrode 506r is formed to pass through the upper surface portion of the semiconductor island portion 502 with the second gate insulating film 504 interposed therebetween. Although not shown in detail in the figure, similarly to the gate electrode 506 r , in this step, the gate electrode 506 g is formed to pass through the upper surface portion of the semiconductor island portion 502 via the second gate insulating film 504 . In addition, although not shown in detail in the figure, similarly to the gate electrode 506 r, in this step, the gate electrodes 506 a and 506 s are formed to penetrate the upper surface portion of the semiconductor island portion 503 via the second gate insulating film 504 .

[0279] In subsequent steps after forming the second gate electrode 506, etc., Figure 24Q and Figure 20 As shown, main electrode regions 507a, 507b, 507c and 507d each consisting of an n-type semiconductor region are formed in the semiconductor island portion 502, and main electrode regions 508a, 508b and 508c each consisting of an n-type semiconductor region are formed in the semiconductor island portion 503. Each of the main electrode regions 507a, 507b, 507c, and 507d is formed by implanting phosphorus ions or arsenic ions as n-type impurities into the semiconductor island portion 502 using the second gate electrode 506 and the gate electrodes 506g and 506r as an impurity introduction mask. Specifically, the main electrode region 507a is formed in the semiconductor island portion 502, aligned with the second gate electrode 506 and the gate electrode 506r. In addition, the main electrode region 507b is formed in the semiconductor island portion 502, aligned with the gate electrode 506r. In addition, the main electrode region 507c is formed in the semiconductor island portion 502, aligned with the second gate electrode 506 and the gate electrode 506g. In addition, the main electrode region 507d is formed in the semiconductor island portion 502, aligned with the gate electrode 506g. Each of the main electrode regions 508a, 508b, and 508c is formed by introducing, for example, phosphorus ions (P + ) or arsenic ion (As + ) is implanted as an n-type impurity into the semiconductor island portion 503. Specifically, the main electrode region 508a is formed in the semiconductor island portion 503, aligned with the gate electrodes 506a and 506s. In addition, the main electrode region 508b is formed in the semiconductor island portion 503, aligned with the gate electrode 506a. In addition, the main electrode region 508c is formed in the semiconductor island portion 503, aligned with the gate electrode 506s. The ion implantation in the semiconductor island portion 502 and the ion implantation in the semiconductor island portion 503 are performed in the same step.

[0280] This step forms transfer transistor TR4, which includes first gate insulating film 404 and second gate insulating film 504, first gate electrode 406a and second gate electrode 506, photo-electric conversion unit 105d mainly used as a source region and main electrode region 507a used as a drain region, and uses semiconductor protrusion 415a and semiconductor island 502 as channel formation parts. In addition, this step forms charge holding unit 15D which overlaps with light-shielding film 409 in a plan view and is shared by main electrode region 507a. In addition, this step forms reset transistor RST, which includes second gate insulating film 504, gate electrode 506r, and a pair of main electrode regions 507a and 507b respectively used as a source region and a drain region, and uses semiconductor island 502 as a channel formation part. In addition, this step forms discharge transistor OFG, which includes second gate insulating film 504, gate electrode 506g, and a pair of main electrode regions 507c and 507d respectively used as a source region and a drain region, and uses semiconductor island 502 as a channel formation part. In addition, this step forms amplification transistor AMP, which includes second gate insulating film 504, gate electrode 506a, and a pair of main electrode regions 508a and 508b respectively used as a source region and a drain region, and uses semiconductor island 503 as a channel formation part. In addition, this step forms selection transistor SEL, which includes second gate insulating film 504, gate electrode 506s, and a pair of main electrode regions 508c and 508a respectively used as a source region and a drain region, and uses semiconductor island 503 as a channel formation part.

[0281] After forming main electrode regions 507a to 507d and main electrode regions 508a to 508c, subsequently, the Figure 24R shown insulating layer 508 is formed on the entire surface of insulating film 411 on the side opposite to semiconductor base 402. As Figure 24R shown, insulating layer 508 covers semiconductor island 502 and second gate electrode 506 and gate electrode 506r provided in the above semiconductor island 502. Although Figure 24R not shown in the figure, insulating layer 508 also covers Figure 20 the shown gate electrode 506r. In addition, although Figure 24R not shown in the figure, insulating layer 508 covers Figure 20 the shown semiconductor island 503 and gate electrodes 506a and 506s provided in the above semiconductor island 503. For example, the insulating layer 508 is formed by forming a silicon oxide film through CVD, and then reducing the film thickness of the silicon oxide film through CMP and planarizing the upper surface portion of the silicon oxide film. The insulating layer 508 is formed to extend two-dimensionally over a plurality of photoelectric conversion regions 102d.

[0282] After the insulating layer 508 is formed, a light-shielding film 509 that extends two-dimensionally over a plurality of photoelectric conversion regions 102d is subsequently formed on the side of the insulating layer 508 opposite to the semiconductor base portion 402, and then Figure 24R the through holes 510a, 510b, and 510c shown in the figure are formed in the light-shielding film 509. For example, the light-shielding film 509 can be prepared by forming a high-melting-point metal film such as titanium (Ti) or tungsten (W) using a known film-forming technique. The light-shielding film 409 is formed to extend two-dimensionally over a plurality of photoelectric conversion regions 102d and overlaps the semiconductor island portions 502 and 503 in a plan view.

[0283] The through hole 510a is formed at a position that overlaps the through hole 410a provided in the light-shielding film 409 located in the lower layer in a plan view. The through hole 510b is formed at a position that overlaps the distal end of the semiconductor protrusion portion located in the lower layer in a plan view. The through hole 510a is formed at a position that overlaps the through hole 410c provided in the light-shielding film 409 located in the lower layer in a plan view. Each of the through holes 510a, 510b, and 510c reaches the insulating layer 508 that overlaps the light-shielding film 509. The through holes 510a, 510b, and 510c can be formed by a known photolithography technique and a known anisotropic dry etching technique.

[0284] Subsequently, an insulating layer 511 as shown in the figure is provided on the side of the insulating layer 508 opposite to the semiconductor base portion 402. As Figure 24S shown, the insulating layer 511 covers the light-shielding film 509 and fills the inside of each of the through holes 510a to 510c. For example, a silicon oxide film can be formed through CVD, and then the film thickness of the silicon oxide film can be reduced through, for example, CMP, and the upper surface portion of the silicon oxide film can be planarized, so as to prepare the insulating layer 511 on the upper part of the insulating layer 508. The insulating layer 511 is formed in a shape that extends two-dimensionally over a plurality of photoelectric conversion regions 102d. Figure 24S Subsequently, as shown in the figure, through contact electrodes 512a that reach the flat portion of the first gate electrode 406a from the upper surface portion of the side of the insulating layer 511 opposite to the semiconductor base portion 402, through contact electrodes 512b that reach the distal end of the semiconductor protrusion portion 415b from the upper surface portion of the insulating layer 511, and through contact circuits 512c that reach the planarization plate 406b from the upper surface portion of the insulating layer 511 are formed.

[0285] Subsequently, as Figure 24R shown, through contact electrodes 512a that reach the flat portion of the first gate electrode 406a from the upper surface portion of the side of the insulating layer 511 opposite to the semiconductor base portion 402, through contact electrodes 512b that reach the distal end of the semiconductor protrusion portion 415b from the upper surface portion of the insulating layer 511, and through contact circuits 512c that reach the planarization plate 406b from the upper surface portion of the insulating layer 511 are formed. The through-contact electrode 512a can be fabricated by forming a connection hole and then selectively filling the conductive film into the connection hole, which penetrates through the upper surface portion of the insulating layer 511, the through-hole 510a of the light-shielding film 509, the insulating layer 508, the insulating film 411, the through-hole of the light-shielding film 409, the insulating film 408, etc., and reaches the flat portion of the first gate electrode 406a. The through-contact electrode 512b can be fabricated by forming a connection hole and then selectively filling the conductive film into the connection hole, which penetrates through the upper surface portion of the insulating layer 511, the through-hole 510b of the light-shielding film 509, the insulating layer 508, etc., and reaches the distal end of the semiconductor protrusion 415b. The through-contact electrode 512c can be fabricated by forming a connection hole and then selectively filling the conductive film into the connection hole, which penetrates through the upper surface portion of the insulating layer 511, the through-hole 510a of the light-shielding film 509, the insulating layer 508, the insulating film 411, the through-hole 410 of the light-shielding film 409, the insulating film 408, etc., and reaches the flat portion of the planarization plate 406b. For example, the through-contact electrodes 512a, 512b, and 512c can be formed by the same steps. For example, the conductive film filled inside each connection hole can be a high-melting-point metal film such as titanium (Ti), tungsten (W), etc.

[0286] Subsequently, as referred to Figure 21 and Figure 22 It can be understood that a first wiring layer is formed on the upper surface portion of the insulating layer 511 on the side opposite to the semiconductor base portion, and the first wiring layer includes a wiring 513a connected to the through-contact electrode 512a, a wiring 513b connected to the through-contact electrode 512b, and a wiring 513c connected to the through-contact electrode 512c.

[0287] Subsequently, although not shown in detail in the figure, an insulating layer covering the first wiring layer is formed on the side of the insulating layer 511 opposite to the semiconductor base portion 402, and a second wiring layer and an insulating layer covering the second wiring are further formed. This step forms a second substrate 50 including semiconductor island portions 502 and 503, a second gate electrode 506, pixel transistors (AMP, SEL, RST, and OFG), a charge holding unit 15D, etc.

[0288] Subsequently, Figure 20 the third substrate 30 shown is bonded to the second substrate 50 on the side opposite to the semiconductor base portion 402, and then Figure 21 the optical layer 420 shown is formed on the second surface S2 side of the semiconductor base portion 402. This step forms the first substrate 40 including a semiconductor base portion 402, a first gate electrode 406a, a light-shielding film 409, semiconductor protrusions 415a and 415b, etc. In addition, this step substantially completes the solid-state imaging device 1D having a three-dimensional structure including a first substrate, a second substrate, and a third substrate.

[0289] Note that the solid-state imaging device 1D is formed by cutting a semiconductor wafer including the first substrate 40, the second substrate 50, and the third substrate 30 into small pieces Figure 20 into the state of the semiconductor chip 3 shown.

[0290] Note that the polycrystalline layer 414 can be eliminated. In addition, the n-type semiconductor region 104a does not need to be provided.

[0291] <<Main effects of the solid-state imaging device>> Subsequently, the beneficial effects of the solid-state imaging device 1D according to the above fourth embodiment will be described. The solid-state imaging device 1D according to the fourth embodiment of the present invention includes a charge holding unit 15D, which is provided outside the photoelectric conversion region 102d of the semiconductor base portion 402 and holds the signal charge transmitted from the photoelectric conversion unit 105d of the photoelectric conversion region 102d via the transfer transistor TR4. Therefore, similar to the above first embodiment, the solid-state imaging device 1D of the fourth embodiment of the present invention can eliminate (abolish) the floating diffusion region from the photoelectric conversion region 102d. The floating diffusion region provides a conventional FD capacitance and becomes one of the factors preventing the reduction of the size of the photoelectric conversion region 102d. Therefore, the size of the photoelectric conversion region 102d is reduced, that is, the miniaturization of the sensor pixel 12d is achieved. On the contrary, when the planar size of the photoelectric conversion region 102d is fixed, the volume of the photoelectric conversion unit 105d (n-type semiconductor region 104) is allowed to increase. Therefore, the saturation signal amount Qs can be increased.

[0292] In addition, the reduction in the size of the photoelectric conversion region 102d (sensor pixel 12d) achieved thereby can improve the resolution of the solid-state imaging device 1D to be provided.

[0293] In addition, according to the transfer transistor TR4 of the solid-state imaging device 1D of the fourth embodiment of the present invention, each of the first gate electrode 406a and the second gate electrode 506 is arranged outside the photoelectric conversion region 102d of the semiconductor base portion 402. Therefore, in the case of the solid-state imaging device 1D of the fourth embodiment of the present invention, the gate electrode (406a and 506) of the transfer transistor TR4, which is one of the factors preventing the size reduction of the photoelectric conversion region 102d, is not arranged in the photoelectric conversion region 102d. As a result, compared with the above-mentioned first embodiment, further size reduction of the photoelectric conversion region 102d, that is, further miniaturization of the sensor pixel 12d can be achieved. On the contrary, in the case where the planar size of the photoelectric conversion region 102d is fixed, the volume of the photoelectric conversion unit 105d (n-type semiconductor region 104) is allowed to increase. Therefore, the saturation signal amount Qs can be further improved.

[0294] Furthermore, the solid-state imaging device 1D of the fourth embodiment of this invention includes a transfer transistor TR4 having a first gate electrode 406a and a second gate electrode 506. In addition, each of the first gate electrode 406a and the second gate electrode 506 is connected to a bonding interface portion Ja between the semiconductor protrusion 415a and the semiconductor island portion 502. 1 Therefore, during the operation of the transfer transistor TR4, the junction interface portion Ja 1 The interface state at is not easily affected by the electric field. In this case, even when the bonding interface portion Ja 1 When present between the semiconductor protrusion 415a and the semiconductor island portion 502 (i.e., in the charge transfer path where the signal charge moves), the signal charge also smoothly moves from the semiconductor protrusion 415a to the semiconductor island portion 502. Therefore, the solid-state imaging device 1D of the fourth embodiment of this invention can improve the image processing speed while miniaturizing the sensor pixel 12d (photoelectric conversion region 102d).

[0295] Furthermore, according to the solid-state imaging device 1D of the fourth embodiment of the present invention, the light shielding film 409 is provided between the charge holding unit 15D and the photoelectric conversion region 102d. This configuration can reduce the light incident from the second surface S2 side (light incident surface side) of the semiconductor base portion 402, transmitted through the photoelectric conversion region 102d, and applied to the charge holding unit 15D. Therefore, while miniaturization of the sensor pixel 12d (photoelectric conversion region 102d) is achieved, the parasitic light sensitivity characteristic (parasitic light sensitivity (PLS: Parasitic Light Sensitivity) characteristic) can be improved.

[0296] In addition, the solid-state imaging device 1D according to the fourth embodiment of the present disclosure includes a semiconductor protrusion 415a protruding from a semiconductor base portion 402 and a semiconductor island portion 502 joined to the distal end of the semiconductor protrusion 415a thus provided. Further, the solid-state imaging device 1D has a transfer transistor TR4 that uses each of the semiconductor protrusion 415a and the semiconductor island portion 502 as a channel formation portion, and also includes a main electrode region 507a in the semiconductor island portion 502. In addition, the solid-state imaging device 1D has a charge holding unit 15D provided in the semiconductor island portion 502 and shared by the main electrode region 507a. Therefore, the light-shielding film 409 can be easily disposed between the charge holding unit 15D and the photoelectric conversion region 102d.

[0297] In addition, the transfer transistor TR4 according to the fourth embodiment of the present disclosure includes a first gate electrode 406a around the semiconductor protrusion 415a. In this case, by increasing the number of semiconductor protrusions 415a, the amount of signal charge transferred by the transfer transistor TR4 per unit time can be increased. Therefore, the shutter time can be shortened, and thus the frame rate can be increased.

[0298] Further, according to the manufacturing process of the solid-state imaging device 1D according to the fourth embodiment of the present disclosure, first, a first gate electrode 406a is formed around the base protrusion 403a, and then a single crystal layer 413a is formed at the distal end of the base protrusion 403 by epitaxial growth to form the semiconductor protrusion 415a. Thereafter, the semiconductor island portion 502 joined to the distal end of the semiconductor protrusion 415a is formed. Therefore, a sufficient distance in the Z direction can be created between the semiconductor island portion 502 and the first gate electrode 406a.

[0299] [Modification Example of the Fourth Embodiment] According to the above fourth embodiment, as Figure 19 shown, the source region of the discharge transistor OFG is electrically connected to the charge holding unit 15D, the source region of the reset transistor RST, and the gate electrode of the amplification transistor AMP. However, the present technology is not limited to such a configuration of the above fourth embodiment. For example, as Figure 25 shown, the present technology is also applicable to the case where the source region of the discharge transistor OFG is connected between the photoelectric conversion unit 105d (PD) and the transfer transistor TR4. The solid-state imaging device according to Modification Example 1 of the fourth embodiment of the present disclosure also provides beneficial effects similar to those of the solid-state imaging device 1D of the above fourth embodiment. In addition, although the reset transistor RST and the discharge transistor OFG are described as being provided in the semiconductor island portion 502 serving as the third semiconductor portion in the above-described fourth embodiment, such a configuration is not necessarily adopted. For example, the present technology is also applicable to a case where at least one of a plurality of pixel transistors included in the pixel circuit is provided in the semiconductor island portion 502.

[0300] [Fifth Embodiment] The solid-state imaging device 1E according to the fifth embodiment of the present technology has a configuration substantially similar to that of the solid-state imaging device 1D according to the above-described fourth embodiment, but is different from the solid-state imaging device 1D in the following configuration.

[0301] Specifically, the solid-state imaging device 1E according to the fifth embodiment of the present technology includes Figure 26 and Figure 27 the discharge transistor OFG5 shown in place of the Figure 19 and Figure 22 discharge transistor OFG shown in the above-described fourth embodiment. In addition, the solid-state imaging device 1E according to the fifth embodiment of the present technology further includes a semiconductor protrusion portion 415c and a semiconductor island portion 503g. The semiconductor protrusion portion 415c protrudes from the semiconductor base portion 402 toward the first surface S1 side of the semiconductor base portion 402 and serves as a fourth semiconductor portion. The semiconductor island portion 503g overlaps the semiconductor protrusion portion 415c in a plan view. A part of the back surface of the semiconductor island portion 503g on the side of the semiconductor protrusion portion 415c is joined to the distal end of the semiconductor protrusion portion 415c. The semiconductor protrusion portion 415c is arranged adjacent to the semiconductor protrusion portion 415a and is provided for each photoelectric conversion region 102d together with the semiconductor protrusion portion 415a.

[0302] As Figure 26 shown, the discharge transistor OFG5 is connected between the photoelectric conversion unit 105d and the transfer transistor TR4. In addition, as Figure 26 and Figure 27 shown, similar to the transfer transistor TR4, the discharge transistor OFG5 is provided so as to pass through the first substrate 40 and the second substrate 50.

[0303] As Figure 27As shown, the drain transistor OFG5 includes a gate electrode 406c adjacent to the semiconductor protrusion 415c with a first gate insulating film 404 interposed therebetween and extending in the protruding direction (Z direction) of the semiconductor protrusion 415c, a photoelectric conversion unit 105d mainly serving as a source region, and a main electrode region 508g provided in the semiconductor island portion 503g and mainly serving as a drain region. For example, the main electrode region 508g includes an n-type semiconductor region with an impurity concentration higher than that of the n-type semiconductor region 104. Therefore, the drain transistor OFG5 is provided in the semiconductor protrusion 415c serving as the fourth semiconductor portion.

[0304] As Figure 27 shown, similar to the semiconductor protrusion 415a, the semiconductor protrusion 415c includes a p-type substrate protrusion 403c integrally formed with the semiconductor substrate portion 402 and a p-type single crystal layer 413c selectively formed by epitaxial growth at the distal end of the p-type substrate protrusion 403c.

[0305] The semiconductor substrate portion 402 and the substrate protrusion 403c have an integral structure in which there is no interface portion between the semiconductor substrate portion 402 and the substrate protrusion 403c. In addition, although there is no interface portion between the substrate protrusion 403c and the single crystal layer 413c, for the sake of convenience of explanation, similar to the semiconductor protrusion 415a, the substrate protrusions 403a and 403b are separately shown from the single crystal layers 413a and 413b in the figure.

[0306] For example, in a plan view, the gate electrode 406a surrounds the outer periphery of the semiconductor protrusion 415a. In addition, the gate electrode 406c, the gate electrode 406a, and the planarization plate 406b are adjacent to each other with an insulating film 408 interposed therebetween in the plan view to be electrically and mechanically isolated from each other. In addition, the gate electrode 406c is electrically insulated from the light-shielding film 409 with the insulating film 408 interposed therebetween.

[0307] As Figure 27 shown, the wiring 513d is electrically connected to the gate electrode 206c via a through-contact electrode 512d that extends through the first substrate 40 and the second substrate 50 in the thickness direction (Z direction) of each of the first substrate 40 and the second substrate 50. In addition, the wiring 513e is electrically connected to the semiconductor island portion 503g via a through-contact electrode 512e that extends in the thickness direction (Z direction) of the second substrate 50.

[0308] The through-contact electrode 512d penetrates through the upper surface portion of the insulating layer 511 on the side opposite to the semiconductor base portion 402, through the through-hole 510a of the insulating layer 511, the light-shielding film 509, the insulating layer 508, the insulating film 411, the through-hole 410a of the light-shielding film 409, the insulating film 408, etc., and reaches the gate electrode 406c. In addition, the through-contact electrode 512c is electrically insulated from the light-shielding film 509 by the insulating layer 511 provided in the through-hole 510d of the light-shielding film 509. In addition, the through-contact electrode 512d is electrically insulated from the light-shielding film 409 by the insulating film 411 provided in the through-hole 410d of the light-shielding film 409.

[0309] The through-contact electrode 512e penetrates through the upper surface portion of the insulating layer 511, through the through-hole 510b of the insulating layer 511, the light-shielding film 509, the insulating layer 508, etc., and reaches the semiconductor island portion 503g. In addition, the through-contact electrode 512e is electrically insulated from the light-shielding film 509 by the insulating layer 511 provided in the through-hole 510e of the light-shielding film 509.

[0310] The solid-state imaging device 1E according to the fifth embodiment of the present invention also provides beneficial effects similar to those of the solid-state imaging device 1D of the above fourth embodiment.

[0311] Note that, similar to the above, for ease of understanding of the figure, Figure 27 the hatching indicating the cross-section is partially omitted. In addition, although the solid-state imaging devices including pixel circuits including the discharge transistor OFG have been described in each of the above fourth and fifth embodiments, the present technology is also applicable to solid-state imaging devices including pixel circuits not including the discharge transistor OFG.

[0312] [Sixth Embodiment] [[Application Example of Electronic Device]] The present technology (technology according to the present disclosure) is applicable to various types of electronic devices, such as imaging devices such as digital cameras and digital video cameras, mobile phones having an imaging function, and other types of devices having an imaging function.

[0313] Figure 28 FIG. is a schematic configuration diagram showing an electronic device (for example, a camera) according to the sixth embodiment of the present technology.

[0314] As Figure 28 shown, the electronic device 600 includes a solid-state imaging device 601, an optical lens 602, a shutter device 603, a drive circuit 604, and a signal processing circuit 605. Here, the electronic device 600 is an electronic device (for example, a camera) according to an embodiment including any one of the solid-state imaging devices 1A to 1E according to the first to fifth embodiments of the present technology as the solid-state imaging device 601.

[0315] The optical lens 602 forms an image of the image light (incident light 606) from the subject on the imaging surface of the solid-state imaging device 601. As a result, signal charges are accumulated in the solid-state imaging device 601 for a fixed period. The shutter device 603 controls the light irradiation period and the light shielding period of the solid-state imaging device 601. The drive circuit 604 provides drive signals for controlling the transfer operation of the solid-state imaging device 601 and the shutter operation of the shutter device 603. The signal transfer of the solid-state imaging device 601 is performed according to the drive signals (timing signals) provided from the drive circuit 604. The signal processing circuit 605 performs various types of signal processing on the signals (pixel signals (image signals)) output from the solid-state imaging device 601. The video signal after signal processing is stored in a storage medium such as a memory or output to a monitor.

[0316] The electronic device 600 according to the sixth embodiment configured as described above includes the solid-state imaging device 601 equipped with the miniaturized sensor pixels 12 or 12d. Therefore, the image quality of the electronic device 600 can be improved.

[0317] Note that the electronic device 600 of the solid-state imaging device to which the above embodiment can be applied is not limited to a camera, but can be other types of electronic devices. For example, the electronic device 600 can be applied to imaging devices such as camera modules for mobile phones, tablet terminals, or other mobile devices.

[0318] In addition, the present technology is generally applicable to optical detection devices, such as a distance measurement sensor called a time-of-flight (ToF: Time of Flight) sensor that measures distance and a solid-state imaging device that constitutes an image sensor as described above. The distance measurement sensor is a sensor that emits irradiation light toward an object, detects the reflected light that is reflected from the surface of the object and returns from the surface of the object, and calculates the distance to the object based on the time of flight from the emission of the irradiation light to the reception of the reflected light. The structure of the above element isolation region can be used as the structure of the element isolation region of the distance measurement sensor.

[0319] It should be noted that the present technology can also have the following configuration. (1) An optical detection device, comprising: A semiconductor layer having a first surface and a second surface located on opposite sides of each other and having a photoelectric conversion region divided by an isolation region; A photoelectric conversion unit provided in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the semiconductor layer into signal charges; A transfer transistor having a gate electrode disposed in the photoelectric conversion region with a gate insulating film interposed therebetween and extending in the thickness direction of the semiconductor layer, and transferring signal charges photoelectrically converted by the photoelectric conversion unit; and A charge holding unit disposed outside the photoelectric conversion region and holding the signal charges transferred from the transfer transistor, wherein the charge holding unit includes a floating contact electrode connected to the photoelectric conversion region. (2) The optical detection device according to (1) above, wherein the contact electrode includes a semiconductor, and the impurity concentration on the side opposite to the photoelectric conversion region side of the semiconductor is higher than that on the photoelectric conversion region side. (3) The optical detection device according to (2) above, wherein the semiconductor includes a single crystal. (4) The optical detection device according to any one of (1) to (3) above, wherein the width of the contact electrode on the side opposite to the photoelectric conversion region side is greater than the width on the photoelectric conversion region side. (5) The optical detection device according to any one of (1) to (4) above, wherein the gate electrode of the transfer transistor includes at least one side adjacent to the contact electrode in a plan view. (6) The optical detection device according to any one of (1) to (5) above, wherein the gate electrode protrudes upward from the first semiconductor layer. (7) The optical detection device according to any one of (1) to (6) above, wherein in a plan view, the contact electrode is provided for each of a plurality of photoelectric conversion regions adjacent to each other across the isolation region. (8) The optical detection device according to any one of (1) to (7) above, wherein the contact electrode is shared by a plurality of photoelectric conversion regions adjacent to each other across the isolation region in a plan view. (9) Regarding the semiconductor layer as the first semiconductor layer, the optical detection device further includes: A second semiconductor layer disposed on the first surface side of the first semiconductor layer and separated from the first semiconductor layer, wherein, The charge holding unit further includes a floating diffusion region provided in the second semiconductor layer and electrically connected to the floating contact electrode. (10) The optical detection device according to (9) above, wherein the floating diffusion region is provided in a surface layer portion of an element formation surface on a side of the second semiconductor layer opposite to the first semiconductor layer side, and the floating contact electrode penetrates the second semiconductor layer and is electrically connected to the charge holding unit through a wiring provided on the element formation surface side of the second semiconductor layer. (11) The optical detection device according to any one of (1) to (10) above further includes: a pixel circuit that converts signal charges held in the charge holding unit into pixel signals and outputs the pixel signals. (12) An optical detection device, comprising: a first semiconductor portion having a first surface and a second surface located on opposite sides of each other and having a photoelectric conversion region; a second semiconductor portion protruding from the first semiconductor portion toward the first surface side; a third semiconductor portion provided on the first surface side of the first semiconductor portion and joined to a distal end of the second semiconductor portion; a photoelectric conversion unit provided in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the first semiconductor portion into signal charges; a charge holding unit provided in the third semiconductor portion; and a transfer transistor that transfers signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit, wherein the transfer transistor includes: a first gate electrode adjacent to the second semiconductor portion with a first gate insulating film interposed therebetween and extending in a protruding direction of the second semiconductor portion, and a second gate electrode arranged side by side with the first gate electrode and spaced apart from the first gate electrode in the protruding direction of the second semiconductor portion and adjacent to the third semiconductor portion with a second gate insulating film interposed therebetween. (13) The optical detection device according to (12) above, wherein each of the first gate electrode and the second gate electrode is spaced apart from a bonding interface portion between the second semiconductor portion and the third semiconductor portion. (14) The optical detection device according to (12) or (13) above, wherein, in a plan view, the first gate electrode surrounds the outer periphery of the second semiconductor portion with the first gate insulating film interposed therebetween. (15) The optical detection device according to any one of (12) to (14) above, wherein the second gate electrode extends on the upper surface portion and the side surface portion of the third semiconductor portion with the second gate insulating film interposed therebetween. (16) The optical detection device according to any one of (12) to (15) above, wherein the charge holding unit includes a semiconductor region provided in the third semiconductor portion in alignment with the second gate electrode. (17) The optical detection device according to any one of (12) to (16) above, wherein a light shielding film is provided between the charge holding unit and the photoelectric conversion region. (18) The optical detection device according to any one of (12) to (17) above, further comprising: a pixel circuit that converts signal charges photoelectrically converted by the photoelectric conversion unit into pixel signals, wherein at least one pixel transistor included in the pixel circuit is provided in the third semiconductor portion. (19) The optical detection device according to any one of (12) to (18) above, further comprising: a fourth semiconductor portion that protrudes from the first semiconductor portion toward the first surface side; and a pixel circuit that converts signal charges photoelectrically converted by the photoelectric conversion unit into pixel signals, wherein the discharge transistor included in the pixel circuit is provided in the fourth semiconductor portion. (20) An electronic device, comprising: an optical detection device; an optical lens that forms an image of image light received from a subject on an imaging surface of the optical detection device; and a signal processing circuit that performs signal processing on a signal output from the optical detection device, wherein the optical detection device includes: a semiconductor layer having a first surface and a second surface located on opposite sides of each other and having a photoelectric conversion region divided by an isolation region, a photoelectric conversion unit that is provided in the photoelectric conversion region and photoelectrically converts light incident from the second surface side of the semiconductor layer into signal charges, A transfer transistor having a gate electrode disposed in the photoelectric conversion region with a gate insulating film interposed therebetween and extending in the thickness direction of the semiconductor layer, and transferring signal charges photoelectrically converted by the photoelectric conversion unit, and a charge holding unit disposed outside the first surface of the semiconductor layer and holding the signal charges transferred from the transfer transistor, and the charge holding unit includes a floating contact electrode connected to the photoelectric conversion region. (21) An electronic device, comprising: an optical detection device; an optical lens that forms an image of image light received from a subject on an imaging surface of the optical detection device; and a signal processing circuit that performs signal processing on a signal output from the optical detection device, wherein, the optical detection device includes: a first semiconductor portion having a first surface and a second surface located on opposite sides of each other and having a photoelectric conversion region, a second semiconductor portion protruding from the first semiconductor portion toward the first surface side, a third semiconductor portion disposed on the first surface side of the first semiconductor portion and joined to a distal end of the second semiconductor portion, a photoelectric conversion unit disposed in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the first semiconductor portion into signal charges, a charge holding unit disposed in the third semiconductor portion, and a transfer transistor that transfers the signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit, and the transfer transistor includes: a first gate electrode adjacent to the second semiconductor portion with a first gate insulating film interposed therebetween and extending in the protruding direction of the second semiconductor portion, and a second gate electrode disposed side by side with the first gate electrode and spaced apart from the first gate electrode in the protruding direction of the second semiconductor portion, and adjacent to the third semiconductor portion with a second gate insulating film interposed therebetween.

[0320] The scope of the present technology is not limited to the illustrated and described exemplary embodiments, but includes all embodiments that provide equivalent beneficial effects corresponding to the object of the present technology. In addition, the scope of the present technology is not limited to the combination of features of the present invention defined by the claims, but may be defined by any desired combination of specific features included in all the disclosed features. [List of Reference Numerals]

[0321] 1A, 1B, 1C, 1D: Solid-state imaging device 2, 3: Semiconductor chip 2A: Pixel array section 2B: Peripheral section 10: First substrate 12, 12d: Sensor pixel 14: Bonding pad 15, 15B, 15C, 15D: Charge holding unit 22, 22d: Pixel circuit (readout circuit) 20: Second substrate 30: Third substrate 101: Semiconductor layer 102, 102D: Photoelectric conversion region 103: p-type well region, 103a: p-type semiconductor region 104, 104a: n-type semiconductor region 105, 105d: Photoelectric conversion unit 106: Isolation region 110: Gate trench portion 111: Insulating film 112: Gate insulating film 113: Gate electrode 120: Multilayer wiring layer 121: Contact electrode 122: Wiring 201: Semiconductor layer 202: p-type well region 203: Element isolation region (field isolation region) 204: Gate insulating film 205a, 205r, 205s: Gate electrode 206: Floating diffusion region 207: Insulating film 208: Floating contact electrode (floating contact electrode) 210: Multilayer wiring layer 211a, 211b: Contact electrode 212: Wiring 212a: First part 212b: Second part 212c: Third part 213: Conductive path 215: Bonding metal pad 219: Bonding film 301: Semiconductor layer 310: Multilayer wiring layer 314, 316: Wiring 315: Bonding metal pad 401: Semiconductor layer 402: Semiconductor base part (first semiconductor part) 403a, 403b: Substrate protrusion 404: First gate insulating film 405: Conductive film 406a: First gate electrode 406b: Planarization plate 408: Insulating film 409: Light-shielding film 410a, 410c: Through hole 411: Insulating film 412a, 412b: Opening 413a, 413b: Single crystal layer 414: Polycrystalline layer 415a: Semiconductor protrusion (second semiconductor part) 415b: Semiconductor protrusion 420: Optical layer 501: Semiconductor layer 502: Semiconductor island part (third semiconductor part) 503: Semiconductor island part 504: Gate insulating film 505: Conductive film 506: Second gate electrode 506a, 506g, 506r, 506s: Gate electrode 508: Insulating layer 509: Light-shielding film 510a, 510b, 510c, 510d, 510e: Through hole 511: Insulating layer 512a, 512b, 512c, 512d, 512e: Through contact electrode 513a, 513b, 513c, 513d, 513e: Wiring PU1, PU2, PU3, PU4: Sensor pixel unit S1: First surface S2: Second surface AMP: Amplifying transistor OFG: Drain transistor RST: Reset transistor SEL: Selection transistor

Claims

1. An optical detection device, comprising: a semiconductor layer having a first surface and a second surface on opposite sides of each other, and having a photoelectric conversion region divided by an isolation region; a photoelectric conversion unit disposed in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the semiconductor layer into signal charges; a transfer transistor having a gate electrode disposed in the photoelectric conversion region with a gate insulating film interposed therebetween and extending in the thickness direction of the semiconductor layer, and transferring the signal charges photoelectrically converted by the photoelectric conversion unit; and a charge holding unit disposed outside the photoelectric conversion region and holding the signal charges transferred from the transfer transistor, wherein the charge holding unit includes a floating contact electrode connected to the photoelectric conversion region.

2. The optical detection device according to claim 1, wherein the contact electrode includes a semiconductor, and an impurity concentration of the semiconductor on a side opposite to the photoelectric conversion region side is higher than that on the photoelectric conversion region side.

3. The optical detection device according to claim 2, wherein the semiconductor includes a single crystal.

4. The optical detection device according to claim 1, wherein a width of the contact electrode on a side opposite to the photoelectric conversion region side is greater than a width on the photoelectric conversion region side.

5. The optical detection device according to claim 1, wherein the gate electrode of the transfer transistor includes at least one side adjacent to the contact electrode in a plan view.

6. The optical detection device according to claim 1, wherein the gate electrode protrudes upward from the first semiconductor layer.

7. The optical detection device according to claim 1, wherein in a plan view, the contact electrode is provided for each of a plurality of the photoelectric conversion regions adjacent to each other across the isolation region.

8. The optical detection device according to claim 1, wherein the contact electrode is shared by a plurality of the photoelectric conversion regions adjacent to each other across the isolation region in a plan view.

9. Regarding the optical detection device with the semiconductor layer as the first semiconductor layer, the optical detection device further comprises: a second semiconductor layer disposed on the first surface side of the first semiconductor layer and spaced apart from the first semiconductor layer, wherein the charge holding unit further includes a floating diffusion region disposed in the second semiconductor layer and electrically connected to the floating contact electrode.

10. The optical detection device according to claim 9, wherein the floating diffusion region is disposed in a surface layer portion of an element formation surface of the second semiconductor layer on a side opposite to the first semiconductor layer side, and the floating contact electrode penetrates the second semiconductor layer and is electrically connected to the charge holding unit through a wiring disposed on the element formation surface side of the second semiconductor layer.

11. The optical detection device according to claim 1, further comprises: a pixel circuit that converts the signal charges held in the charge holding unit into pixel signals and outputs the pixel signals.

12. An optical detection device, Comprising: A first semiconductor portion having a first surface and a second surface located on opposite sides of each other and having a photoelectric conversion region; A second semiconductor portion protruding from the first semiconductor portion toward the first surface side; A third semiconductor portion provided on the first surface side of the first semiconductor portion and joined to a distal end of the second semiconductor portion; A photoelectric conversion unit provided in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the first semiconductor portion into signal charges; A charge holding unit provided in the third semiconductor portion; And A transfer transistor that transfers the signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit, wherein The transfer transistor includes: A first gate electrode adjacent to the second semiconductor portion with a first gate insulating film interposed therebetween and extending in a protruding direction of the second semiconductor portion, and A second gate electrode arranged side by side with the first gate electrode and spaced apart from the first gate electrode in the protruding direction of the second semiconductor portion, and adjacent to the third semiconductor portion with a second gate insulating film interposed therebetween.

13. The optical detection device according to claim 12, Wherein, Each of the first gate electrode and the second gate electrode is spaced apart from a bonding interface portion between the second semiconductor portion and the third semiconductor portion.

14. The optical detection device according to claim 12, Wherein, In a plan view, the first gate electrode surrounds an outer periphery of the second semiconductor portion with the first gate insulating film interposed therebetween.

15. The optical detection device according to claim 12, Wherein, The second gate electrode extends on an upper surface portion and a side surface portion of the third semiconductor portion with the second gate insulating film interposed therebetween.

16. The optical detection device according to claim 12, Wherein, The charge holding unit includes a semiconductor region provided in the third semiconductor portion in alignment with the second gate electrode.

17. The optical detection device according to claim 12, Wherein, A light-shielding film is provided between the charge holding unit and the photoelectric conversion region.

18. The optical detection device according to claim 12, further Comprising: A pixel circuit that converts the signal charges photoelectrically converted by the photoelectric conversion unit into pixel signals, wherein At least one pixel transistor included in the pixel circuit is provided in the third semiconductor portion.

19. The optical detection device according to claim 12, further Comprising: A fourth semiconductor portion protruding from the first semiconductor portion toward the first surface side; And A pixel circuit that converts the signal charges photoelectrically converted by the photoelectric conversion unit into pixel signals, wherein An ejecting transistor included in the pixel circuit is provided in the fourth semiconductor portion.

20. An electronic device, Comprising: An optical detection device; An optical lens that forms an image of image light received from a subject on an imaging surface of the optical detection device; And A signal processing circuit that performs signal processing on a signal output from the optical detection device, wherein The optical detection device includes: A semiconductor layer having a first surface and a second surface located on opposite sides of each other, and having a photoelectric conversion region divided by isolation regions, A photoelectric conversion unit provided in the photoelectric conversion region and photoelectrically converting light incident from the second surface side of the semiconductor layer into signal charges, A transfer transistor having a gate electrode provided in the photoelectric conversion region with a gate insulating film interposed therebetween and extending in the thickness direction of the semiconductor layer, and transferring the signal charges photoelectrically converted by the photoelectric conversion unit, and A charge holding unit provided outside the first surface of the semiconductor layer and holding the signal charges transferred from the transfer transistor, and The charge holding unit includes a floating contact electrode connected to the photoelectric conversion region.

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