Power detector and method for operating a power detector

Abstract

Described herein is a power detector (100) comprising: a transformer (L1, L2) configured to sense a current (Iload) of a load (Zload) and to provide an image current (Isense) of the current (Iload); a first multiplier (10) configured to perform a multiplication of the image current (I sense) and a sign of a voltage (V load) of a load (Z load) and feed a result of the multiplication to a filter (11) configured to provide a DC signal; a peak voltage detector (50) configured to determine a peak value (S2) of the voltage (Vload); a second multiplier (40) configured to perform a linear multiplication of an output (S1) of the filter with a peak value; and a bias circuit (20) configured to provide a bias signal for the first multiplier, where the bias signal is substantially independent of the temperature and / or process of the first multiplier.

Description

Technical Field

[0001] The present disclosure relates to a power detector. Furthermore, the present invention relates to a method for operating a power detector. Background Art

[0002] In conventional electrical power detector implementations, a linear multiplication (current and voltage) of the RF signal is performed. The multiplier that performs this multiplication needs to remain linear regardless of the PVT conditions in order to have accurate power measurements. Maintaining multiplier linearity in PVT requires large and complex bias circuits. In addition, the bias circuit output must be variable with the condition PVT in order to keep the multiplier in its linear region. In addition, a variable attenuator is required to cover the power range to be measured in order to keep the multiplier in its linear region. If all these conditions are not met, the power measurement will suffer from a lack of accuracy and will be unavailable. Classical power detector implementations suffer from limited accuracy in PVT and when changing the voltage standing wave ratio (VSWR).

[0003] V. Qunaj and P. Reynaert, “An E-band Fully-Integrated True Power Detector in 28nm CMOS,” KU Leuven, Belgium, 2019 IEEE Radio Frequency Integrated Circuit Conference (RFIC), discloses the design of a power amplifier with a low-power fully-integrated E-band true power detector in 28nm CMOS technology.

[0004] US 10,082,528 B2 discloses a power detector including a voltage sensor configured to detect a voltage of a load and a current sensor configured to detect a current of the load.

[0005] The power detector also includes circuitry configured to introduce a phase delay between a detected voltage of the load and a detected current of the load, thereby producing a voltage measurement and a current measurement. The circuitry is further configured to multiply the voltage measurement and the current measurement.

[0006] US 9,686,024 B2 discloses a real radio frequency (RF) power detector that detects real power provided by a power amplifier of an RF transmitter. The power detector may include a plurality of voltage detectors that determine one or more voltages of a power amplifier included in the RF transmitter and / or a transformer included in the RF transmitter. At least one of the voltage detectors may be coupled to a sensing inductor that senses one or more magnetic fields emitted by the transformer. Summary of the invention

[0007] An object of the present invention is to provide an improved electrical power detector.

[0008] According to a first aspect, the present disclosure provides a power detector, the power detector comprising:

[0009] - a transformer configured to sense a current of a load and to provide an image current of said current;

[0010] a first multiplier configured to perform a multiplication of the image current and the sign of the voltage of the load and to feed the result of the multiplication to a filter configured to provide a DC signal;

[0011] - a peak voltage detector configured to determine a peak value of said voltage;

[0012] - a second multiplier configured to perform a linear multiplication of the output of the filter and the peak value; and

[0013] - a bias circuit configured to provide a bias signal to the first multiplier, wherein the bias signal is substantially independent of temperature and / or process of the first multiplier.

[0014] In this way, the bias circuit can be implemented more easily than in the prior art. This is due to the fact that the first multiplier is implemented as a nonlinear hard-switched mixer, which means that there is no need to compensate for the nonlinearity of the multiplier. The second multiplier multiplies two DC signals, so the second multiplier can be implemented more easily than in the prior art. As a result, the proposed power detector is implementable in terms of current and semiconductor area saving. The proposed power detector provides an improved trade-off between accuracy and area.

[0015] According to another aspect, the present disclosure provides a method for operating a power detector, the method comprising the following steps:

[0016] - sensing the current of the load and providing an image current of the current;

[0017] - performing a multiplication of the image current and the sign of the voltage of the load;

[0018] - feeding the result of the multiplication to a filter, the filter being configured to provide a DC signal;

[0019] - determining the peak value of said voltage;

[0020] - performing a linear multiplication of the output of the filter and the peak value; and

[0021] - providing a bias signal for the first multiplier during the measurement of the electrical power of the load, wherein the bias signal is substantially independent of the temperature and / or process of the first multiplier.

[0022] In one or more embodiments, the output signal of the filter represents the image current multiplied by the cosine of the phase difference between the load current and the load voltage.

[0023] In one or more embodiments, the bias circuit is one of: a constant current source, a bandgap voltage source.

[0024] In one or more embodiments, the power detector further comprises an attenuator configured to adapt the operating range of the first multiplier. In this way, the presence of the attenuator depends on the range of the established measurement. If the power is too large and cannot prevent damage to the components of the first multiplier, then an attenuator may be required.

[0025] According to one or more embodiments, the attenuator is programmable.

[0026] According to one or more embodiments, the second multiplier is a digital multiplier. Due to the static input signal to the second multiplier, a linear multiplication of the outputs of the peak voltage detector and the filter is performed in the digital world.

[0027] According to one or more embodiments, the second multiplier is an analog multiplier.

[0028] According to one or more embodiments, the bias circuit and the attenuator are implemented in a single component.

[0029] According to one or more embodiments, the first multiplier corresponds to a Heaviside function of the voltage rather than a sign function. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Various exemplary embodiments may be more fully understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

[0031] Figure 1 A block diagram showing a conventional power detector;

[0032] Figure 2 A block diagram of another conventional power detector is shown;

[0033] Figure 3 A block diagram showing an embodiment of the proposed power detector;

[0034] Figure 4 A block diagram showing another embodiment of the proposed power detector;

[0035] Figure 5A block diagram showing another embodiment of the proposed power detector; and

[0036] Figure 6 is a diagram showing the flow of the proposed method of operating a power detector.

[0037] The above discussion / overview is not intended to describe every embodiment or every implementation of the present disclosure. The following figures and detailed description also illustrate various embodiments. The aspects as defined above and further aspects of the present disclosure are apparent from the examples of embodiments to be described below with reference to the accompanying drawings, which are explained with reference to the examples of embodiments. Needless to say, the present disclosure is not limited to the examples of embodiments.

[0038] All illustrations in the drawings are schematic. It should be noted that in different drawings, similar or identical elements or features have the same reference numerals or have reference numerals that differ from the corresponding reference numerals only within the first digit. In order to avoid unnecessary repetition, elements or features that have been explained with respect to previously described embodiments are not explained again at a later point in the description. DETAILED DESCRIPTION

[0039] Figure 1 Shown for measuring load Z 负载 The block diagram of a conventional electric power detector 100 for measuring electric power. Basically, the current I 负载 Image current I 感测 With load Z 负载 The voltage V 负载 The power is measured by multiplying the voltage V 负载 is sensed by the attenuator 30 and fed to the first multiplier 10. It will be appreciated that a transformer having two inductors L1, L2 (with a transfer factor k) senses the image current I fed to the first multiplier 10. 感测 The first multiplier 10 performs the image current I 感测 With voltage V 负载 That is, the first multiplier 10 performs linear multiplication of the RF signal.

[0040] For this purpose, the first multiplier 10 needs to be biased by means of a bias signal from a bias circuit 20 in order to keep the operating characteristics of the first multiplier 10 as linear as possible. In addition, an attenuator 30 is provided, which adjusts the suitable operating range of the first multiplier 10. The output of the first multiplier 10 is filtered by a filter 11 in order to provide a DC signal. The DC signal is the load Z 负载 Image of the electric power P.

[0041] Since the value of the output of the first multiplier 10 is important, it is important that the first multiplier 10 has a linear characteristic. The attenuator 30 is required because the measurement load Z 负载 , so as to keep the input of the first multiplier 10 fairly constant within a given power range. This is indicated by the sub-graph near the attenuator 30, which shows an exemplary attenuation step of a programmable step attenuator with power.

[0042] The bias circuit 20 needs to follow the behavior of the first multiplier 10 in terms of temperature and process in order to keep the first multiplier 10 in its linear region, which is indicated in two exemplary sub-figures close to the bias circuit 20. The bias circuit 20 can be, for example, a current source or a voltage regulator. The linear first multiplier 10 is implemented in an analog manner using transistors, and the transfer function of the first multiplier 10 is not linear in temperature and process, so when the temperature and / or process changes, the output of the first multiplier 10 does not exactly represent the multiplication of the two inputs. The bias circuit 20 needs to be accurate in order to keep the linear first multiplier 10 in its linear region, which requires a large semiconductor area. In addition, the bias circuit 20 requires an output signal that is variable with respect to PVT, which can lead to a rather complex implementation of the bias circuit 20.

[0043] The following method can be used to perform the load Z at the frequency ω / 2p 负载 The RMS power P 负载 Measurements:

[0044] V 负载 (t) = V L sin(ωt)

[0045]

[0046]

[0047] The parameters are:

[0048] V L ...peak value of load voltage

[0049] I L ...peak value of load current

[0050] …the phase between the load voltage and the load current

[0051] By using I 负载 and V 负载 Multiply linearly and use the DC term of the multiplied signal to estimate the RMS power P 负载 :

[0052] m(t)=V 负载(t)·I 负载 (t)

[0053]

[0054] This method requires an analog RF multiplier 10 that performs a linear time multiplication between two RF signals. This multiplier is difficult to implement over a wide range of P 负载 and implemented over process, voltage and temperature variations (PVT).

[0055] Figure 2 Detail of a conventional implementation of a power detector using a voltage peak detector 50 is shown. In practice, this represents an example of a power detector implemented only by the peak detector 50. 负载 The peak voltage detector 50 can also be used to measure the RMS power when the impedance of the input voltage is well known (for example, fixed at 50 ohms). The output signal of the peak voltage detector 50 is 负载 is proportional and fed to an ADC 51 which outputs a signal representing the power P.

[0056] At the load impedance Z 负载 In the case of a purely resistive (e.g., 50 ohms), the voltage V from the peak voltage detector 50 is calculated as follows: 负载 Information to get RMS power:

[0057]

[0058] In this case, the voltage V 负载 With current I 负载 In phase, this produces a pure voltage detector. However, a problem in this case may be that if the load impedance changes, the power measured by the peak voltage detector 50 alone is no longer accurate.

[0059] Figure 3 is a block diagram of a first embodiment of the proposed power detector 100. It should be appreciated that a transformer having two inductors L1, L2 (with an emission factor k) provides a current I 负载 Image I 感测 and bias circuit 20. Figure 1 Unlike the conventional arrangement shown in FIG. , the first multiplier 10 uses the image current I 感测 , and in addition use the current I 负载 With voltage V 负载 The phase relationship between ). Cosine is the load Z 负载 The current I 负载 With voltage V 负载The first multiplier performs the image current I 感测 The first multiplier 10 is implemented as a nonlinear hard-switching mixer, which means that the mixer does not perform a multiplication of the two inputs, but in fact one of its inputs has a very high amplitude in order to perform a switching operation and it is essentially nonlinear.

[0060] In practice, the first multiplier 10 has a nonlinear transfer function, which means that the first multiplier 10 acts as a limiter. As a result, the first multiplier 10 acts as a hard-switching mixer. Only the input signal (V 输出 ) so that the phase relationship of the input signals is known. At the output of the first multiplier 10, a signal is provided, wherein this signal represents the current I 感测 The image with the output voltage V 输出 The phase multiplication of .

[0061] The attenuator 30 may be optional, depending on the range to be detected, in order to protect the components of the first multiplier 10 from damage. In the case where the output of the first multiplier 10 is not too strong, the attenuator 30 is not required. The output S1 of the filter 11 removes the high frequency components of the output signal of the first multiplier, leaving only the DC component. Its output signal S1 represents the current I 感测 The image is multiplied by the load current (I 负载 ) and load voltage (V 输出 ) is the cosine of the phase difference between them.

[0062] In addition to the load current and the phase information between the load current and the load voltage, information about the load voltage amplitude is also required. For this purpose, a peak voltage detector 50 is used, which is easier to implement than a power detector. The output signal S2 of the maximum peak detector 50 represents the voltage V 负载 The signals S1 and S2 are both DC signals, so they can be multiplied by the linear multiplier 40 via analog or digital linear multiplication.

[0063] It should be appreciated that the bias circuit 20 is functionally connected to the first multiplier 10 and the bias signal diagram, wherein the bias signal is substantially independent of process and temperature. This allows the bias circuit 20 to be implemented much easier. For example, the bias circuit 20 can be implemented as a constant current source, a bandgap voltage source, etc.

[0064] In case the operating range has to be adjusted for the first multiplier 10, an optional attenuator 30 is provided. Alternatively, the bias circuit 20 and the attenuation circuit 50 may be implemented in one single element. Furthermore, the attenuator 30 may be implemented as a programmable unit.

[0065] As a result, in the proposed power detector 100, as in Figure 1 The linear multiplication of the two RF signals performed in the arrangement of is replaced by two multipliers 10, 40 and a voltage peak detector 50. This means that a hard-switched RF multiplier is provided to retrieve the phase relationship between the RF current and the voltage of the load together with a linear second multiplier 40, the input signals S1, S2 of which are DC signals. As a result, a much more relaxed bias circuit 20 for the RF multiplier 10 can be implemented, since it is no longer necessary to operate in the linear region. For the same power range to be covered, the attenuator 30 can be simpler and even removed. The linear multiplication of the second multiplier 40 is performed between DC signals, which is easier to implement and can be done digitally (after ADC conversion) or in analog.

[0066] By I 负载 Multiply by V 负载 The sign of the multiplication, take the DC value, and multiply this DC value by V in the following way 负载 The peak value can achieve the same result:

[0067]

[0068] Where m DC is the DC part of the output of the filter 11 (signal S1), and the factor 4 / π can be easily removed. 峰值 represents the peak value of the voltage determined by the peak voltage detector 50 .

[0069] …scaling factor, which takes into account the relationship between the sine wave and the square wave

[0070] In the proposed power detector 100, the hard-switched mixer of the first multiplier 10 may correspond to V 负载 is a Heaviside function rather than a sign function, so a factor of two must be applied.

[0071] The advantage of the proposed power detector 100 and the power detection method it performs is that the required linear multiplication is now applied to two DC signals and is thus much easier to implement (in analog or digital form). The first multiplication still requires multiplying two RF signals, but it can be implemented as a hard-switched multiplier, which is stable over a wide range of P. 负载 It is much easier to implement on PVT.

[0072] Thus, the proposed power detector 100 is easier to implement than conventional approaches and allows for current saving and / or area saving implementation of the power detector.

[0073] Figure 4FIG. 1 is a block diagram of another embodiment of the proposed power detector 100. The coupled inductor L 1 , L 2 Provides load current I 负载 Image current I 感测 The manner of sensing the current is not limiting and may also be done with a sensing inductor coupled to a transformer.

[0074] The “hard switching” first multiplier 10 implements the current I 负载 Image current I 感测 With positive and negative signs (V 负载 (t)). A filter 11 at the output of the first multiplier 10 isolates the DC component of the signal and provides some amplification. The DC signal at the output of the filter 11 is The output signal of the peak voltage detector 50 is proportional to V 负载 Proportional.

[0075] Also in this case, the linear second multiplier 40 may be implemented in the analog or digital domain.It will be appreciated that the bias circuit 20 and the attenuator 30 may be combined in one single element.

[0076] Figure 5 1 shows a block diagram of another exemplary embodiment of the proposed power detector 100. In this embodiment, the first multiplier 10 (hard switching mixer) comprises a capacitor C that has been implemented with a passive switching mixer design. S and FET. The output current of the first multiplier 10 is filtered by means of a filter 11 having a transimpedance amplifier (TIA) 11a and converted into a voltage signal. The linear multiplication by means of the second multiplier 40 is performed in the digital domain by means of a multiplexer 40a and an analog / digital converter 40b. Since both signals to be multiplied by the second multiplier 40 are DC signals, a single time multiplexed ADC is sufficient.

[0077] Most of today's ICs already contain a general-purpose ADC anyway. In this case, the digital linear multiplication does not require any additional hardware beyond the actual multiplier (a few digital gates).

[0078] The following table shows the values ​​for the different power detectors explained above:

[0079]

[0080] Table 1

[0081] Line 2… Antenna Power Range

[0082] Row 3…Number of attenuator steps

[0083] Row 4…Overall Accuracy

[0084] Line 5…Estimate silicon area

[0085] Row 6 ... Current consumption of bias circuit 20

[0086] As can be seen from Table 1, the proposed power detector 100 with the values ​​shown in column 2 has a good compromise between power detection accuracy and silicon area. It also results in less current consumption because the bias circuit for the mixer is simpler, which can be provided, for example, by V dd A basic resistor divider is made between and ground.

[0087] Figure 2 The + / -4 dB accuracy of the peak voltage detector shown in is due to a VSWR variation between 1 and 2. The proposed power detector has a good + / -1 dB accuracy even with a VSWR variation between 1 and 2.

[0088] The proposed power detector 100 provides a way to implement a real power detector by removing the linear multiplication of the RF signal (current and voltage). The proposed power detector is characterized by generating a load output current I 负载 Copy I 感测 The circuit generates a load voltage V 负载 A voltage detector that generates a proportional DC signal; and two multipliers: performing I 感测 With V 负载 A first multiplier 10 performs multiplication between the positive and negative signs of the voltage detector, and a second multiplier 40 performs multiplication between the DC component of the first multiplier output and the voltage detector output.

[0089] A filter 11 may be needed between the first multiplier output and the second multiplier input to extract only the DC value of the signal and provide some amplification.

[0090] It will be appreciated that only the second multiplier 40 performs a linear multiplication. Due to the fact that it multiplies two DC signals, it is much easier to implement than the prior art where the linear multiplier 10 multiplies two RF signals.

[0091] Figure 6 The main process of the proposed method is shown as follows:

[0092] In step 200, the load Z is sensed. 负载 The current I 负载 , and provide the current I 负载 Image current I 感测 .

[0093] In step 210, the image current I 感测 With load Z负载 The voltage V 负载 Multiplication of positive and negative signs.

[0094] In step 220, the result of the multiplication is fed to the filter 11, which is configured to provide a DC signal.

[0095] In step 230, the voltage V 负载 The peak value S2.

[0096] In step 240 , a linear multiplication of the output S1 of the filter 11 and the peak value S2 is performed.

[0097] In step 250, a load Z is provided. 负载 A bias signal is used for the first multiplier 10 during measurement of the electrical power, wherein the bias signal is substantially independent of the temperature and / or process of the first multiplier 10 .

[0098] All mentioned values ​​are exemplary only and may be exchanged with alternative suitable values. Furthermore, the disclosed values ​​are to be understood in a qualitative sense and expressed in a standardized form.

[0099] The novelty in the proposed invention is that the power detector is accomplished by performing two consecutive multiplications: I 感测 With V 负载 Instead of a single RF multiplication of voltage and current as in a classical power detector, a first multiplication between the signs of the positive and negative values ​​of the first multiplier and a second multiplication between the DC component of the first multiplier output and the peak voltage detector output is used. The specification of the linear multiplier is relaxed and a digital implementation is now possible, which allows very accurate linear multiplication with only a few digital gates, resulting in a power detector with good accuracy with less silicon area. The biasing for the RF multiplier and the optional RF attenuator is relaxed because the RF multiplier no longer has to be linear.

[0100] The proposed power detector 100 may be used, for example, in a radio platform for Bluetooth connectivity.

[0101] In the above description, various specific details have been set forth to describe the specific examples presented herein. However, it should be apparent to those skilled in the art that one or more other examples and / or variations of these examples may be implemented without all of the specific details given below. In other cases, well-known features are not described in detail to avoid confusing the description of the examples herein. For ease of illustration, the same reference numerals may be used in different figures to refer to the same elements or additional examples of the same elements. Moreover, although various aspects and features may be described in individual figures in some cases, it should be understood that features from one figure or embodiment may be combined with features of another figure or embodiment, even if the combination is not explicitly shown or explicitly described as a combination.

[0102] For example, the specification describes and / or illustrates aspects useful for implementing the claimed disclosure with the aid of various circuits or circuit systems, which may be shown as or using items such as blocks, modules, devices, systems, units, controllers, and / or other circuit-type depictions. Such circuits or circuit systems are used with other elements to illustrate how certain embodiments may be implemented in form or structure, steps, functions, operations, activities, etc. As an example, where such circuits or circuit systems may correspond to logic circuit systems (which may refer to or include a code-programmed / configured CPU), in one example, the logic circuit system may implement a process or method (sometimes an "algorithm") by performing such activities and / or steps associated with the functionality discussed above. In other examples, the logic circuit system may implement a process or method by performing these same activities / operations.

[0103] For example, in certain embodiments discussed above, one or more modules are discrete logic circuits or programmable logic circuits configured and arranged to implement these operations / activities. In certain embodiments, this programmable circuit is one or more computer circuits, including a memory circuit system for storing and accessing a program to be executed as an instruction set (and / or used as configuration data to define how the programmable circuit executes), and the programmable circuit uses an algorithm or process as described above to perform the relevant steps, functions, operations, activities, etc. Depending on the application, the instructions (and / or configuration data) may be configured to be implemented in a logic circuit, where the instructions (whether characterized by object code, firmware or software) are stored in the memory (circuitry) and can be accessed from the memory. As another example, where the specification may refer to a "first" type of structure, a "second" type of structure, the adjectives "first" and "second" are not used to imply any description of the structure or provide any substantial meaning; in fact, such adjectives are only used in English antecedents to distinguish one such similarly named structure from another similarly named structure.

[0104] Based on the above discussion and illustration, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, the method as illustrated in the figures may involve steps performed in various orders, wherein one or more aspects of the embodiments herein are maintained, or may involve fewer or more fewer or more steps.

[0105] Although the various embodiments discussed herein are subject to various modifications and alternative forms, aspects of the embodiments have been illustrated by way of example in the drawings, and aspects of the embodiments will be described in detail. However, it should be understood that the intent is not to be limited to the specific embodiments described. On the contrary, it is intended to cover all modifications, equivalents, and alternatives to the various aspects defined in the claims that fall within the scope of the present disclosure. In addition, the term "example" used throughout this application is intended to be illustrative only and not limiting.

[0106] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. Moreover, elements described in connection with different embodiments may be combined. It should also be noted that reference signs in the claims should not be interpreted as limiting the scope of the claims.

[0107] The disclosed apparatus, devices, units, elements, systems, and methods described herein may be embodied, at least in part, by a computer program or multiple computer programs, which may exist in a single computer system or across multiple computer systems in multiple forms in both active and inactive states. For example, the computer program may exist as a software program consisting of program instructions in source code, object code, executable code, or other formats for performing some steps. Any of the above may be embodied in a compressed or uncompressed form on a computer-readable medium that may include a storage device and a signal.

[0108] It should be noted that the above embodiments have been described with reference to different subject matters. In particular, some embodiments may have been described with reference to method-type claims, whereas other embodiments may have been described with reference to apparatus-type claims.

[0109] However, those skilled in the art will understand from the above that, unless otherwise stated, in addition to any combination of features belonging to one type of subject matter, any combination of features related to different subjects, in particular combinations of features of method-type claims and features of apparatus-type claims, are also deemed to be disclosed together with this document.

[0110] It has to be noted that the embodiments have been described with reference to different subject matters. In particular, some embodiments have been described with reference to method type claims, whereas other embodiments have been described with reference to apparatus type claims.

[0111] However, those skilled in the art will understand from the foregoing and the following description that, unless otherwise stated, in addition to any combination of features belonging to one type of subject matter, any combination of features related to different subject matters, in particular, the combination of features of method claims with features of apparatus claims, are also deemed to be disclosed together with the present application.

[0112] Reference numerals:

[0113] 10 First multiplier

[0114] 11 Filter

[0115] 20 Bias Circuit

[0116] 30 Attenuator

[0117] 40 Second multiplier

[0118] 40a Multiplexer

[0119] 40b ADC

[0120] 50 Voltage peak detector

[0121] 51 ADC

[0122] 100 Power Detector

[0123] 200…250 Method steps

[0124] L1, L2 Inductors

[0125] I 负载 Load current

[0126] I 感测 Image current

[0127] V 负载 Load voltage

[0128] Z load.

Claims

1. A power detector (100), characterized in that: include: - a transformer (L1, L2) configured to sense the load (Z 负载 ) current (I 负载 ) and provides the current (I 负载 ) of the image current (I 感测 ); - a first multiplier (10) configured to perform a multiplication of the image current (I 感测 ) and the load (Z 负载 ) voltage (V 负载 ) and feeding the result of the multiplication to a filter (11), the filter (11) being configured to provide a DC signal; - a peak voltage detector (50) configured to determine the voltage (V 负载 )’s peak value (S2); - a second multiplier (40) configured to perform a linear multiplication of the output (S1) of the filter (11) and the peak value (S2); as well as - a bias circuit (20) configured to provide a bias signal to the first multiplier (10), wherein the bias signal is substantially independent of the temperature and / or process of the first multiplier (10).

2. The power detector (100) according to claim 1, characterized in that The output signal (S1) of the filter (11) represents the image current (I 感测 ) multiplied by the load current (I 负载 ) and load voltage (V 输出 ) is the cosine of the phase difference between them.

3. The power detector (100) according to claim 1 or 2, characterized in that: The bias circuit (20) is one of the following: a constant current source, a bandgap voltage source.

4. A power detector (100) according to any one of the preceding claims, characterized in that Also included is an attenuator (30) configured to adapt an operating range of the first multiplier (10).

5. The power detector (100) according to claim 4, characterized in that The attenuator (30) is programmable.

6. A power detector (100) according to any one of the preceding claims, characterized in that The second multiplier (40) is a digital multiplier.

7. The power detector (100) according to any one of claims 1 to 5, characterized in that: The second multiplier (40) is an analog multiplier.

8. The power detector (100) according to any of the preceding claims, characterized in that The bias circuit (20) and the attenuator (30) are implemented in a single component.

9. The power detector (100) according to any of the preceding claims, characterized in that The first multiplier (10) corresponds to the voltage (V 负载 ) is a Heaviside function rather than a sign function.

10. A method for providing a load (Z 负载 ) is a method for measuring electric power, characterized in that The following steps are involved: - Sense load (Z 负载 ) current (I 负载 ), and provides the current (I 负载 ) of the image current (I 感测 ); - Execute the image current (I 感测 ) and the load (Z 负载 ) voltage (V 负载 )'s positive and negative signs; - feeding the result of said multiplication to a filter (11), said filter (11) being configured to provide a DC signal; - Determine the voltage (V 负载 )’s peak value (S2); - performing a linear multiplication of the output (S1) of the filter (11) and the peak value (S2); as well as - Under the load (Z 负载 ) during the measurement of the electrical power of the first multiplier (10), wherein the bias signal is substantially independent of the temperature and / or process of the first multiplier (10).

Images