Memory management method and device, storage system and computer readable medium

Abstract

The invention discloses a memory management method and device, a storage system and a computer readable medium, and relates to the technical field of mobile terminals.The method comprises the steps that a target pre-erasure mode is determined in an automatic mode and an active mode, in the automatic mode, a memory automatically executes pre-erasure operation on the memory, and in the active mode, the pre-erasure operation is executed on the memory; in the active mode, the memory executes a pre-erasure operation based on an instruction sent by the host; and executing a pre-erasing operation on the memory based on the target pre-erasing mode. Therefore, aiming at the automatic pre-erasing mode of the memory and the pre-erasing mode triggered by the host, one of the automatic mode and the active mode can be freely selected to execute the pre-erasing operation, so that the setting of the pre-erasing operation is more reasonable.

Description

Technical Field

[0001] The present application relates to the field of mobile terminal technology, and more specifically, to a memory management method, device, storage system and computer-readable medium. Background Art

[0002] At present, in flash memory, especially NAND type flash memory, it is usually necessary to perform a pre-erase operation. Usually, when the current block of such memory is full and switched to a new block, the new block must be erased first and then data is written. Summary of the invention

[0003] The present application proposes a memory management method, device, storage system and computer-readable medium to improve the above-mentioned defects.

[0004] In a first aspect, the present application provides a memory management method, which is applied to a host of a storage system, wherein the storage system also includes the memory, and the host is connected to the memory, and the method includes: determining a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host; and performing a pre-erase operation on the memory based on the target pre-erase mode.

[0005] In a second aspect, the present application also provides a memory management device, which is applied to a host of a storage system, wherein the storage system also includes the memory, and the host is connected to the memory, and the device includes: a determination unit and an erasing unit. The determination unit is used to determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host. The erasing unit is used to perform a pre-erase operation on the memory based on the target pre-erase mode.

[0006] In a third aspect, the present application also provides a storage system, comprising: a host; a memory; the host is connected to the memory, and the host is used to execute the above method.

[0007] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.

[0008] The memory management method, device, storage system and computer-readable medium provided by the present application determine the target pre-erase mode in the automatic mode and the active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on the instruction sent by the host; the pre-erase operation is performed on the memory based on the target pre-erase mode. Therefore, for the automatic pre-erase mode of the memory and the pre-erase mode triggered by the host, one of the modes can be freely selected in the automatic mode and the active mode to perform the pre-erase operation, making the setting of the pre-erase operation more reasonable.

[0009] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram of a storage system provided by an embodiment of the present application is shown;

[0012] Figure 2 A method flow chart of a memory management method provided by an embodiment of the present application is shown;

[0013] Figure 3 A schematic diagram showing the interaction between the automatic mode and the active mode provided in another embodiment of the present application is shown;

[0014] Figure 4 A schematic diagram showing the effects of the automatic mode and the active mode provided by another embodiment of the present application is shown;

[0015] Figure 5 A schematic diagram showing the format of a UPIP provided in an embodiment of the present application is shown;

[0016] Figure 6 A schematic diagram of an EHS field provided by an embodiment of the present application is shown;

[0017] Figure 7 A method flow chart of a memory management method provided by another embodiment of the present application is shown;

[0018] Figure 8 Shows Figure 7 A schematic diagram of step S780 in FIG.

[0019] Fig. 9 A module block diagram of a memory management device provided by an embodiment of the present application is shown;

[0020] Fig.10 A storage unit for storing or carrying program codes for implementing the method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] In order to make those skilled in the art better understand the present application scheme, the technical scheme in the present application embodiment will be clearly and completely described below in conjunction with the drawings in the present application embodiment. Obviously, the described embodiment is only a part of the present application embodiment, rather than all the embodiments. The components of the present application embodiment usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application for protection, but merely represents the selected embodiment of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0022] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0023] At present, in flash memory, especially NAND type flash memory, it is usually necessary to perform a pre-erase operation. Usually, in a host system that uses universal flash storage (UFS) as a storage device, the UFS firmware manages the medium (NAND flash) in units of virtual blocks (VB). When the current block is full and the UFS device switches to a new block, it must first erase the new block (in milliseconds) and then write data (program). This is because the media in the erased state has poor stability and cannot be used for data writing after a certain period of time.

[0024] Pre-erase operation refers to the process of erasing the block where the data is to be written before the flash memory write operation. This process is usually managed and executed by the controller. In NAND type flash memory, data can only be erased and written in blocks. Therefore, if you want to write new data to a block that already stores old data, you need to erase the entire block before writing. This leads to an operation process called "erase-write". The purpose of the pre-erase operation is to erase the block where the data is stored in advance before the actual write operation is performed to reduce the write delay. In this way, during the actual write operation, the controller does not need to perform the erase operation again, thereby speeding up the write speed of the memory and reducing the errors that may occur during the write. In actual applications, for flash memory, the pre-erase operation is usually managed and executed by the controller. When the controller receives a request for a write operation, it checks whether the block where the data is located has been erased. If the block has not been erased, the controller automatically performs an erase operation and then performs a write operation.

[0025] Due to the above-mentioned erase-before-write strategy, flash memory (e.g., UFS device) will always be unable to write for a period of milliseconds when the write pressure is high. Therefore, erasing some blocks in advance and reducing the time taken by UFS to switch blocks can significantly improve the write performance of the device and reduce the maximum delay caused by the erase action during the block switching process.

[0026] However, the inventors found in their research that the current pre-erasing schemes generally have the following disadvantages:

[0027] 1) Relatively fixed pre-erase capacity threshold: In the current device autonomous pre-erase solution, the pre-erase capacity is determined by the device itself, and pre-erasing is performed to the set threshold when idle. In order to obtain greater performance benefits, the threshold should be expanded as much as possible; but considering stability and the lack of free blocks, the threshold cannot be too large. Therefore, the device will choose a threshold that compromises benefits and risks. This threshold is relatively fixed and cannot adapt to changes in host write actions.

[0028] 2) Stability risk of pre-erased blocks: Currently, the device cannot know the host's write action, and the pre-erased threshold is relatively fixed, so there will always be some pre-erased blocks in the device. When the host has not written for a period of time, the pre-erased blocks are prone to stability risks.

[0029] Therefore, it is extremely important to set a reasonable pre-erase strategy.

[0030] In order to overcome the above-mentioned defects, an embodiment of the present application provides a memory management method, which can adaptively adjust the pre-erase mode in combination with the actual data writing situation of the electronic device.

[0031] It should be noted that the memory management method provided in the embodiment of the present application is applied to a system composed of hosts using a flash memory, such as Figure 1 As shown, the storage system 10 includes a host 100 and a memory 200, and the host 100 is connected to the memory 200. Exemplarily, the host 100 may be an electronic device, and the electronic device may be a device capable of running an application such as a smart phone, a tablet computer, an e-book, etc. In the embodiment of the present application, the host 100 is a smart phone. The memory 200 may be the above-mentioned flash memory, for example, the memory 200 is UFS.

[0032] It is understandable that the memory 200 can be a built-in memory of the host 100, that is, the memory 200 can be integrated into the motherboard of the host 100 and used as the ROM of the mobile phone to store the operating system, application programs and user data. In addition, the memory 200 can be an external memory of the host 100, that is, a peripheral device belonging to the host 100. For example, taking the memory 200 as UFS as an example, the host 100 and the memory 200 are connected through a USB interface. Of course, the UFS storage device can also be designed as a pluggable memory card, similar to a traditional SD card or microSD card. In this way, the user can insert the UFS storage device into the USB interface of the mobile phone and perform data transmission and access through the USB interface. In the embodiment of the present application, it is not limited to whether the memory 200 is an external memory or a built-in memory of the host 100, and the host is used to execute the following embodiments.

[0033] See also Figure 2 The method is applied to the above-mentioned host. For the convenience of description, in the following embodiments, the memory is described as UFS as an example. Of course, the memory may also be of other types, which is not limited to this. The method includes: S201 to S202.

[0034] S201: Determine a target pre-erase mode in the automatic mode and the active mode.

[0035] As an implementation method, the host can generally use two pre-erase modes, namely automatic mode and active mode. Among them, the automatic mode is Auto mode, in which UFS automatically performs a pre-erase operation. When the host sends a write command, the UFS device automatically detects the state of the target physical block and performs an erase operation when necessary. In this mode, the host does not need to explicitly send a pre-erase command, and the erase operation is handled by the UFS device itself. The active mode is Host Trigger mode. In Host Trigger mode, the host needs to explicitly send a pre-erase command to trigger the erase operation. After the host sends the pre-erase command, the UFS device will perform an erase operation according to the requirements of the command. In this mode, the host can more accurately control when to perform the erase operation. That is, in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on the instruction sent by the host.

[0036] See also Figure 3 , Figure 3 The figure shows the difference between the automatic mode and the active mode. In the automatic mode, the host sends the first erase command, namely, Wr ite(10)EHS:open auto pre erase. The storage device responds to the first erase command and enters the automatic mode. In the automatic mode, 2GB of free physical blocks are pre-erased to obtain 2GB of pre-erased blocks. Then, the host performs a write operation and applies the pre-erased blocks, namely, Wr ite cmds,use pre erase b locks. The storage device detects that the pre-erased blocks are used and automatically pre-erases 2GB of free physical blocks again. This process continues in this way until the automatic mode is turned off, namely, Wr ite(10)EHS:c lose auto pre erase. Figure 3 It can be seen that in the active mode, each pre-erase operation is actively triggered by the host, specifically, it can be actively triggered according to the return information of the memory, which will be described in detail later.

[0037] Specifically, the beneficial effects of the automatic mode and the active mode are as follows: Figure 4 shown.

[0038] It can be seen that in the active mode (host trigger mode), the pre-erase amount is fully controllable by the host, and it can effectively prevent the stability risk caused by the retention of pre-erased blocks, but the IO coverage is lower than that in the automatic mode (auto mode). This is mainly because the host trigger mode first triggers the pre-erase with a large number of write IOs (write operations), which always has a certain lag and cannot guarantee that all IOs will benefit from the pre-erase. Based on the aforementioned conditions for sending the second erase operation, it can be seen that the second erase instruction is sent only when it is determined that the write rate is greater than the current first specified threshold. Therefore, multiple write operations may have been performed before the write rate reaches the first specified threshold. Figure 4 As shown, in active mode, the write operation during the time period of the diagonal fill cannot enjoy the pre-erase benefit.

[0039] The auto mode has a higher io coverage, but the host is not completely controllable. If it is always turned on, the erase block may not be used and stability problems may occur. Therefore, for the first scenario, it can be determined that there are a lot of sequential writes, and the automatic mode can be turned on to maximize the pre-erase benefit of the write operation. Among them, the io coverage refers to the ratio of the time period during which the write operation enjoys the pre-erase benefit to the time period of the entire write operation. Among them, the pre-erase benefit refers to the fact that the write operation can use the pre-erase block.

[0040] In the present application, based on the characteristics of the aforementioned active mode and automatic mode, a mode may be selected from the automatic mode and the active mode as a target pre-erase mode based on actual needs, so as to perform a pre-erase operation.

[0041] As an implementation mode, the embodiment of the present application can determine the target pre-erase mode based on the application scenario of the storage system. Exemplarily, the application scenario can be a scenario of writing data to the UFS of the storage system. As mentioned above, the purpose of the pre-erase operation is to erase the data in the storage device before writing new data to ensure the stability and security of data writing. Therefore, for different amounts of data written, there should be different requirements for the capacity of the physical block of the pre-erase operation. In order to make the pre-erase operation more reasonable, it is necessary to determine the current data writing situation of the storage system, that is, the application scenario, before determining the pre-erase operation mode.

[0042] As an implementation method, the application scenario can reflect the amount of data written to the storage system currently or in a certain period of time in the future. Therefore, multiple scenarios can be pre-set, and the amount of data written to each scenario is different. Among them, the amount of data written represents the amount of data written that may occur in the scenario. For example, it can be the maximum amount of data written in the scenario, that is, it can be the historical peak value of the amount of data written in the scenario, or it can be the historical average value of the amount of data written in the scenario. Therefore, for different scenarios, it can be determined by analyzing the amount of data written to the UFS of the storage system in the historical time period before the current moment, and by counting the amount of data written to the UFS in the historical time period, the data range of the data write amount corresponding to the current historical time period is determined, and based on the scenarios corresponding to the pre-set different data ranges, the current application scenario is determined.

[0043] As an implementation manner, after the application scenario is determined, a target pre-erasing mode is determined in the automatic mode and the active mode based on the application scenario.

[0044] In the embodiment of the present application, the application scenario of the storage system can be divided into a first scenario and a second scenario, wherein the data writing amount of the first scenario is greater than the data writing amount of the second scenario. It should be noted that the preset data writing amount represents the data writing capacity corresponding to the scenario, that is, it is an estimate of the maximum data writing amount in the scenario.

[0045] It can be understood that in the embodiments of the present application, the first scenario is a scenario in which a large amount of data is written compared to the second scenario. That is, in the first scenario, the storage system may write a large amount of data sequentially into the memory, while in the second scenario, the amount of data written into the memory is often smaller.

[0046] As another implementation, the target pre-erase mode can also be determined by the application program running on the host. For example, the application program running on the host is determined, and based on the running application program, the target pre-erase mode is determined in the automatic mode and the active mode. Since different applications have different requirements for the number of writes and the write rate, different applications may have different requirements for the automatic mode and the active mode. Therefore, the modes corresponding to different applications can be pre-set to obtain a mode correspondence relationship. Based on the mode correspondence relationship, it can be determined whether the current application program should use the active mode or the automatic mode. Specifically, it will be explained in the subsequent embodiments.

[0047] In the embodiment of the present application, the different pre-erase modes correspond to different pre-erase strategies, and the pre-erase strategy can specify the timing of the pre-erase operation, the capacity of the pre-erase block, etc., wherein the pre-erase block refers to the physical block in the memory on which the pre-erase operation is performed, and the capacity of the pre-erase block can refer to the number of physical blocks of the specified capacity in the memory on which the pre-erase operation is performed.

[0048] Therefore, through the above correspondence, the pre-erasing mode corresponding to the current application scenario of the storage system can be determined as the target pre-erasing mode for the memory.

[0049] S202: Perform a pre-erase operation on the memory based on the target pre-erase mode.

[0050] As mentioned above, different pre-erasure modes specify pre-erasure strategies such as the timing of pre-erasure, the capacity of pre-erasure blocks, and the subject of executing the pre-erasure operation. After determining the target pre-erasure mode corresponding to the current application scenario of the storage system, the pre-erasure operation is performed on the memory based on the target pre-erasure strategy corresponding to the target pre-erasure mode. Subsequent embodiments will explain different pre-erasure operations according to different pre-erasure modes.

[0051] It should be noted that after determining the target pre-erase mode, a pre-erase instruction corresponding to the target pre-erase mode can be determined, and the pre-erase instruction can be sent to the memory so that the memory performs a pre-erase operation based on the pre-erase instruction. In an embodiment of the present application, the host can send the pre-erase instruction to the memory in three ways.

[0052] The first method is to add the pre-erase command in the preset field of the specified instruction to be sent to the memory to obtain the target instruction; and send the target instruction to the memory so that the memory performs the pre-erase operation based on the pre-erase command. The specified instruction to be sent to the memory may be a write or read instruction that the host currently needs to send to the memory, that is, a WRITE / READ command. The preset field may be an EHS field or other fields of the specified instruction.

[0053] In the embodiment of the present application, the specified instruction is a read or write instruction in a UFS Protocol Information Unit (UPIU), and the preset field is an extra header segment (EHS). The format of UPIU is as follows: Figure 5 As shown, it can be seen that the UPIU includes an EHS field, wherein the definition of the EHS field in the UPIU is as follows: Figure 6As shown, it can be seen that the type, parameters and specific contents of specific instructions can be defined in the EHS, so that the pre-erase command can be added in the EHS.

[0054] It can be understood that UPIU is the basic protocol used for communication in UFS. It is a standard command format used for control and data transmission between UFS devices, and contains commands and data structures used for communication. In UPIU, various commands for reading and writing, status information, error codes, etc., as well as some additional header information, such as Extra Header Segment (EHS) are included. Among them, EHS is part of UPIU, which contains extended header information for carrying some additional control information or metadata. EHS can be used to transmit some auxiliary information specific to commands or data transmission to support more complex operations or provide additional contextual information.

[0055] Exemplarily, the identifier of the pre-erase command can be determined first, and then the EHS data structure is configured. According to the definition in the UFS specification, the data structure of the pre-erase command to be added in the EHS needs to be determined. This may include command type, command parameters, length field, etc. Then, the data structure and identifier of the pre-erase command are encapsulated in the EHS field of the UPIU. It should be noted that the EHS field is an extension of the aforementioned specified instruction.

[0056] In addition, the memory needs to be adaptively configured so that after receiving the specified instruction, it can parse the EHS field of the instruction to obtain the pre-erase command and execute the pre-erase command if the execution conditions are met. The implementation of the execution conditions can be referred to in subsequent embodiments and will not be repeated here.

[0057] Therefore, by adding the pre-erase command in the preset field of the specified instruction to be sent to the memory, the pre-erase command is also included in the specified instruction to be sent to the memory, so that there is no need to send a pre-erase command separately in addition to the specified instruction. In other words, there is no need to generate additional interaction due to sending a pre-erase command separately, which can prevent the real-time performance of the user from being affected.

[0058] The second method is to obtain the pre-erase command corresponding to the target pre-erase mode, generate a pre-erase instruction based on the pre-erase command based on the UPIU protocol, and send the pre-erase instruction to the memory so that the memory performs a pre-erase operation based on the pre-erase instruction. Exemplarily, by creating an Erase Command data packet, encapsulating the Erase Command into the UPIU, configuring the UPIU header information, and sending the UPIU, the UPIU instruction (i.e., the pre-erase instruction) containing the erase command is sent to the UFS device to trigger the pre-erase operation. For example, a pre-erase instruction is issued using a separate UPIU, such as using a WRITE BUFFER command to define a pre-erase vendor command. Among them, the WRITE BUFFER command may include the following functions: Write data: This command can instruct the storage device to receive a certain amount of data and write this data into the device's buffer; Buffer management: The WRITE BUFFER command may involve the management of the device's internal buffer, including clearing, refreshing, or allocating buffer operations; Data transfer preparation: Some storage devices may use the WRITE BUFFER command to prepare for data transfer so that data can be effectively transferred to a specific location in the memory. For example, according to the UFS memory specification, a specific vendor command is defined using the WRITE BUFFER command to perform an erase operation. The specific vendor command structure and content need to be constructed according to the specification document of the UFS memory. In the vendor command, command codes and parameters can be defined to instruct the memory to perform an erase operation. Send the Vendor Command, that is, send the constructed vendor command to the UFS memory using UPI U.

[0059] It should be noted that the difference between the second method and the first method is that in the first method, the host sends a specified instruction, and the preset field of the specified instruction has a pre-erase command, and the pre-erase command is used as the extended information of the specified instruction in the preset field. For example, if the specified instruction is a write instruction of the UPI U protocol, the pre-erase command belongs to the extended content of the write instruction. The host sends a specified instruction to the memory, and the memory obtains the pre-erase command by parsing the content of the preset field of the specified instruction. At the same time, the memory responds to the specified instruction and performs the operation corresponding to the specified instruction. For example, if the specified instruction is a write instruction, the memory will simultaneously respond to the write instruction to perform a write operation and respond to the pre-erase command to perform a pre-erase operation. In the second method, the pre-erase instruction sent by the host is a pre-erase instruction directly defined by the UPIU protocol. Therefore, the memory receives the instruction and responds to the pre-erase instruction to perform a pre-erase operation.

[0060] The third method is to issue a pre-erase command through other requests such as query request and task management request, where query request is used to query the properties and status of the memory, and task management request can be used to manage and control the task execution of the memory. In other words, the pre-erase command can be added to the request.

[0061] It should be noted that, among the three methods mentioned above, the embodiment of the present application can select any one method to send the pre-erase command. However, considering reducing the interactive impact on the memory, in the embodiment of the present application, the pre-erase command corresponding to the target pre-erase mode is sent through the first method.

[0062] Therefore, the embodiments of the present application can determine the pre-erase mode for the memory based on the current data writing situation of the storage system, so that the pre-erase operation of the memory can be combined with the application scenario of the storage system, thereby making the pre-erase operation more in line with the current data writing requirements of the storage system, and making the setting of the pre-erase operation more reasonable.

[0063] See also Figure 7 The method is applied to the above-mentioned host. For the convenience of description, in the following embodiments, the memory is described as UFS as an example. Of course, the memory may also be of other types, which is not limited to this. The method includes: S710 to S780.

[0064] S710: Determine the application program currently running on the host.

[0065] As mentioned above, the target pre-erase mode can be determined by the application program running on the host. Therefore, in the embodiment of the present application, the application program running on the host is first determined.

[0066] As an implementation mode, taking the host as a smartphone as an example, the running application may be an application running in the foreground and / or background of the smartphone. In the embodiment of the present application, the running application may be an active application, which may refer to an application that has run in the foreground during the current time period and is currently running in the foreground or background, or an application that has written data to the memory during the current time period, or an application that is currently running in the foreground, or an application that is currently reading and / or writing data.

[0067] In the case where an active application is an application that has run in the foreground within the current time period and is currently running in the foreground or background, the current time period may be a time period of a specified length of time before the current moment, and the active application may include the application that is currently running in the foreground and the application that is switched from the foreground to the background within the current time period. In other words, considering that the application that the user has recently switched to the background may be switched to the foreground again, all the applications that have run in the foreground within the current time period are regarded as active applications, that is, the aforementioned running applications.

[0068] In the case where the active application is an application that has written data to the memory within the current time period and is currently running in the foreground or background, the electronic device determines the application currently running in the foreground or background of the electronic device as an alternative application, and then searches for the application that has written data to the memory within the current time period from the alternative applications as the active application, that is, the aforementioned running application. Among them, the application that has written data to the memory can be further defined as the amount of data written to the memory is greater than the specified amount of data. Therefore, among the various applications currently running in the foreground and background of the electronic device, the application that has written data recently can be regarded as the active application, that is, the application currently running by the host.

[0069] In an embodiment of the present application, the active application refers to the application currently running in the foreground of the electronic device, that is, to determine the implementation method of the application currently running on the host, determine the application currently running in the foreground of the host, that is, the application currently running in the foreground of the electronic device.

[0070] S720: Determine whether there is a designated application in the running applications.

[0071] As an implementation method, the designated application may be an application in an application list, and the application list may be an application that has been pre-counted to have a large number of sequential write operations. For example, when a game application performs an installation package installation operation or a version update operation, there are a large number of sequential write operations. A large number of sequential write operations refers to continuous execution of write operations within a preset time period and the amount of data written is greater than the preset amount of data. It is understandable that the applications in the application list may be manually added or determined by the host based on whether there are a large number of sequential write operations for each application within the statistical period, and this is not specifically limited here.

[0072] Therefore, after the host determines the running application, the running application is taken as the active application and matched with each designated application in the application list to determine whether there is an application that is the same as the designated application. Assuming that the running application is the application currently running in the foreground, it is determined whether the application belongs to the designated application in the application list. If so, S730 is executed, otherwise, S750 is executed.

[0073] As an implementation mode, if there is a designated application in the running applications, the application scenario in which the target pre-erase mode is determined to be the automatic mode host is the first scenario; if there is no designated application in the running applications, the application scenario in which the target pre-erase mode is determined to be the active mode host is the second scenario. In the embodiment of the present application, the two application scenarios of the designated application in the running applications and the non-designated application in the running applications can be named as the first scenario and the second scenario, respectively. It can be understood that in some embodiments, the first scenario and the second scenario may not be set. When it is determined that there is a designated application in the running applications, the target pre-erase mode is directly determined to be the automatic mode, and when there is no designated application in the running applications, the target pre-erase mode is directly determined to be the active mode. By adopting the first scenario and the second scenario, it is more convenient to describe the active mode scenario and the automatic mode scenario.

[0074] S730: Determine that the application scenario of the host is the first scenario.

[0075] That is, when it is determined that there is a designated application among the running applications, the application scenario of the host is determined to be the first scenario.

[0076] As mentioned above, the application scenario may include a first scenario and a second scenario, and the amount of data written in the first scenario is greater than the amount of data written in the second scenario. Each designated application in the application list is a predetermined application with a large number of sequential write operations, so when the designated application is running, the application may perform a large number of sequential write operations. Therefore, the application scenario with the designated application running is defined as the first scenario, and correspondingly, the application scenario without the designated application running is defined as the second scenario, which complies with the setting that the amount of data written in the first scenario is greater than the amount of data written in the second scenario.

[0077] S740: Determine that the target pre-erase mode for the memory is an automatic mode.

[0078] If the application scenario is the first scenario, the target pre-erase mode for the memory is determined to be the automatic mode, that is, for application scenarios with a large number of sequential writes, an application list is pre-set and the automatic mode is turned on during the activities of these applications.

[0079] S750: Send a first erase instruction to the memory to trigger the memory to enter an automatic mode.

[0080] The pre-erase instruction corresponding to the automatic mode is the first erase instruction, and the function of the first erase instruction is to trigger the memory to enter the automatic mode. It can be understood that the first erase instruction can be sent in any of the three aforementioned ways. In the embodiment of the present application, the first erase instruction can be sent in the first way.

[0081] As an implementation method, the memory corresponds to a device management unit, which can be a controller in the memory. In addition, in a host system using universal flash storage (UFS) as a storage device, the UFS firmware manages the medium (NAND flash) in units of virtual blocks (VB). In UFS, the storage area is divided into multiple physical blocks, each of which contains multiple sectors, and the size of each sector is usually 512 bytes or 4KB. The virtual block is a layer of logical mapping built on the physical block, which combines multiple physical blocks into a logical block and assigns a virtual address to the logical block. Through the mapping of virtual blocks, more efficient data reading, writing and management can be achieved. For example, in UFS, if a bad block occurs, the virtual block can automatically remove the block from the logical block and migrate the data to other available physical blocks, thereby ensuring the integrity and reliability of the data. In addition, the virtual block can also realize the high-speed random read and write operations of UFS, as well as the optimization and support of the TRIM command.

[0082] It is understandable that in a UFS memory, the pre-erase operation is usually performed by a controller inside the memory, that is, the aforementioned device management unit. For example, the UFS controller inside the memory is responsible for managing and executing the erase operation. The controller of the memory can perform the erase operation by searching for an idle physical block through VB.

[0083] Exemplarily, an implementation method of sending a first erase instruction to the memory to trigger the memory to enter the automatic mode may be:

[0084] In the automatic mode, a first erase instruction is sent to the memory; the memory erases the free physical blocks of the first capacity in the memory as pre-erase blocks; if it is detected that the amount of data written to the pre-erase blocks is greater than a threshold, the operation of erasing the free physical blocks of the first capacity in the memory as pre-erase blocks is performed again until the automatic mode ends. Wherein, the first capacity can be the pre-erase capacity specified by the host contained in the first erase instruction, that is, the host triggers the memory to automatically trigger the pre-erase operation, and reserves the pre-erased physical space of the first capacity size, that is, the pre-erase block. A free physical block refers to a storage block that has not been used or allocated to any data on a storage medium (such as a solid state drive, flash memory, etc.). A physical block is the smallest writable unit of a storage medium, and they usually have a fixed size. In a storage device, physical blocks are organized into continuous blocks for storing data. When data is deleted or moved, the corresponding physical block becomes a free physical block, which can be reused to store new data. Therefore, the capacity of a pre-erase block usually refers to the number of physical blocks based on which the pre-erase operation is performed.

[0085] That is to say, in automatic mode, the host turns on the pre-erasure of the Auto mode of the memory through the first erase instruction, and specifies the pre-erasure capacity (i.e., the first capacity) and the VB usage mode. The UFS device will automatically pre-erase to the first capacity after the read operation and / or write operation is idle. Among them, the VB usage mode is described in the subsequent content. When the pre-erased block is consumed by the write operation, the device automatically pre-erases according to its own idleness and replenishes the pre-erased block to the set capacity. When the host sends a command to turn off the Auto mode, the device stops automatic pre-erasure. The pre-erased blocks will gradually be consumed by subsequent writes.

[0086] Therefore, the host can specify the following in the pre-erase command: a) Pre-erase mode: automatic mode (Automode) or active mode (Host trigger mode); b) VB usage mode: including the currently commonly used NAND flash SLC / TLC / QLC modes, including but not limited to the media usage modes of new media such as MRAM / PCM / XL-Flash; c) Capacity configuration: the host can configure the pre-erase capacity within a certain range.

[0087] S760: Determine that the application scenario of the host is the second scenario.

[0088] That is, when it is determined that the designated application does not exist in the running applications, it is determined that the application scenario of the host is the second scenario.

[0089] S770: Determine that the target pre-erase mode for the memory is an active mode.

[0090] Among them, the implementation methods of the second scenario and the active mode can refer to the aforementioned content.

[0091] S780: Send a second erase instruction to the memory, instructing the memory to perform a pre-erase operation on the free physical blocks in the memory to obtain a pre-erase space.

[0092] In the active mode, a second erase instruction is sent to the memory, instructing the memory to perform a pre-erase operation on the free physical blocks in the memory to obtain a pre-erase space. That is, in the active mode, the host specifies the capacity of the pre-erase space as the second capacity, and the memory erases the free physical blocks of the second capacity to obtain a pre-erase space of the second capacity, i.e., a pre-erase block. Therefore, when the application layer detects that the specified application is active, the host determines that the application scenario is the first scenario, and sends an instruction to start the automatic mode, i.e., the open auto preerase instruction, to the driver layer. Then, the driver layer sends a pre-erase command to turn on the auto mode, i.e., the first erase instruction, to the memory. For example, the driver layer uses the EHS field of commands such as write(10) to send a pre-erase command to turn on the auto mode, i.e., the first erase instruction is sent to the memory in the first manner described above. Wherein, write(10) is a write command, and "(10)" represents that this is a 10-byte write command for writing data.

[0093] It should be noted that, in the automatic mode, the host also needs to determine whether the automatic mode is ended. If the automatic mode is ended, the host needs to send a first shutdown instruction to the memory, and the first shutdown instruction is used to close the automatic mode. Among them, determining whether the automatic mode is ended can be returning to execute again to determine the application program running on the host. Then the end of the automatic mode can include entering the active mode, and can also include neither the active mode nor the automatic mode, for example, no application is currently running. Similarly, the active mode can also determine whether the active mode is ended in this way.

[0094] In addition, since NAND flash has different usage modes for a physical block, namely SLC / MLC / TLC / QLC modes, and the number of bits that can be stored in each minimum unit is different in different modes, usually the number of bits of storage in the minimum unit corresponding to SLC / MLC / TLC / QLC is 1bit / 2bit / 3bit / 4bit respectively. Therefore, in the case of a pre-erase operation on the memory, while sending the pre-erase instruction corresponding to the target pre-erase mode, the usage mode corresponding to the pre-erase operation is also sent, so that the memory performs the pre-erase operation in this usage mode. In other words, the host can specify the usage mode of the pre-erase VB.

[0095] As an implementation mode, in different usage modes, the prerequisites for the memory to respond to the pre-erase instruction and perform the pre-erase operation are different.

[0096] For example, if the VB usage mode of the pre-erase operation specified by the host is the SLC (Single-Level Cell) mode, the prerequisite for the memory to respond to the pre-erase instruction is that the write booster (WB) buffer of the memory is available. That is, when WB available buffer size! = 0, that is to say, the WB buffer is not empty, the pre-erase operation of the SLC mode issued by the host can be executed by the memory. If the WB buffer of the memory is not available, the memory will return a failure message to the host if the capacity of the memory is insufficient, and the host will know through the failure message that the pre-erase operation cannot be successfully executed.

[0097] It is understood that SLC mode is a memory operation mode in UFS devices, which uses a higher cell density (i.e., each storage cell stores one bit) to achieve a larger capacity and provide faster data transfer speeds. In SLC mode, UFS devices usually have a dedicated WB (Write Booster) buffer. The WB buffer is usually a high-speed storage area used to temporarily store write data from the host system so that it can be written to the storage medium of the UFS device in batches at the appropriate time.

[0098] When the host system needs to perform a write operation, the data is first written to the WB buffer of the UFS device. However, before performing an erase operation, the UFS device must ensure that all data in the WB buffer has been written to the storage medium to avoid data loss or inconsistency. Therefore, in SLC mode, the UFS device usually checks whether the WB buffer is empty before performing an erase operation. If the WB buffer still contains data to be written, the UFS device will first organize the data reasonably and write it to the memory in batches before performing the erase operation. Therefore, when the WB buffer is not empty, a failure message is returned and the host needs to send a pre-erase command again.

[0099] In addition, if the host specifies that the usage mode of the pre-erase operation is in TLC or QLC mode, the precondition for the memory to respond to the pre-erase instruction is that the number of free physical blocks currently meets the preset requirement, wherein the preset requirement may be that the number of free physical blocks is greater than the first number, wherein the first number may be set according to actual usage requirements, and when the number of free physical blocks is less than or equal to the first number, it indicates that the number of free physical blocks of the memory is insufficient. Therefore, when the memory determines that the number of free physical blocks currently is less than or equal to the first number, a failure message is returned to the host.

[0100] It should be noted that, when the application currently running on the electronic device is not a designated application, this means that the current application scenario does not involve the writing of a large amount of data, that is, there is no large amount of sequential writing. This means that there may be a data writing operation at present, but the amount of data written is not large. It also means that the current scenario may be data writing or the data written is very small. Therefore, it is necessary to determine whether the amount of data written is not large by the write rate. Therefore, if Figure 8 As shown, S780 may include: S781 to S789.

[0101] S781: In the active mode, obtain the current write rate of the memory.

[0102] It should be noted that the current write rate is the write rate within the preset time length corresponding to the current moment, that is, the write rate can be the amount of data written to the memory within the preset time length corresponding to the current moment. Therefore, the implementation method of obtaining the current write rate of the memory can be to obtain the number of specified write commands sent to the memory within the preset time length corresponding to the current moment, and use the number as the write rate, wherein the specified write command is used to write a data block of a specified data size. For example, the specified data size is 512KB. Usually, for larger data write operations, it is usually cut by the block layer of the operating system to adapt it to the characteristics of the underlying storage device. In current storage devices, data read and write operations are performed in blocks, and the size of the block can be configured according to the specific storage device and file system. Common block sizes are 512KB, 1KB, 2KB, 4KB, etc. In the embodiment of the present application, the size of the data block is 512KB, so the specified write command is used to write a 512KB data block. Therefore, the number of data blocks written can measure the amount of data written within a period of time, and since the specified write command is used to write a data block of a specified data size, the number of specified write commands can reflect the size of the data written, so the number of specified write commands sent to the memory within the preset time length corresponding to the current moment is taken as the write rate. For example, the preset time length is 100ms, so the write rate is represented by the number n of 512KB chunksizewrite commands within 100ms, where chunksize refers to a parameter used to control the block size or buffer size of the data write operation.

[0103] It can be understood that the preset time length corresponding to the current moment is the corresponding time period which can be named as the current time period. The time length of the current time period is the preset time length. The end moment of the current time period is the current moment. Therefore, if the current moment changes, although the preset time length is the same, the current time period is still different.

[0104] S782: Obtain the current first specified threshold.

[0105] The first specified threshold is used to determine whether the pre-erase operation needs to be triggered by the active mode under the current write rate. The first specified threshold can be variable, and its change method can refer to the subsequent description. Since the first specified threshold is variable, before each execution of determining whether the write rate is greater than the current first specified threshold, the current first specified threshold needs to be obtained first.

[0106] S783: Determine whether the write rate is greater than the current first specified threshold.

[0107] S784: Send the second erase instruction to the memory.

[0108] If the write rate is greater than the current first specified threshold, execute S784. If the write rate is less than or equal to the current first specified threshold, return to execute S781. Of course, it is also possible to return to execute the step of determining the application program running on the host and subsequent steps.

[0109] It should be noted that the method of sending the second erase instruction to the memory can refer to the above description and will not be repeated here.

[0110] S785: Obtain response information returned by the memory in response to the second erase instruction currently sent.

[0111] In the embodiment of the present application, after the memory receives the first erase instruction or the second erase instruction, it will send a reply message to the host, and the reply message may include a failure message, a success message, a first message, and a second message. Among them, the failure message (fail) indicates that the memory cannot perform the pre-erase operation this time, such as the command requires the VB of the pre-erase s lc mode to be pre-erased, but the WB buffer is 0, or there are not enough empty blocks, etc. The implementation method of the memory sending the failure message (fail) can refer to the above embodiment, which will not be repeated here. In the case that the memory successfully performs the pre-erase operation, a success message (Success) will be sent to the host, and Success indicates that the pre-erase of the set capacity corresponding to the pre-erase operation has been completed. For example, the first erase instruction is used to instruct the memory to automatically erase the free physical blocks of the first capacity, that is, each pre-erase operation can obtain the pre-erase block of the first capacity; the second erase instruction is used to instruct the memory to obtain the pre-erase block of the second capacity, so after the memory successfully erases the pre-erase block of the corresponding capacity, a success message will be returned.

[0112] As an implementation mode, when the host determines that the current write rate is greater than the current first specified threshold, the host sends a second erase instruction to the memory. After receiving the second erase instruction, the memory determines whether the current remaining capacity of the pre-erase space obtained by the last pre-erase operation is lower than the second specified threshold. If it is lower than the second specified threshold, the first information is returned. If it is greater than or equal to the second specified threshold, the second information is returned. When the first information or the second information is returned this time, the pre-erase operation is performed based on the second erase instruction. The last pre-erase operation refers to the pre-erase operation performed before the second erase instruction is received this time. The first information and the second information reflect the efficiency of issuing the second erase instruction this time.

[0113] It can be understood that the first information efficient is used to indicate that the current remaining capacity of the pre-erasing space obtained by the last pre-erasing operation of the memory is lower than the second specified threshold, and the second information inefficient is used to indicate that the current remaining capacity of the pre-erasing space obtained by the last pre-erasing operation of the memory is higher than or equal to the second specified threshold. It can be seen that after receiving the first information, the host can determine that the capacity of the pre-erasing space obtained by the last pre-erasing operation performed on the memory is insufficient, that is, there is not enough space to write data, so the first information is returned to inform the host that the use efficiency of the pre-erasing block obtained by the current pre-erasing operation is relatively high, that is, the efficiency of issuing the second erase instruction this time is relatively high. Similarly, after receiving the second information, the host can determine that the capacity of the pre-erasing space obtained by the last pre-erasing operation performed on the memory is still sufficient, that is, there is still a certain amount of space that has not been written to data, and then the second information is returned to the host to inform the host that the use efficiency of the pre-erasing block obtained by the current pre-erasing operation is relatively low, that is, the efficiency of issuing the second erase instruction this time is relatively low.

[0114] S786: Determine whether the reply message is the first message or the second message.

[0115] S787: Increase the first specified threshold.

[0116] S788: Reduce the first specified threshold.

[0117] As mentioned above, the premise of sending the second erase instruction to the memory is to determine that the current mode is active, and the current write rate of the memory is greater than the current first specified threshold. Therefore, by changing the first specified threshold, the frequency of sending the second erase instruction to the memory can be adjusted, that is, the host is helped to dynamically adjust the frequency of issuing pre erase. It can be seen that if the first specified threshold is increased this time, the next time when the second erase instruction is determined by the write rate whether to issue the second erase instruction, the write rate needs to be greater in order to meet the condition that the next write rate is greater than the first specified threshold used next time, that is, the write operation needs to be more active to send the second erase instruction, to a certain extent, the frequency of issuing the second erase instruction can be reduced. Similarly, if the first specified threshold is reduced this time, the next time when the second erase instruction is determined by the write rate whether to issue the second erase instruction, the write rate can be smaller in order to meet the condition that the next write rate is greater than the first specified threshold used next time, that is, it is easier to trigger the sending of the second erase instruction, and the frequency of issuing the second erase instruction can be increased.

[0118] Therefore, it is determined whether the reply information is the first information or the second information. If it is the first information, the first specified threshold is reduced; if it is the second information, the first specified threshold is increased.

[0119] S789: Waiting for the data of this pre-erase to be written.

[0120] After returning the first information or the second information, the memory performs a pre-erase operation and waits for the pre-erase block to be written with data. It should be noted that if the active mode has not ended, that is, if the application scenario is still the second scenario, the step of obtaining the current write rate of the memory and subsequent steps are returned to execute. In other words, the write rate detection continues, and the first specified threshold used next time is the first specified threshold adjusted based on the first information or the second information this time.

[0121] As an implementation mode, the first specified threshold has an initial value, and when the current active mode ends or the next active mode starts, the first specified threshold will be initialized, that is, set to the initial value. In addition, the first specified threshold also has an upper limit value and a lower limit value, so that the first specified threshold will not increase or decrease blindly. Therefore, the implementation mode of reducing the first specified threshold if the reply information is the first information is that if the reply information is the first information, it is determined whether the current first specified threshold is less than or equal to the lower limit value, if it is less than or equal to the lower limit value, the first specified threshold is maintained as the lower limit value, and if it is greater than the lower limit value, the first specified threshold is reduced. Similarly, if the reply information is the second information, the implementation mode of increasing the first specified threshold may be that if the reply information is the second information, it is determined whether the current first specified threshold is greater than or equal to the upper limit value, if it is greater than or equal to the upper limit value, the first specified threshold is maintained as the upper limit value, and if it is less than the upper limit value, the first specified threshold is increased.

[0122] Therefore, in the first scenario, that is, when there are a large number of write operations, the automatic mode is used so that the memory can automatically perform the pre-erase operation in time through the current idle physical state to avoid the host actively triggering the pre-erase operation in time. If there are no large number of write operations, the active mode can be used to avoid the long-term existence of pre-erase blocks in the memory, which may lead to stability risks.

[0123] Therefore, by detecting the running designated application, it can be determined whether to enter the active mode or the automatic mode, so that in a scenario where there is a large amount of sequential writing, the pre-erase benefit of the write operation can be increased through the automatic mode.

[0124] See also Fig. 9, which shows a structural block diagram of a memory management device 900 provided in an embodiment of the present application. The device may include: a determination unit 901 and an erasure unit 902.

[0125] The determination unit 901 is used to determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host.

[0126] Furthermore, the determination unit 901 is further configured to determine an application program being run by the host; and determine a target pre-erasing mode in the automatic mode and the active mode based on the running application program.

[0127] Furthermore, the determination unit 901 is also used to determine that if there is a specified application among the running applications, the application scenario of the target pre-erase mode as the automatic mode host is the first scenario; if there is no specified application among the running applications, the application scenario of the target pre-erase mode as the active mode host is the second scenario.

[0128] The erasing unit 903 is configured to perform a pre-erasing operation on the memory based on the target pre-erasing mode.

[0129] Furthermore, the erasing unit 903 is also used to send a first erasing instruction to the memory to trigger the memory to enter an automatic mode, wherein in the automatic mode, the memory automatically performs a pre-erasing operation on the free physical blocks in the memory to obtain a pre-erasing space.

[0130] Furthermore, the erasing unit 903 is further configured to send a second erasing instruction to the memory in the active mode, instructing the memory to perform a pre-erasing operation on the free physical blocks in the memory to obtain a pre-erasing space.

[0131] Furthermore, the erasing unit 903 is also used to obtain the current write rate of the memory in the active mode; if the write rate is greater than the current first specified threshold, send the second erasing instruction to the memory.

[0132] Furthermore, the erasing unit 903 is also used to obtain the number of specified write commands sent to the memory within a preset time length corresponding to the current moment, and use the number as the write rate, wherein the specified write command is used to write a data block of a specified data size.

[0133] Furthermore, the erasing unit 903 is also used to obtain the reply information returned by the memory for the second erase instruction currently sent after sending the erase instruction to the memory if the write rate is greater than the specified threshold; if the reply information is the first information, the first specified threshold is reduced, wherein the first information is used to characterize that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation of the memory is lower than the second specified threshold, wherein the last pre-erase operation refers to the pre-erase operation performed before the second erase instruction is received this time; if the reply information is the second information, the first specified threshold is increased, wherein the second information is used to characterize that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation of the memory is higher than or equal to the second specified threshold; if the application scenario is still the second scenario, return to execute the step of obtaining the current write rate of the memory and subsequent steps.

[0134] Furthermore, the erasing unit 903 is also used to obtain a pre-erase command corresponding to the target pre-erase mode; add the pre-erase command in a preset field of the specified instruction to be sent to the memory to obtain the target instruction; and send the target instruction to the memory so that the memory performs a pre-erase operation based on the pre-erase command.

[0135] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0136] In several embodiments provided in the present application, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0137] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0138] Please refer to Fig.10 , which shows a structural block diagram of a computer-readable medium provided in an embodiment of the present application. The computer-readable medium 1000 stores program codes, which can be called by a processor to execute the method described in the above method embodiment.

[0139] The computer readable medium 1000 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk or a ROM. Optionally, the computer readable medium 1000 includes a non-transitory computer-readable storage medium. The computer readable medium 1000 has a storage space for program code 1010 that performs any method step in the above method. These program codes can be read from or written to one or more computer program products. The program code 1010 can be compressed, for example, in an appropriate form.

[0140] In summary, the memory management method, device, storage system and computer-readable medium provided by the present application determine the application scenario of the storage system, and based on the application scenario, determine the target pre-erase mode for the memory among multiple preset pre-erase modes; and perform a pre-erase operation on the memory based on the target pre-erase mode. Therefore, the pre-erase mode for the memory can be determined based on the current data writing situation of the storage system, so that the pre-erase operation of the memory can be combined with the application scenario of the storage system, so that the pre-erase operation is more in line with the current data writing requirements of the storage system, and the setting of the pre-erase operation is more reasonable.

[0141] In addition, erasing VB in advance saves a lot of time for erasing VB during the sequential write process, improves the sequential write performance of the storage system, and reduces the delay spike (i.e., maximum delay) caused by erasing VB. The host and device are linked to pre-erase on demand through scene recognition. While ensuring maximum benefits, the pre-erased blocks will not exist for a long time, improving the stability risk of existing solutions. Solution 1 does not use independent commands, but uses the EHS field or reserved field of UPI U, which does not affect the user's performance.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method, It is characterized in that A host applied to a storage system, the storage system further comprising the storage, the host being connected to the storage, the method comprising: determining a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host; A pre-erase operation is performed on the memory based on the target pre-erase pattern.

2. The method according to claim 1, It is characterized in that The determining of the target pre-erase mode in the automatic mode and the active mode comprises: determining an application program running on the host; A target pre-erase mode is determined in the automatic mode and the active mode based on the running application program.

3. The method according to claim 2, It is characterized in that The determining of the target pre-erase mode in the automatic mode and the active mode based on the running application program comprises: If there is a designated application in the running applications, determining that the target pre-erasure mode is the automatic mode; If the designated application does not exist in the running application programs, the target pre-erasing mode is determined to be the active mode.

4. The method according to claim 1, It is characterized in that The target pre-erase mode is the automatic mode, and the performing a pre-erase operation on the memory based on the target pre-erase mode includes: A first erasing instruction is sent to the memory to trigger the memory to enter an automatic mode, wherein in the automatic mode, the memory automatically performs a pre-erasing operation on an idle physical block in the memory to obtain a pre-erasing space.

5. The method according to claim 1, It is characterized in that The target pre-erase mode is the active mode, and the performing a pre-erase operation on the memory based on the target pre-erase mode includes: In the active mode, a second erasing instruction is sent to the memory to instruct the memory to perform a pre-erasing operation on an idle physical block in the memory to obtain a pre-erasing space.

6. The method according to claim 5, It is characterized in that The sending a second erase instruction to the memory in the active mode comprises: In the active mode, obtaining a current write rate of the memory; If the write rate is greater than a current first specified threshold, the second erase instruction is sent to the memory.

7. The method according to claim 6, It is characterized in that The obtaining of the current write rate of the memory includes: The number of designated write commands sent to the memory within a preset time length corresponding to the current moment is obtained, and the number is used as the write rate, wherein the designated write command is used to write a data block of a designated data size.

8. The method according to claim 6, It is characterized in that If the write rate is greater than a specified threshold, after sending an erase instruction to the memory, the method further includes: Obtaining reply information returned by the memory in response to the second erase instruction currently sent; If the reply information is the first information, reducing the first specified threshold, wherein the first information is used to indicate that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation of the memory is lower than the second specified threshold, wherein the last pre-erase operation refers to the pre-erase operation performed before the second erase instruction is received this time; If the reply information is second information, increasing the first specified threshold, wherein the second information is used to indicate that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation of the memory is higher than or equal to the second specified threshold; If the active mode is not ended, return to execute the step of obtaining the current write rate of the memory and subsequent steps.

9. The method according to any one of claims 1 to 8, It is characterized in that The performing a pre-erase operation on the memory based on the target pre-erase mode comprises: Obtaining a pre-erase command corresponding to the target pre-erase mode; Adding the pre-erase command in a preset field of a designated instruction to be sent to the memory to obtain a target instruction; The target instruction is sent to the memory to cause the memory to perform a pre-erase operation based on the pre-erase command.

10. The method according to any one of claims 1 to 8, It is characterized in that The memory is a general flash memory.

11. A memory management device, It is characterized in that A host applied to a storage system, the storage system further comprising the memory, the host being connected to the memory, the device comprising: a determining unit, configured to determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host; An erasing unit is used to perform a pre-erasing operation on the memory based on the target pre-erasing mode.

12. A storage system, It is characterized in that include: Host; Memory; The host is connected to the memory, and the host is used to execute the method according to any one of claims 1-10.

13. A computer readable medium, It is characterized in that The computer-readable medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the method according to any one of claims 1 to 10.

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