Data processing method and device for NOR memory

Abstract

The invention provides a data processing method and device for a NOR memory, and relates to the field of data processing, in particular to the field of semiconductor devices, data transmission and data storage. According to the implementation scheme, input data is obtained, the input data comprises parallel write data provided for a NOR memory and a gating signal associated with the parallel write data, the parallel write data is in the form of a continuous data sequence comprising a plurality of data parts, and the parallel write data comprises a first data part needing to be written into the NOR memory and a second data part not needing to be written into the NOR memory, the first data portion and the second data portion are indicated by a strobe signal; encoding a second data part indicated by the strobe signal into a predetermined data form which is not written by default of the NOR memory to obtain target parallel write-in data, so that the target parallel write-in data is maintained in a continuous data sequence form; and performing parallel-serial conversion on the target parallel write-in data to obtain serial write-in data used for being written into the NOR memory.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing, in particular to the field of semiconductor devices, data transmission and data storage, and more particularly to a data processing method and device for a NOR memory. Background Art

[0002] NOR memory is a non-volatile memory. The storage cell is usually based on a floating gate transistor structure. It can store data for a long time without power supply. It is widely used in scenarios that require fast random access and code execution. When reading data, since each storage cell in NOR memory is directly connected to the bit line, it supports fast access to a single address, which makes it very suitable for storing boot code or firmware. When writing data, the floating gate voltage state is usually changed by electron injection, thereby changing the threshold voltage of the storage cell to achieve data programming. How to improve the data writing efficiency of NOR memory has always been one of the hot topics in NOR memory research. Summary of the invention

[0003] The present disclosure provides a data processing method and device for a NOR memory.

[0004] According to one aspect of the present disclosure, a data processing method for a NOR memory is provided, comprising: acquiring input data, the input data comprising parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data, the parallel write data having a continuous data sequence form including a plurality of data parts, the plurality of data parts comprising a first data part to be written into the NOR memory and a second data part not to be written into the NOR memory, the first data part and the second data part being indicated by the strobe signal; obtaining target parallel write data by encoding a second data part indicated by the strobe signal among the plurality of data parts into a second encoded data part having a predetermined data form that is not written by the NOR memory by default, so that the target parallel write data maintains a continuous data sequence form; and performing parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing into the NOR memory.

[0005] According to another aspect of the present disclosure, a data processing device for a NOR memory is provided, comprising: a data acquisition module, configured to acquire input data, the input data comprising parallel write data provided to the NOR memory and a selection signal associated with the parallel write data, the parallel write data having a continuous data sequence form including a plurality of data parts, the plurality of data parts comprising a first data part to be written into the NOR memory and a second data part not to be written into the NOR memory, the first data part and the second data part being indicated by the selection signal; a data encoding module, configured to obtain target parallel write data by encoding a second data part indicated by the selection signal among the plurality of data parts into a second encoded data part having a predetermined data form that is not written into the NOR memory by default, so that the target parallel write data maintains a continuous data sequence form; and a parallel-to-serial conversion module, configured to perform parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing into the NOR memory.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the data processing method for NOR memory as described above in the present disclosure.

[0007] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, where the computer instructions are used to enable a computer to execute the data processing method for a NOR memory as described above in the present disclosure.

[0008] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the computer program implements the data processing method for a NOR memory as described above in the present disclosure.

[0009] According to one or more embodiments of the present disclosure, the data writing efficiency of a NOR memory can be effectively improved.

[0010] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0012] Figure 1 A schematic diagram showing the processing of parallel write data provided to a NOR memory in a conventional manner.

[0013] Figure 2 A flow chart of a data processing method for a NOR memory according to an exemplary embodiment of the present disclosure is shown.

[0014] Figure 3 A schematic diagram showing a corresponding relationship between a strobe signal and parallel write data according to an exemplary embodiment of the present disclosure.

[0015] Figure 4 A schematic diagram of obtaining target parallel write data according to a strobe signal and parallel write data according to an exemplary embodiment of the present disclosure is shown.

[0016] Figure 5 A schematic diagram showing a method of performing parallel-to-serial conversion on target parallel write data to obtain serial write data according to an exemplary embodiment of the present disclosure.

[0017] Figure 6 A structural block diagram of a data processing device for a NOR memory according to an exemplary embodiment of the present disclosure is shown.

[0018] Figure 7 A structural block diagram of a data processing device for a NOR memory according to another exemplary embodiment of the present disclosure is shown.

[0019] Figure 8 A block diagram of an exemplary electronic device that can be applied to the exemplary embodiments is shown. DETAILED DESCRIPTION

[0020] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0021] In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of these elements, and such terms are only used to distinguish one element from another element. In some examples, the first element and the second element may refer to the same instance of the element, and in some cases, based on the description of the context, they may also refer to different instances.

[0022] The terms used in the description of various examples described in this disclosure are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. As used herein, the term "plurality" means two or more, and the term "based on" should be interpreted as "based at least in part on". In addition, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations.

[0023] When writing data to a NOR memory, such as a NOR memory that communicates with protocols such as a serial peripheral interface (SPI), a quad serial peripheral interface (QSPI), and an inter-integrated circuit (I2C), it is usually necessary to process the parallel write data from interfaces such as AXI4 (Advanced eXtensible Interface 4) and a memory interface in a certain way and convert them into serial write data that can be written to the NOR memory. The traditional method usually splits the parallel write data into multiple segments of parallel data based on the bytes that do not need to be written in the parallel write data, and then converts the multiple segments of parallel data into multiple segments of serial write data to write to the NOR memory. This method requires multiple transmissions of the split multiple segments of serial write data, which reduces the data transmission efficiency. At the same time, the NOR memory also needs to write multiple segments of serial write data multiple times, and needs to repeatedly wait for the NOR memory to complete the write, resulting in low write efficiency and reduced reliability of the NOR memory.

[0024] Figure 1 A schematic diagram showing the processing of parallel write data provided to a NOR memory in a conventional manner.

[0025] like Figure 1 As shown, the specific contents of the parallel write data and the serial write data processed by the traditional method are schematically shown. The parallel write data can be data from a parallel interface such as AXI4, memory, etc., which is used to provide data to the NOR memory for data writing. The serial write data can be data input to the NOR memory that communicates using a serial protocol such as SPI, QSPI, I2C, etc. Figure 1As shown in , the parallel write data can be composed of eight bytes of data from byte 1 to byte 8, and byte 4 in the figure, for example, represents that the byte does not need to be written into the NOR. After the parallel write data is processed in a traditional manner, byte 4 is discarded, and the serial write data is obtained after a series of processing such as parallel-to-serial conversion. The serial write data includes a first serial data sequence 102a and a second serial data sequence 102b. When writing the serial write data into the NOR memory, the first serial data sequence 102a and the second serial data sequence 102b need to be written separately.

[0026] In such Figure 1 In the conventional processing method shown, by splitting and processing the parallel write data into multiple groups of serial write data, and then writing them into the NOR memory, it is necessary to repeatedly wait for the NOR memory to complete the write, resulting in low write efficiency. In addition, multiple write operations may also reduce the reliability of the NOR memory.

[0027] In order to effectively improve the writing efficiency of a NOR memory, the present disclosure provides a data processing method for a NOR memory.

[0028] Exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0029] Figure 2 A flow chart of a data processing method 200 for a NOR memory according to an exemplary embodiment of the present disclosure is shown.

[0030] like Figure 2 As shown, method 200 includes step S201, step S202 and step S203.

[0031] In step S201, input data is acquired, the input data including parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data. The parallel write data has a continuous data sequence form including a plurality of data portions, the plurality of data portions including a first data portion to be written to the NOR memory and a second data portion not to be written to the NOR memory. The first data portion and the second data portion are indicated by the strobe signal.

[0032] In the example, writing data in parallel can be done with Figure 1The parallel write data shown have the same source, for example, from parallel interfaces such as AXI4, memory, etc., and are used to provide data to the NOR memory for data writing. The selection signal can be an identifier for indicating whether the sub-data in the parallel write data needs to be written into the NOR controller, for example, it can be represented by a data bit with a value of 0 / 1 and other similar forms that can have two clear meanings. The selection signal may include multiple sub-signals, which are used to identify the sub-data in the parallel write data. According to the different values ​​of the selection signal, the parallel write data is divided into a first data part that needs to be written into the NOR memory and a second data part that does not need to be written into the NOR memory. The parallel write data has a continuous data sequence form, which means that from the time it is acquired, its data length is always fixed, and it is a continuous, undivided data bit set in space.

[0033] In step S202, target parallel write data is obtained by encoding a second data portion indicated by a selection signal among multiple data portions into a second encoded data portion having a predetermined data format that the NOR memory does not write by default, so that the target parallel write data maintains a continuous data sequence form.

[0034] In the example, when a data bit with a value of 1 is written to a storage cell of the NOR memory, the NOR memory will ignore the data bit. By utilizing this writing characteristic of the NOR memory, the second part of the data in the parallel write data indicated by the selection signal that does not need to be written into the NOR memory can be encoded in a specific form to obtain the target parallel write data, so that the parallel write data is not split into multiple segments during the data processing process, and the continuous data sequence form is maintained, thereby reducing the overhead of multiple transmissions and writes.

[0035] In step S203, the target parallel write data is converted into serial data to obtain serial write data for writing into the NOR memory.

[0036] In the example, since the NOR memory communication method in this solution is based on serial protocols such as SPI, QSPI, I2C, etc., before writing into the NOR memory, the target parallel write data needs to be converted into serial data to obtain the serial write data that the NOR memory in this solution can support.

[0037] According to an embodiment of the present disclosure, a data processing method for a NOR memory is proposed. The method encodes parallel write data to maintain a continuous data sequence form, and then converts it into serial write data that can be written into a NOR memory based on a serial protocol through parallel-to-serial conversion. This avoids the segmented transmission and segmented writing of data in traditional methods, eliminates the overhead of multiple transmissions and multiple writing in traditional methods, shortens the overall write operation time of the NOR memory, and improves the write performance of the NOR memory.

[0038] In some embodiments, the number of bits of the parallel write data may be eight times the number of bits of the strobe signal, and each bit of the strobe signal may be used to indicate whether eight consecutive bits of the parallel write data need to be written into the NOR memory.

[0039] Figure 3 A schematic diagram showing a corresponding relationship between a strobe signal and parallel write data according to an exemplary embodiment of the present disclosure.

[0040] like Figure 3 As shown, the parallel write data consists of a plurality of bits such as b1-b17 shown, and the strobe signal consists of a plurality of bits such as s1, s2, s3 shown. Each bit in the strobe signal may correspond to eight bits in the parallel write data, for example Figure 3 The s1 shown in FIG. 1 corresponds to b1-b8, and s2 corresponds to b9-b16. Alternatively, s1 may correspond to b9-b16, and s2 may correspond to b1-b8. The value of each bit of the selection signal may be used to determine whether the eight consecutive bits of the parallel write data corresponding to the bit need to be written into the NOR memory. For example, in the case of Figure 3 In the case where s1 corresponds to b1-b8 and s2 corresponds to b9-b16, the value of s1 can be used to determine whether b1-b8 needs to be written to the NOR memory, and the value of s2 can be used to determine whether b9-b16 needs to be written to the NOR memory.

[0041] Therefore, through the correspondence between the selection signal and the parallel write data, it can be indicated which data in the parallel write data needs to be written into the NOR memory and which data does not need to be written into the NOR memory, providing a basis for data encoding.

[0042] In some embodiments, the above Figure 2 The step S202 shown obtains the target parallel write data by encoding the second data part indicated by the selection signal in the multiple data parts into a second encoded data part having a predetermined data form that the NOR memory does not write by default. It may include: traversing each bit of the selection signal so that in response to the value of the bit being 0, encoding the eight consecutive bits indicated by the bit in the parallel write data into a predetermined data form to obtain the second encoded data part, wherein the second encoded data part includes at least one bit set, each bit set includes eight consecutive bits.

[0043] In the example, the second data portion is the data in the parallel write data indicated by the selection signal that does not need to be written into the NOR memory, and can be composed of multiple bit sets, each bit set including eight consecutive bits. The second encoded data portion can be obtained by encoding the second data portion in a predetermined data form. Specifically, the selection signal can be traversed to obtain the value of each selection signal. When the bit value is 0, it indicates that the continuous eight bits corresponding to the bit in the parallel write data of the bit do not need to be written into the NOR memory. At this time, the continuous eight bits of data can be encoded into a predetermined data form. The second encoded data portion is a data set obtained after the second data portion is encoded, and can be composed of multiple bit sets, each bit set including eight consecutive bits, which has the characteristic that the NOR memory is not written by default, and is also a part of the target parallel write data.

[0044] Therefore, by encoding the data in the parallel write data that does not need to be written into the NOR memory in a predetermined data form, the data that does not need to be written into the NOR memory can be converted into a data representation form that the NOR memory does not write by default, so as to maintain the continuous data sequence form of the parallel write data.

[0045] In some embodiments, the step of encoding the eight consecutive bits indicated by the bit in the parallel write data into a predetermined data format may include: replacing the eight consecutive bits with 0xFF.

[0046] In an example, when a bit value in the strobe signal is 0, the consecutive eight bits corresponding to the bit in the parallel write data may be encoded as 0xFF.

[0047] Therefore, by setting the predetermined data format to 0xFF, that is, setting 8 consecutive bits to 1, according to the above-mentioned writing characteristic of the NOR memory that writing 1 will ignore, when writing 0xFF to the NOR memory, the NOR memory will ignore these 0xFFs, so it will not affect the writing of other data contents. At the same time, by replacing data instead of discarding data, it can also prevent the first data part from being split into multiple segments.

[0048] In some embodiments, the above Figure 2 The data processing method 200 for a NOR memory shown may further include: traversing each bit of the selection signal so that in response to the value of the bit being 1, the values ​​of eight consecutive bits indicated by the bit in the parallel write data are retained, wherein the first data portion includes at least one bit set, each bit set including eight consecutive bits.

[0049] In the example, the first data portion is the data in the parallel write data indicated by the selection signal that needs to be written into the NOR memory, and can be composed of multiple bit sets, each bit set including eight consecutive bits. Since the first data portion needs to be written into the NOR memory, the data content of the first data portion needs to be retained during the data processing. Specifically, the selection signal can be traversed to obtain the value of each selection signal. When the bit value is 1, it indicates that the consecutive eight bits corresponding to the bit in the parallel write data need to be written into the NOR memory. At this time, the value of the consecutive eight bits is retained.

[0050] Therefore, by retaining the data in the parallel write data that needs to be written into the NOR memory, these data can be combined with the encoded second encoded data portion to jointly form the target parallel write data, thereby ensuring that the target parallel write data can maintain a continuous data sequence form.

[0051] Figure 4 A schematic diagram of obtaining target parallel write data according to a strobe signal and parallel write data according to an exemplary embodiment of the present disclosure is shown.

[0052] like Figure 4 As shown, a strobe signal, parallel write data, and a data processing process of processing the strobe signal and the parallel write data to obtain target parallel write data are schematically shown.

[0053] like Figure 4 As shown in , the selection signal may include 8 consecutive bits with values ​​of 1, 1, 0, 1, 0, 1, 1, 0, which may correspond to 64 consecutive bits with values ​​of 0x1F, 0x16, 0x3C, 0x66, 0xEF, 0xCC, 0xB0, and 0x56 in the parallel write data, respectively. It can be understood that 0x1F, 0x16, 0x3C, 0x66, 0xEF, 0xCC, 0xB0, and 0x56 are all hexadecimal numbers, which may correspond to eight binary numbers, respectively.

[0054] First, the selection signal can be traversed to obtain the first bit value of 1 in the selection signal, so the corresponding continuous eight-bit value 0x1F in the parallel write data can be retained. The second bit value of 1 in the selection signal can be obtained, so the corresponding continuous eight-bit value 0x16 in the parallel write data can be retained. The third bit value of 0 in the selection signal can be obtained, so the corresponding continuous eight-bit value 0x3C in the parallel write data can be replaced with 0xFF. The fourth bit value of 1 in the selection signal can be obtained, so the corresponding continuous eight-bit value 0x66 in the parallel write data can be retained. The fifth bit value of 0 in the selection signal can be obtained, so the corresponding continuous eight-bit value 0xEF in the parallel write data can be replaced with 0xFF. The sixth bit value of 1 in the selection signal can be obtained, so the corresponding continuous eight-bit value 0xCC in the parallel write data can be retained. The seventh bit value of 1 in the selection signal can be obtained, so the corresponding continuous eight-bit value 0xB0 in the parallel write data can be retained. The value of the eighth bit in the selection signal can be obtained as 0, so the corresponding continuous eight-bit value 0x56 in the parallel write data can be replaced with 0xFF.

[0055] Therefore, the target parallel write data with consecutive 64-bit values ​​of 0x1F, 0x16, 0xFF, 0x66, 0xFF, 0xCC, 0xB0, and 0xFF can be obtained.

[0056] In some embodiments, the input data may further include an address signal associated with the parallel write data, and the address signal may include a starting address at which the parallel write data is written into the NOR memory. Figure 2 The step S203 shown performs parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing into the NOR memory, which may include: attaching a start address to the target parallel write data in the form of a continuous data sequence; and performing parallel-to-serial conversion on the target parallel write data attached with the start address to obtain serial write data.

[0057] In the example, the address signal may come from an AXI4 interface, a memory interface, and may generally include 32-bit or 64-bit data. The target parallel write data in the form of a continuous data sequence may be spliced ​​with the start address in a certain manner, for example, the start address may be in front and the target parallel write data may be in the back.

[0058] In the example, after the target parallel write data and the start address are spliced, the spliced ​​data sequence can be converted from parallel to serial to obtain serial write data that can be written into a NOR memory that communicates using a serial protocol. The above parallel-to-serial conversion can be performed by, for example, a parallel-to-serial converter (PSC) or a circuit module with a similar parallel-to-serial conversion function.

[0059] Therefore, by performing parallel-to-serial conversion on the target parallel write data maintained in the form of a continuous data sequence to which the start address is attached, serial write data that can be written into the NOR memory communicating using the serial protocol can be obtained.

[0060] Figure 5 A schematic diagram showing a method of performing parallel-to-serial conversion on target parallel write data to obtain serial write data according to an exemplary embodiment of the present disclosure.

[0061] like Figure 5 As shown, schematically shows a starting address 501, a target parallel write data 502 and a target parallel write data 503 attached with the starting address. The starting address 501 can be composed of 32 consecutive bits, for example, a value of 0x66CCFFEE. The target parallel write data 502 can be composed of 64 consecutive bits, for example, a value of 0x1F, 0x16, 0xFF, 0x26, 0xFF, 0xC1, 0xB0, 0xFF. The two are spliced ​​in a manner that the starting address 501 is in front and the target parallel write data 502 is in the back, and the target parallel write data 503 attached with the starting address can be obtained, which can be composed of 96 consecutive bits, and the values ​​are 0x66, 0xCC, 0xFF, 0xEE, 0x1F, 0x16, 0xFF, 0x26, 0xFF, 0xC1, 0xB0, 0xFF. The target parallel write data 503 attached with the starting address is converted to serial, and serial write data can be obtained.

[0062] Figure 6 A structural block diagram of a data processing device for a NOR memory according to an exemplary embodiment of the present disclosure is shown.

[0063] like Figure 6As shown, a data processing device for a NOR memory includes a data acquisition module, a data encoding module and a parallel-to-serial conversion module. The data acquisition module is configured to acquire input data, the input data includes parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data, the parallel write data has a continuous data sequence form including multiple data parts, the multiple data parts include a first data part that needs to be written to the NOR memory and a second data part that does not need to be written to the NOR memory, and the first data part and the second data part are indicated by the strobe signal. The data encoding module is configured to obtain target parallel write data by encoding the second data part indicated by the strobe signal in the multiple data parts into a second encoded data part having a predetermined data form that the NOR memory does not write by default, so that the target parallel write data maintains a continuous data sequence form. The parallel-to-serial conversion module is configured to perform parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing into the NOR memory.

[0064] The operations of the above-mentioned data acquisition module, data encoding module and parallel-to-serial conversion module can respectively correspond to the following: Figure 2 The operations of steps S201, S202 and S203 are shown in FIG. Therefore, the details of each aspect thereof will not be repeated here.

[0065] Figure 7 FIG. 7 is a block diagram showing a structure of a data processing device 700 for a NOR memory according to another exemplary embodiment of the present disclosure.

[0066] like Figure 7 As shown, the data processing device 700 for NOR memory may include a data acquisition module 701, a data encoding module 702 and a parallel-to-serial conversion module 703. The operations of the data acquisition module 701, the data encoding module 702 and the parallel-to-serial conversion module 703 may be similar to those in FIG. Figure 6 The operations of the data acquisition module, data encoding module and parallel-to-serial conversion module shown are the same.

[0067] In some embodiments, the data encoding module 702 may include a first response module 702a. The first response module 702a may be configured to traverse each bit of the selection signal, so that in response to the value of the bit being 0, the eight consecutive bits indicated by the bit in the parallel write data are encoded into a predetermined data form to obtain a second encoded data portion, wherein the second encoded data portion includes at least one bit set, and each bit set includes eight consecutive bits.

[0068] In some embodiments, the first response module 702a may include a data replacement module 702a-1. The data replacement module 702a-1 may be configured to replace eight consecutive bits with 0xFF.

[0069] In some embodiments, the input data may include an address signal associated with the parallel write data, and the address signal includes a start address at which the parallel write data is written into the NOR memory. The parallel-to-serial conversion module 703 may include an address attachment module 703a and a data conversion module 703b. The address attachment module 703a may be configured to attach the start address to the target parallel write data in the form of a continuous data sequence. The data conversion module 703b may be configured to perform parallel-to-serial conversion on the target parallel write data attached with the start address to obtain the serial write data.

[0070] In some embodiments, the data processing device 700 for the NOR memory may further include a second response module 704. The second response module 704 may be configured to traverse each bit of the selection signal so that in response to the value of the bit being 1, the value of the eight consecutive bits indicated by the bit in the parallel write data is retained, wherein the first data portion includes at least one bit set, and each bit set includes eight consecutive bits.

[0071] Although specific functions are discussed above with reference to specific modules, it should be noted that the functions of the various modules discussed herein may be divided into multiple modules, and / or at least some functions of multiple modules may be combined into a single module. The specific module discussed herein performing an action includes the specific module itself performing the action, or alternatively the specific module calling or otherwise accessing another component or module that performs the action (or performs the action in conjunction with the specific module). Therefore, the specific module that performs an action may include the specific module itself that performs the action and / or another module that the specific module calls or otherwise accesses to perform the action.

[0072] It should also be understood that various techniques may be described herein in the general context of software or program modules. Figure 6 The various modules described may be implemented in hardware or in hardware in combination with software and / or firmware. For example, these modules may be implemented as computer program code / instructions configured to be executed in one or more processors and stored in a computer-readable storage medium. Alternatively, these modules may be implemented as hardware logic / circuits. For example, in some embodiments, as Figure 6One or more of the data acquisition module, data encoding module, and parallel-to-serial conversion module shown may be implemented together in a system on chip (SoC). The SoC may include an integrated circuit chip (which includes a processor (e.g., a central processing unit (CPU), a microcontroller, a microprocessor, a digital signal processor (DSP), etc.), a memory, one or more communication interfaces, and / or one or more components in other circuits), and may optionally execute received program codes and / or include embedded firmware to perform functions.

[0073] According to an embodiment of the present disclosure, an electronic device is provided, comprising at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the data processing method for NOR memory as described above in the present disclosure.

[0074] According to an embodiment of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, where the computer instructions are used to enable a computer to execute the data processing method for a NOR memory as described above in the present disclosure.

[0075] According to an embodiment of the present disclosure, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the computer program implements the data processing method for a NOR memory as described above in the present disclosure.

[0076] In the following, combined Figure 8 Illustrative examples of such electronic devices and non-transitory computer-readable storage media are described.

[0077] Figure 8 8 shows an example configuration of an electronic device 800 that can be used to implement the data processing method for NOR memory described herein. Figure 8 The structure shown is only an example. According to the specific implementation, the electronic device of the present disclosure may only include Figure 8 One or more of the components shown.

[0078] The electronic device 800 can be a variety of different types of devices. Examples of the electronic device 800 include, but are not limited to, desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablet computers, cellular or other wireless phones (e.g., smart phones), notepad computers, mobile stations), wearable devices (e.g., glasses, watches), entertainment devices (e.g., entertainment appliances, set-top boxes communicatively coupled to a display device, game consoles), televisions or other display devices, automotive computers, and the like.

[0079] The electronic device 800 may include at least one processor 802, memory 804, communication interface(s) 806, a display device 808, other I / O devices 810, one or more mass storage devices 812, all capable of communicating with one another, such as via a system bus 814 or other appropriate connection.

[0080] The processor 802 may be a single processing unit or multiple processing units, all of which may include a single or multiple computing units or multiple cores. The processor 802 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operating instructions. Among other capabilities, the processor 802 may be configured to obtain and execute computer-readable instructions stored in the memory 804, mass storage device 812, or other computer-readable media, such as program codes of an operating system 816, program codes of an application program 818, program codes of other programs 820, and the like.

[0081] The memory 804 and the mass storage device 812 are examples of computer-readable storage media for storing instructions that are executed by the processor 802 to implement the various functions described above. For example, the memory 804 may generally include both volatile memory and non-volatile memory (e.g., RAM, ROM, etc.). In addition, the mass storage device 812 may generally include a hard drive, a solid-state drive, a removable medium, including external and removable drives, a memory card, a flash memory, a floppy disk, an optical disk (e.g., a CD, a DVD), a storage array, a network attached storage, a storage area network, etc. The memory 804 and the mass storage device 812 may all be collectively referred to herein as memory or computer-readable storage media, and may be a non-transitory medium capable of storing computer-readable, processor-executable program instructions as computer program code, which may be executed by the processor 802 as a specific machine configured to implement the operations and functions described in the examples herein.

[0082] A number of programs may be stored on the mass storage device 812. These programs include an operating system 816, one or more application programs 818, other programs 820, and program data 822, and they may be loaded into the memory 804 for execution. Examples of such applications or program modules may include, for example, computer program logic (e.g., computer program code or instructions) for implementing the method 200 and / or other embodiments described herein.

[0083] Although in Figure 8 800, but modules 816, 818, 820, and 822, or portions thereof, may be implemented using any form of computer-readable media accessible by the electronic device 800. As used herein, "computer-readable media" includes at least two types of computer-readable media, namely, computer-readable storage media and communication media.

[0084] Computer-readable storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information, such as computer-readable instructions, data structures, program modules or other data. Computer-readable storage media include but are not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD), or other optical storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices or other magnetic storage devices, or any other non-transmission media that can be used to store information for access by electronic devices. In contrast, communication media can embody computer-readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms. Computer-readable storage media defined herein do not include communication media.

[0085] One or more communication interfaces 806 are used to exchange data with other devices, such as through a network, a direct connection, etc. Such communication interfaces can be one or more of the following: any type of network interface (e.g., a network interface card (NIC)), a wired or wireless (such as IEEE 802.11 wireless LAN (WLAN)) wireless interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, a cellular network ... TM The communication interface 806 may facilitate communication within a variety of network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. The communication interface 806 may also provide for communication with external storage devices (not shown) such as in a storage array, network attached storage, a storage area network, etc.

[0086] In some examples, a display device 808 such as a monitor may be included for displaying information and images to the user. Other I / O devices 810 may be devices that receive various inputs from the user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and the like.

[0087] The technology described herein can be supported by these various configurations of the electronic device 800, and is not limited to the specific examples of the technology described herein. For example, the functionality can also be implemented in whole or in part on the "cloud" by using a distributed system. The cloud includes and / or represents a platform for resources. The platform abstracts the underlying functionality of the hardware (e.g., server) and software resources of the cloud. Resources may include applications and / or data that can be used when performing computing processing on a server away from the electronic device 800. Resources may also include services provided over the Internet and / or through a subscriber network such as a cellular or Wi-Fi network. The platform can abstract resources and functions to connect the electronic device 800 to other electronic devices. Therefore, the implementation of the functions described herein can be distributed throughout the cloud. For example, the functions can be implemented partially on the electronic device 800 and partially through a platform that abstracts the functions of the cloud.

Claims

1. A data processing method for a NOR memory, comprising: Acquire input data, the input data including parallel write data provided to a NOR memory and a strobe signal associated with the parallel write data, the parallel write data having a continuous data sequence form including a plurality of data portions, the plurality of data portions including a first data portion to be written to the NOR memory and a second data portion not to be written to the NOR memory, the first data portion and the second data portion being indicated by the strobe signal; Obtaining target parallel write data by encoding the second data portion indicated by the strobe signal among the plurality of data portions into a second encoded data portion having a predetermined data form that the NOR memory does not write by default, so that the target parallel write data maintains the continuous data sequence form; as well as The target parallel write data is converted into serial data to obtain serial write data for writing into the NOR memory.

2. The method according to claim 1, wherein: The number of bits of the parallel write data is eight times the number of bits of the strobe signal, and each bit of the strobe signal is used to indicate whether eight consecutive bits of the parallel write data need to be written into the NOR memory.

3. The method according to claim 2, wherein: The method of obtaining the target parallel write data by encoding the second data portion indicated by the strobe signal among the plurality of data portions into a second encoded data portion having a predetermined data form that is not written by the NOR memory by default comprises: Each bit of the selection signal is traversed so that in response to the value of the bit being 0, the eight consecutive bits indicated by the bit in the parallel write data are encoded into the predetermined data form to obtain the second encoded data portion, wherein the second encoded data portion includes at least one bit set, each bit set including the eight consecutive bits.

4. The method according to claim 3, wherein: The step of encoding the eight consecutive bits indicated by the bit in the parallel write data into the predetermined data form comprises: The eight consecutive bits are replaced with 0xFF.

5. The method according to claim 2, wherein: The method further comprises: Each bit of the selection signal is traversed so that in response to the value of the bit being 1, the value of the eight consecutive bits indicated by the bit in the parallel write data is retained, wherein the first data portion includes at least one bit set, each bit set including the eight consecutive bits.

6. The method according to claim 5, wherein: The input data further includes an address signal associated with the parallel write data, the address signal includes a starting address at which the parallel write data is written into the NOR memory, and the parallel-to-serial conversion of the target parallel write data to obtain serial write data for writing into the NOR memory includes: appending the start address to the target parallel write data in the form of the continuous data sequence; and The target parallel write data to which the start address is attached is parallel-to-serial converted to obtain the serial write data.

7. A data processing device for a NOR memory, comprising: a data acquisition module configured to acquire input data, the input data comprising parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data, the parallel write data having a continuous data sequence form including a plurality of data portions, the plurality of data portions comprising a first data portion to be written to the NOR memory and a second data portion not to be written to the NOR memory, the first data portion and the second data portion being indicated by the strobe signal; a data encoding module configured to obtain target parallel write data by encoding the second data portion indicated by the strobe signal among the plurality of data portions into a second encoded data portion having a predetermined data form that the NOR memory does not write by default, so that the target parallel write data maintains the continuous data sequence form; as well as The parallel-to-serial conversion module is configured to perform parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing into the NOR memory.

8. An electronic device, comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to make a computer execute the method according to claims 1-6.

10. A computer program product comprising a computer program, wherein: The computer program implements the method according to claims 1-6 when being executed by a processor.

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