A data processing method and apparatus for a NOR memory

Abstract

The present disclosure provides a data processing method and apparatus for a NOR memory, relating to the field of data processing, and particularly to the fields of semiconductor devices, data transmission, and data storage. The implementation scheme is as follows: obtaining input data, including parallel write data provided to the NOR memory and a strobe signal associated therewith, the parallel write data having a form of a continuous data sequence including a plurality of data portions, including a first data portion to be written into the NOR memory and a second data portion not to be written into the NOR memory, the first data portion and the second data portion being indicated by the strobe signal; encoding the second data portion indicated by the strobe signal into a predetermined data form that is not written by the NOR memory by default to obtain target parallel write data, so that the target parallel write data maintains the form of a continuous data sequence; performing a parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing into the NOR memory.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing, and particularly to the fields of semiconductor devices, data transmission, and data storage, and in particular to a data processing method and apparatus for a NOR memory. Background Art

[0002] A NOR memory is a non-volatile memory. The storage cells are usually based on a floating-gate transistor structure and can store data for a long time without power supply. It is widely used in scenarios that require fast random access and code execution. When reading data, since each storage cell in the NOR memory is directly connected to the bit line, it supports fast access to a single address, which makes it very suitable for storing startup code or firmware. When writing data, the floating-gate voltage state is usually changed by electron injection, and then the threshold voltage of the storage cell is changed to achieve data programming. How to improve the data writing efficiency of NOR memories has always been one of the research hotspots of NOR memories. Summary of the Invention

[0003] The present disclosure provides a data processing method and apparatus for a NOR memory.

[0004] According to one aspect of the present disclosure, there is provided a data processing method for a NOR memory, including: obtaining input data, the input data including parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data, the parallel write data having a form of a continuous data sequence including a plurality of data portions, the plurality of data portions including a first data portion to be written into the NOR memory and a second data portion not to be written into the NOR memory, the first data portion and the second data portion being indicated by the strobe signal; obtaining target parallel write data by encoding the second data portion indicated by the strobe signal in the plurality of data portions into a second encoded data portion having a predetermined data form that is not written by default in the NOR memory, so that the target parallel write data maintains the form of a continuous data sequence; and performing a parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing into the NOR memory.

[0005] According to another aspect of the present disclosure, there is provided a data processing apparatus for a NOR memory, including: a data acquisition module configured to acquire input data, the input data including parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data, the parallel write data having a form of a continuous data sequence including a plurality of data portions, the plurality of data portions including a first data portion to be written to the NOR memory and a second data portion not to be written to the NOR memory, the first data portion and the second data portion being indicated by the strobe signal; a data encoding module configured to obtain target parallel write data by encoding the second data portion indicated by the strobe signal among the plurality of data portions into a second encoded data portion having a predetermined data form that is not written by default in the NOR memory, so that the target parallel write data maintains the form of a continuous data sequence; and a parallel-to-serial conversion module configured to perform parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing to the NOR memory.

[0006] According to another aspect of the present disclosure, there is provided an electronic device, including at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the data processing method for a NOR memory as described above in the present disclosure.

[0007] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the data processing method for a NOR memory as described above in the present disclosure.

[0008] According to another aspect of the present disclosure, there is provided a computer program product including a computer program, and the computer program implements the data processing method for a NOR memory as described above in the present disclosure when executed by a processor.

[0009] According to one or more embodiments of the present disclosure, the data writing efficiency of the NOR memory can be effectively improved.

[0010] According to the embodiments described hereinafter, these and other aspects of the present disclosure will be apparent and will be elucidated with reference to the embodiments described hereinafter. Description of the Drawings

[0011] The drawings exemplarily show embodiments and form part of the specification, and are used together with the written description of the specification to explain the exemplary embodiments of the embodiments. The shown embodiments are for illustrative purposes only and do not limit the scope of the claims. In all the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0012] Figure 1 It shows a schematic diagram of processing parallel write data provided to a NOR memory in a traditional manner.

[0013] Figure 2 It shows a flowchart of a data processing method for a NOR memory according to an exemplary embodiment of the present disclosure.

[0014] Figure 3 It shows a schematic diagram of the correspondence between a strobe signal and parallel write data according to an exemplary embodiment of the present disclosure.

[0015] Figure 4 It shows a schematic diagram of obtaining target parallel write data based on a strobe signal and parallel write data according to an exemplary embodiment of the present disclosure.

[0016] Figure 5 It shows a schematic diagram of performing parallel-to-serial conversion on target parallel write data to obtain serial write data according to an exemplary embodiment of the present disclosure.

[0017] Figure 6 It shows a block diagram of a data processing apparatus for a NOR memory according to an exemplary embodiment of the present disclosure.

[0018] Figure 7 It shows a block diagram of a data processing apparatus for a NOR memory according to another exemplary embodiment of the present disclosure.

[0019] Figure 8 It shows a block diagram of an exemplary electronic device that can be applied to the exemplary embodiment. Detailed implementation manners

[0020] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0021] In the present disclosure, unless otherwise specified, the terms "first", "second", etc. are used to describe various elements, and are not intended to limit the positional relationship, timing relationship, or importance relationship of these elements. Such terms are only used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of the element, and in certain cases, based on the context description, they may also refer to different instances.

[0022] In the description of the various examples in this disclosure, the terms used are for the purpose of describing specific examples only and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. As used herein, the term "plurality" means two or more, and the term "based on" should be interpreted as "at least partially based on". In addition, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0023] When writing data to a NOR memory, such as a NOR memory that communicates using protocols such as Serial Peripheral Interface (SPI), Quad Serial Peripheral Interface (QSPI), and Inter-Integrated Circuit (I2C), it is usually necessary to process the parallel write data from interfaces such as AXI4 (Advanced eXtensible Interface 4) interface and Memory interface in a certain way and convert it into serial write data that can be written to the NOR memory. Traditional methods usually split the parallel write data into multiple segments of parallel data according to the bytes that do not need to be written in the parallel write data, and then convert the above multiple segments of parallel data into multiple segments of serial write data respectively to write to the NOR memory. This method requires multiple transmissions of the multiple segments of serial write data after splitting, reducing the data transmission efficiency. At the same time, the NOR memory also needs to write the multiple segments of serial write data multiple times, and needs to repeatedly wait for the NOR memory to finish writing, resulting in problems of low writing efficiency and reduced reliability of the NOR memory.

[0024] Figure 1 The figure shows a schematic diagram of processing the parallel write data provided to the NOR memory in the traditional manner.

[0025] As Figure 1 shown, the specific contents of the parallel write data and the serial write data processed by the traditional method are schematically shown. The parallel write data can be data from parallel interfaces such as AXI4 and Memory, and is used to provide data writing to the NOR memory. The serial write data can be data input to a NOR memory that communicates using a serial protocol such as SPI, QSPI, and I2C. As Figure 1As shown, the parallel write data can consist of eight bytes of data from byte 1 to byte 8. For example, byte 4 in the figure represents that this byte does not need to be written to the NOR. After the parallel write data is processed in the traditional way, byte 4 is discarded, and after a series of processes such as serial-to-parallel conversion, the serial write data is obtained. The serial write data includes a first serial data sequence 102a and a second serial data sequence 102b. When writing the serial write data to the NOR memory, the first serial data sequence 102a and the second serial data sequence 102b need to be written separately.

[0026] In a traditional processing method such as Figure 1 shown, by splitting the parallel write data and processing it into multiple groups of serial write data and then writing it to the NOR memory, it is necessary to repeatedly wait for the NOR memory write to complete, resulting in low write efficiency. In addition, multiple write operations may also cause a decrease in the reliability of the NOR memory.

[0027] To effectively improve the write efficiency of the NOR memory, the present disclosure provides a data processing method for the NOR memory.

[0028] The exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0029] Figure 2 The flowchart of a data processing method 200 for a NOR memory according to an exemplary embodiment of the present disclosure is shown.

[0030] As Figure 2 shown, the method 200 includes step S201, step S202, and step S203.

[0031] In step S201, input data is obtained. The input data includes parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data. The parallel write data has a form of a continuous data sequence including multiple data parts. The multiple data parts include a first data part that needs to be written to the NOR memory and a second data part that does not need to be written to the NOR memory. The first data part and the second data part are indicated by the strobe signal.

[0032] In the example, the parallel write data can be associated with Figure 1The parallel write data shown comes from the same source, for example, from parallel interfaces such as AXI4, memory, etc., and is used to provide data for writing to the NOR memory. The strobe signal can be an identifier for indicating whether the sub-data in the parallel write data needs to be written to the NOR controller. For example, it can be represented by a data bit with a value of 0 / 1 and other similar forms with two clear meanings. The strobe signal can include multiple sub-signals, which are respectively used to identify the sub-data in the parallel write data. According to different values of the strobe signal, the parallel write data is divided into a first data part that needs to be written to the NOR memory and a second data part that does not need to be written to the NOR memory. The parallel write data having the form of a continuous data sequence means that from the time it is acquired, its data length is always fixed, and it is a continuous and undivided set of data bits in space.

[0033] In step S202, the target parallel write data is obtained by encoding the second data part indicated by the strobe signal in the multiple data parts into a second encoded data part having a predetermined data form that is not written by default in the NOR memory, so that the target parallel write data maintains the form of a continuous data sequence.

[0034] In the example, when writing a data bit with a value of 1 to the storage unit of the NOR memory, the NOR memory will ignore this data bit. Utilizing this write characteristic of the NOR memory, the second part of the data in the parallel write data that does not need to be written to the NOR memory indicated by the strobe signal can be encoded in a specific form to obtain the target parallel write data, so that the parallel write data is not split into multiple segments during the data processing process, maintains the form of a continuous data sequence, and thus reduces the overhead of multiple transmissions and writes.

[0035] In step S203, the target parallel write data is subjected to parallel-to-serial conversion to obtain the serial write data for writing to the NOR memory.

[0036] In the example, since the communication mode of the NOR memory in this solution is based on serial protocols such as SPI, QSPI, I2C, etc., before writing to the NOR memory, the target parallel write data also needs to be subjected to parallel-to-serial conversion to obtain the serial write data that can be supported by the NOR memory in this solution.

[0037] According to an embodiment of the present disclosure, a data processing method for a NOR memory is proposed. This method encodes the parallel write data to maintain the form of a continuous data sequence, and then converts it into serial write data that can be written to a NOR memory based on a serial protocol through parallel-to-serial conversion, avoiding data segmented transmission and segmented writing in the traditional method, eliminating the overhead of multiple transmissions and multiple writes in the traditional method, shortening the overall write operation time of the NOR memory, and improving the write performance of the NOR memory.

[0038] In some embodiments, the number of bits of data written in parallel may be eight times the number of bits of the strobe signal, and each bit of the strobe signal may be used to indicate whether eight consecutive bits in the data written in parallel need to be written into the NOR memory.

[0039] Figure 3 A schematic diagram showing the correspondence between the strobe signal and the data written in parallel according to an exemplary embodiment of the present disclosure is shown.

[0040] As Figure 3 shown, the data written in parallel consists of multiple bits such as b1 - b17 shown, and the strobe signal consists of multiple bits such as s1, s2, s3 shown. Each bit in the strobe signal may correspond to eight bits in the data written in parallel. For example, Figure 3 as shown in Figure 3 s1 corresponds to b1 - b8, and s2 corresponds to b9 - b16. Alternatively, s1 may correspond to b9 - b16, and s2 may correspond to b1 - b8. It can be determined whether eight consecutive bits in the data written in parallel corresponding to each bit of the strobe signal need to be written into the NOR memory by the value of each bit of the strobe signal. For example, in the case where

[0041] s1 corresponds to b1 - b8 and s2 corresponds to b9 - b16 as shown in

[0042] In some embodiments, the above-mentioned step S202 as Figure 2 shown obtains the target data written in parallel by encoding the second data part indicated by the strobe signal in multiple data parts into a second encoded data part having a predetermined data form that is not written by default in the NOR memory, and may include: traversing each bit of the strobe signal, so that in response to the value of the bit being 0, encoding eight consecutive bits in the data written in parallel indicated by the bit into the predetermined data form to obtain the second encoded data part, where the second encoded data part includes at least one set of bits, and each set of bits includes eight consecutive bits.

[0043] In the example, the second data part is the data in the parallel write data indicated by the strobe signal that does not need to be written to the NOR memory. It can be composed of multiple bit sets, and each bit set includes eight consecutive bits. The second encoded data part can be obtained by encoding the second data part in a predetermined data form. Specifically, the strobe signal can be traversed to obtain the value of each bit of the strobe signal. When the bit value is 0, it indicates that the eight consecutive bits corresponding to this bit in the parallel write data do not need to be written to the NOR memory. At this time, the eight consecutive bits of data can be encoded into a predetermined data form. The second encoded data part is a data set obtained after encoding the second data part. It can be composed of multiple bit sets, and each bit set includes eight consecutive bits. It has the characteristic that the NOR memory does not write by default and is also a part of the target parallel write data.

[0044] Therefore, by encoding the data in the parallel write data that does not need to be written to the NOR memory in a predetermined data form, the data that does not need to be written to the NOR memory can be converted into a data representation form that the NOR memory does not write by default, so as to maintain the continuous data sequence form of the parallel write data.

[0045] In some embodiments, the step of encoding the eight consecutive bits indicated by the bit in the parallel write data into a predetermined data form may include: replacing the eight consecutive bits with 0xFF.

[0046] In the example, when the value of a certain bit in the strobe signal is 0, the eight consecutive bits corresponding to this bit in the parallel write data can be encoded as 0xFF.

[0047] Therefore, by setting the predetermined data form to 0xFF, that is, all eight consecutive bits are set to 1. According to the write characteristic mentioned above that writing 1 to the NOR memory will be ignored, when writing 0xFF to the NOR memory, the NOR memory will ignore these 0xFF, so it will not affect the writing of other data contents. At the same time, by replacing the data instead of discarding the data, it can also avoid splitting the first data part into multiple segments.

[0048] In some embodiments, the above-mentioned Figure 2 The data processing method 200 for the NOR memory as shown may further include: traversing each bit of the strobe signal so that in response to the value of the bit being 1, the values of the eight consecutive bits indicated by the bit in the parallel write data are retained, where the first data part includes at least one bit set, and each bit set includes eight consecutive bits.

[0049] In the example, the first data part is the data in the parallel write data indicated by the strobe signal that needs to be written into the NOR memory. It can be composed of multiple bit sets, and each bit set includes eight consecutive bits. Since the first data part needs to be written into the NOR memory, the data content of the first data part needs to be retained during the data processing. Specifically, the strobe signal can be traversed to obtain the value of each bit of the strobe signal. When the bit value is 1, it indicates that the eight consecutive bits corresponding to this bit in the parallel write data need to be written into the NOR memory. At this time, the values of these eight consecutive bits are retained.

[0050] Therefore, by retaining the data in the parallel write data that needs to be written into the NOR memory, these data can be combined with the encoded second encoded data part to jointly form the target parallel write data, so as to ensure that the target parallel write data can maintain the form of a continuous data sequence.

[0051] Figure 4 FIG. shows a schematic diagram of obtaining the target parallel write data according to the strobe signal and the parallel write data according to an exemplary embodiment of the present disclosure.

[0052] As Figure 4 shown, it schematically shows the strobe signal, the parallel write data, and the data processing process of processing the strobe signal and the parallel write data to obtain the target parallel write data.

[0053] As Figure 4 shown, the strobe signal can include eight consecutive bits with values of 1, 1, 0, 1, 0, 1, 1, 0, which can respectively correspond to 64 consecutive bits with values of 0x1F, 0x16, 0x3C, 0x66, 0xEF, 0xCC, 0xB0, 0x56 in the parallel write data. It can be understood that 0x1F, 0x16, 0x3C, 0x66, 0xEF, 0xCC, 0xB0, 0x56 are all hexadecimal numbers and can respectively correspond to eight-bit binary numbers.

[0054] First, the strobe signal can be traversed to obtain that the first bit in the strobe signal has a value of 1. Therefore, the corresponding consecutive eight-bit value 0x1F in the parallel write data can be retained. It can be obtained that the second bit in the strobe signal has a value of 1. Therefore, the corresponding consecutive eight-bit value 0x16 in the parallel write data can be retained. It can be obtained that the third bit in the strobe signal has a value of 0. Therefore, the corresponding consecutive eight-bit value 0x3C in the parallel write data can be replaced with 0xFF. It can be obtained that the fourth bit in the strobe signal has a value of 1. Therefore, the corresponding consecutive eight-bit value 0x66 in the parallel write data can be retained. It can be obtained that the fifth bit in the strobe signal has a value of 0. Therefore, the corresponding consecutive eight-bit value 0xEF in the parallel write data can be replaced with 0xFF. It can be obtained that the sixth bit in the strobe signal has a value of 1. Therefore, the corresponding consecutive eight-bit value 0xCC in the parallel write data can be retained. It can be obtained that the seventh bit in the strobe signal has a value of 1. Therefore, the corresponding consecutive eight-bit value 0xB0 in the parallel write data can be retained. It can be obtained that the eighth bit in the strobe signal has a value of 0. Therefore, the corresponding consecutive eight-bit value 0x56 in the parallel write data can be replaced with 0xFF.

[0055] Therefore, the target parallel write data with 64 consecutive bits having values of 0x1F, 0x16, 0xFF, 0x66, 0xFF, 0xCC, 0xB0, and 0xFF can be obtained.

[0056] In some embodiments, the input data may further include an address signal associated with the parallel write data. The address signal may include the starting address where the parallel write data is written to the NOR memory. Accordingly, the above steps S203 as Figure 2 shown for performing parallel-to-serial conversion on the target parallel write data to obtain the serial write data for writing to the NOR memory may include: attaching the starting address to the target parallel write data in the form of a continuous data sequence; and performing parallel-to-serial conversion on the target parallel write data attached with the starting address to obtain the serial write data.

[0057] In the example, the address signal may come from interfaces such as the AXI4 interface and the memory interface, and usually may include 32-bit or 64-bit data. The target parallel write data maintaining the form of a continuous data sequence and the starting address can be spliced in a certain way. For example, they can be spliced in the way that the starting address is in the front and the target parallel write data is in the back.

[0058] In the example, after concatenating the target parallel write data and the start address, the concatenated data sequence can be converted from parallel to serial to obtain serial write data that can be written into a NOR memory communicating using a serial protocol. The above parallel-to-serial conversion can be performed by, for example, a parallel-to-serial converter (PSC) or a circuit module having a similar parallel-to-serial conversion function.

[0059] Therefore, by performing a parallel-to-serial conversion on the target parallel write data that holds a continuous data sequence with the start address attached, serial write data that can be written into a NOR memory communicating using a serial protocol can be obtained.

[0060] Figure 5 A schematic diagram of performing a parallel-to-serial conversion on target parallel write data to obtain serial write data according to an exemplary embodiment of the present disclosure is shown.

[0061] As Figure 5 shown, schematically shown are a start address 501, target parallel write data 502, and target parallel write data 503 with the start address attached. The start address 501 can consist of 32 consecutive bits, for example, with a value of 0x66CCFFEE. The target parallel write data 502 can consist of 64 consecutive bits, for example, with values of 0x1F, 0x16, 0xFF, 0x26, 0xFF, 0xC1, 0xB0, 0xFF. By concatenating the two in the order of the start address 501 first and the target parallel write data 502 second, target parallel write data 503 with the start address attached can be obtained, which can consist of 96 consecutive bits with values of 0x66, 0xCC, 0xFF, 0xEE, 0x1F, 0x16, 0xFF, 0x26, 0xFF, 0xC1, 0xB0, 0xFF. Performing a parallel-to-serial conversion on the target parallel write data 503 with the start address attached can obtain serial write data.

[0062] Figure 6 A structural block diagram of a data processing device for a NOR memory according to an exemplary embodiment of the present disclosure is shown.

[0063] As Figure 6As shown, the data processing device for a NOR memory includes a data acquisition module, a data encoding module, and a parallel-to-serial conversion module. The data acquisition module is configured to acquire input data, where the input data includes parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data. The parallel write data has a form of a continuous data sequence including multiple data parts, and the multiple data parts include a first data part to be written to the NOR memory and a second data part not to be written to the NOR memory. The first data part and the second data part are indicated by the strobe signal. The data encoding module is configured to obtain target parallel write data by encoding the second data part indicated by the strobe signal among the multiple data parts into a second encoded data part having a predetermined data form that is not written by default in the NOR memory, so that the target parallel write data maintains the form of a continuous data sequence. The parallel-to-serial conversion module is configured to perform parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing to the NOR memory.

[0064] The operations of the above data acquisition module, data encoding module, and parallel-to-serial conversion module can respectively correspond to the operations of steps S201, S202, and S203 as shown in Figure 2 Therefore, the details of each aspect are not elaborated here.

[0065] Figure 7 The structural block diagram of a data processing device 700 for a NOR memory according to another exemplary embodiment of the present disclosure is shown.

[0066] As shown in Figure 7 The data processing device 700 for a NOR memory may include a data acquisition module 701, a data encoding module 702, and a parallel-to-serial conversion module 703. The operations of the data acquisition module 701, the data encoding module 702, and the parallel-to-serial conversion module 703 may be the same as the operations of the data acquisition module, the data encoding module, and the parallel-to-serial conversion module as shown in Figure 6 Therefore, the details of each aspect are not elaborated here.

[0067] In some embodiments, the data encoding module 702 may include a first response module 702a. The first response module 702a may be configured to traverse each bit of the strobe signal, so that in response to the value of the bit being 0, eight consecutive bits indicated by the bit in the parallel write data are encoded into a predetermined data form to obtain a second encoded data part, where the second encoded data part includes at least one bit set, and each bit set includes eight consecutive bits.

[0068] In some embodiments, the first response module 702a may include a data replacement module 702a-1. The data replacement module 702a-1 may be configured to replace eight consecutive bits with 0xFF.

[0069] In some embodiments, the above input data may include an address signal associated with parallel write data, and the address signal includes a starting address where the parallel write data is written to the NOR memory. The serial-to-parallel conversion module 703 may include an address attachment module 703a and a data conversion module 703b. The address attachment module 703a may be configured to attach the starting address to the target parallel write data in the form of a continuous data sequence. The data conversion module 703b may be configured to perform serial-to-parallel conversion on the target parallel write data with the starting address attached thereto to obtain serial write data.

[0070] In some embodiments, the data processing apparatus 700 for the NOR memory may further include a second response module 704. The second response module 704 may be configured to traverse each bit of the strobe signal such that, in response to the value of the bit being 1, the values of eight consecutive bits in the parallel write data indicated by the bit are retained, wherein the first data portion includes at least one set of bits, and each set of bits includes eight consecutive bits.

[0071] Although specific functions have been discussed above with reference to specific modules, it should be noted that the functions of the various modules discussed herein can be divided into multiple modules, and / or at least some of the functions of multiple modules can be combined into a single module. The actions performed by the specific modules discussed herein include the specific module itself performing the action, or alternatively the specific module calling or otherwise accessing another component or module that performs the action (or performs the action in combination with the specific module). Thus, the specific module that performs the action may include the specific module itself that performs the action and / or another module that the specific module calls or otherwise accesses and that performs the action.

[0072] It should also be understood that the various techniques herein may be described in the general context of software or program modules. The various modules described above Figure 6 may be implemented in hardware or in hardware in combination with software and / or firmware. For example, these modules may be implemented as computer program code / instructions configured to be executed in one or more processors and stored in a computer-readable storage medium. Alternatively, these modules may be implemented as hardware logic / circuitry. For example, in some embodiments, as Figure 6One or more of the illustrated data acquisition module, data encoding module, and serial-to-parallel conversion module may be implemented together in a system on chip (SoC). The SoC may include an integrated circuit chip (which includes one or more components such as a processor (e.g., a central processing unit (CPU), a microcontroller, a microprocessor, a digital signal processor (DSP), etc.), a memory, one or more communication interfaces, and / or other circuitry), and may optionally execute the received program code and / or include embedded firmware to perform functions.

[0073] According to an embodiment of the present disclosure, there is provided an electronic device, including at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the data processing method for NOR memory as described above in the present disclosure.

[0074] According to an embodiment of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the data processing method for NOR memory as described above in the present disclosure.

[0075] According to an embodiment of the present disclosure, there is provided a computer program product, including a computer program, and the computer program implements the data processing method for NOR memory as described above in the present disclosure when executed by a processor.

[0076] Hereinafter, in conjunction with Figure 8 illustrative examples of such an electronic device and a non-transitory computer-readable storage medium will be described.

[0077] Figure 8 An example configuration of an electronic device 800 that can be used to implement the data processing method for NOR memory described herein is shown. It should be noted that Figure 8 the structure shown is only an example, and according to a specific implementation, the electronic device of the present disclosure may include only Figure 8 one or more of the components shown.

[0078] The electronic device 800 can be various different types of devices. Examples of the electronic device 800 include, but are not limited to: desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablet computers, cellular or other wireless telephones (e.g., smart phones), notepad computers, mobile stations), wearable devices (e.g., glasses, watches), entertainment devices (e.g., entertainment appliances, set-top boxes communicatively coupled to a display device, game consoles), televisions or other display devices, automotive computers, and so on.

[0079] The electronic device 800 may include at least one processor 802, a memory 804, (one or more) communication interfaces 806, a display device 808, other I / O devices 810, and one or more mass storage devices 812 that are capable of communicating with each other, such as via a system bus 814 or other suitable connections.

[0080] The processor 802 can be a single processing unit or multiple processing units, and all processing units can include single or multiple computing units or multiple cores. The processor 802 can be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operation instructions. Among other capabilities, the processor 802 can be configured to obtain and execute computer-readable instructions stored in the memory 804, the mass storage device 812, or other computer-readable media, such as program code of an operating system 816, program code of an application 818, program code of other programs 820, and so on.

[0081] The memory 804 and the mass storage device 812 are examples of computer-readable storage media for storing instructions that are executed by the processor 802 to implement the various functions described above. For example, the memory 804 generally can include both volatile and non-volatile memory (e.g., RAM, ROM, etc.). In addition, the mass storage device 812 generally can include a hard disk drive, a solid state drive, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical discs (e.g., CD, DVD), storage arrays, network-attached storage, storage area networks, and so on. The memory 804 and the mass storage device 812 can both be collectively referred to as memory or computer-readable storage media in this document, and can be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code that can be executed by the processor 802 as a specific machine configured to implement the operations and functions described in the examples in this document.

[0082] Multiple programs can be stored on the mass storage device 812. These programs include an operating system 816, one or more application programs 818, other programs 820, and program data 822, and they can be loaded into the memory 804 for execution. Examples of such application programs or program modules can include, for example, computer program logic (e.g., computer program code or instructions) for implementing the method 200 and / or additional embodiments described herein.

[0083] Although illustrated in Figure 8 as being stored in the memory 804 of the electronic device 800, the modules 816, 818, 820, and 822 or portions thereof can be implemented using any form of computer-readable medium accessible to the electronic device 800. As used herein, "computer-readable medium" includes at least two types of computer-readable media, namely computer-readable storage media and communication media.

[0084] Computer-readable storage media includes volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD), or other optical storage devices, magnetic cassettes, tapes, disk storage devices or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to an electronic device. In contrast, communication media can embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism. Computer-readable storage media as defined herein does not include communication media.

[0085] One or more communication interfaces 806 are used to exchange data with other devices, such as via a network, direct connection, etc. Such communication interfaces can be one or more of the following: any type of network interface (e.g., network interface card (NIC)), wired or wireless (such as IEEE 802.11 wireless LAN (WLAN)) wireless interface, Worldwide Interoperability for Microwave Access (Wi-MAX) interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth TM interface, Near Field Communication (NFC) interface, etc. The communication interface 806 can facilitate communication within a variety of network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. The communication interface 806 can also provide communication with external storage devices (not shown) such as in storage arrays, network-attached storage, storage area networks, etc.

[0086] In some examples, a display device 808, such as a monitor, may be included for displaying information and images to a user. Other I / O devices 810 may be devices that receive various inputs from a user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and the like.

[0087] The techniques described herein may be supported by these various configurations of the electronic device 800 and are not limited to the specific examples of the techniques described herein. For example, the functionality may also be implemented in whole or in part on a "cloud" by using a distributed system. The cloud includes and / or represents a platform for resources. The platform abstracts the underlying functionality of the hardware (e.g., servers) and software resources of the cloud. Resources may include applications and / or data that may be used when performing computing processing on servers remote from the electronic device 800. Resources may also include services provided over the Internet and / or over a subscriber network such as a cellular or Wi-Fi network. The platform may abstract the resources and functionality to connect the electronic device 800 with other electronic devices. Thus, the implementation of the functionality described herein may be distributed throughout the cloud. For example, the functionality may be implemented partially on the electronic device 800 and partially by a platform that abstracts the functionality of the cloud.

Claims

1. A data processing method for a NOR memory, comprising: Obtaining input data, the input data including parallel write data provided to the NOR memory and a strobe signal associated with the parallel write data, the parallel write data having a form of a continuous data sequence including a plurality of data portions, the plurality of data portions including a first data portion to be written to the NOR memory and a second data portion not to be written to the NOR memory, the first data portion and the second data portion being indicated by the strobe signal; Obtaining target parallel write data by encoding the second data portion indicated by the strobe signal among the plurality of data portions into a second encoded data portion having a predetermined data form that the NOR memory does not write by default, so that the target parallel write data maintains the form of the continuous data sequence; And Performing a parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing to the NOR memory.

2. The method according to claim 1, wherein, The number of bits of the parallel write data is eight times the number of bits of the strobe signal, and each bit of the strobe signal is used to indicate whether eight consecutive bits in the parallel write data need to be written to the NOR memory.

3. The method according to claim 2, wherein The obtaining target parallel write data by encoding the second data portion indicated by the strobe signal among the plurality of data portions into a second encoded data portion having a predetermined data form that the NOR memory does not write by default, includes: Traversing each bit of the strobe signal, so that in response to the value of the bit being 0, encoding eight consecutive bits in the parallel write data indicated by the bit into the predetermined data form to obtain the second encoded data portion, wherein the second encoded data portion includes at least one set of bits, and each set of bits includes the eight consecutive bits.

4. The method according to claim 3, wherein The encoding eight consecutive bits in the parallel write data indicated by the bit into the predetermined data form, includes: Replacing the eight consecutive bits with 0xFF.

5. The method according to claim 2, wherein The method further includes: Traversing each bit of the strobe signal, so that in response to the value of the bit being 1, retaining the values of eight consecutive bits in the parallel write data indicated by the bit, wherein the first data portion includes at least one set of bits, and each set of bits includes the eight consecutive bits.

6. The method according to claim 5, wherein, The input data further includes an address signal associated with the parallel write data, the address signal including a starting address where the parallel write data is written to the NOR memory, the performing a parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing to the NOR memory, includes: Attaching the starting address to the target parallel write data having the form of the continuous data sequence; and Performing a parallel-to-serial conversion on the target parallel write data attached with the starting address to obtain the serial write data.

7. A data processing apparatus for a NOR memory, comprising: A data acquisition module, configured to acquire input data, where the input data includes parallel write data provided to a NOR memory and a strobe signal associated with the parallel write data, the parallel write data having a form of a continuous data sequence including a plurality of data parts, the plurality of data parts including a first data part to be written to the NOR memory and a second data part not to be written to the NOR memory, and the first data part and the second data part being indicated by the strobe signal; A data encoding module, configured to obtain target parallel write data by encoding the second data part indicated by the strobe signal in the plurality of data parts into a second encoded data part having a predetermined data form that is not written by default in the NOR memory, so that the target parallel write data maintains the form of the continuous data sequence; And A parallel-to-serial conversion module, configured to perform parallel-to-serial conversion on the target parallel write data to obtain serial write data for writing to the NOR memory.

8. An electronic device, comprising: At least one processor; And A memory communicatively connected to the at least one processor; Wherein The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method according to any one of claims 1-6.

9. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause a computer to execute the method according to any one of claims 1-6.

10. A computer program product, comprising a computer program, wherein, The computer program, when executed by a processor, implements the method according to any one of claims 1-6.

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