Hardware module for modular multiplication calculations

By employing a hardware module with a minimum radix-4 redundancy representation, combined with a partial product generator and a hybrid redundancy modular reduction array, the problem of existing technologies being unable to balance acceleration and programmability in modular multiplication calculations is solved. This results in a hardware module with a short critical path and strong programmability, making it suitable for modular multiplication calculations in FHE accelerators.

CN120104097BActive Publication Date: 2026-06-12ZHEJIANG ANT SECRET TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
ZHEJIANG ANT SECRET TECH CO LTD
Filing Date
2025-02-12
Publication Date
2026-06-12

AI Technical Summary

⚠Technical Problem

Existing modular multiplication computing hardware modules cannot balance acceleration and programmability, have long critical paths or poor programmability, and support a limited set of modules.

⚗Method used

The hardware module, which adopts the minimum radix-4 redundancy representation, includes a partial product generator and a hybrid redundancy modular reduction array. Partial product generation is achieved through a Booth encoder and a multiplexer, and modular multiplication is performed using a minimum redundancy hybrid radix-4 adder and registers, resulting in a short critical path and strong programmability.

🎯Benefits of technology

It achieves a balance between acceleration of modular multiplication and programmability, supports programmability of arbitrary moduli, has a short critical path and strong programmability of hardware modules, and is suitable for modular multiplication in FHE accelerators.

✦ Generated by Eureka AI based on patent content.

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Abstract

The embodiment of the present specification provides a hardware module for modular multiplication calculation. The hardware module comprises: a partial product generator configured to receive a current quantization bit of a second multiplier in a minimum base 4 redundancy mr4 form input in a current clock cycle, and output a first bit string, the first bit string being a binary representation of a partial product of multiplication of the current quantization bit and a first multiplier in a binary form; a hybrid redundancy modular reduction array comprising a plurality of minimum redundancy hybrid base 4 adders mrHY4A and a set of registers; and the plurality of mrHY4A are configured to output intermediate sum data in the mr4 form obtained in a last clock cycle from the set of registers according to the first bit string, a target product in a binary form related to a modulus, and an intermediate sum data in the current clock cycle, and cache the intermediate sum data in the current clock cycle in the set of registers, and the intermediate sum data in the last clock cycle is a modular multiplication result of the first multiplier, the second multiplier and a scaling factor under the modulus.
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