Initialization method of physical layer chip and related device

Abstract

The invention provides a physical layer chip initialization method and a related device, the method is applied to a system comprising h physical layer chips, the system comprises m processors used for initializing the h physical layer chips, h is larger than or equal to 2, m is larger than or equal to 1, m and h are integers, and the method can be executed by a first processor. The method comprises the steps that after a first processor in the m processors is powered on, the first processor conducts parallel initialization on n physical layer chips, the n physical layer chips belong to the h physical layer chips, n is larger than or equal to 2 and smaller than or equal to h, and n is an integer. According to the invention, the consumed time for initializing the plurality of PHY chips is shortened in a mode of initializing the plurality of PHY chips in parallel, so that the rapid initialization of the plurality of PHY chips is realized.

Description

Technical Field

[0001] The present application relates to the field of vehicle technology, and in particular to a method for initializing a physical layer chip and related devices. Background Art

[0002] With the development of the vehicle industry, the number of electronic components and the complexity of wiring in the vehicle have increased significantly. At the same time, with the continuous increase in the number of devices such as vehicle-mounted cameras and lidars, the scenarios of in-vehicle data transmission are constantly enriched, the amount of related data is surging, and the requirements for data bandwidth are gradually increasing. Traditional in-vehicle networks can no longer meet the current in-vehicle data transmission needs. With the evolution of electronic and electrical and autonomous driving technologies, in-vehicle Ethernet technology has gradually taken a dominant position. The in-vehicle Ethernet physical layer (PHY) is one of the basic technologies in Ethernet technology. PHY chips are mainly used to realize signal transmission and conversion.

[0003] Currently, a physical layer chip initialization method is known, which can initialize multiple PHY chips after the system is powered on, but the method takes a long time to initialize multiple PHY chips. In some business scenarios, multiple PHY chips need to be initialized quickly.

[0004] Therefore, how to achieve rapid initialization of multiple physical layer chips has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present application provides a physical layer chip initialization method and related devices, in order to achieve rapid initialization of multiple physical layer chips.

[0006] In a first aspect, the present application provides a method for initializing a physical layer chip, which is applied to a system including h physical layer chips, and the system includes m processors for initializing the h physical layer chips, h≥2, m≥1, m and h are integers, and the method can be executed by a first processor.

[0007] Exemplarily, the method includes: after a first processor among the m processors is powered on, the first processor initializes n physical layer chips in parallel, the n physical layer chips belong to the h physical layer chips, 2≤n≤h, and n is an integer.

[0008] Based on the above solution, by initializing multiple PHY chips in parallel, the time consumed for initializing multiple PHY chips is shortened, thereby achieving rapid initialization of multiple PHY chips.

[0009] In combination with the first aspect, in some possible implementations, the first processor may be one processor among the m processors.

[0010] In combination with the first aspect, in some possible implementations, the first processor may be any one of the m processors.

[0011] In combination with the first aspect, in some possible implementations, a first processor initializes n physical layer chips in parallel, including: the first processor obtains a first message, the first message includes first data for initializing the n physical layer chips, the destination address field of the first message is a first address, and the first address is used to indicate the n physical layer chips; the first processor sends the first message to the n physical layer chips.

[0012] The destination address field of the first message is a first address, and the first address is used to indicate the n physical layer chips, that is, the n physical layer chips can be selected through the first address, that is, the n physical layer chips can respond to the message whose destination address field is the first address. It can be understood that the first address can be a reserved address, or a pre-configured address, which is not limited in this application.

[0013] In this implementation, the first processor can send the data required for initializing the multiple PHY chips to the multiple PHY chips connected to the first processor in a broadcast manner, so that the multiple PHY chips can be initialized in parallel, thereby shortening the time consumed for initializing the multiple PHY chips and realizing rapid initialization of the multiple PHY chips.

[0014] In combination with the first aspect, in some possible implementations, the first processor sends the first message to the n physical layer chips, including: the first processor sends the first message to the n physical layer chips through a management data input / output (MDIO) bus.

[0015] In actual application scenarios, the first processor and the n PHY chips may also be connected via other buses, which is not limited in this application.

[0016] In combination with the first aspect, in some possible implementations, the first processor obtains the first message, including: the first processor generates the first message.

[0017] In combination with the first aspect, in some possible implementations, the first processor obtains the first message, including: the first processor receives the first message from a master controller, the master controller is connected to the m processors, and the master controller controls the h physical layer chips.

[0018] In a second aspect, the present application provides a method for initializing a physical layer chip, which is applied to a system including h physical layer chips, and the system includes m processors for initializing the h physical layer chips, h≥2, m≥1, m and h are integers, and the method can be executed by a first physical layer chip.

[0019] Exemplarily, the method includes: a first physical layer chip among the h physical layer chips receives a first message from a first processor, the first message includes first data for initializing n physical layer chips, the n physical layer chips belong to the h physical layer chips, and the n physical layer chips are connected to the first processor, the first physical layer chip is one of the n physical layer chips, 2≤n≤h, n is an integer; when the destination address field of the first message is a first address or the address of the first physical layer chip, the first physical layer chip is initialized based on the first data, and the first address is used to indicate the n physical layer chips.

[0020] Based on the above scheme, the processor can send the data required for initializing the multiple PHY chips connected to the processor in a broadcast manner based on the first address. Accordingly, the first physical layer chip among the multiple PHY chips can receive the first message based on the first address, and the first address is not the address of the first physical layer chip, but is used to indicate the address of the multiple PHY chips. Therefore, the multiple PHY chips can all receive the first message based on the first address, and then can be initialized in parallel based on the first data in the first message, thereby shortening the time consumed for initializing the multiple PHY chips and realizing rapid initialization of the multiple PHY chips.

[0021] The initialization of each PHY chip may include access to registers included in the PHY chip (e.g., reading and / or writing to registers), and configuration of port parameters of the PHY chip. In the case where the first data includes data for access to registers included in the PHY chip, but does not include data for configuration of port parameters of the PHY chip, the first PHY chip is initialized based on the first data, which can be understood as the first PHY chip accessing registers in the first PHY chip based on the first data. In the case where the first data includes data for access to registers included in the PHY chip, and also includes data for configuration of port parameters of the PHY chip, the first PHY chip is initialized based on the first data, which can be understood as the first PHY chip accessing registers in the first PHY chip based on the first data, and configuring port parameters of the first PHY chip based on the first data.

[0022] In conjunction with the second aspect, in some possible implementations, the first physical layer chip may be one physical layer chip among the h physical layer chips.

[0023] In conjunction with the second aspect, in some possible implementations, the first physical layer chip may be any physical layer chip among the h physical layer chips.

[0024] In combination with the second aspect, in some possible implementations, the first physical layer chip receives a first message from a first processor, including: the first physical layer chip receives the first message from the first processor through an MDIO bus.

[0025] In combination with the second aspect, in some possible implementations, the first message is generated by the first processor.

[0026] In combination with the second aspect, in some possible implementations, the first message is received by the first processor from a general controller, the general controller is connected to the m processors, and the general controller controls the h physical layer chips.

[0027] In combination with the first aspect and the second aspect, in some possible implementations, the first address is MDIO address 0.

[0028] In combination with the first aspect and the second aspect, in some possible implementations, the first message also includes second data, and the second data is used to configure port parameters of k physical layer chips among the n physical layer chips, 0≤k≤n, and k is an integer.

[0029] In combination with the first aspect and the second aspect, the first processor is a microcontroller unit (MCU) or a system on chip (SOC).

[0030] In a third aspect, the present application provides a processor, which can be used to implement the method in the first aspect and any possible implementation of the first aspect. The processor includes a corresponding module for executing the above method. The module included in the processor can be implemented by software and / or hardware.

[0031] In a fourth aspect, the present application provides a processor, which can be used to execute a computer program to implement the method in the first aspect and any possible implementation manner of the first aspect.

[0032] In a fifth aspect, the present application provides a physical layer chip, which can be used to implement the method in the second aspect and any possible implementation of the second aspect. The physical layer chip includes a corresponding module for executing the above method. The module included in the physical layer chip can be implemented by software and / or hardware.

[0033] In a sixth aspect, the present application provides a physical layer chip, which can be used to execute a computer program to implement the method in the second aspect and any possible implementation manner of the second aspect.

[0034] In a seventh aspect, the present application provides a physical layer chip system, which may include m processors and h physical layer chips, the m processors are used to initialize the h physical layer chips, m≥1, h≥2, m and h are integers; wherein the first processor among the m processors is used to support the implementation of the functions involved in the above-mentioned first aspect and any possible implementation method of the first aspect, or the first physical layer chip among the h physical layer chips is used to support the implementation of the functions involved in the above-mentioned second aspect and any possible implementation method of the second aspect, for example, processing the data involved in the above-mentioned method, etc.

[0035] In one possible design, the physical layer chip system also includes a memory, which is used to store program instructions and data, and the memory is located inside or outside the first processor.

[0036] The physical layer chip system may be composed of a chip, or may include a chip and other discrete devices.

[0037] In an eighth aspect, the present application provides a vehicle, which can be used to implement the method in the first aspect and any possible implementation of the first aspect, and / or can be used to implement the method in the second aspect and any possible implementation of the second aspect. The vehicle includes a corresponding module for executing the above method. The module included in the vehicle can be implemented by software and / or hardware.

[0038] In a ninth aspect, the present application provides a vehicle, the vehicle comprising at least one processor and at least one communication interface. The processor is coupled to the communication interface and can be used to execute a computer program to implement the method in the first aspect and any possible implementation of the first aspect.

[0039] Optionally, the vehicle further includes a memory, and the processor is coupled to the memory.

[0040] In a tenth aspect, the present application provides a vehicle comprising a physical layer chip that can be used to execute a computer program to implement the method in the second aspect and any possible implementation of the second aspect.

[0041] In the eleventh aspect, the present application provides a vehicle, which includes the above-mentioned physical layer chip system, and the vehicle can be used to implement the method in the above-mentioned first aspect and any possible implementation of the first aspect, and / or can be used to implement the method in the above-mentioned second aspect and any possible implementation of the second aspect.

[0042] In the twelfth aspect, a readable storage medium is provided, on which a program (also referred to as code, or instruction) is stored. When the program is run, the method in the above-mentioned first aspect and any possible implementation of the first aspect is executed, and / or the method in the above-mentioned second aspect and any possible implementation of the second aspect is executed.

[0043] In the thirteenth aspect, a program product is provided, comprising: a program (also referred to as code, or instruction), wherein when the program is run, the method in the above-mentioned first aspect and any possible implementation of the first aspect is executed, and / or the method in the above-mentioned second aspect and any possible implementation of the second aspect is executed.

[0044] It should be understood that the third to thirteenth aspects of the present application correspond to the technical solutions of the first and second aspects of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a structural diagram of the physical layer chip system;

[0046] Figure 2 is a schematic flow chart of a method for initializing a physical layer chip;

[0047] Figure 3 is another structural schematic diagram of a physical layer chip system applicable to the physical layer chip initialization method provided in an embodiment of the present application;

[0048] Figure 4 It is another structural schematic diagram of a physical layer chip system applicable to the physical layer chip initialization method provided in the embodiment of the present application;

[0049] Figure 5 is a schematic flow chart of a method for initializing a physical layer chip provided in an embodiment of the present application;

[0050] Figure 6 is a schematic diagram of a first processor provided in an embodiment of the present application communicating with n physical layer chips in a broadcasting manner based on a first address;

[0051] Figure 7It is a schematic diagram of a vehicle applicable to the method for initializing the physical layer chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0053] First, in this application, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a device, system, product or equipment comprising a series of modules, modules or units is not necessarily limited to those modules, modules or units explicitly listed, but may include other modules, modules or units that are not explicitly listed or inherent to these devices, systems, products or equipment.

[0054] Second, in this application, the words "exemplarily", "for example", etc. are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0055] Third, in the present application, "when...", "in the case of...", "if" and "if" all mean that the device will take corresponding actions under certain objective circumstances, but do not limit the time, nor do they require that the device must have a judgment action when it is implemented, nor do they mean that there are other limitations.

[0056] Fourth, in this application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first data and the second data are used to distinguish between different data, and do not limit their order. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily mean that they are different.

[0057] Fifth, in this application, preset can be understood as predefined, defined, predefined, stored, pre-stored, pre-negotiated, or pre-configured, etc.

[0058] Sixth, in this application, "at least one" means one or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship, but it does not exclude the situation where the previous and next associated objects are in an "and" relationship. The specific meaning can be understood in conjunction with the context.

[0059] Seventh, "sending" and "receiving" in this application indicate the direction of signal transmission. For example, "the first processor sends the first message to the n physical layer chips" can be understood as the destination end of the first message is the n physical layer chips, which can include direct sending through the air interface, and also include indirect sending through the air interface by other units or modules. "Each physical layer chip among the n physical layer chips receives the first message from the first processor" can be understood as the source end of the first message is the first processor, which can include directly receiving from the first processor through the air interface, and also include indirectly receiving from the first processor through the air interface from other units or modules. "Sending" can also be understood as the "output" of the chip interface, and "receiving" can also be understood as the "input" of the chip interface.

[0060] In other words, sending and receiving can be performed between devices, for example, between the first processor and the n physical layer chips; it can also be performed within the device, for example, sending or receiving between components, modules, chips, software modules or hardware modules within the device through a bus, wiring or interface.

[0061] Eighth, in this application, indication includes explicit indication (also called direct indication) and implicit indication (also called indirect indication). Among them, explicit indication information A means including the information A; implicit indication information A means indicating information A through the correspondence between information A and information B and directly indicating information B. The correspondence between information A and information B can be predefined, pre-stored, pre-burned, or pre-configured; or, it can also mean indicating information A through information B and preset rules.

[0062] First, a brief explanation of the terms involved in this application is given.

[0063] 1. Central Gateway: It can be referred to as Gateway (GW) for short. GW is the data exchange hub of the vehicle network, which enables data to be transmitted safely and reliably in multiple networks inside the vehicle (such as Controller Area Network (CAN), Local Interconnect Network (LIN), Media Oriented System Transport (MOST), FlexRay, etc.). The related hardware of GW can include switches, transceivers of various network types (CAN, LIN, MOST, FlexRay, etc.) and system chips.

[0064] 2. Vehicle control unit (VCU): It is the core electronic control unit that realizes the control decision of the whole vehicle. It is equivalent to the brain of the car, and can also be called the command and management center of the car. It plays the role of controlling the operation of the vehicle.

[0065] 3. Telematics box (T-BOX): The vehicle's external communication interface, which can provide remote control, remote query, security and other service functions.

[0066] In addition, the parameters involved in the embodiments of the present application are briefly described below.

[0067] h: the number of all PHY chips included in the PHY chip system, h≥2, h is an integer.

[0068] m: the number of processors included in the PHY chip system and used to initialize h PHY chips, m≥1, and m is an integer.

[0069] n: the number of PHY chips that the first processor among the m processors needs to initialize, 2≤n≤h, where n is an integer.

[0070] k: the number of physical layer chips among n physical layer chips for which port parameters are configured based on the second data, 0≤k≤n, and k is an integer.

[0071] With the development of the vehicle industry, the number of electronic components and the complexity of wiring in the vehicle have increased significantly. At the same time, with the continuous increase in the number of devices such as vehicle-mounted cameras and lidars, the scenarios of in-vehicle data transmission are constantly enriched, the amount of related data is surging, and the requirements for data bandwidth are gradually increasing. Traditional in-vehicle networks can no longer meet the current in-vehicle data transmission needs. With the evolution of electronic and electrical and autonomous driving technologies, in-vehicle Ethernet technology has gradually taken a dominant position. In-vehicle Ethernet PHY is one of the basic technologies in Ethernet technology. PHY chips are mainly used to realize signal transmission and conversion.

[0072] Figure 1 It is a structural diagram of the physical layer chip system.

[0073] like Figure 1 The physical layer chip system shown includes 1 processor and n PHY chips, for example, PHY chip 1, PHY chip 2, ..., PHY chip n, etc., where n≥2, and n is an integer. Figure 1As shown, in a possible implementation, the processor (or main control chip) and each PHY chip can be connected through a management data input / output (MDIO) bus, that is, the processor and each PHY chip can communicate through the MDIO bus. The MDIO bus is a shared bus, and each PHY chip has an independent address. When the processor initiates a read or write to the PHY chip, it will specify the corresponding MDIO address to operate the corresponding PHY chip.

[0074] Figure 2 The present invention is a schematic flow chart of a method for initializing a physical layer chip.

[0075] like Figure 2 As shown, each PHY chip corresponds to an independent address, that is, the addresses corresponding to each PHY chip are different, for example Figure 2 As shown, the PHY chip system includes n PHY chips, wherein the address of PHY chip 1 is address 1, the address of PHY chip 2 is address 2, and the address of PHY chip n is address n. When the processor initiates a read or write, it will specify an address to operate the corresponding PHY chip.

[0076] like Figure 2 As shown, to initialize the n PHY chips, the processor can specify addresses in sequence to initialize the corresponding PHY chips, such as Figure 2 a), the processor may first specify address 1 to select PHY chip 1, that is, initialize PHY chip 1 corresponding to address 1; after initialization of PHY chip 1 is completed, Figure 2 b), then specify address 2 to select PHY chip 2, that is, initialize PHY chip 2 corresponding to address 2; after initialization of PHY chip n-1 is completed, Figure 2 c), and then specify address n to select PHY chip n, that is, initialize the PHY chip n corresponding to address n. In this way, the processor realizes the initialization of the n PHY chips in a serial manner.

[0077] In this known physical layer chip initialization method, assuming that it takes t milliseconds (ms) to initialize a PHY chip, it takes t×n milliseconds to complete the initialization of the n PHY chips. That is, the larger the value of n is, the longer it takes to complete the initialization of the n PHY chips.

[0078] However, in some business scenarios, multiple physical layer chips need to be initialized quickly.

[0079] Figure 3 It is another structural schematic diagram of a physical layer chip system applicable to the physical layer chip initialization method provided in an embodiment of the present application.

[0080] By way of example and not limitation, Figure 3 As shown, the vehicle-mounted central gateway is an example of a physical layer chip system. The vehicle-mounted central gateway is located at the central forwarding node in the vehicle and is responsible for the forwarding core of each component of the vehicle. Therefore, it has more Ethernet ports and expands multiple high-speed Ethernet ports through the PHY chip.

[0081] It is understandable that the requirements for the startup performance of vehicle-mounted equipment are relatively high. Taking the above-mentioned vehicle-mounted central gateway as an example, the required startup time is in the hundreds of milliseconds, which is usually less than 300ms. The control channel of the vehicle-mounted PHY chip is the MDIO channel, which is a slow bus. When a PHY chip is initialized, it needs to access (read and write) hundreds of registers, that is, perform hundreds of MDIO read and write operations, which is time-consuming. In addition, an electronic control unit (ECU) device in a car will include multiple PHY chips, so the initialization time of all PHY chips must be multiplied by n times (n is the number of PHY chips included in the ECU device). In other words, using this known physical layer chip initialization method, it may not be possible to complete the startup of the central gateway within 300ms. In other words, this known physical layer chip initialization method cannot quickly complete the initialization of multiple PHY chips.

[0082] In addition, the initialization of each PHY chip may include access to hundreds (or even more) registers included in the PHY chip (for example, reading and / or writing to the registers), as well as configuration of the port parameters of the PHY chip, and the number of registers to which the configuration of the port parameters of the PHY chip is set is relatively small, that is, the configuration of the port parameters of the PHY chip takes relatively little time. Therefore, in the above-mentioned known physical layer chip initialization method, an important reason why the initialization of the PHY chip takes a long time is the access to the hundreds of registers included in the PHY chip.

[0083] In summary, the currently known initialization method of the physical layer chip takes a long time to initialize multiple PHY chips. Therefore, how to achieve rapid initialization of multiple physical layer chips has become a technical problem to be solved urgently. Therefore, the embodiment of the present application provides a method and a related device for initializing a physical layer chip, which shortens the time taken to initialize multiple PHY chips by initializing multiple PHY chips in parallel, so as to achieve rapid initialization of multiple PHY chips.

[0084] In order to better understand the initialization method of the physical layer chip provided in the embodiment of the present application, before introducing the initialization method of the physical layer chip provided in the embodiment of the present application, the following is combined with Figure 4 , the physical layer chip system applicable to the physical layer chip initialization method provided in the embodiment of the present application is described again.

[0085] Figure 4 It is another structural schematic diagram of a physical layer chip system applicable to the physical layer chip initialization method provided in the embodiment of the present application.

[0086] like Figure 4 The physical layer chip system shown may include m processors and h PHY chips, and the m processors may be used to initialize the h physical layer chips, where m≥1, h≥2, and m and h are integers. For example, processor 1 may initialize PHY chip 1, PHY chip 2, ..., and PHY chip n connected thereto; processor 2 may initialize PHY chip n+1, PHY chip n+2, ..., and PHY chip n+x connected thereto, where x is an integer greater than or equal to 2; processor 3 may initialize PHY chip h, PHY chip h-1, ..., and PHY chip hy connected thereto, where y is an integer greater than or equal to 2.

[0087] In the present application, when m≥2, the m processors may or may not be connected to each other. In other words, the m processors may or may not communicate with each other, and the present application does not impose any limitation on this.

[0088] like Figure 4 As shown, in a possible implementation, the physical layer chip system may further include a master controller, which may be connected to the m processors, and the master controller may control the h PHY chips. As an example but not limitation, the master controller in the vehicle may be a VCU or a central controller.

[0089] The physical layer chip initialization method provided in the embodiment of the present application can be applied to a system including h physical layer chips, and the system includes m processors for initializing the h physical layer chips. The method includes: after a first processor among the m processors is powered on, the first processor initializes n physical layer chips in parallel, and the n physical layer chips belong to the h physical layer chips. Figure 4 As shown, any processor in the physical layer chip system can be an example of a first processor.

[0090] Figure 5 It is a schematic flow chart of the initialization method of the physical layer chip provided in an embodiment of the present application.

[0091] like Figure 5 As shown, method 500 may include steps 510 to 530. Figure 5 Detailed description of each step in.

[0092] In step 510, the first processor obtains a first message.

[0093] The first processor is one of the m processors included in the physical layer chip system, or any one of the m processors. In a possible implementation, the first processor is an MCU or a SOC, which is not limited in this application.

[0094] The first message includes first data for initializing n physical layer chips connected to the first processor. It is understandable that the n physical layer chips belong to the h physical layer chips included in the above-mentioned physical layer chip system. The destination address field of the first message is a first address, and the first address is used to indicate the n physical layer chips, that is, the n physical layer chips can be selected through the first address, that is, the n physical layer chips can respond to the message whose destination address field is the first address. It is understandable that the first address can be a reserved address, or a pre-configured address, and the present application does not limit this.

[0095] After the first processor is powered on, the first processor may obtain the first message.

[0096] In a possible implementation manner, the first processor obtains the first message, including: the first processor generates the first message.

[0097] In this implementation manner, after the first processor is powered on, the first processor can autonomously generate the first message.

[0098] In another possible implementation, the first processor obtains the first message, including: the first processor receives the first message from a general controller, the general controller is connected to the m processors, and the general controller controls the h physical layer chips.

[0099] In this implementation, after the first processor is powered on, the first processor can receive the first message from the master controller. That is, the first message can be generated by the master controller. For a detailed description of the master controller, please refer to the above Figure 3 For the sake of brevity, the relevant instructions in are not repeated here.

[0100] In step 520, the first processor sends the first message to the n physical layer chips. Accordingly, each of the n physical layer chips receives the first message from the first processor.

[0101] Taking the first physical layer chip among the n physical layer chips as an example, the first physical layer chip receives the first message from the first processor. It can be understood that the first physical layer chip is one of the n physical layer chips connected to the first processor, or the first physical layer chip is any one of the n physical layer chips.

[0102] That is to say, after acquiring the first message, the first processor may send the first message to the n physical layer chips connected to it in a broadcast manner.

[0103] Figure 6 It is a schematic diagram of a first processor provided in an embodiment of the present application communicating with n physical layer chips in a broadcasting form based on a first address.

[0104] like Figure 6 As shown, the destination address field of the first message is the first address, and the first address can be used to indicate the n physical layer chips. That is to say, the n physical layer chips can be selected through the first address, that is, the n physical layer chips can all respond to the message whose destination address field is the first address.

[0105] In a possible implementation, the first processor sends the first message to the n physical layer chips, including: the first processor sends the first message to the n physical layer chips through the MDIO bus. Correspondingly, the first physical layer chip receives the first message from the first processor, including: the first physical layer chip receives the first message from the first processor through the MDIO bus.

[0106] In this implementation, if Figure 1 As shown, the first processor and the n physical layer chips can be connected via an MDIO bus. Therefore, the first processor can send the first message to the n physical layer chips via the MDIO bus, that is, based on the first address and through the MDIO bus, the first message is sent to the n physical layer chips in the form of broadcast.

[0107] In a possible implementation, the first address is MDIO address 0.

[0108] In this implementation, the first address may be set to MDIO address 0, and the first message may be sent to the n physical layer chips in a broadcasting manner using MDIO address 0.

[0109] It is understandable that MDIO address 0 may be an example of the first address and should not impose any limitation on the application. That is, in actual application scenarios, the first address may also be set to other addresses, and this application does not limit this.

[0110] In actual application scenarios, the first processor and the n PHY chips may also be connected via other buses, which is not limited in this application.

[0111] The first processor and the n PHY chips may also be connected via other buses, for example, including but not limited to Ethernet (ETH) bus, etc., which is not limited in the present application.

[0112] In step 530, when the destination address field of the first message is the first address or the address of the first physical layer chip, the first physical layer chip is initialized based on the first data in the first message.

[0113] After the first PHY chip receives the message, the first PHY chip may first determine whether the message is related to the first PHY chip, that is, the first PHY chip may first determine whether the destination address field of the message is the first address or the address of the first PHY chip. In the case where the destination address field of the message is the first address or the address of the first PHY chip, the first PHY chip may determine that the message is related to the first PHY chip. In other words, after the first PHY chip receives the first message, the first PHY chip determines that the destination address field of the first message is the first address, and then determines that the first message is related to the first PHY chip, so that the first PHY chip can further parse the first message to obtain the first data in the first message, and then the first PHY chip can be initialized based on the first data.

[0114] As an example and not a limitation, the first data may include, but is not limited to, data related to the default interface mode configuration of the PHY chip, the sending and receiving parameter configuration, etc., which is not limited in this application.

[0115] exist Figure 3As mentioned in the relevant description, the initialization of each PHY chip may include access to hundreds (or even more) registers included in the PHY chip (for example, reading and / or writing to the registers), as well as configuration of the port parameters of the PHY chip. In the case where the first data includes data for accessing the registers included in the PHY chip, but does not include data for configuring the port parameters of the PHY chip, the first PHY chip is initialized based on the first data, which can be understood as the first PHY chip accessing the registers in the first PHY chip based on the first data. In the case where the first data includes data for accessing the registers included in the PHY chip, and also includes data for configuring the port parameters of the PHY chip, the first PHY chip is initialized based on the first data, which can be understood as the first PHY chip accessing the registers in the first PHY chip based on the first data, and configuring the port parameters of the first PHY chip based on the first data.

[0116] In a possible implementation manner, the first message further includes second data, and the second data is used for configuring port parameters of k physical layer chips among the n physical layer chips, where 0≤k≤n, and k is an integer.

[0117] As an example and not a limitation, the second data may include but is not limited to data of differential configurations between different projects, mainly including content such as port master-slave modes, etc., which is not limited in this application.

[0118] It can be understood that in this implementation, the above-mentioned first data may include data on access to hundreds (or even more) registers included in the PHY chip, but does not include data on configuration of port parameters of the PHY chip, while the second data includes data on configuration of port parameters of the PHY chip.

[0119] That is, in the case where the first PHY chip is one of the k PHY chips, the first PHY chip can access hundreds (or even more) registers in the first PHY chip based on the first data in the first message (for example, read and / or write to the registers), and configure the port parameters of the first PHY chip based on the second data. In the case where the first PHY chip is not any of the k chips, the first PHY chip can access hundreds (or even more) registers in the first PHY chip based on the first data in the first message (for example, read and / or write to the registers), without configuring the port parameters of the first PHY chip based on the second data.

[0120] It can be understood that in this implementation manner, the first message may further indicate which several (i.e., k) PHYs are based on which data in the second data to configure the port parameters of the PHY chips, and the present application does not limit the specific indication manner.

[0121] In a possible implementation manner, when the first message includes the second data, any one of the n PHY chips may not configure the port parameters based on the second data, that is, k = 0. By way of example and not limitation, for example, the first message may not only include the second data, but also include a first field, and the first field may be used to indicate which k of the n PHY chips configure the port parameters based on the second data. When this field is empty or "NULL", that is, any one of the n PHY chips does not need to configure the port parameters based on the second data.

[0122] In a possible implementation manner, the first message may further include a second field, and the second field is used to indicate the addressing manner of the k PHY chips for the second data, that is, which bits of data in the second data the k PHY chips are respectively based on to configure the port parameters.

[0123] By way of example and not limitation, for example, the second field indicates addressing the second data based on the address number of the PHY chip. For example, the one with a smaller address number performs addressing the second data first, and each PHY chip may take a preset number of bits of the second data to configure the port parameters. It can be understood that in this implementation manner, when the total number of bits of the second data < n × the preset number of bits (that is, k < n), there may be at least one PHY chip that does not need to configure the port parameters of the first PHY chip based on the second data.

[0124] When the first message does not include the data for configuring the port parameters of the PHY chip, the first processor may subsequently broadcast the data for configuring the port parameters of the n PHY chips to the n PHY chips, so that the n PHY chips can configure the port parameters in parallel; or, the first processor may also serially send the data for configuring the port parameters of the n PHY chips to the n PHY chips in sequence, so that the n PHY chips can configure the port parameters serially in sequence. The present application does not make any limitation on this.

[0125] Based on the above scheme, the processor can send the data required for initializing the multiple PHY chips to the multiple PHY chips connected to the processor in a broadcast manner, so that the multiple PHY chips can be initialized in parallel, thereby shortening the time consumed for initializing the multiple PHY chips, thereby achieving rapid initialization of the multiple PHY chips.

[0126] The embodiment of the present application further provides a processor, which includes corresponding modules for executing the steps executed by the first processor in the above method 500. The modules included in the processor can be implemented in software and / or hardware.

[0127] An embodiment of the present application also provides a processor, which can be used to call and execute a computer program so that the processor executes the steps of the first processor in the above method 500.

[0128] In a possible implementation, the processor may be an MCU or a SOC.

[0129] The embodiment of the present application further provides a physical layer chip, which includes corresponding modules for executing the steps executed by the first physical layer chip in the above method 500. The modules included in the physical layer chip can be implemented by software and / or hardware.

[0130] The embodiment of the present application further provides a physical layer chip, which can be used to call and execute a computer program so that the processor executes the steps of the first physical layer chip in the above method 500.

[0131] An embodiment of the present application further provides a physical layer chip system, which may include m processors and h physical layer chips, wherein the m processors are used to initialize the h physical layer chips, m≥1, h≥2, and m and h are integers; wherein a first processor among the m processors is used to execute the steps of the first processor in the above method 500; or, a first physical layer chip among the h physical layer chips is used for the steps of the first physical layer chip in the above method 500.

[0132] In one possible design, the physical layer chip system also includes a memory, which is used to store program instructions and data, and the memory is located inside or outside the first processor.

[0133] The physical layer chip system may be composed of a chip, or may include a chip and other discrete devices.

[0134] The embodiment of the present application further provides a vehicle, which includes corresponding modules for executing the steps in the above method 500. The modules included in the vehicle can be implemented in software and / or hardware.

[0135] An embodiment of the present application also provides a vehicle, which includes a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call and execute the computer program, so that the vehicle executes the steps of the first processor in the above method 500.

[0136] An embodiment of the present application also provides a vehicle, which includes a physical layer chip, so that the vehicle executes the steps of the first physical layer chip in the above method 500.

[0137] An embodiment of the present application also provides a vehicle, which includes the above-mentioned physical layer chip system, so that the vehicle executes the steps in the above-mentioned method 500.

[0138] Figure 7 It is a schematic diagram of a vehicle applicable to the method for initializing the physical layer chip provided in an embodiment of the present application.

[0139] like Figure 7 As shown, a vehicle suitable for the initialization method of the physical layer chip provided in an embodiment of the present application may include the above-mentioned physical layer chip system, which may include a T-BOX module, an advanced driving assistance system (ADAS) module, a GW module, an intelligent cockpit domain controller (CDC) module, and a mobile data center (MDC, which is an intelligent driving computing power platform) module, etc. Each of the above modules may include a processor and multiple PHY chips, and the processor connected to the multiple PHY chips in each module may be an example of the above-mentioned first processor, and any one of the multiple PHY chips may be an example of the above-mentioned first PHY chip.

[0140] In a possible implementation, the physical layer chip system may further include a master controller, which may be connected to the processors in the multiple modules, and the master controller may control the multiple PHY chips connected to the processors in the multiple modules. As an example and not a limitation, the master controller in the automotive field may be a VCU or a central controller.

[0141] The method provided in the embodiment of the present application can be applied to various vehicle-mounted ECUs, and is particularly suitable for multi-Ethernet port devices, including but not limited to central network devices, central controllers, and other ECUs involved in Ethernet communication in the vehicle.

[0142] The embodiment of the present application also provides a readable storage medium on which a program is stored. When the program is executed by a device, the device executes the above Figure 5The steps involved.

[0143] The embodiment of the present application also provides a program product, including a program, which, when executed, enables the device to execute the above Figure 5 The steps involved.

[0144] It should be understood that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor can be combined to perform. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0145] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0146] The terms "unit", "module", etc. used in this specification may be used to represent an entity related to a device or an apparatus, hardware, firmware, a combination of hardware and software, software, or software in execution.

[0147] It will be appreciated by those skilled in the art that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in combination with software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. In the several embodiments provided in this application, it should be understood that the disclosed devices, equipment and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0148] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0149] In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more units may be integrated into one module.

[0150] In the above embodiments, the functions of each functional module can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a program product. The program product includes one or more instructions (programs). When the program instructions (programs) are loaded and executed on a device or apparatus, the process or function described in the embodiment of the present application is generated in whole or in part. The instructions can be stored in a readable storage medium, or transmitted from one readable storage medium to another readable storage medium, for example, the instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The readable storage medium can be any available medium that can be accessed by a device or apparatus or a data storage device such as a server or data center that contains one or more available media integrations. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disk (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0151] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The software product is stored in a storage medium and includes several instructions for enabling a device or apparatus (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0152] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for initializing a physical layer chip, It is characterized in that The method is applied to a system including h physical layer chips, and the system includes m processors for initializing the h physical layer chips, where h≥2, m≥1, and m and h are integers. The method includes: After a first processor among the m processors is powered on, the first processor initializes n physical layer chips in parallel, where the n physical layer chips belong to the h physical layer chips, 2≤n≤h, and n is an integer.

2. The method according to claim 1, It is characterized in that The first processor initializes n physical layer chips in parallel, including: The first processor obtains a first message, where the first message includes first data for initializing the n physical layer chips, where a destination address field of the first message is a first address, and where the first address is used to indicate the n physical layer chips; The first processor sends the first message to the n physical layer chips.

3. The method according to claim 2, It is characterized in that The first processor sending the first message to the n physical layer chips includes: The first processor sends the first message to the n physical layer chips via a management data input and output MDIO bus.

4. The method according to claim 3, It is characterized in that The first address is MDIO address 0.

5. The method according to any one of claims 2 to 4, It is characterized in that The first processor obtains a first message, including: The first processor generates the first message; or, The first processor receives the first message from a general controller, the general controller is connected to the m processors, and the general controller controls the h physical layer chips.

6. The method according to any one of claims 2 to 5, It is characterized in that The first message also includes second data, and the second data is used for configuring port parameters of k physical layer chips among the n physical layer chips, 0≤k≤n, and k is an integer.

7. The method according to any one of claims 1 to 6, It is characterized in that The first processor is a microcontroller unit MCU or a system on chip SOC.

8. A method for initializing a physical layer chip, It is characterized in that The method is applied to a system including h physical layer chips, and the system includes m processors for initializing the h physical layer chips, where h≥2, m≥1, and m and h are integers. The method includes: A first physical layer chip among the h physical layer chips receives a first message from the first processor, the first message includes first data for initializing n physical layer chips, the n physical layer chips belong to the h physical layer chips, and the n physical layer chips are connected to the first processor, the first physical layer chip is one of the n physical layer chips, 2≤n≤h, and n is an integer; When the destination address field of the first message is a first address or an address of the first physical layer chip, the first physical layer chip is initialized based on the first data, and the first address is used to indicate the n physical layer chips.

9. The method according to claim 8, It is characterized in that The first physical layer chip receives a first message from a first processor, including: The first physical layer chip receives the first message from the first processor through a management data input and output MDIO bus.

10. The method according to claim 9, It is characterized in that The first address is MDIO address 0.

11. The method according to any one of claims 8 to 10, It is characterized in that The first message is generated by the first processor; or, The first message is received by the first processor from a general controller, the general controller is connected to the m processors, and the general controller controls the h physical layer chips.

12. The method according to any one of claims 8 to 11, It is characterized in that The first message also includes second data, and the second data is used for configuring port parameters of k physical layer chips among the n physical layer chips, 0≤k≤n, and k is an integer.

13. The method according to any one of claims 8 to 12, It is characterized in that The first processor is a microcontroller unit MCU or a system on chip SOC.

14. A processor, It is characterized in that The processor comprises a module for executing the method according to any one of claims 1 to 7, or, The processor is used to call a program to execute the method according to any one of claims 1 to 7.

15. A physical layer chip, It is characterized in that The physical layer chip comprises a module for executing the method according to any one of claims 8 to 13, or, The physical layer chip is used to call a program to execute the method according to any one of claims 8 to 13.

16. A physical layer chip system, It is characterized in that It includes m processors and h physical layer chips, wherein the m processors are used to initialize the h physical layer chips, m≥1, h≥2, and m and h are integers; wherein, The first processor among the m processors is configured to execute the method according to any one of claims 1 to 7; or, The first physical layer chip among the h physical layer chips is used to execute the method according to any one of claims 8 to 13.

17. A vehicle, It is characterized in that The vehicle comprises means for performing the method as claimed in any one of claims 1 to 13, or, The vehicle comprises the physical layer chip system as claimed in claim 16, and the physical layer chip system is used to execute the method as claimed in any one of claims 1 to 13, or, The vehicle comprises a processor according to claim 14, wherein the processor is configured to execute the method according to any one of claims 1 to 7, or The vehicle comprises the physical layer chip according to claim 15 , and the physical layer chip is used to execute the method according to any one of claims 8 to 13 .

18. A readable storage medium having a program stored thereon, It is characterized in that When the program is executed, the method according to any one of claims 1 to 13 is performed.

19. A program product, It is characterized in that The invention comprises a program, which, when being executed, enables the method according to any one of claims 1 to 13 to be performed.

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