Memory device testing management method and apparatus, electronic device, and storage medium

By obtaining the standard configuration information of the memory device, determining a unique ID identifier and associating it with test results, and generating log files and data packets, the systemic and accuracy issues of memory device test management are resolved, and efficient data traceability and management are achieved.

CN120104409BActive Publication Date: 2025-12-19SHENZHEN JINGCUN TECH CO LTD
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Patent Information

Application Number
CN202510073055.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-01-17
Publication Date
2025-12-19
Estimated Expiration
2045-01-17

AI Technical Summary

Technical Problem

Existing memory testing management methods lack systematicity and accuracy, and cannot effectively record and integrate test results, leading to difficulties in subsequent traceability and management.

Method used

By obtaining the standard configuration information of the memory, a unique ID is determined, and the test results are associated with it to generate log files, which are then integrated into log data packages. Logical tables and rule engines are used for data filtering and format conversion.

Benefits of technology

It achieves clarity and standardization of memory test results, improves query efficiency and data readability, supports multi-condition queries, and facilitates product quality traceability and fault diagnosis.

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Abstract

The application discloses a memory device test management method and device, electronic equipment and storage medium, and relates to the technical field of test management, which comprises the following steps: obtaining standard configuration information of the memory device; obtaining a plurality of number information about the register according to the standard configuration information; determining the unique ID identification corresponding to the memory device from the corresponding register through identification combination processing according to the number information; performing a preset performance test on the memory device to obtain a test result; generating a log file according to the test result and the corresponding unique ID identification; and integrating the log files of a plurality of memory devices to obtain a log data packet. The application can improve the management clarity and standardization of the memory device test result.
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Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of test management, and particularly relates to a memory device test management method and device, electronic equipment and a storage medium. BACKGROUND

[0002] In modern electronic equipment, the memory device is a key component, and its performance and stability directly affect the operation of the entire equipment. With the rapid development of technology, the functions of electronic equipment are becoming increasingly complex, and the requirements for memory devices are also becoming higher and higher. In the production and use of memory devices, comprehensive and accurate test management is required.

[0003] Currently, in the field of memory device test management, there are many challenges. After the performance test of the memory device, there is a lack of effective means for recording and integrating the test results, and the test results cannot be accurately associated with the memory device. The traditional memory device test management method is scattered and chaotic, lacks systematicness and accuracy, and is not convenient for subsequent tracing and management of the log files of the test results. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a memory device test management method and device, electronic equipment and a storage medium, which can improve the management clarity and standardization of the memory device test results.

[0005] In a first aspect, the present application provides a memory device test management method, comprising:

[0006] obtaining standard configuration information of the memory device;

[0007] obtaining a plurality of number information about the register according to the standard configuration information;

[0008] determining the unique ID of the memory device according to the number information through identification and combination processing;

[0009] performing a preset performance test on the memory device to obtain a test result;

[0010] generating a log file according to the test result and the corresponding unique ID;

[0011] integrating the log files of a plurality of memory devices to obtain a log data packet.

[0012] According to the memory device test management method of the first aspect of the present application, the following beneficial effects are achieved: the standard configuration information is obtained, the standard configuration information obtained is analyzed and processed according to the pre-set rules and algorithms, and a plurality of register number information is extracted, the register corresponding to the number information records the identification information of the memory device, the identification information read is subjected to specific combination operation to determine the unique ID identification corresponding to the memory device. According to the pre-set performance test scheme, the performance of the memory device is tested in various actual use scenarios to obtain the test result of the performance data of the memory device in various actual use scenarios. The test result obtained is closely associated with the unique ID identification, and the corresponding log file is generated according to the unified and standardized log format requirement. The log files generated by the plurality of memory devices are collected and sorted to finally form a complete log data package. By determining the unique ID identification, each memory device has a clear and unique identity in the test management process, and the test result is associated with the unique ID identification. The memory device ID and the test result are accurately recorded in the generated log file, so that in the subsequent tracing and management process, the test data corresponding to each memory device can be quickly and accurately found, and the management clarity and standardization of the test result of the memory device are improved.

[0013] According to some embodiments of the first aspect of the present application, the unique ID identification corresponding to the memory device is determined by identifying and combining processing according to the number information, comprising:

[0014] According to the number information, a logical table is established; wherein the logical table comprises a plurality of units, and the number of units matches the number of number information;

[0015] According to the order of the number information, the data in each register is read in sequence to obtain an ID sub-identification;

[0016] The ID sub-identification is sequentially filled into the units of the logical table;

[0017] According to the filled logical table, a unique ID identification is obtained through a pre-set combination order.

[0018] According to some embodiments of the first aspect of the present application, each unit of the logical table comprises an abscissa and an ordinate;

[0019] According to the filled logical table, a unique ID identification is obtained through a pre-set combination order, comprising:

[0020] According to the order from small to large of the abscissa, a first priority order is set;

[0021] According to the order from small to large of the ordinate, a second priority order is set; wherein, the priority of the first priority order is higher than the priority of the second priority order;

[0022] According to the first priority order and the second priority order, the ID sub-identifiers in the unit are combined in sequence to obtain a unique ID identifier.

[0023] According to some embodiments of the first aspect of the application, the generating a log file according to the test result and the corresponding unique ID identifier comprises:

[0024] Obtaining a test order number and a test timestamp about the memory device;

[0025] Generating a log file according to the test result, the corresponding unique ID identifier, the test order number and the test timestamp.

[0026] According to some embodiments of the first aspect of the application, after the step of integrating the log files of the plurality of memory devices to obtain a log data packet, the method further comprises:

[0027] Obtaining at least one of a query ID identifier, a query time period or a query order number;

[0028] According to the query ID identifier, the query time period or the query order number, performing data filtering based on the log data packet to obtain the log file meeting the condition.

[0029] According to some embodiments of the first aspect of the application, after the step of obtaining at least one of a query ID identifier, a query time period or a query order number, performing data filtering based on the log data packet to obtain the log file meeting the condition, the method further comprises:

[0030] Obtaining a rule engine;

[0031] Performing information extraction on the filtered log file to obtain a test data feature set;

[0032] Based on the rule engine, performing format conversion on the test data feature set to obtain a test data result table convenient for checking.

[0033] According to some embodiments of the first aspect of the application, the performing a preset performance test on the memory device to obtain a test result comprises:

[0034] Writing a preset test sequence into the memory device;

[0035] After the test sequence is completed to be written into the memory device, reading the memory device to obtain a target sequence;

[0036] According to the test sequence and the target sequence, a test result is obtained.

[0037] In a second aspect, the present application further provides a management device for memory testing, comprising:

[0038] An acquisition unit is configured to acquire standard configuration information of the memory;

[0039] A processing unit is configured to obtain a plurality of number information about the memory according to the standard configuration information;

[0040] A determination unit is configured to determine a unique ID corresponding to the memory by identifying combination processing according to the number information;

[0041] A test unit is configured to perform a preset performance test on the memory to obtain a test result;

[0042] A generation unit is configured to generate a log file according to the test result and the corresponding unique ID;

[0043] An integration unit is configured to integrate log files of a plurality of memories to obtain a log data packet.

[0044] In a third aspect, the present application further provides an electronic device, comprising:

[0045] At least one memory;

[0046] At least one processor;

[0047] At least one program;

[0048] The program is stored in the memory, and the processor executes at least one of the programs to implement the management method for memory testing according to any one of the embodiments of the first aspect.

[0049] In a fourth aspect, the present application further provides a computer readable storage medium, which stores computer executable signals, and the computer executable signals are used to execute the management method for memory testing according to any one of the embodiments of the first aspect.

[0050] Additional aspects and advantages of the present application will be given in part in the following description, become apparent from the following description, or be understood by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0051] Additional aspects and advantages of the present application will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:

[0052] Figure 1 A flowchart of the management method for memory testing provided by some embodiments of the present application;

[0053] Figure 2 for the flowchart in the present application Figure 1 regarding step S130;

[0054] Figure 3 for the flowchart in the present application Figure 2 regarding step S240;

[0055] Figure 4 for the flowchart in the present application Figure 1 regarding step S150;

[0056] Figure 5 for the flowchart in the present application Figure 1 regarding step S160;

[0057] Figure 6 for the flowchart in the present application Figure 5 regarding step S520;

[0058] Figure 7 for the flowchart in the present application Figure 1 regarding step S140. DETAILED DESCRIPTION

[0059] Embodiments of the present application are described below in detail with reference to the accompanying drawings, wherein the same or similar components or components having the same or similar functions are denoted by the same or similar reference numerals throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are only used to explain the present application and cannot be understood as limiting the present application.

[0060] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or position relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or component referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0061] In the description of the present application, if the first, second, etc. are described for the purpose of distinguishing technical features, it cannot be understood as indicating or implying the relative importance of the technical features indicated or implying the number of technical features indicated or implying the order of the technical features indicated.

[0062] In the description of the present application, unless otherwise explicitly limited, the words such as arrangement, installation, connection, etc. should be broadly understood, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0063] In modern electronic devices, memory as a key component, its performance and stability directly affect the operation of the entire device. With the rapid development of science and technology, the function of electronic equipment is increasingly complex, and the demand for memory is also increasing. In the production and use of memory, it needs to be tested comprehensively and accurately.

[0064] At present, in the aspect of memory test management, there are many challenges. After the performance test of the memory, the record and integration of the test results also lack effective means, which cannot accurately associate the test results with the memory. The traditional memory test management method is scattered and chaotic, lacks systematicness and accuracy, and is not convenient for subsequent tracing and management of the log file of the test results.

[0065] Based on this, the present application provides a memory test management method, device, electronic equipment and storage medium to solve the technical problems proposed above. The technical solutions provided by the present application are described in detail one by one as follows.

[0066] In the first aspect, with reference to Figure 1 The present application provides a memory test management method, including but not limited to the following steps:

[0067] Step S110: obtaining the standard configuration information of the memory;

[0068] Step S120: obtaining a plurality of number information about the register according to the standard configuration information;

[0069] Step S130: determining the unique ID identification corresponding to the memory from the corresponding register by recognizing and combining according to the number information;

[0070] Step S140: performing a preset performance test on the memory to obtain a test result;

[0071] Step S150: generating a log file according to the test result and the corresponding unique ID identification;

[0072] Step S160: integrating the log files of a plurality of memories to obtain a log data packet.

[0073] In steps S110 to S160, the standard configuration information is obtained, and the standard configuration information obtained is parsed and processed according to a preset rule and algorithm, and a plurality of number information about the registers is extracted, the register corresponding to the number information records the identification information about the register, and the identification information read is subjected to specific combination operation to determine the unique ID identification corresponding to the register. According to the performance test scheme prepared in advance, the performance of the register is tested comprehensively, so as to obtain the test result of the performance of the register in various actual use scenarios. The test result obtained is closely associated with the corresponding unique ID identification, and the corresponding log file is generated according to the unified and standardized log format requirement. The log files generated by the plurality of registers are collected and arranged, and finally a complete log data package is formed. By determining the unique ID identification, each register has a clear and unique identity in the test management process, and the test result is associated with the unique ID identification, and the register ID and the test result are accurately recorded in the log file, so that in the subsequent tracing and management process, the test data corresponding to each register can be quickly and accurately found, and the management clarity and standardization of the test result of the register are improved.

[0074] It should be noted that the standard configuration information in step S110 can be obtained by internal acquisition, and the standard configuration information is read from a specific storage area or register in the register according to a predetermined protocol and instruction. The standard configuration information can also be obtained by external acquisition, and the relevant information can be obtained from the user manual and other external materials of the register. By carefully checking the user manual, the content related to the configuration of the register is extracted.

[0075] Referring to Figure 2 It can be understood that in step S130, the following steps can be included but are not limited to the following steps:

[0076] Step S210: establishing a logical table according to the number information; wherein the logical table includes a plurality of units, and the number of units matches the number of number information;

[0077] Step S220: reading the data in each register in sequence according to the order of the number information to obtain an ID sub-identification;

[0078] Step S230: filling the ID sub-identification in the units of the logical table in sequence;

[0079] Step S240: obtaining the unique ID identification through the preset combination order according to the filled logical table.

[0080] In steps S210 to S240, by establishing a logical table and matching the number of units with the number of numbering information, the entire ID identification determination process is more orderly and structured, the ID sub-identifiers are read in the numbering information order to obtain the ID sub-identifiers, then the ID sub-identifiers are filled into the logical table units in sequence, and the unique ID identifier is obtained according to the filled logical table and the preset combination order. Through the above-mentioned way, the generation of the unique ID identifier has high standardization and repeatability.

[0081] With reference to Figure 3 It can be understood that each unit of the logical table includes a horizontal coordinate and a vertical coordinate. In step S240, the following steps can be included but are not limited to:

[0082] Step S310: According to the order of the horizontal coordinate from small to large, a first priority order is set;

[0083] Step S320: According to the order of the vertical coordinate from small to large, a second priority order is set; wherein the priority of the first priority order is greater than the priority of the second priority order;

[0084] Step S330: According to the first priority order and the second priority order, the ID sub-identifiers in the units are combined in sequence to obtain the unique ID identifier.

[0085] According to the order of the horizontal coordinate from small to large, a first priority order is set, and according to the order of the vertical coordinate from small to large, a second priority order is set. By setting the clear horizontal coordinate and vertical coordinate order rules and the priority relationship, the determinacy and uniqueness of the ID sub-identifier combination are ensured. This standardization also facilitates the subsequent maintenance and optimization of the algorithm and process. In the face of a large number of memory registers requiring ID identifier generation and management, this ordered combination method can efficiently process data.

[0086] For example, according to the standard configuration information, the number information of the registers is MR47, MR48, MR49, MR50, MR51, MR52, MR53 and MR54 respectively, and the ID sub-identifiers are A, B, C, D, E, F, G and H respectively extracted from the above 8 registers. In practice, the ID sub-identifiers can be a string composed of binary. Then, the ID sub-identifiers are filled into the cells of the logical table in turn. The logical table includes 8 cells, which are distributed in two rows and four columns. The horizontal coordinate of the first cell is 0, and the vertical coordinate is 0; the horizontal coordinate of the second cell is 0, and the vertical coordinate is 1; the horizontal coordinate of the fourth cell is 0, and the vertical coordinate is 3; the horizontal coordinate of the fifth cell is 1, and the vertical coordinate is 0; the horizontal coordinate of the eighth cell is 1, and the vertical coordinate is 3; and so on. Thus, A, B, C, D, E, F, G and H are filled into the first to eighth cells respectively, and the unique ID identifier obtained by combination according to the first priority order and the second priority order should be ABCDEFGH.

[0087] With reference to Figure 4 It can be understood that, in step S150, the following steps are included but not limited to:

[0088] Step S410: obtaining the test order number and test timestamp of the memory device;

[0089] Step S420: generating a log file according to the test result, the corresponding unique ID identifier, the test order number and the test timestamp.

[0090] In steps S410 to S420, by introducing the test order number, each memory device test is associated with a specific order. In the product production process, when the quality of the memory devices of a batch or an order needs to be traced back, the corresponding log file can be quickly located according to the test order number to understand the detailed test situation of the memory devices of the order, including various performance indicators, whether there is a problem, etc., greatly improving the accuracy and efficiency of product quality traceability. Integrating the test result, the unique ID identifier, the test order number and the test timestamp in the log file enriches the content of the log file, so that each log file becomes an independent recording unit containing comprehensive information. This not only facilitates in-depth analysis of the test situation of a single memory device, but also provides a more complete and reliable data basis for the entire memory device test management system, facilitating data statistics, analysis and mining, and providing a strong basis for decision-making.

[0091] With reference to Figure 5 It can be understood that, after step S160, the following steps are included but not limited to:

[0092] Step S510: obtaining at least one of the ID identifier to be queried, the time period to be queried or the order number to be queried.

[0093] Step S520: According to the query ID identification, the to-be-queried time period, or the to-be-queried order number, data filtering is performed based on the log data packet to obtain a log file meeting the condition.

[0094] In steps S510 to S520, the required log file can be accurately found from a large number of log data packets according to conditions such as the to-be-queried ID identification, the to-be-queried time period, or the to-be-queried order number. For example, if the detailed test situation of a certain memory is to be viewed, the to-be-queried ID identification can be used to directly locate the log file corresponding to the memory, without the need to browse numerous irrelevant files one by one, thereby greatly improving the query efficiency. Meanwhile, multiple query conditions are supported, and the user can flexibly select according to actual needs. The test records of all memories in a certain period can be queried according to the time period, or the log files of all memories under a certain order can be queried according to the order number, thereby meeting the query needs of different scenarios.

[0095] With reference to Figure 6 It can be understood that, after step S520, the following steps are included but are not limited to the following steps:

[0096] Step S610: Obtain a rule engine;

[0097] Step S620: Perform information extraction on the filtered log file to obtain a test data feature set;

[0098] Step S630: Based on the rule engine, perform format conversion on the test data feature set to obtain a test data result table convenient for reading.

[0099] In steps S610 to S630, the test data feature set in the filtered log file is converted into a test data result table convenient for reading through the rule engine, and the originally complex and disordered log data is presented in a clear and intuitive table form. Whether it is a technical personnel, a management personnel, or other relevant personnel, key information can be quickly understood and obtained, thereby greatly improving the readability and usability of the data. Meanwhile, the test data result table after format conversion is more convenient for data analysis and mining, thereby greatly saving the time and effort of manual data processing.

[0100] With reference to Figure 7 It can be understood that, in step S140, the following steps are included but are not limited to the following steps:

[0101] Step S710: Write a preset test sequence into a memory;

[0102] Step S720: After the to-be-tested sequence is written into the memory, the memory is read to obtain a target sequence;

[0103] Step S730: obtaining a test result according to the test sequence and the target sequence.

[0104] In steps S710-S730, the read-write performance of the memory device can be accurately evaluated by writing the preset test sequence into the memory device, reading the target sequence, and comparing the two. The preset test sequence can include various types of data and operations, such as random data, continuous data, and combinations of read-write operations, to comprehensively detect the performance of the memory device under different conditions. In the test, when the target sequence does not match the test sequence, the possible fault points of the memory device can be quickly located according to the specific differences. For example, if the read data is incorrect, it may be due to a problem with the memory cell of the memory device; if the read speed is too slow, it may be due to a performance bottleneck in the read-write circuit or control chip. This helps to quickly diagnose faults and improve maintenance efficiency.

[0105] In a second aspect, the present application also provides a memory device test management apparatus, comprising:

[0106] An acquisition unit is configured to acquire standard configuration information of the memory device.

[0107] A processing unit is configured to obtain a plurality of number information of the registers according to the standard configuration information.

[0108] A determination unit is configured to determine a unique ID of the memory device from the corresponding registers by identifying and processing according to the number information.

[0109] A test unit is configured to perform a preset performance test on the memory device to obtain a test result.

[0110] A generation unit is configured to generate a log file according to the test result and the unique ID.

[0111] An integration unit is configured to integrate the log files of a plurality of memory devices to obtain a log data packet.

[0112] The specific embodiments of the memory device test management apparatus are basically the same as the specific embodiments of the memory device test management method described above, and will not be repeated here.

[0113] In a third aspect, the present application also provides an electronic device, comprising at least one memory, at least one processor, and at least one program, the program being stored in the memory, and the processor executing one or more programs to implement the above-mentioned memory device test management method.

[0114] In the electronic device, standard configuration information is acquired, the acquired standard configuration information is parsed and processed according to a pre-set rule and algorithm, and a plurality of register number information is extracted therefrom, the register corresponding to the number information records identification information about the register, and the read identification information is subjected to specific combination operation to determine the unique ID identification corresponding to the register. According to a pre-prepared performance test scheme, the register is subjected to comprehensive performance test to obtain the test result of the performance data of the register in various actual use scenarios. The obtained test result is closely associated with the corresponding unique ID identification, and a corresponding log file is generated according to unified and standardized log format requirements. The log files generated by the plurality of registers are collected and arranged to finally form a complete log data package. By determining the unique ID identification, each register has a clear and unique identity in the test management process, and the test result is associated with the unique ID identification, the register ID and the test result are accurately recorded when the log file is generated, so that the corresponding test data of each register can be quickly and accurately found in the subsequent tracing and management process, and the management clarity and standardization of the test result of the register are improved.

[0115] The memory can include a program storage area and a data storage area, wherein the program storage area can store an operating system, application programs required by at least one function; the data storage area can store related data of the above-mentioned memory test management method, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one disk storage device, a flash memory device or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory remotely arranged with respect to the processor, and these remote memories can be connected to the processing module through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and combinations thereof.

[0116] One or more signals are stored in the memory, and when executed by one or more processors, the memory test management method in any of the above method embodiments is executed.

[0117] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, the computer readable storage medium stores a computer program, and the computer program is executed by one or more processors, so that the above-mentioned one or more processors execute the memory test management method in the above-mentioned method embodiments.

[0118] The apparatus embodiments described above are only illustrative, wherein the units illustrated as separate components can or can not be physically separate, and the components illustrated as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purposes of the embodiments.

[0119] From the above description of the embodiments, those skilled in the art can understand that all or some of the steps in the method disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable signals, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally includes computer readable signals, data structures, program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

[0120] It should be understood that in this application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can mean that there are three cases of only A, only B, and A and B at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c, can mean a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0121] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the division of the above units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0122] The units described above as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. can be located in one place or can be distributed to a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0123] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0124] If the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that makes a contribution or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for making a computer device (such as a personal computer, a server, or a network device) execute all or part of the steps of the method of each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program storage media.

[0125] The embodiments of the present application are described in detail above in combination with the drawings, but the present application is not limited to the above embodiments, and within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the purpose of the present application.

Claims

1. A method of managing memory testing, the method comprising: The method comprises the following steps: acquiring standard configuration information of the memory device; obtaining a plurality of number information of registers according to the standard configuration information; determining a unique ID identifier corresponding to the memory device from the corresponding registers through identification and combination processing according to the number information; performing a preset performance test on the memory device to obtain a test result; generating a log file according to the test result and the corresponding unique ID identifier; integrating log files of a plurality of memory devices to obtain a log data packet; wherein, determining a unique ID identifier corresponding to the memory device from the corresponding registers through identification and combination processing according to the number information comprises: establishing a logical table according to the number information; wherein the logical table comprises a plurality of units, and the number of units matches the number of number information; reading data in each register in turn according to the order of the number information to obtain an ID sub-identifier; filling the ID sub-identifier into the units of the logical table in turn; obtaining a unique ID identifier through a preset combination order according to the filled logical table.

2. The management method of memory tests according to claim 1, characterized in that, Each unit of the logical table comprises an abscissa and an ordinate; obtaining a unique ID identifier through a preset combination order according to the filled logical table comprises: setting a first priority order according to the order from small to large of the abscissa; setting a second priority order according to the order from small to large of the ordinate; wherein the priority of the first priority order is higher than that of the second priority order; combining the ID sub-identifiers in the units in turn according to the first priority order and the second priority order to obtain a unique ID identifier.

3. The method of claim 1, wherein, The method comprises the following steps: obtaining a test order number and a test timestamp of the memory device; generating a log file according to the test result and the corresponding unique ID identifier, the test order number and the test timestamp.

4. The management method of memory tests according to claim 3, characterized in that, After the step of integrating log files of a plurality of memory devices to obtain a log data packet, the method further comprises the following steps: obtaining at least one of a query ID identifier, a query time period or a query order number; performing data filtering based on the log data packet to obtain the log file meeting the conditions according to the query ID identifier, the query time period or the query order number.

5. The management method of memory tests according to claim 4, characterized in that, After the step of performing data filtering based on the log data packet to obtain the log file meeting the conditions according to the query ID identifier, the query time period or the query order number, the method further comprises the following steps: obtaining a rule engine; extracting information from the filtered log file to obtain a test data feature set; performing format conversion on the test data feature set based on the rule engine to obtain a test data result table convenient for reading.

6. The method of claim 1, wherein, The method comprises the following steps: writing a preset test sequence into the memory device; after the test sequence is completed, reading the memory device to obtain a target sequence; According to the test sequence and the target sequence, a test result is obtained.

7. A management apparatus of a memory tester, characterized by, The method comprises the steps of: An acquisition unit is configured to acquire standard configuration information of the memory device. A processing unit is configured to obtain a plurality of number information of registers according to the standard configuration information. A determination unit is configured to determine a unique ID identifier corresponding to the memory device from the registers by identification combination processing according to the number information. A test unit is configured to perform a preset performance test on the memory device to obtain a test result. A generation unit is configured to generate a log file according to the test result and the unique ID identifier. An integration unit is configured to integrate log files of a plurality of memory devices to obtain log data packets. The determination unit is specifically configured to: establish a logical table according to the number information, wherein the logical table comprises a plurality of units, and the number of units matches the number of number information. read data in each register in sequence according to the order of the number information to obtain an ID sub-identifier. fill the ID sub-identifier into the units of the logical table in sequence. obtain a unique ID identifier through a preset combination order according to the filled logical table.

8. An electronic device, comprising: The method comprises the steps of: at least one memory; at least one processor; at least one program; The program is stored in the memory, and the processor executes at least one program to implement the memory testing management method of any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable signals, and the computer executable signals are used to execute the memory testing management method of any one of claims 1 to 6.

Citation Information

Patent Citations

  • Implementation method and a device of a device identification combination engine

    CN109492352A

  • Data splicing instruction processing method and data splicing instruction processing device

    CN111813447A