Bus hot plug and redundancy design system and method

Abstract

A bus hot plug and redundancy design system comprises a first chip, a second chip, a third chip, a fourth chip, a first terminal and a second terminal. Wherein the output end of the first chip is connected with the input end of the third chip through the MII interface, the output end of the third chip is connected with the input end of the first terminal, the output end of the first terminal is connected with the input end of the fourth chip, and the output end of the fourth chip is connected with the input end of the second chip through the MII interface; the output end of the first chip is connected with the input end of the second terminal through the USB interface, and the output end of the second terminal is connected with the input end of the second chip through the USB interface. According to the invention, the industrial bus can be converted into Ethernet data through the STM32 chip and the PHY chip or converted into USB signals through the STM32 chip, so that the industrial bus has a hot plug capability, and the problem that the industrial bus in the prior art does not have the hot plug capability is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial control equipment, and in particular to a bus hot plug and redundancy design system and method. Background Art

[0002] Industrial control equipment usually needs to withstand harsh working environments and high-intensity operation requirements, so the stability and reliability of its bus system are crucial. However, traditional industrial control equipment bus systems often face many challenges when dealing with equipment replacement, upgrades or failures. On the one hand, the hot-swap function of the equipment is limited, which may cause system downtime or data loss; on the other hand, there is a lack of effective redundancy mechanisms. Once the bus or key equipment fails, the entire system may be paralyzed.

[0003] In industrial control equipment, due to the particularity of application scenarios, most equipment needs to run for a long time and cannot be shut down. Therefore, when a device fails, it needs to be plugged in and out while powered on, that is, hot-swap technology, to ensure the continuous operation of the equipment. Due to the particularity of industrial control equipment applications, hot-swap technology is required, but general industrial buses do not have hot-swap capabilities. Therefore, it is necessary to process the industrial bus and apply related circuits to enable it to have hot-swap capabilities. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide a bus hot-plug and redundancy design system and method that overcomes the above problems or at least partially solves the above problems.

[0005] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0006] In the first aspect, an embodiment of the present invention discloses a bus hot-swap and redundant design system, comprising: a first chip, a second chip, a third chip, a fourth chip, a first terminal and a second terminal; wherein the output end of the first chip is connected to the input end of the third chip through an MII interface, the output end of the third chip is connected to the input end of the first terminal, the output end of the first terminal is connected to the input end of the fourth chip, and the output end of the fourth chip is connected to the input end of the second chip through the MII interface; the output end of the first chip is simultaneously connected to the input end of the second terminal through a USB interface, and the output end of the second terminal is connected to the input end of the second chip through the USB interface.

[0007] Furthermore, the first chip and the fourth chip are STM32 chips, and the second chip and the third chip are PHY chips.

[0008] Furthermore, the first terminal is an RJ45 terminal, and the second terminal is a USB-A terminal.

[0009] Furthermore, the first chip is used to communicate with other industrial bus communication chips, obtain other industrial bus data, and convert the other industrial bus data into MII data or USB signals.

[0010] Furthermore, when the first chip converts the other industrial bus data into MII data, the first chip transmits the data obtained from the other industrial bus communication chips to the third chip through the MII interface, the third chip converts the parallel data sent by the first chip into serial stream data, encodes the data according to the encoding rules of the physical layer, and then converts it into a differential analog signal to transmit the data to the network cable through the first terminal. The differential analog signal is then received by the fourth chip, and the fourth chip converts the differential analog signal into serial stream data according to the encoding rules of the physical layer, and transmits it to the second chip through the MII interface. The second chip then transmits the data to other industrial bus communication chips.

[0011] Furthermore, when the first chip converts the other industrial bus data into a USB signal, the first chip converts the data obtained from the other industrial bus communication chips into a USB signal through the USB interface and connects to the second terminal. The USB signal is then received by the second chip, and the second chip then passes the data to the other industrial bus communication chips.

[0012] Furthermore, the third chip converts the parallel data sent by the first chip into serial stream data, and encodes the data according to the encoding rules of the physical layer. The specific method includes: arranging each bit of the parallel data stream in sequence through a parallel / serial converter to form a serial data stream; encoding the serial data stream using a non-return-to-zero encoding method; and converting the encoded digital signal into a differential analog signal through the third chip.

[0013] Furthermore, the first chip converts the data obtained from other industrial bus communication chips into USB signals through the USB interface. The specific method includes: obtaining data from the industrial bus communication chip, performing data protocol conversion on the data according to different protocols between the industrial bus and the USB, converting the original data received from the industrial bus into a data format suitable for USB transmission, and encapsulating the data according to the USB data packet structure. The USB protocol divides the data into different packets, including at least data packets, control packets, and synchronization packets; defining the USB bus layer, USB transmission layer, and USB protocol layer during the transmission of USB data, and generating a signal suitable for USB transmission according to the defined data packet structure and transmission protocol.

[0014] In a second aspect, an embodiment of the present invention discloses a bus hot-swap and redundancy design method, including: a first chip communicates with other industrial bus communication chips to obtain other industrial bus data, and converts the other industrial bus data into MII data or USB signals;

[0015] When the first chip converts the other industrial bus data into MII data, the first chip transmits the data obtained from the other industrial bus communication chip to the third chip through the MII interface, the third chip converts the parallel data sent by the first chip into serial stream data, encodes the data according to the encoding rules of the physical layer, and then converts it into a differential analog signal to transmit the data to the network cable through the first terminal, and then the differential analog signal is received by the fourth chip, the fourth chip converts the differential analog signal into serial stream data according to the encoding rules of the physical layer, and transmits it to the second chip through the MII interface, and the second chip then transmits the data to the other industrial bus communication chip;

[0016] When the first chip converts the other industrial bus data into USB signals, the first chip converts the data obtained from other industrial bus communication chips into USB signals through the USB interface and connects to the second terminal. The USB signal is then received by the second chip, and the second chip then transmits the data to other industrial bus communication chips.

[0017] In a third aspect, an embodiment of the present invention discloses an electronic device, including:

[0018] one or more processors;

[0019] A memory for storing one or more programs;

[0020] When the one or more programs are executed by the one or more processors, the one or more processors implement the bus hot-plug and redundancy design method.

[0021] The beneficial effects of the above technical solution provided by the embodiment of the present invention include at least:

[0022] A bus hot-swap and redundant design system disclosed in the present invention comprises: a first chip, a second chip, a third chip, a fourth chip, a first terminal and a second terminal; wherein the output end of the first chip is connected to the input end of the third chip through an MII interface, the output end of the third chip is connected to the input end of the first terminal, the output end of the first terminal is connected to the input end of the fourth chip, and the output end of the fourth chip is connected to the input end of the second chip through the MII interface; the output end of the first chip is simultaneously connected to the input end of the second terminal through a USB interface, and the output end of the second terminal is connected to the input end of the second chip through a USB interface. The present invention can convert the industrial bus into Ethernet data through an STM32 chip and a PHY chip or into a USB signal through an STM32 chip, thereby having hot-swap capability, solving the problem that the industrial bus in the prior art does not have hot-swap capability.

[0023] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0025] Figure 1 This is a structural diagram of a bus hot-swap and redundant design system in Embodiment 1 of the present invention;

[0026] Figure 2 This is a schematic diagram of the structure of an electronic device in Example 3 of the present invention. DETAILED DESCRIPTION

[0027] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0028] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a bus hot-swap and redundancy design system and method.

[0029] Example 1

[0030] The present invention discloses a bus hot plug and redundancy design system, such as Figure 1 , including: a first chip, a second chip, a third chip, a fourth chip, a first terminal and a second terminal; wherein the output end of the first chip is connected to the input end of the third chip through the MII interface, the output end of the third chip is connected to the input end of the first terminal, the output end of the first terminal is connected to the input end of the fourth chip, and the output end of the fourth chip is connected to the input end of the second chip through the MII interface; the output end of the first chip is simultaneously connected to the input end of the second terminal through the USB interface, and the output end of the second terminal is connected to the input end of the second chip through the USB interface.

[0031] Specifically, Figure 1In this embodiment, the first chip and the fourth chip use STM32 chips, and the second chip and the third chip use PHY chips. Among them, STM32 is a series of microcontrollers based on ARM Cortex-M core launched by STMicroelectronics (STMicroelectronics), which are widely used in various embedded systems and industrial automation applications. The STM32 series chips have rich peripheral interfaces, powerful computing power and low power consumption characteristics, and are a very popular choice in embedded design. STM32 can be used as a processing unit to obtain data from an industrial bus communication chip, and convert the data into USB signal transmission through a USB interface. In this embodiment, the STM32 chip used can be any model, only requiring it to have an MII interface and a USB interface. PHY chip (Physical Layer Chip, physical layer chip) is one of the core components in network communication, responsible for converting the data in the network protocol stack from the link layer (MAC layer) to physical signals, and transmitting through physical media (such as cables, optical fibers). PHY chips are generally used in various communication standards, such as Ethernet, USB, Wi-Fi, CAN, etc., and play a role in physical signal generation and reception. PHY chips are key components that connect the data link layer to the physical medium and play a vital role in various communication technologies. Their role is to convert data from upper layer protocols (such as the MAC layer or controller) into signals suitable for transmission through physical media, and to receive and convert them. The selection and configuration of these chips depends on the specific communication standard (such as Ethernet, USB, CAN, Wi-Fi, etc.).

[0032] In this embodiment, the first terminal adopts an RJ45 terminal and the second terminal adopts a USB-A terminal; the RJ45 terminal (Registered Jack 45) is a common network connector, which is commonly used in Ethernet and other data communication networks. It is a standard network interface for connecting computers, routers, switches and other network devices. The RJ45 terminal is usually used with network cables of categories such as Cat5e, Cat6, and Cat6a, and can support high-speed data transmission. Easy to use and install: Compared with other types of connectors, the RJ45 terminal is easy to install and is widely used in home and enterprise networks. The RJ45 terminal has a high transmission speed: it supports high-bandwidth network transmission, can transmit high-speed Internet signals, and adapt to different network requirements (such as 10 / 100 / 1000Mbps or even higher). Low cost: RJ45 terminals and related accessories are low in price, easy to purchase, and have low maintenance costs. Strong compatibility: The RJ45 terminal is an international standard interface, widely used in various devices and network technologies, and has good compatibility. The USB-A terminal (Universal Serial Bus Type-A) is one of the most common USB interfaces, widely used for connection and data transmission of computers, smartphones, TVs, game consoles and other devices. The USB-A terminal is usually used to connect computers, chargers and other peripheral devices such as keyboards, mice, printers, storage devices, etc. Devices connected to the USB-A terminal usually have two functions: data transmission and power supply. During data transmission, the USB port transmits signals through the bus communication protocol; during power supply, the USB port transmits power to the external device through the power line.

[0033] In this embodiment, the first chip is used to communicate with other industrial bus communication chips, obtain other industrial bus data, and convert the other industrial bus data into MII data or USB signals. Specifically, the MII interface is a standard interface for transmitting data in a local area network (LAN), especially between Ethernet devices. MII is mainly used to connect the Ethernet physical layer (PHY) chip and the MAC (media access control) chip, responsible for the transmission and reception of data. USB signals use differential signals to transmit data, which means that there is a pair of complementary signals on the data line at the same time, namely a positive signal and a negative signal. Data can be transmitted by measuring the voltage difference between the two signals. The use of differential signals enhances the anti-interference ability of the signal, making the USB signal more stable and reliable during the transmission process. USB 3.0 and higher versions will use more complex signal transmission schemes to achieve higher data transmission speeds.

[0034] In some preferred embodiments, when the first chip converts the other industrial bus data into MII data, the first chip transmits the data obtained from the other industrial bus communication chips to the third chip through the MII interface, the third chip converts the parallel data sent by the first chip into serial stream data, encodes the data according to the encoding rules of the physical layer, and then converts it into a differential analog signal to transmit the data to the network cable through the first terminal. The differential analog signal is then received by the fourth chip, and the fourth chip converts the differential analog signal into serial stream data according to the encoding rules of the physical layer, and transmits it to the second chip through the MII interface. The second chip then transmits the data to other industrial bus communication chips.

[0035] Specifically, the third chip converts the parallel data sent by the first chip into serial stream data, and encodes the data according to the encoding rules of the physical layer. The specific method includes: arranging each bit of the parallel data stream in sequence through a parallel / serial converter to form a serial data stream; encoding the serial data stream using a non-return-to-zero encoding method; and converting the encoded digital signal into a differential analog signal through the third chip.

[0036] In some preferred embodiments, when the first chip converts the other industrial bus data into a USB signal, the first chip converts the data obtained from the other industrial bus communication chips into a USB signal through the USB interface and connects it to the second terminal. The USB signal is then received by the second chip, and the second chip then passes the data to the other industrial bus communication chips.

[0037] Specifically, the first chip converts the data obtained from other industrial bus communication chips into USB signals through the USB interface. The specific method includes: obtaining data from the industrial bus communication chip, performing data protocol conversion on the data according to different protocols between the industrial bus and the USB, converting the original data received from the industrial bus into a data format suitable for USB transmission, and encapsulating the data according to the USB data packet structure. The USB protocol divides the data into different packets, including at least data packets, control packets, and synchronization packets; defining the USB bus layer, USB transmission layer, and USB protocol layer during the transmission of USB data, and generating a signal suitable for USB transmission according to the defined data packet structure and transmission protocol.

[0038] Depend on Figure 1 It can be seen that in the system disclosed in the present invention, signal transmission is reversible. The signal can be transmitted from area A to area B, and can also be transmitted from area B to area A. When the signal is transmitted from area B to area A, the specific transmission method is the same as described above, and this embodiment will not be repeated here.

[0039] A bus hot-swap and redundant design system disclosed in the present embodiment includes: a first chip, a second chip, a third chip, a fourth chip, a first terminal and a second terminal; wherein the output end of the first chip is connected to the input end of the third chip through an MII interface, the output end of the third chip is connected to the input end of the first terminal, the output end of the first terminal is connected to the input end of the fourth chip, and the output end of the fourth chip is connected to the input end of the second chip through the MII interface; the output end of the first chip is simultaneously connected to the second terminal input end through a USB interface, and the second terminal output end is connected to the second chip input end through a USB interface. The present invention can convert the industrial bus into Ethernet data through an STM32 chip and a PHY chip or into a USB signal through an STM32 chip, thereby having hot-swap capability, solving the problem that the industrial bus does not have hot-swap capability in the prior art.

[0040] Example 2

[0041] Based on the same inventive concept, the disclosed embodiment also provides a bus hot-swap and redundancy design method, including: a first chip communicates with other industrial bus communication chips to obtain other industrial bus data, and converts the other industrial bus data into MII data or USB signals;

[0042] When the first chip converts the other industrial bus data into MII data, the first chip transmits the data obtained from the other industrial bus communication chip to the third chip through the MII interface, the third chip converts the parallel data sent by the first chip into serial stream data, encodes the data according to the encoding rules of the physical layer, and then converts it into a differential analog signal to transmit the data to the network cable through the first terminal, and then the differential analog signal is received by the fourth chip, the fourth chip converts the differential analog signal into serial stream data according to the encoding rules of the physical layer, and transmits it to the second chip through the MII interface, and the second chip then transmits the data to the other industrial bus communication chip;

[0043] When the first chip converts the other industrial bus data into USB signals, the first chip converts the data obtained from other industrial bus communication chips into USB signals through the USB interface and connects to the second terminal. The USB signal is then received by the second chip, and the second chip then transmits the data to other industrial bus communication chips.

[0044] Depend on Figure 1 It can be seen that in the method disclosed in the present invention, signal transmission is reversible. The signal can be transmitted from area A to area B, and can also be transmitted from area B to area A. When the signal is transmitted from area B to area A, the specific transmission method is the same as described above, and this embodiment will not be repeated here.

[0045] Example 3

[0046] Based on the same inventive concept, an embodiment of the present disclosure also provides an electronic device. Figure 2 FIG. 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Figure 2 As shown, an embodiment of the present disclosure provides an electronic device including: one or more processors 101, a memory 102, and one or more I / O interfaces 103. The memory 102 stores one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors implement any optimization method in the above embodiments; the one or more I / O interfaces 103 are connected between the processor and the memory, and are configured to implement information interaction between the processor and the memory.

[0047] Among them, the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU), etc.; the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus), etc.

[0048] In some embodiments, the processor 101 , the memory 102 , and the I / O interface 103 are connected to each other via a bus 104 , and further connected to other components of the computing device.

[0049] In some embodiments, the one or more processors 101 include a field programmable gate array.

[0050] According to an embodiment of the present disclosure, a computer-readable medium is further provided, wherein a computer program is stored on the computer-readable medium, wherein when the program is executed by a processor, the steps in any optimization method in the above-mentioned embodiment are implemented.

[0051] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0052] In the above detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are clearly stated in each claim. On the contrary, as reflected in the appended claims, the invention is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the appended claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0053] Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments herein can all be implemented as electronic hardware, computer software, or a combination thereof. In order to clearly illustrate the interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above around their functions. Whether such functions are implemented as hardware or software depends on specific applications and the design constraints imposed on the entire system. A skilled person can implement the described functions in an alternative manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of protection of the present disclosure.

[0054] The steps of the method or algorithm described in conjunction with the embodiments herein may be directly embodied as hardware, a software module executed by a processor, or a combination thereof. The software module may be located in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a mobile disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and the storage medium may be located in an ASIC. The ASIC may be located in a user terminal. Of course, the processor and the storage medium may also be present in a user terminal as discrete components.

[0055] For software implementation, the techniques described in this application can be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described in this application. These software codes can be stored in a memory unit and executed by a processor. The memory unit can be implemented within the processor or outside the processor. In the latter case, it is coupled to the processor in a communication manner via various means, which are well known in the art.

[0056] The above description includes examples of one or more embodiments. Of course, it is impossible to describe all possible combinations of components or methods for the purpose of describing the above embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", just as "including," is explained as a transitional word in the claims. In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

Claims

1. A bus hot-swap and redundant design system, characterized in that: include: A first chip, a second chip, a third chip, a fourth chip, a first terminal and a second terminal; wherein the output end of the first chip is connected to the input end of the third chip through the MII interface, the output end of the third chip is connected to the input end of the first terminal, the output end of the first terminal is connected to the input end of the fourth chip, and the output end of the fourth chip is connected to the input end of the second chip through the MII interface; the output end of the first chip is simultaneously connected to the input end of the second terminal through the USB interface, and the output end of the second terminal is connected to the input end of the second chip through the USB interface.

2. A bus hot-swap and redundant design system as claimed in claim 1, characterized in that: The first chip and the fourth chip adopt STM32 chips, and the second chip and the third chip adopt PHY chips.

3. A bus hot-swap and redundant design system as claimed in claim 1, characterized in that: The first terminal uses an RJ45 terminal, and the second terminal uses a USB-A terminal.

4. A bus hot-swap and redundant design system as claimed in claim 1, characterized in that: The first chip is used to communicate with other industrial bus communication chips, obtain other industrial bus data, and convert the other industrial bus data into MII data or USB signals.

5. A bus hot-swap and redundant design system as claimed in claim 4, characterized in that: When the first chip converts the other industrial bus data into MII data, the first chip transmits the data obtained from the other industrial bus communication chips to the third chip through the MII interface. The third chip converts the parallel data sent by the first chip into serial stream data, encodes the data according to the encoding rules of the physical layer, and then converts it into a differential analog signal to transmit the data to the network cable through the first terminal. The differential analog signal is then received by the fourth chip. The fourth chip converts the differential analog signal into serial stream data according to the encoding rules of the physical layer, and transmits it to the second chip through the MII interface. The second chip then transmits the data to other industrial bus communication chips.

6. A bus hot-swap and redundant design system as claimed in claim 4, characterized in that: When the first chip converts the other industrial bus data into USB signals, the first chip converts the data obtained from other industrial bus communication chips into USB signals through the USB interface and connects to the second terminal. The USB signal is then received by the second chip, and the second chip then transmits the data to other industrial bus communication chips.

7. A bus hot-swap and redundant design system as claimed in claim 5, characterized in that: The third chip converts the parallel data sent by the first chip into serial stream data and encodes the data according to the encoding rules of the physical layer. The specific method includes: arranging each bit of the parallel data stream in sequence through a parallel / serial converter to form a serial data stream; encoding the serial data stream using a non-return-to-zero encoding method; and converting the encoded digital signal into a differential analog signal through the third chip.

8. A bus hot-swap and redundant design system as claimed in claim 6, characterized in that: The first chip converts the data obtained from other industrial bus communication chips into USB signals through the USB interface. The specific method includes: obtaining data from the industrial bus communication chip, performing data protocol conversion on the data according to different protocols between the industrial bus and the USB, converting the original data received from the industrial bus into a data format suitable for USB transmission, and encapsulating the data according to the USB data packet structure. The USB protocol divides the data into different packets, including at least data packets, control packets, and synchronization packets; defining the USB bus layer, USB transmission layer, and USB protocol layer during the transmission of USB data, and generating a signal suitable for USB transmission according to the defined data packet structure and transmission protocol.

9. A bus hot-swap and redundancy design method, applied to any system in claims 1-8, characterized in that: include: The first chip communicates with other industrial bus communication chips, obtains other industrial bus data, and converts the other industrial bus data into MII data or USB signals; When the first chip converts the other industrial bus data into MII data, the first chip transmits the data obtained from the other industrial bus communication chip to the third chip through the MII interface, the third chip converts the parallel data sent by the first chip into serial stream data, encodes the data according to the encoding rules of the physical layer, and then converts it into a differential analog signal to transmit the data to the network cable through the first terminal, and then the differential analog signal is received by the fourth chip, the fourth chip converts the differential analog signal into serial stream data according to the encoding rules of the physical layer, and transmits it to the second chip through the MII interface, and the second chip then transmits the data to the other industrial bus communication chip; When the first chip converts the other industrial bus data into USB signals, the first chip converts the data obtained from other industrial bus communication chips into USB signals through the USB interface and connects to the second terminal. The USB signal is then received by the second chip, and the second chip then transmits the data to other industrial bus communication chips.

10. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the design method in claim 9.

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