SOC interconnection system, method and device for SOC interconnection system, and storage medium

Abstract

The invention discloses an SOC interconnection system, a method for the SOC interconnection system, electronic equipment and a storage medium. The SOC interconnection system includes: a plurality of computing devices configured as a plurality of computing device groups; wherein the plurality of computing device groups are groups of the plurality of computing devices based on mutual access frequencies among the plurality of computing devices, each computing device group in the plurality of computing device groups is provided with a corresponding routing device, and each computing device in each computing device group is coupled with the corresponding routing device. The plurality of routing devices corresponding to the plurality of computing device groups are mutually coupled. According to the SOC interconnection system, the wiring congestion risk can be reduced, and the realization of the physical architecture of the SOC is facilitated.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a SOC (System on a Chip) interconnection system, a method for the SOC interconnection system, an electronic device, and a storage medium. Background Art

[0002] As semiconductor processes evolve from micron-level to nano-level, the number of transistors that can be integrated on a chip has increased significantly, which enables SOC to integrate multiple functional modules, such as CPU, GPU, various accelerators, memory controller communication modules, etc. In order to achieve efficient communication between these modules, an advanced bus architecture is required to connect the modules to improve the rapid transmission and processing of data. The need for multiple hosts and multiple slaves on SOCs places higher demands on the design of the interconnect architecture, for example, meeting the different requirements for bandwidth and latency for various types of access, and for example, the need to consider the back-end layout and routing for better implementation. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a SOC interconnection system, comprising: a plurality of computing devices, configured as a plurality of computing device groups; wherein the plurality of computing device groups are groupings of the plurality of computing devices based on the frequency of mutual access between the plurality of computing devices, each of the plurality of computing device groups is provided with a corresponding routing device, each computing device in each of the computing device groups is coupled to the corresponding routing device, and the plurality of routing devices corresponding to the plurality of computing device groups are coupled to each other.

[0004] For example, in the SOC interconnection system provided by an embodiment of the present disclosure, the mutual access frequency includes: the interaction frequency between multiple computing devices based on data dependency, control relationship and / or upstream and downstream task collaboration.

[0005] For example, in the SOC interconnection system provided by an embodiment of the present disclosure, the plurality of computing devices also include a corresponding plurality of memories, and the types of the memories include static random access memory, tightly coupled memory or read-only memory.

[0006] For example, in the SOC interconnection system provided in one embodiment of the present disclosure, the SOC interconnection system also includes: at least one delay-sensitive computing device, wherein the at least one delay-sensitive computing device is coupled to the corresponding multiple routing devices, and the at least one delay-sensitive computing device is configured to access the first target computing device through the routing device corresponding to the first target computing device.

[0007] For example, in the SOC interconnection system provided in one embodiment of the present disclosure, the multiple computing device groups include a first computing device group and a second computing device group, a first routing device corresponding to the first computing device group is coupled to a second routing device corresponding to the second computing device group, and a first computing device in the first computing device group is configured to access a second target computing device in the second computing device group through the first routing device and the second routing device.

[0008] At least one embodiment of the present disclosure provides a SOC interconnection system, comprising: a plurality of computing devices, configured as a plurality of computing device groups; wherein the plurality of computing device groups are groupings of the plurality of computing devices based on the functional coupling degree between the plurality of computing devices; each computing device group in the plurality of computing device groups is provided with a corresponding routing device, and each computing device in each computing device group is coupled to the corresponding routing device.

[0009] For example, in the SOC interconnection system provided by an embodiment of the present disclosure, the functional coupling degree includes the type of computing device.

[0010] For example, in the SOC interconnection system provided in one embodiment of the present disclosure, the SOC interconnection system also includes: a memory; wherein the type of the memory includes a dynamic random access memory; each of the multiple computing device groups is provided with a corresponding memory port, and each computing device group is configured to be coupled to the corresponding memory port through the corresponding routing device to form a corresponding data transmission path.

[0011] For example, in a SOC interconnection system provided in an embodiment of the present disclosure, the multiple computing device groups include a first computing device group and a second computing device group, wherein a first computing device in the first computing device group is coupled to a first memory port corresponding to the first computing device group through a first routing device corresponding to the first computing device group, and the first computing device is coupled to a second memory port corresponding to the second computing device group through a second routing device corresponding to the second computing device group, and the first computing device is configured to form a first data transmission path through the first routing device and the first memory port; the first computing device is also configured to form a second data transmission path through the second routing device and the second memory port, wherein the second data transmission path is configured as an alternative data transmission path for the first computing device.

[0012] For example, in the SOC interconnection system provided in an embodiment of the present disclosure, the SOC interconnection system also includes: a monitoring device; wherein the monitoring device is configured to monitor the bandwidth occupancy threshold of the second routing device, and generate a corresponding memory port idle signal in response to the bandwidth occupancy threshold of the second routing device being lower than the corresponding preset threshold; the first computing device is provided with a corresponding data transmission path selector; wherein the data transmission path selector is configured to switch the data transmission path of the first computing device to the second data transmission path in response to receiving the memory port idle signal.

[0013] For example, in the SOC interconnection system provided by an embodiment of the present disclosure, the first computing device includes a computing device of a high bandwidth requirement type.

[0014] At least one embodiment of the present disclosure provides a SOC interconnection system, comprising: a plurality of computing devices, configured as a plurality of computing device groups; wherein the plurality of computing device groups are groupings of the plurality of computing devices based on a first grouping type and / or a second grouping type between the plurality of computing devices, each computing device group in the plurality of computing device groups is provided with a corresponding routing device, and each computing device in each computing device group is coupled to the corresponding routing device.

[0015] For example, in the SOC interconnection system provided by an embodiment of the present disclosure, the first grouping type includes the mutual access frequency between the multiple computing devices, and the second grouping type includes the functional coupling degree between the multiple computing devices.

[0016] At least one embodiment of the present disclosure provides a method for a SOC interconnection system, wherein the SOC interconnection system includes multiple computing devices and a memory, and the method includes: grouping the multiple computing devices into multiple computing device groups based on the purpose requirements of the multiple computing devices and the type of the memory; and setting a corresponding routing device for each computing device group in the multiple computing device groups, wherein each computing device in each computing device group is coupled to the corresponding routing device.

[0017] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the purpose requirement includes the frequency of mutual access between the multiple computing devices, and the type of the memory includes static random access memory, tightly coupled memory or read-only memory.

[0018] For example, in a method for a SOC interconnection system provided by an embodiment of the present disclosure, the mutual access frequency includes the interaction frequency between multiple computing devices based on data dependency, control relationship and / or upstream and downstream task collaboration.

[0019] For example, in a method for a SOC interconnection system provided by an embodiment of the present disclosure, the SOC interconnection system also includes at least one delay-sensitive computing device, the at least one delay-sensitive computing device is coupled to a plurality of routing devices, and the at least one delay-sensitive computing device is configured to access the first target computing device through a routing device corresponding to the first target computing device.

[0020] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, multiple routing devices corresponding to the multiple computing device groups are coupled to each other, and the method further includes: establishing an interconnection relationship between the multiple computing device groups through the multiple routing devices.

[0021] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the multiple computing device groups include a first computing device group and a second computing device group, a first routing device corresponding to the first computing device group is coupled to a second routing device corresponding to the second computing device group, and an interconnection relationship between the multiple computing device groups is established through the multiple routing devices, including: a first computing device in the first computing device group accesses a second target computing device in the second computing device group through the first routing device and the second routing device.

[0022] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the target requirement includes the functional coupling degree between multiple computing devices, the functional coupling degree includes the host types corresponding to the multiple computing devices, and the memory type includes dynamic random access memory.

[0023] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, setting a corresponding routing device for each of the multiple computing device groups includes: setting a corresponding routing device for each computing device group; the method also includes: forming a corresponding data transmission path through the routing device corresponding to each computing device group and the memory port corresponding to each computing device group.

[0024] For example, in a method for a SOC interconnection system provided by an embodiment of the present disclosure, the multiple computing device groups include a third computing device group and a fourth computing device group; the third computing devices in the third computing device group are respectively coupled to a routing device corresponding to the third computing device group and a routing device corresponding to the fourth computing device group.

[0025] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the third computing device is configured to form a main data transmission path through a routing device corresponding to the third computing device group and a memory port corresponding to the third computing device group; the third computing device is also configured to form an alternative data transmission path through a routing device corresponding to the fourth computing device group and a memory port corresponding to the fourth computing device group. For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the method further includes: in response to monitoring that a bandwidth occupancy threshold of a routing device corresponding to the third computing device is lower than a corresponding preset threshold, generating a corresponding memory port idle signal; and in response to receiving the memory port idle signal, switching the data transmission path of the third computing device from the main data transmission path to the alternative data transmission path.

[0026] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the host type corresponding to the third computing device is a high bandwidth requirement category.

[0027] At least one embodiment of the present disclosure provides an electronic device, comprising: a processor and a memory, wherein the memory stores at least one computer program, and when the at least one computer program is executed by the processor, the method for a SOC interconnection system provided by any embodiment of the present disclosure is implemented.

[0028] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium for non-temporarily storing computer-readable instructions. When the computer-readable instructions are executed by a computer, the method for a SOC interconnection system provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0030] Figure 1 A schematic block diagram of a SOC interconnection system provided by at least one embodiment of the present disclosure is shown;

[0031] Figure 2 A schematic block diagram of another SOC interconnection system provided by at least one embodiment of the present disclosure is shown;

[0032] Figure 3 A schematic block diagram of another SOC interconnection system provided by at least one embodiment of the present disclosure is shown;

[0033] Figure 4A schematic block diagram of another SOC interconnection system provided by at least one embodiment of the present disclosure is shown;

[0034] Figure 5 An application schematic diagram of a SOC interconnection system provided by at least one embodiment of the present disclosure is shown;

[0035] Figure 6 An application schematic diagram of another SOC interconnection system provided by at least one embodiment of the present disclosure is shown;

[0036] Figure 7 A flow chart of a method for a SOC interconnection system provided by at least one embodiment of the present disclosure is shown;

[0037] Figure 8 A schematic diagram of an application of another SOC interconnection system provided by at least one embodiment of the present disclosure is shown;

[0038] Fig. 9 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0039] Fig.10 A schematic block diagram showing another electronic device provided by at least one embodiment of the present disclosure; and

[0040] Fig.11 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0042] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0043] For example, tablet SOC or other SOC (as a key component of electronic devices, its performance will affect the user experience of the final product. As semiconductor technology evolves from micron level to nano level, the number of transistors that can be integrated on the chip has increased significantly, which allows SOC to integrate multiple functional modules, such as CPU, GPU, memory controller, communication module, etc. However, this high degree of integration also brings new challenges, especially in bus architecture design. In order to achieve efficient communication between these modules, an advanced bus architecture is needed to connect the modules so that data can be quickly transmitted and processed.

[0044] Moreover, as users’ performance requirements continue to increase, they also hope that electronic devices can have a longer battery life. This requires that the SOC bus architecture not only meet the needs of high-performance data transmission, but also reduce power consumption as much as possible. For example, low-voltage differential signaling (LVDS) technology can be used to achieve high-speed data transmission while reducing power consumption12. In addition, by optimizing the clock management of the bus and dynamically adjusting the clock frequency according to different workloads, power consumption can be further reduced.

[0045] SOC integrates a variety of modules with different functions and performance requirements, and the data transmission rate, data format, operating frequency, etc. of each module are different. For example, high-speed, bursty data transmission is required between the CPU and the memory, while low-speed, periodic data transmission is required between the sensor module and the processor. Therefore, the bus architecture needs to have a flexible topology and protocol. For example, a multi-layer bus structure can be used to connect high-speed modules and low-speed modules to different levels of buses to improve the overall performance and reliability of the system.

[0046] In order to facilitate the interconnection between chips of different types or models and external devices, the SOC bus architecture needs to follow certain standards and specifications. For example, the AMBA (Advanced Microcontroller Bus Architecture) bus standard can be applied to the ARM (Advanced RISC Machine) architecture SOC, which defines a variety of bus protocols and interface specifications, allowing computing devices of different types or models to work together on the same bus, improving the compatibility and scalability of the system.

[0047] However, the inventors of the present disclosure have noticed that although the above-mentioned technology can improve the performance of SOC, there are still some problems that need to be solved in practical applications. For example, in low-power scenarios, due to the limitations of battery technology and heat generation / heat dissipation during chip use, the power consumption requirements of chips in various application scenarios are very high, and the bus architecture design needs to be targeted according to the different application scenarios of the chip. For another example, the scheduling performance inside the DDR (Double Data Rate) memory will be better than the scheduling performance on the system NoC (Network on Chip), but in some scenarios some DDR ports (DDR Port) may be idle, and the bus needs to be targeted based on the above considerations in terms of evenly allocating bandwidth. Design. For another example, since there are multiple hosts and slaves in the SOC, and each host and slave needs to be interconnected, this will result in too many interconnection lines, which is not conducive to physical implementation.

[0048] Embodiments of the present disclosure provide a SOC interconnection system, a method for the SOC interconnection system, an electronic device, and a storage medium. The SOC interconnection system includes a plurality of computing devices, which are configured as a plurality of computing device groups; wherein the plurality of computing device groups are groups of a plurality of computing devices based on the frequency of mutual access between the plurality of computing devices, each computing device group in the plurality of computing device groups is provided with a corresponding routing device, each computing device in each computing device group is coupled to a corresponding routing device, and the plurality of routing devices corresponding to the plurality of computing device groups are coupled to each other. The SOC interconnection system can reduce the risk of wiring congestion, which is conducive to the realization of the physical architecture of the SOC.

[0049] Figure 1 A schematic block diagram of a SOC interconnection system provided by at least one embodiment of the present disclosure is shown.

[0050] The SOC interconnection system includes a plurality of computing devices, which are configured as a plurality of computing device groups.

[0051] For example, Figure 1As shown, computing device 1 and computing device 2 may form one computing device group, and computing device 3 and computing device 4 may form another computing device group. It should be noted that Figure 1 The computing device group shown is only an exemplary description, and the embodiments of the present disclosure do not limit the form and number of the computing device group.

[0052] Multiple computing device groups are groups of multiple computing devices based on the frequency of mutual access between the multiple computing devices. Each of the multiple computing device groups is provided with a corresponding routing device, each computing device in each computing device group is coupled to a corresponding routing device, and the multiple routing devices corresponding to the multiple computing device groups are coupled to each other.

[0053] For example, multiple computing devices in the SOC interconnection system may be grouped based on the characteristics of the mutual access frequencies between the multiple computing devices to optimize communication efficiency and physical layout.

[0054] For example, in a SOC interconnect system, a computing device may include circuit modules having independent functions in an integrated circuit.

[0055] For example, the computing device may include a corresponding host, such as a CPU (central processing unit), a GPU (graphics processing unit) or a DSP (digital signal processor), etc., and the embodiments of the present disclosure are not limited to this.

[0056] For example, Figure 1 As shown, the SOC interconnection system also includes multiple memories. Here, the memory can be a memory to be operated or accessed by the computing device. For example, the slave corresponding to the computing device can be a memory corresponding to the host (such as SRAM, TCM, ROM memory, etc.).

[0057] For example, taking a general computing accelerator (such as DSP, Digital Signal Processor) as an example, DSP can access system memory and system peripheral space as a host. At the same time, DSP also has corresponding memory (such as some tightly coupled instruction storage and data storage), and these tightly coupled storages of DSP can be accessed by other hosts. Therefore, DSP has the characteristics of both host and slave.

[0058] In some embodiments of the present disclosure, the plurality of computing device groups may be groupings of the plurality of computing devices based on purpose requirements among the plurality of computing devices.

[0059] For example, the purpose requirements of multiple computing devices refer to the functional goals, performance requirements, and interaction characteristics that different computing devices undertake in the system. These requirements directly determine their grouping, interconnection, and resource allocation strategies in the chip architecture.

[0060] For example, "purpose requirements" is a comprehensive description of the collaborative relationships, data flow characteristics, and performance constraints that a computing device relies on when implementing its functions in a SOC system. "Purpose requirements" may include functional collaboration requirements, performance requirements, or resource dependency requirements, etc.

[0061] For example, functional collaboration requirements may include data dependencies between computing devices, such as whether there is a data pipeline or shared data source between computing devices. For example, in an image processing pipeline, the ISP (Image Signal Processor) needs to pass the processed data to the GPU or NPU, and the two need to work closely together.

[0062] For example, the functional cooperation requirements may also include the control relationship between computing devices, such as whether there is master-slave control or instruction interaction between computing devices. For example, if the CPU is used as the main control unit, it needs to send configuration instructions to the sensor controller through the bus.

[0063] For example, the functional collaboration requirements may also include task collaboration between computing devices, such as whether multiple computing devices belong to upstream and downstream modules of the same task chain. For example, in an audio processing chain, a DSP (digital signal processor) and an audio codec need to collaborate to complete real-time audio stream processing.

[0064] For example, the performance requirements may include the frequency of interaction between computing devices, such as the frequency of data interaction between computing devices (high / low frequency). For example, the CPU and cache (SRAM) need to interact frequently, while the temperature sensor and the CPU may only report data periodically.

[0065] For example, performance requirements may also include bandwidth requirements between computing devices, such as data transmission rate requirements (such as bursty large bandwidth or sustained low bandwidth). For example, GPU rendering requires high bandwidth access to DRAM, while RTC (real-time clock) requires only very low bandwidth.

[0066] For example, resource dependency requirements may include the binding of computing devices to memory types, such as the computing device's access dependency on specific memory. For example, an AI accelerator (NPU) needs to frequently access large-capacity DRAM, while an interrupt controller may only require a small amount of SRAM.

[0067] For example, resource dependency requirements may also include power domain associations between computing devices, such as whether the computing devices belong to the same dynamic voltage / frequency scaling (DVFS) domain. For example, a low-power sensor group may share an independent power domain to support a sleep mode.

[0068] For example, the type of memory may include static random access memory, tightly coupled memory, read-only memory (ROM), flash memory (FLASH) or dynamic random access memory. Exemplarily, the static random access memory may include SRAM memory, etc., and the dynamic random access memory may include DDR memory, etc., which is not limited in the embodiments of the present disclosure.

[0069] In a possible implementation, for example, the plurality of computing device groups are groups of the plurality of computing devices based on the frequency of mutual access between the plurality of computing devices.

[0070] For example, the plurality of computing device groups are groups of the plurality of computing devices based on the mutual access frequencies between the plurality of computing devices, that is, groups of the first grouping type.

[0071] For example, the plurality of computing device groups are composed of a plurality of computing devices based on the mutual access frequency between the plurality of computing devices and the types of memories corresponding to the plurality of computing devices (eg, SRAM, TCM, ROM, FLASH, etc.).

[0072] For example, as described above, the mutual access frequency may include the interaction frequency between multiple computing devices based on data dependency, control relationship and / or upstream and downstream task collaboration.

[0073] For example, the mutual access frequency may include data dependencies between multiple computing devices (e.g., data transfer frequency in pipeline processing), control relationships (e.g., instruction interaction frequency between host 1 and host 2), and upstream and downstream task collaboration (e.g., ISP and GPU collaboration in an image processing pipeline), to quantify the interaction frequency between modules.

[0074] For example, for computing devices in the same computing device group (taking host M1 and host M2 as examples), the following conditions can be met: M1 has a need to frequently access M2's internal slave (e.g., SRAM 2 memory), and M2 has a need to frequently access M1's internal slave (e.g., SRAM 1 memory), but M1 and M2 will not have a need to access each other's slave at the same time. For example, M1 can be a dedicated computing accelerator with a small-core processor, and M2 can be a general-purpose computing accelerator. During some initialization processes, the small-core processor in M1 can access the slave in M2 (e.g., TCM memory) to initialize M2. For example, in some work scenarios, M2 needs to access M1's internal slave (e.g., SRAM 1 memory) to obtain data completed by M1's operation for the next step of analysis. For example, the two processes of M1 accessing M2's slave and M2 accessing M1's slave can be separated in timing and do not occur at the same time.

[0075] For example, the intra-group protocol of multiple computing device groups can be based on the AMBA standard (such as AXI-Stream for stream data processing) to enable computing devices provided by different manufacturers (such as third-party DSPs) to be integrated within the group. The embodiments of the present disclosure do not limit the intra-group protocol of the computing device group.

[0076] Each computing device group in the plurality of computing device groups is provided with a corresponding routing device. Through the corresponding routing design, it is possible to reduce physical connections while ensuring low latency on critical paths.

[0077] For example, each computing device group may be configured with a corresponding routing device (Group Router). For example, communication within a computing device group may only pass through a single-stage routing.

[0078] For example, a dedicated computing accelerator or a general computing accelerator can be configured to be directly connected to the SRAM through the GroupRouter, which can significantly reduce latency.

[0079] For example, Figure 1 As shown, multiple routing devices are coupled to each other.

[0080] For example, multiple computing device groups can establish interconnection relationships between the multiple computing device groups through their corresponding routing devices (Group Router).

[0081] In at least one embodiment of the present disclosure, by grouping computing devices and hierarchical routing, the original fully connected N×M complexity can be reduced to N×M within the computing device group. 1 ×M 1 + K×L cross-computing device groups significantly reduce metal layer wiring density. For example, 10*10=100 links are required to fully interconnect 10 computing devices, but only 5+5+1+1=12 links are required after grouping into 2 groups, thereby reducing the delay and connection overhead of infrequent paths. The number of connections is reduced by about 88%, reducing the risk of wiring congestion and improving the data transmission performance of the chip.

[0082] Figure 2 A schematic block diagram of another SOC interconnection system provided by at least one embodiment of the present disclosure is shown.

[0083] The SOC interconnection system further includes at least one delay-sensitive computing device. The at least one delay-sensitive computing device is coupled to a plurality of corresponding routing devices. The at least one delay-sensitive computing device can be configured to access the first target computing device through the routing device corresponding to the first target computing device.

[0084] For example, Figure 2 As shown, the delay-sensitive computing device is coupled to routing device 1 and routing device 2 .

[0085] For example, for a delay-sensitive computing device, a delay-sensitive path priority may be set, that is, the delay-sensitive computing device may be coupled to routing devices (Group Router) corresponding to multiple computing device groups.

[0086] For example, the delay-sensitive computing device may include a CPU, a real-time interrupt controller, a high-priority hardware accelerator, etc., and the embodiments of the present disclosure are not limited in this regard.

[0087] For example, if the CPU is a delay-sensitive module, its access path (such as to the TCM memory of other general-purpose computing accelerators outside the CPU) can adopt a dedicated low-latency channel, such as using a direct connection or bypass link to directly access the TCM memory through the routing device corresponding to the TCM memory, thereby reducing scheduling congestion and causing system performance degradation.

[0088] For example, delay-sensitive computing devices have strict requirements for communication delays (e.g., nanoseconds). For example, if the CPU is a delay-sensitive computing device and the CPU delay is not met, the overall performance of the entire system will be affected. For example, the CPU needs a single-cycle delay to access the TCM tightly coupled memory of other general-purpose computing accelerators outside the CPU, and the display controller needs to ensure the deterministic refresh cycle of the frame buffer data.

[0089] For example, a delay-sensitive computing device can be configured to be simultaneously coupled to routing devices corresponding to multiple computing device groups, that is, to be coupled to multiple routing devices rather than being bound to only a single routing device, thereby allowing the delay-sensitive computing device to access target computing devices in different computing device groups through the shortest path, thereby reducing additional delays introduced by cross-group routing levels.

[0090] For example, assume that the delay-sensitive computing device is a CPU, which needs to access SRAM 1 (the SRAM corresponding to the first target computing device) in computing device group 1 and the DMA controller in group 2 (the second target computing device). Then the CPU can be directly connected to the routing device of computing device group 1 (e.g., Group Router A) and the routing device of computing device group 2 (e.g., GroupRouter B). When the CPU accesses SRAM 1, the data path can be: CPU→Group Router A→SRAM 1 (only 1 hop); when the CPU accesses the DMA controller, the path is: CPU→Group Router B→DMA controller (also only 1 hop). On the contrary, if multi-routing connection is not adopted, the CPU needs to forward through two layers of local router and global router (path: CPU→local router→global router→target group router→target computing device), and the delay will increase by 2-3 cycles.

[0091] For example, a dedicated physical link (such as a bypass link, which is not limited in the embodiments of the present disclosure) can be used between a delay-sensitive computing device and multiple routing devices to further reduce contention delays caused by sharing data paths with other computing devices.

[0092] For example, an access request of a delay-sensitive computing device may be given the highest arbitration priority so that data transmission of the delay-sensitive computing device is not blocked.

[0093] For example, dynamic voltage / frequency scaling (DVFS) isolation can also be used to use an independent power domain for the link where the delay-sensitive computing device is located to maintain a high voltage / high frequency state, while other routing nodes can dynamically reduce the frequency according to the load.

[0094] For example, differential signaling (LVDS) and shielding layer wiring may be used to isolate data transmission links of delay-sensitive computing devices, thereby reducing the possibility of high-frequency signal crosstalk introduced by direct connections of multiple routes.

[0095] In at least one embodiment of the present disclosure, the end-to-end delay of the delay-sensitive path is reduced by 30%-50% to meet the real-time critical task requirements. Through priority arbitration and dedicated links, the random delay jitter caused by bus contention is further reduced. In addition, the delay-sensitive link is powered independently, and the non-critical path can be dynamically down-converted / shutdown, and the overall power consumption is reduced by 15%-20%. In addition, the global wiring complexity is further reduced, the utilization of the metal layer is improved, and the chip area can be further reduced by 5%-10%.

[0096] In some embodiments of the present disclosure, the plurality of computing device groups include a first computing device group and a second computing device group, and a first routing device corresponding to the first computing device group is coupled to a second routing device corresponding to the second computing device group. The first computing device in the first computing device group is configured to access a second target computing device in the second computing device group through the first routing device and the second routing device.

[0097] For example, multiple routing devices (eg, a first routing device and a second routing device) corresponding to multiple computing device groups (eg, a first computing device group and a second computing device group) are coupled to each other to optimize latency and physical resource consumption.

[0098] For example, in the SOC interconnection system, the computing devices in the first computing device group and the second computing device group have a high mutual access frequency, but the access modes or interaction characteristics of the two groups may be different. For example, the mutual access frequency between the multiple computing devices corresponding to the first computing device group is different from the mutual access frequency between the multiple computing devices corresponding to the second computing device group.

[0099] It should be noted that, as mentioned above, since the delay-sensitive computing devices are respectively coupled to multiple routing devices, the multiple computing devices in the first computing device group and the second computing device group do not include the delay-sensitive computing devices.

[0100] In one possible implementation, the SOC interconnection system includes a first computing device group and a second computing device group. The first computing device group may include multiple computing devices with short-term high-bandwidth bursts (e.g., frequent reading and writing of texture data during GPU rendering). Exemplarily, the first computing device group may include a GPU, an L2 Cache, and a texture compression engine. The second computing device group may include multiple computing devices with continuous and stable high-bandwidth streaming (e.g., 4K video encoding). Exemplarily, the second computing device group may include a video codec (H.264 / H.265) and a video buffer.

[0101] For example, the intra-group communication path of the first computing device group may be represented as the GPU and L2 Cache interacting through GroupRouter 1.

[0102] For example, the intra-group communication path of the second computing device group may be represented as the codec interacting with the video buffer through Group Router 2.

[0103] For example, for the communication path of cross-group communication between the first computing device group and the second computing device group, for example, when the GPU in the first computing device group needs to access the video buffer in the second computing device group, the communication path can be expressed as GPU→Group Router 1→Group Router 2→video buffer.

[0104] In another possible implementation, the SOC interconnection system includes a first computing device group, a second computing device group, and a delay-sensitive computing device CPU. For example, in an AI visual processing scenario, the CPU can send instructions to the GPU through Group Router 1, and the data processed by the GPU is transmitted to the NPU via Group Router 1→Group Router 2.

[0105] The second routing device (Group Router 2) supports continuous high-bandwidth streaming. For example, when the GPU reads texture data from the video memory, the path is GPU→Group Router 2→video memory controller.

[0106] For example, for a cross-group communication path between a first computing device group and a second computing device group.

[0107] Exemplarily, the communication path for the first computing device group to access the second computing device group may be a first computing device in the first computing device group→Group Router 1→Group Router 2→a target computing device in the second computing device group.

[0108] For example, when the CPU needs to transfer computing instructions to the GPU, it can be forwarded through Group Router 1 to GroupRouter 2 and then delivered to the GPU.

[0109] In at least one embodiment of the present disclosure, by independently setting up a delay-sensitive computing device and coupling it to multiple routing devices respectively, and designing differentiated routing strategies for multiple computing device groups, functional isolation of key high mutual access frequency tasks and high-performance computing is achieved, and flexible expansion of the architecture is also achieved.

[0110] Figure 3 A schematic block diagram of yet another SOC interconnection system provided by at least one embodiment of the present disclosure is shown.

[0111] The SOC interconnection system includes multiple computing devices, which are configured as multiple computing device groups; the multiple computing device groups are groupings of the multiple computing devices based on the functional coupling degree between the multiple computing devices; each computing device group in the multiple computing device groups is provided with a corresponding routing device, and each computing device in each computing device group is coupled to the corresponding routing device.

[0112] like Figure 3 As shown, the plurality of computing devices may include computing devices 1 to 4. Computing devices 1 and 2 may form a corresponding computing device group based on corresponding functional coupling degrees, and computing devices 3 and 4 may form a corresponding computing device group based on corresponding functional coupling degrees.

[0113] For example, the plurality of computing device groups may also be a grouping of the plurality of computing devices based on the functional coupling degree between the plurality of computing devices, that is, a grouping of the second grouping type.

[0114] For example, the plurality of computing device groups may also be a plurality of computing device groups composed of a plurality of computing devices based on the functional coupling degree between the plurality of computing devices and the types of memories corresponding to the plurality of computing devices (eg, dynamic random access memory).

[0115] For example, the functional coupling degree may include the types of computing devices corresponding to the multiple computing devices, and the grouping strategy may be dynamically adjusted according to the types of computing devices corresponding to the multiple computing devices and the memory types (eg, DDR memory) corresponding to the computing devices.

[0116] For example, the types of computing devices may include real-time computing devices, high-bandwidth demand computing devices, or high-speed interface computing devices, etc., and the embodiments of the present disclosure are not limited in this regard.

[0117] For example, the intra-group protocol of multiple computing device groups can be based on the AMBA standard (such as AXI-Stream for stream data processing) to enable computing devices provided by different manufacturers (such as third-party DSPs) to be integrated within the group. The embodiments of the present disclosure do not limit the intra-group protocol of the computing device group.

[0118] In some embodiments of the present disclosure, the SOC interconnection system may be grouped into at least one of the two types of groupings described above. Figure 1-Figure 2 (which may correspond to a packet of the first packet type) and Figure 3-Figure 4 At least one of the schematic diagrams of a packet described (e.g., a packet corresponding to a second packet type).

[0119] In some embodiments of the present disclosure, Figure 3 The SOC interconnection system shown also includes: a memory. The type of memory includes a dynamic random access memory; each computing device group in the plurality of computing device groups is provided with a corresponding memory port. Each computing device group is configured to be coupled to a corresponding memory port through a corresponding routing device to form a corresponding data transmission path.

[0120] For example, Figure 3 As shown, the SOC interconnection system includes memory port 1 and memory port 2. The routing device 1 corresponding to the computing device group composed of computing device 1 and computing device 2 is coupled to the memory port 1 corresponding to the computing device group, and the routing device 2 corresponding to the computing device group composed of computing device 3 and computing device 4 is coupled to the memory port 2 corresponding to the computing device group.

[0121] As mentioned above, the functional coupling degree grouping strategy includes dividing the functional groups according to the host type of the computing device, and the computing devices in the same group share the same type of storage resource requirements.

[0122] The computing device type corresponding to the computing device may include a real-time category computing device, a high-bandwidth requirement category computing device, or a high-speed interface category computing device, etc. For example, a real-time category computing device may include a computing device that is extremely sensitive to delay and requires a deterministic response (such as a CPU, a real-time interrupt controller, and a motion control unit). For example, a high-bandwidth requirement category computing device may include a computing device that relies on high-bandwidth streaming data transmission (such as a GPU, a video codec, and a display engine), which can adapt to high burst traffic, such as 4K / 8K video processing, where the bandwidth requirement can reach tens to hundreds of GB / s. For example, a high-speed interface category computing device may include a computing device that requires high throughput and low jitter (such as a PCIe controller, USB 3.1PHY, and a 10G Ethernet MAC).

[0123] For example, multiple computing device groups can all be associated with corresponding DDR ports, but different DDR port characteristics can be configured according to functional requirements. For example, a DDR port can be bound to a real-time computing device group, for example, it can be configured using the QoS control policy of the real-time computing device. For example, for a delay-sensitive computing device, an exclusive DDR port can be configured. For example, a DDR port configured for a computing device group with a high bandwidth requirement can also be configured using the host's QoS control policy.

[0124] For example, the QOS policy of a real-time computing device can be adjusted based on the monitored delay. When the delay meets the preset conditions, its QOS value can be lower than the QOS value of a delay-sensitive computing device and higher than the QOS value of a large bandwidth-demand computing device; when the delay does not meet the preset conditions, its QOS value will be adjusted to the highest priority of the system. For example, the priority of a delay-sensitive computing device can be configured as the second highest priority of the system. For example, the priority of a large bandwidth-demand type computing device can be configured as a low priority of the system. For example, based on different computing device grouping conditions, different QOS policies can be configured for the DDR ports corresponding to different computing device groups, and the embodiments of the present disclosure are not limited to this.

[0125] For example, a corresponding routing device (DDR Port Router) may be allocated to each computing device group.

[0126] For example, the computing device is directly connected to the dedicated DDR port through the corresponding DDR Port Router to form a corresponding storage data path.

[0127] Exemplarily, the communication path may be represented as: CPU of the real-time computing device group→DDR Port Router A→LPDDR5X Port 1; GPU of the high bandwidth requirement group→DDR Port Router B→GDDR6 Port 1.

[0128] In at least one embodiment of the present disclosure, by grouping computing devices based on functional coupling and memory type and designing a dedicated routing device, function-oriented resource allocation is achieved, storage paths are customized for scenarios such as real-time, high-bandwidth requirements, and high-speed interfaces, and the performance design of the SOC is further improved.

[0129] Figure 4 A schematic block diagram of another SOC interconnection system provided by at least one embodiment of the present disclosure is shown.

[0130] In some embodiments of the present disclosure, the plurality of computing device groups include a first computing device group and a second computing device group. A first computing device in the first computing device group is coupled to a first memory port corresponding to the first computing device group through a first routing device corresponding to the first computing device group, and the first computing device is coupled to a second memory port corresponding to the second computing device group through a second routing device corresponding to the second computing device group. The first computing device is configured to form a first data transmission path through the first routing device and the first memory port. The first computing device is also configured to form a second data transmission path through the second routing device and the second memory port.

[0131] For example, the second data transmission path may be configured as an alternative data transmission path for the first computing device.

[0132] like Figure 4 As shown, for example, the data transmission path formed by the computing device 2 (i.e., the first computing device in this embodiment) and the routing device 1 (i.e., the first routing device) and the memory port 1 (i.e., the first memory port) can serve as the first data transmission path of the computing device 2, and the data transmission path formed by the computing device 2 and the routing device 2 (i.e., the second routing device) and the memory port 2 (i.e., the second memory port) can serve as the second data transmission path of the computing device 2, that is, as an alternative data transmission path of the computing device 2.

[0133] For example, the alternative data transmission path of the first computing device may be a preconfigured alternative data transmission path.

[0134] For example, the alternative data transmission path of the first computing device may also be an alternative data transmission path selected based on the bandwidth conditions of the data transmission paths corresponding to each computing device group.

[0135] In some embodiments of the present disclosure, the SOC interconnection system further includes a monitoring device (not shown in the figure). The monitoring device is configured to monitor the bandwidth occupancy threshold of the second routing device, and in response to the bandwidth occupancy threshold of the second routing device being lower than the corresponding preset threshold, generate a corresponding memory port idle signal. The first computing device is provided with a corresponding data transmission path selector. The data transmission path selector can be configured to switch the data transmission path of the first computing device to the second data transmission path in response to receiving the memory port idle signal.

[0136] For example, the memory port idle signal may be used to indicate that the corresponding memory port is in an idle state or a low occupancy state.

[0137] For example, the computing device type corresponding to the first computing device may be a high bandwidth requirement category computing device.

[0138] In this embodiment, the SOC interconnection system realizes flexible allocation of bandwidth resources across groups by dynamically monitoring the load of alternative memory ports (such as alternative DDR ports) corresponding to computing devices with high bandwidth requirements and adaptive path switching, thereby optimizing system performance and resource utilization.

[0139] For example, the monitoring device may dynamically monitor the bandwidth of the alternative data transmission path and generate a corresponding memory port idle signal (eg, ddrc_port_not_busy).

[0140] For example, the monitoring device may be deployed in each routing device, and the embodiments of the present disclosure do not limit the deployment location of the monitoring device.

[0141] For example, the monitoring device may monitor bandwidth occupancy, such as the percentage of data transmission volume per unit time to the theoretical maximum bandwidth of the port.

[0142] For example, the monitoring device may also monitor the transaction queue depth, such as the length of the queue of read and write requests waiting to be processed.

[0143] For example, the monitoring device may also monitor latency fluctuations, such as average transaction processing latency and standard deviation.

[0144] For example, monitoring the bandwidth occupation threshold of the second routing device may include monitoring whether the bandwidth occupation threshold of each computing device in the computing device group corresponding to the second routing device exceeds the corresponding preset threshold. For example, it may also include monitoring whether the bandwidth occupation threshold of the data path between the second routing device and the corresponding second memory port exceeds the corresponding preset threshold.

[0145] For example, switching the data transmission path of the first computing device to the second data transmission path may completely switch the data transmission path of the first computing device to the second data transmission path. For example, it may also be switching (at least part of) the traffic of the first computing device to the second data transmission path.

[0146] Exemplarily, when the memory port (e.g., DDR Port Router B) corresponding to the alternative data transmission path of a computing device with high bandwidth requirements detects that the bandwidth occupancy rate is continuously lower than a preset threshold (e.g., the preset threshold is set to 30%) for 5ms, a memory port idle signal is triggered.

[0147] For example, the generation conditions of the memory port idle signal may include: bandwidth occupancy threshold, duration window or signal encoding, etc., which is not limited by the embodiments of the present disclosure. For example, for the bandwidth occupancy threshold, the preset threshold can be dynamically configured according to the DDR type (such as LPDDR5 is set to 40%, GDDR6 is set to 50%). For example, for the duration window, in order to reduce the instantaneous low load false triggering, the preset threshold can be configured to meet the low occupancy rate for a certain period of time (such as 1ms to 10ms programmable). For example, for signal encoding, the memory port idle signal may include information such as port ID, available bandwidth ratio, priority tag, etc.

[0148] In one possible implementation, for example, a corresponding alternative data transmission path may be configured for a computing device (e.g., a computing device with high bandwidth requirements). For example, the alternative data transmission path may be preconfigured, such as preconfiguring at least one data transmission path from a plurality of data transmission paths as an alternative data transmission path for the computing device.

[0149] For example, a fixed alternative data transmission path may be preconfigured for the computing device.

[0150] For example, the bandwidth occupancy of the alternative data transmission path and the routing device corresponding to the computing device is monitored, and the data transmission path of the computing device is adaptively switched.

[0151] For example, for burst video stream processing scenarios, the 8K video encoder of a computing device group with high bandwidth requirements corresponds to GDDR6 Port 1 (for example, a bandwidth of 512GB / s is configured). For example, in the case of a burst load, the video input traffic surges, and the bandwidth occupancy rate of Port 1 reaches 95%, which triggers switching detection. For example, if it is monitored that the occupancy rate of the routing device corresponding to the alternative data transmission path of the computing device and the corresponding memory port (for example, DDR5 Port 3 of the high-speed interface computing device group) is only 35% (lower than the corresponding preset threshold), and the corresponding memory port idle signal is generated, then (at least part of) the traffic of the 8K video encoder can be switched to Port 3.

[0152] In another possible implementation, for example, for the selection of alternative data transmission paths, for example, the main DDR port corresponding to the functional group to which the computing device belongs can be regarded as the default path or the main data transmission path, and the low-load DDR ports of other groups can be regarded as alternative data transmission paths (such as LPDDR5X Port 2 of the real-time group or DDR5 Port 3 of the high-speed interface group).

[0153] For example, in this another possible implementation, it can be monitored whether the bandwidth occupancy threshold of the routing device corresponding to the plurality of computing device groups is lower than the corresponding preset threshold; if it is lower than the corresponding preset threshold, a corresponding memory port idle signal is generated; the routing device indicated by the corresponding memory port idle signal and the corresponding memory port are used as alternative data transmission paths; and the data transmission path of the computing device whose bandwidth occupancy threshold is higher than the corresponding preset threshold (for example, a computing device of a high bandwidth requirement type, with a memory port configured as GDDR6 Port 1)) is switched to the alternative data transmission path.

[0154] For example, based on the proximity principle, the DDR port indicated by the idle signal of the physically adjacent memory port can be preferentially selected as an alternative data transmission path to reduce wiring delay (eg, a high bandwidth demand group can select the same cluster GDDR6 Port 2).

[0155] For example, an alternative data transmission path may be selected based on protocol compatibility, and the alternative port must support the transmission protocol corresponding to the current computing device (eg, AXI-Stream or ACE-Lite).

[0156] Exemplarily, when the bandwidth occupancy rate of GDDR6 Port 1 of the high bandwidth demand group reaches 90% (exceeding the preset threshold corresponding to GDDR6 Port 1), and the occupancy rate of LPDDR5X Port 2 of the real-time group is only 25% (lower than the preset threshold corresponding to LPDDR5X Port 2), a corresponding memory port idle signal can be generated to mark LPDDR5X Port 2 as an alternative data transmission path, and notify the computing device of the high bandwidth demand group to switch the data transmission path.

[0157] For example, the switching trigger condition of the data transmission path may be further configured. For example, the switching trigger condition may include source group bandwidth exceeding the limit or target port being idle. For example, for source group bandwidth exceeding the limit, the path bandwidth occupancy rate may be configured to continuously exceed a preset threshold value (such as >85%). For example, for target port being idle, the alternative path bandwidth occupancy rate may be configured to be lower than a preset threshold value and meet protocol and physical constraints.

[0158] For example, a QoS strategy may also be adopted. For example, when the data transmission path corresponding to a certain computing device group is used as an alternative data transmission path for other computing device groups, the minimum bandwidth of the data transmission path corresponding to the computing device group may be forcibly reserved (such as when the aforementioned LPDDR5X Port 2 is used as an alternative data transmission path, at least 20% of the bandwidth may be reserved for LPDDR5X Port 2).

[0159] In one possible implementation, for example, for a burst video stream processing scenario, the 8K video encoder of a computing device group with a high bandwidth requirement type corresponds to GDDR6 Port 1 (for example, a configured bandwidth of 512GB / s). For example, in the case of a burst load, the video input traffic surges, and the bandwidth occupancy rate of Port 1 reaches 95%, which triggers a switching detection. For example, if it is monitored that the occupancy rate of DDR5 Port 3 of the high-speed interface computing device group is only 35% (lower than the corresponding preset threshold), a corresponding memory port idle signal is generated, and DDR5 Port 3 is used as an alternative data transmission path for the 8K video encoder, then (at least part of) the traffic of the 8K video encoder can be switched to Port 3.

[0160] In at least one embodiment of the present disclosure, a dynamic DDR port path monitoring and switching mechanism is used to achieve on-demand allocation of storage port resources, break the static grouping restrictions, and maximize DDR bandwidth utilization. In addition, through heterogeneous QoS guarantees, differentiated service strategies ensure the coexistence of multiple computing device groups such as real-time, high bandwidth requirements, and high-speed interfaces.

[0161] In some embodiments of the present disclosure, Figures 1 to 4 The SOC interconnection system shown can be implemented in the same electronic device.

[0162] For example, Figures 1 to 4 The components and structures of the SOC interconnection system shown are only exemplary and not restrictive. Figures 1 to 4 The SOC interconnection system shown may share the same circuit, chip or module, which is not limited in the embodiments of the present disclosure.

[0163] For example, Figures 1 to 4 The SOC interconnection system shown may share the same source interface module, system address mapper, encoder, interleaver, decoder, register, etc., which is not limited in the embodiments of the present disclosure.

[0164] For example, Figures 1 to 4 The SOC interconnection system shown may include multiple identical computing devices, and the multiple computing devices may be formed into multiple computing device groups based on different grouping types. For example, the multiple computing device groups are groupings of multiple computing devices based on the first grouping type and / or the second grouping type between the multiple computing devices, thereby realizing different data transmission methods.

[0165] Figure 5 An application schematic diagram of a SOC interconnection system provided by at least one embodiment of the present disclosure is shown.

[0166] like Figure 5 As shown, the SOC interconnection system includes multiple computing devices (eg, host 1, host 2, host 3, host 4) and corresponding multiple memories (eg, slave 1, slave 2).

[0167] The plurality of computing devices are configured to group the plurality of computing devices into a plurality of computing device groups based on the purpose requirements of the plurality of computing devices and the types of memory. A corresponding routing device is respectively provided for each computing device group in the plurality of computing device groups, and the computing devices in each computing device group are connected to the corresponding routing device.

[0168] For example, the plurality of hosts are grouped based on the mutual access frequencies between the plurality of computing devices and the types of memories corresponding to the plurality of computing devices.

[0169] For example, the types of memory include static random access memory, tightly coupled memory, read only memory, or flash memory.

[0170] For example, the SOC interconnection system includes two computing device groups (a first computing device group and a second computing device group) and a delay-sensitive computing device (M0).

[0171] For example, the mutual access frequency between host 1 and host 2 is frequency 1, and the mutual access frequency between host 3 and host 4 is frequency 2, and frequency 1 is different from frequency 2. The memory types of slave 1 and slave 2 corresponding to host 1 and host 2 are both static random access memory (such as SRAM memory). Therefore, host 1, host 2 and slave 1, slave 2 can be divided into the same computing device group and connected through routing device 1. Host 3, host 4 and slave 3 and slave 4 can be divided into another computing device group and connected through routing device 2. In addition, the delay-sensitive computing device (M0) is connected to routing device 1 and routing device 2 respectively.

[0172] In a possible implementation, for example, host 0 can be implemented as a CPU, host 1 can be implemented as a GPU, host 3 can be implemented as an NPU, and host 4 can be implemented as a DSP. For example, slave 3 corresponding to host 3 can be implemented as an NPUSRAM memory. For example, slave 4 corresponding to host 4 can be implemented as a DSP TCM memory. Then the CPU can access slave 1 corresponding to host 1 through routing device 1 to send instructions to the GPU, and the data processed by the GPU can access slave 3 corresponding to the NPU through routing device 1 and routing device 2 to pass the data to the NPU.

[0173] In at least one embodiment of the present disclosure, by independently setting up delay-sensitive computing devices and respectively connecting to multiple routing devices, and designing differentiated routing strategies for multiple computing device groups, functional isolation of key high mutual access frequency tasks and high-performance computing is achieved, and flexible expansion of the architecture is also achieved.

[0174] Figure 5 The functions, configurations, implementation methods, beneficial effects, etc. of each host, slave, and routing device involved in the invention can be referred to the description of the SOC interconnection system in the above-mentioned embodiment, and will not be repeated here. Figure 5 The various hosts, slaves, and routing devices involved may be dedicated or general circuits, chips, or devices, or may be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the above modules.

[0175] It should be noted that, in the embodiments of the present disclosure, each module of the SOC interconnection system may correspond to each step of the method for the SOC interconnection system provided by the present disclosure (to be described below). Figure 5 The components and structures of the SOC interconnection system shown are merely exemplary and non-limiting. The SOC interconnection system may further include other components and structures as required.

[0176] Figure 6A schematic diagram of another application of a SOC interconnection system provided by at least one embodiment of the present disclosure is shown.

[0177] like Figure 6 As shown, the SOC interconnection system includes multiple computing devices and memory ports corresponding to multiple computing device groups. For example, the multiple computing devices may include hosts 1-4, and the corresponding memory ports include memory ports 1-2.

[0178] For example, the computing devices and the memory ports may be grouped based on the functional coupling between the multiple computing devices and the corresponding memory ports.

[0179] For example, the functional coupling degree includes the computing device types corresponding to the plurality of computing devices. The memory type may include, for example, a dynamic random access memory (eg, a DDR memory).

[0180] For example, the memory port may be a memory port corresponding to the host. For example, the computing devices corresponding to host 1 and host 2 are of the same type (for example, both are computing device type 1), and the memory ports corresponding to host 1 and host 2 are both memory port 1 (DDR_port_1). Then host 1 and host 2 may establish a corresponding data transmission path with memory port 1 (DDR_port_1) through routing device 1 (ddrc_p1_router) to access DDR. Similarly, host 3 and host 4 may establish a corresponding data transmission path with memory port 2 (DDR_port_2) through routing device 2 (ddrc_p2_router) to access DDR.

[0181] For example, computing devices with high bandwidth requirements may include modules that need to frequently access memory and transmit large amounts of data during operation, and these computing devices may be used to process complex data-intensive tasks, such as image and video processing, machine learning reasoning, big data analysis, and other applications. Exemplarily, these computing devices with high bandwidth requirements may include digital signal processing modules such as FIR filters, FFT transforms, or convolutional neural network (CNN) accelerators, and high-speed communication interface modules such as PCIe controllers or Ethernet MAC layers, and the embodiments of the present disclosure are not limited thereto.

[0182] For example, in the SOC interconnection system, backup data transmission paths may be configured for computing devices with high bandwidth requirements.

[0183] For example, the SOC interconnection system also includes a monitoring device (not shown in the figure).

[0184] For example, the monitoring device may be included in the routing device.

[0185] For example, the monitoring device may be configured to monitor bandwidth occupancy of each computing device or a corresponding routing device in the computing device group corresponding to the backup data transmission path.

[0186] For example, when the occupied bandwidth of a routing device is lower than a preset threshold (the preset threshold can be configured according to actual needs, and the embodiments of the present disclosure are not limited to this), a corresponding memory port idle signal can be generated (for example, the memory port corresponding to the routing device is DDR_port_2, then the corresponding memory port idle signal can be expressed as ddrc_p2_not_busy), and the status can be recorded in the status register.

[0187] For example, when the bandwidth occupancy threshold of the routing device (e.g., ddrc_p1_router) corresponding to the main data transmission path (host 2—ddrc_p1_router—DDR_port_1) of a computing device with high bandwidth requirements (e.g., host 2) is higher than the corresponding preset threshold, and the ddrc_p2_not_busy status is found to be valid, the data transmission path can be switched to the backup data transmission path (host 2—ddrc_p2_router—DDR_port_2) through the data transmission path selector corresponding to host 2.

[0188] For example, when the data transmission path corresponding to the host 2 is switched to the backup data transmission path, the host 1 can monopolize the bandwidth of the DDR_port_1.

[0189] Figure 6 The functions, configurations, implementation methods, and beneficial effects of each host, slave, data transmission path selector, and routing device involved in the above embodiment can be referred to for example, and will not be repeated here. Figure 6 The various hosts, slaves, data transmission path selectors and routing devices involved in the invention may be dedicated or general circuits, chips or devices, or a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the above modules.

[0190] It should be noted that, in the embodiments of the present disclosure, each module of the SOC interconnection system may correspond to each step of the method for the SOC interconnection system provided by the present disclosure. Figure 6 The components and structures of the SOC interconnection system shown are merely exemplary and non-limiting. The SOC interconnection system may further include other components and structures as required.

[0191] Figure 7 A flow chart of a method for a SOC interconnection system provided by at least one embodiment of the present disclosure is shown.

[0192] like Figure 7 As shown, the method for the SOC interconnection system includes steps S100 to S110. The method for the SOC interconnection system can be applied to the SOC interconnection system provided by any embodiment of the present disclosure, for example.

[0193] Step S100: Grouping a plurality of computing devices into a plurality of computing device groups based on the purpose requirements and memory types of the plurality of computing devices.

[0194] Step S110: Setting a corresponding routing device for each computing device group in the plurality of computing device groups.

[0195] For the specific contents of S100 to S110 , for example, reference may be made to the relevant description of the aforementioned embodiment, which will not be repeated here.

[0196] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the purpose requirements include the frequency of mutual access between multiple computing devices, and the type of memory includes static random access memory, tightly coupled memory, or read-only memory.

[0197] For example, in a method for a SOC interconnection system provided by an embodiment of the present disclosure, the mutual access frequency includes the interaction frequency between multiple computing devices based on data dependency, control relationship and / or upstream and downstream task collaboration.

[0198] For example, in a method for a SOC interconnection system provided by an embodiment of the present disclosure, the SOC interconnection system also includes at least one delay-sensitive computing device, the at least one delay-sensitive computing device is coupled to multiple routing devices, and the at least one delay-sensitive computing device is configured to access the first target computing device through the routing device corresponding to the first target computing device.

[0199] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, multiple routing devices corresponding to multiple computing device groups are coupled to each other, and the method also includes step S120: establishing an interconnection relationship between multiple computing device groups through multiple routing devices.

[0200] For example, in a method for a SOC interconnection system provided by an embodiment of the present disclosure, multiple computing device groups include a first computing device group and a second computing device group, a first routing device corresponding to the first computing device group is coupled to a second routing device corresponding to the second computing device group, and S120 also includes step S121: the first computing device in the first computing device group accesses the second target computing device in the second computing device group through the first routing device and the second routing device.

[0201] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the target requirements include the functional coupling degree between multiple computing devices, the functional coupling degree includes the host types corresponding to the multiple computing devices, and the type of memory includes dynamic random access memory.

[0202] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, a corresponding routing device is set for each computing device group in a plurality of computing device groups, including: setting a corresponding routing device for each computing device group; the method also includes step S130: forming a corresponding data transmission path through the routing device corresponding to each computing device group and the memory port corresponding to each computing device group.

[0203] For example, in a method for a SOC interconnection system provided by an embodiment of the present disclosure, multiple computing device groups include a third computing device group and a fourth computing device group; the third computing devices in the third computing device group are respectively coupled to a routing device corresponding to the third computing device group and a routing device corresponding to the fourth computing device group.

[0204] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the third computing device is configured to form a main data transmission path through a routing device corresponding to the third computing device group and a memory port corresponding to the third computing device group; the third computing device is also configured to form an alternative data transmission path through a routing device corresponding to the fourth computing device group and a memory port corresponding to the fourth computing device group. For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the method further includes step S140: in response to monitoring that a bandwidth occupancy threshold of a routing device corresponding to the third computing device is lower than a corresponding preset threshold, generating a corresponding memory port idle signal; and in response to receiving the memory port idle signal, switching the data transmission path of the third computing device from the main data transmission path to the alternative data transmission path.

[0205] For example, in a method for a SOC interconnection system provided in an embodiment of the present disclosure, the host type corresponding to the third computing device is a high bandwidth requirement category.

[0206] It should be noted that, for the relevant contents of the functions or beneficial effects of each step in the method for a SOC interconnection system provided in any embodiment of the present disclosure, for example, reference can be made to the relevant description of the SOC interconnection system provided in any embodiment of the present disclosure, and will not be repeated here.

[0207] Figure 8 A schematic diagram of an application of another SOC interconnection system provided by at least one embodiment of the present disclosure is shown.

[0208] At least one embodiment of the present disclosure also provides a SOC interconnection system.

[0209] For example, Figure 8 As shown, the SOC interconnection system includes bus domain division and subsystem interconnection.

[0210] For example, the AP domain NOC bus can be used to connect the main CPU and high-performance processing subsystems, including NPU, GPU, DPU, and VPU. The bus can, for example, adopt a high-bandwidth and low-latency design and support dynamic voltage frequency scaling (DVFS).

[0211] For example, the TOP domain NOC bus can be used to connect low-power management and light-load modules, including PMU, SensorHub, and security subsystem. The bus can, for example, adopt a low static power design and support multi-level clock gating.

[0212] For example, the DDR domain NOC bus can be used to provide a DDR access channel with a built-in address interleaver to achieve bandwidth optimization.

[0213] For example, a DDRC includes multiple DDRC ports.

[0214] For example, the subsystems of the SOC interconnect system can be configured to access the DDR through the following paths:

[0215] AP domain subsystem → AP-DDR bus interface → DDR domain;

[0216] TOP domain subsystem → TOP-DDR bus interface → DDR domain;

[0217] The TOP domain security CPU can access the AP domain slaves across domains through the TOP-AP bus interface.

[0218] For example, the SOC interconnect system also includes a power management architecture.

[0219] For example, the Always-on system (AON), independent of the NOC bus, includes a wake-up controller and a basic timing unit that can be configured to maintain power in deep sleep mode.

[0220] For example, the SOC interconnection system also includes a voltage domain configuration.

[0221] For example, the main voltage domain, including CPU / GPU / NPU / DDR controller. For example, it can support DVFS (0.6V-1.2V dynamic adjustment)

[0222] For example, a low power voltage domain may cover the aforementioned TOP domain module.

[0223] For example, programmable voltage domains can be dynamically merged according to DVS requirements, such as merging the ISP module into the main voltage domain.

[0224] For example, the PMU island design can adopt an independent power supply loop to support the reconstruction of the SOC power supply sequence after external interrupt wake-up.

[0225] For example, the SOC interconnection system also includes a memory access optimization design.

[0226] For example, a low latency path can be configured. For example, the CPU directly accesses the DDR after address interleaving through the DDR_NOC and exclusively uses a port of the DDRC.

[0227] For example, a high-bandwidth path can be configured. For example, the NPU can directly access the DDR after address interleaving through the DDR_NOC, or it can exclusively use a port of the DDRC.

[0228] For example, a hybrid access mechanism can be configured, such as GPUs sharing the AP domain bus, and a priority arbiter is used to ensure that real-time tasks are scheduled first.

[0229] For example, the SOC interconnection system is also configured with a dynamic power consumption control process.

[0230] For example, scene recognition can be performed. For example, the PMU switches the working mode (performance / balanced / low power consumption) according to the load characteristics.

[0231] For example, voltage domain adjustments can be made, such as performing sequential power-down of inactive subsystems (first shutting down peripheral interfaces, then shutting down clocks, and finally shutting down power).

[0232] For example, bus state management can be performed, such as an inactive bus domain entering retention mode, retaining register states while reducing power.

[0233] Fig. 9 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0234] At least some embodiments of the present disclosure also provide an electronic device.

[0235] For example, processor 501 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities; for example, the central processing unit (CPU) may be a RISC, X86, or ARM architecture, etc.

[0236] The electronic device 500 in the embodiment of the present disclosure may include mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as any devices such as digital TVs, desktop computers, servers, etc., and may also be a combination of any data processing devices and hardware, which is not limited by the embodiments of the present disclosure.

[0237] For example, the electronic device 500 may also include the SOC interconnection system provided by any embodiment of the present disclosure.

[0238] Fig. 9 The electronic device 500 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0239] For example, Fig. 9 As shown, in some examples, the processor 501 can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 502 or the program loaded from the memory 508 to the random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the computer system are also stored. The processor 501, ROM 502 and RAM 503 are connected to each other through a communication channel 504. An input / output (I / O) interface 505 is also connected to the communication channel 504.

[0240] For example, the following components may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a memory 508 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 509 may allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 510 is also connected to the I / O interface 505 as needed. Removable media 511, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 510 as needed, so that the computer program read therefrom can be installed into the memory 508 as needed. Although Fig. 9 The electronic device 500 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0241] For example, the electronic device 500 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 509 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0242] It should be noted that in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 500 can be referred to, for example, the method for the SOC interconnection system and the related description of the SOC interconnection system in the above embodiments of the present disclosure, and will not be repeated here.

[0243] Fig.10 A schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure is shown.

[0244] At least one embodiment of the present disclosure further provides an electronic device, such as Fig.10 As shown, the electronic device 600 includes at least one processor 610 and at least one memory 620 .

[0245] For example, the memory 620 may be used to store computer-readable instructions (e.g., one or more computer program modules) in a non-temporary manner. The processor 610 may be used to execute the computer-readable instructions, and when the computer-readable instructions are executed by the processor 610, one or more steps in the method for the SOC interconnection system described above may be executed. The memory 620 and the processor 610 may be interconnected through a bus or link, in a wired, wireless, and / or other form of communication medium, etc., and the embodiments of the present disclosure are not limited to this.

[0246] For example, the processor 610 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be a RISC, X86, or ARM architecture, etc. The processor 610 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 600 to perform desired functions.

[0247] For example, the memory 620 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 610 may run one or more computer program modules to implement various functions of the electronic device 600. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0248] At least one embodiment of the present disclosure further provides a non-transitory computer-readable storage medium, which is used to non-temporarily store computer-readable instructions. When the computer-readable instructions are executed by a computer, the above-mentioned method for the SOC interconnection system can be implemented.

[0249] Fig.11 A schematic diagram of a computer-readable storage medium provided for some embodiments of the present disclosure.

[0250] like Fig.11 As shown, the computer-readable storage medium 700 is used to store computer-readable instructions 710. For example, when the computer-readable instructions 710 are executed by a computer, one or more steps in the method for the SOC interconnection system described above can be performed.

[0251] For example, the computer-readable storage medium 700 may be applied to the electronic device 500 or the electronic device 600. For example, the relevant description of the non-volatile computer-readable storage medium 700 may also refer to Fig. 9 The memory 508 in the electronic device 500 is shown as well as Fig.10 The corresponding description of the memory 620 in the electronic device 600 is shown and will not be repeated here.

[0252] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the computer-readable storage medium 700 can be referred to, for example, the above description of the method for the SOC interconnection system and the SOC interconnection system, and will not be repeated here.

[0253] There are a few points to note:

[0254] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0255] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0256] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A SOC interconnection system, comprising: a plurality of computing devices configured as a plurality of computing device groups; The plurality of computing device groups are groups of the plurality of computing devices based on the frequency of mutual access between the plurality of computing devices. Each computing device group in the plurality of computing device groups is provided with a corresponding routing device, Each computing device in each computing device group is coupled to the corresponding routing device, The multiple routing devices corresponding to the multiple computing device groups are coupled to each other.

2. The SOC interconnection system according to claim 1, wherein: The mutual access frequencies include: The frequency of interactions between multiple computing devices based on data dependencies, control relationships, and / or upstream and downstream task collaboration.

3. The SOC interconnection system according to claim 1, wherein: The plurality of computing devices also include a corresponding plurality of memories, The types of the memory include static random access memory, tightly coupled memory or read-only memory.

4. The SOC interconnection system according to claim 1, further comprising: at least one delay-sensitive computing device, wherein the at least one delay-sensitive computing device is coupled to the corresponding plurality of routing devices, The at least one delay-sensitive computing device is configured to access the first target computing device through a routing device corresponding to the first target computing device.

5. The SOC interconnection system according to claim 1, wherein: The plurality of computing device groups include a first computing device group and a second computing device group, The first routing device corresponding to the first computing device group is coupled to the second routing device corresponding to the second computing device group, The first computing device in the first computing device group is configured to access the second target computing device in the second computing device group through the first routing device and the second routing device.

6. A SOC interconnection system, comprising: a plurality of computing devices configured as a plurality of computing device groups; The plurality of computing device groups are groupings of the plurality of computing devices based on functional coupling between the plurality of computing devices; Each computing device group in the plurality of computing device groups is provided with a corresponding routing device, Each computing device in each computing device group is coupled to the corresponding routing device.

7. The SOC interconnection system according to claim 6, wherein: The degree of functional coupling includes the type of computing device.

8. The SOC interconnection system according to claim 6, further comprising: Memory; Wherein, the type of the memory includes dynamic random access memory; Each computing device group in the plurality of computing device groups is provided with a corresponding memory port, Each computing device group is configured to be coupled to the corresponding memory port through the corresponding routing device to form a corresponding data transmission path.

9. The SOC interconnection system according to claim 8, wherein: The plurality of computing device groups include a first computing device group and a second computing device group, The first computing device in the first computing device group is coupled to the first memory port corresponding to the first computing device group through the first routing device corresponding to the first computing device group. The first computing device is coupled to a second memory port corresponding to the second computing device group through a second routing device corresponding to the second computing device group. The first computing device is configured to form a first data transmission path through the first routing device and the first memory port; The first computing device is further configured to form a second data transmission path through the second routing device and the second memory port, wherein the second data transmission path is configured as an alternative data transmission path of the first computing device.

10. The SOC interconnection system according to claim 8, further comprising: Monitoring devices; The monitoring device is configured to monitor a bandwidth occupancy threshold of the second routing device, and In response to the bandwidth occupancy threshold of the second routing device being lower than the corresponding preset threshold, generating a corresponding memory port idle signal; The first computing device is provided with a corresponding data transmission path selector; The data transmission path selector is configured to switch the data transmission path of the first computing device to the second data transmission path in response to receiving the memory port idle signal.

11. The SOC interconnection system according to claim 9, wherein: The first computing device comprises a high bandwidth demanding type of computing device.

12. A SOC interconnection system, comprising: a plurality of computing devices configured as a plurality of computing device groups; The plurality of computing device groups are groups of the plurality of computing devices based on a first grouping type and / or a second grouping type among the plurality of computing devices. Each computing device group in the plurality of computing device groups is provided with a corresponding routing device, Each computing device in each computing device group is coupled to the corresponding routing device.

13. The SOC interconnection system according to claim 12, wherein: The first grouping type includes a frequency of mutual access between the plurality of computing devices, The second grouping type includes a degree of functional coupling between the plurality of computing devices.

14. A method for a SOC interconnection system, the SOC interconnection system comprising a plurality of computing devices and a memory, the method comprising: Based on the purpose requirements of the plurality of computing devices and the types of the memory, the plurality of computing devices are grouped into a plurality of computing device groups; as well as A corresponding routing device is provided for each computing device group in the plurality of computing device groups, wherein each computing device in each computing device group is coupled to the corresponding routing device.

15. The method of claim 14, wherein: The purpose requirement includes the frequency of mutual access between the plurality of computing devices, The mutual access frequency includes the interaction frequency between multiple computing devices based on data dependency, control relationship and / or upstream and downstream task collaboration, The types of the memory include static random access memory, tightly coupled memory or read-only memory.

16. The method of claim 14, wherein: The purpose requirements include the functional coupling between multiple computing devices, The functional coupling degree includes the host types corresponding to the plurality of computing devices, The types of memory include dynamic random access memory.

17. An electronic device comprising: processor; as well as A memory, wherein the memory stores at least one computer program, and when the at least one computer program is executed by the processor, the method for a SOC interconnection system described in any one of claims 14 to 16 is implemented.

18. A non-transitory computer-readable storage medium for non-temporarily storing computer-readable instructions, which, when executed by a computer, implements the method for a SOC interconnection system as claimed in any one of claims 14 to 16.

19. An electronic device comprising the SOC interconnection system according to any one of claims 1-13.

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