A Fast Fourier Transform Method, Device, and Medium Based on FPGA for 256K Points

Abstract

The present invention discloses a method, device and medium for fast Fourier transform of 256K points based on FPGA. This method realizes the fast Fourier transform of real-time data stream of 256K points based on FPGA, adopts fixed-point calculation, and supports two precisions of 16 bits and 32 bits. The present invention adopts a pipeline design, uses a radix-2<supgt;2< / supgt> butterfly basic processing unit, and divides the 256K-point FFT into 18 levels for processing in the way of frequency extraction. Each level of operation unit is divided into a delay unit and a butterfly calculation unit. Different from the traditional radix-2 decomposition that decomposes the 256K-point FFT into 2×2<supgt;17< / supgt>, the present invention decomposes the whole FFT into 2<supgt;10< / supgt>×2<supgt;8< / supgt>, which can reduce the storage occupancy of rotation factors; at the same time, logic is used to implement the delay under the condition of short delay, reducing the use of on-chip storage resources and improving the utilization rate of storage resources; only 8 levels of the 18-level processing units require multipliers, reducing the use of multipliers.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and particularly to a method, device and medium for fast Fourier transform of 256K points based on FPGA. Background Art

[0002] DFT (Discrete Fourier Transform) is one of the most effective digital signal processing methods and is widely used in various fields such as astronomical signal processing, radar signal processing, mobile communication, etc. In 1965, Cooley and Tukey proposed the fast Fourier transform algorithm by using the symmetry of the rotation factor, which greatly improved the calculation speed of DFT and reduced the calculation complexity of DFT. Since then, FFT (Fast Fourier Transform) has become one of the most commonly used digital signal processing methods. With the development of front-end collectors, the sampling rate is getting higher and higher, and there is a further demand for the processing rate and depth of FFT. FFT with a large number of points has received more and more attention. The increase in the depth of FFT means more storage space, more multipliers, and more calculation delays.

[0003] Currently, the high-performance computing processors for FFT mainly include digital signal processors (DSP), application specific integrated circuits (ASIC), and field programmable gate arrays (FPGA). Among them, FPGA has relatively high flexibility compared to DSP and ASIC, integrates a large number of parallel computing resources and storage resources inside, and has a high matching degree with the pipelined FFT processing structure. Therefore, the FFT method based on FPGA has been widely studied and applied.

[0004] At present, a large number of studies have been carried out by research scholars on the FFT method based on FPGA. However, for the real-time calculation requirements of FFT with a large number of points and configurable precision, the current FFT methods have problems of low calculation efficiency and high storage resources. Summary of the Invention

[0005] The purpose of the present invention is to provide a method, device and medium for fast Fourier transform of 256K points based on FPGA in view of the deficiencies of the prior art. The specific technical solutions are as follows:

[0006] A method for fast Fourier transform of 256K points based on FPGA includes the following steps:

[0007] Step 1: Determine the calculation precision to be 16 bits or 32 bits, calculate and store the rotation factors of 16, 64, 256, 1024, and 256K points in advance in the storage unit; instantiate the rotation factor storage units with different bit widths according to the calculation precision.

[0008] Step 2: Adopt the radix-2 2 butterfly basic processing unit, and decompose the 256K-point data stream into 2 10 ×2 8 firstly in the way of frequency extraction, then decompose the 2 10 into 2 2 ×2 8 , decompose the 2 8 into 2 2 ×2 6 , then decompose the 2 6 into 2 2 ×2 4 again, then decompose the 2 4 into 2 2 ×2 2 finally, decompose the 2 2 into 2×2, and perform 18 levels of delay and butterfly calculations, that is, the rotation factor bases of 18 levels are 2 2 、2 10 、2 2 、2 8 、2 2 、2 6 、2 2 、2 4 、2 2 、2 18 、2 2 、2 8 、2 2 、2 6 、2 2 、2 4 、2 2 、2 0 respectively.

[0009] Furthermore, in the second step, 18 levels of delay and butterfly calculations are performed, where

[0010] the specific operations of the odd-level decomposition in 18 levels are as follows:

[0011] The S-th level is divided into 2 S-1 group operations in total, S represents the level number, and S takes odd numbers from 1 to 18; taking 2 19-S points as a group in sequence, cache the first 2 18-S points of the input data; when the last 2 18-S points are input, read out the first 2 18-S points in sequence, with an interval of 2 18-SThe two points are grouped in pairs for butterfly operations; the sum of the two data of the nth pair of butterflies in the mth group gives the output of the (n + 2) 19-S ×(m - 1) points, and the difference between the two data of the nth pair of butterflies in the mth group gives the output of the (n + 2) 19-S ×(m - 1)+ 2 18-S points; the result of adding the two data is directly output; the result of subtracting the two data is written in-place into the storage unit, and after the second 18-S butterfly calculations are complete, they are read out sequentially starting from the first storage address; then the subsequent group of data is calculated in the same way; the last 2 17-S points of each group of output data are multiplied by -j, where j*j = -1, that is, the sign bit of the real part is inverted to become the imaginary part, and the imaginary part becomes the real part;

[0012] The specific operations for the even-level decomposition in the 18 levels are as follows:

[0013] The Sth level is divided into 2 S-1 group operations in total, S represents the level number, and S takes even numbers from 1 to 18; in groups of 2 19-S points in sequence, the first 2 18-S points of the input data are cached; when the last 2 18-S points are input, the first 2 18-S points are read out in sequence, and the two points with an interval of 2 18-S are grouped in pairs for butterfly operations; for the nth pair of butterflies in the mth group, the sum of the two data gives the output of the (n + 2) 19-S ×(m - 1) points, and the difference between the two data gives the output of the (n + 2) 19-S ×(m - 1)+ 2 18-S points; the result of adding the two data is directly output; the result of subtracting the two data is written in-place into the storage unit, and after the second 18-S butterfly calculations are complete, they are read out sequentially starting from the first storage address; then the subsequent group of data is calculated in the same way; the 256K points output by the first sixteen levels are multiplied by the calculated rotation factors respectively, and the calculated data is truncated to the high-order data according to the precision configuration, and the bit width remains unchanged, and the data of the eighteenth level is directly output to obtain the final FFT result.

[0014] Furthermore, in the first step, the rotation factors for 16, 64, and 256 points are calculated in advance and stored in registers respectively; the rotation factors for 1024 and 256K points are calculated in advance and stored in ROM respectively.

[0015] Furthermore, when the depth of the delay unit for performing delay calculations is not less than 256, a memory is used to implement the delay; otherwise, an on-chip logic unit is used to implement the delay.

[0016] Further, when performing 18 - level delay and butterfly calculations, the multiplier appears only at the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th levels.

[0017] Further, when the multiplier performs complex multiplication, it is implemented using 3 real - number multiplications and 5 real - number additions.

[0018] Further, the storage of the rotation factors only stores 1 / 8 of the length.

[0019] Further, the rotation factors at even levels are obtained as follows:

[0020] The 256K points obtained from each - level butterfly calculation are respectively multiplied by the rotation factors, and the output sequence number index is represented in 18 - bit binary as index[17:0];

[0021] The rotation factor at the second level is ;

[0022] The rotation factor at the fourth level is ;

[0023] The rotation factor at the sixth level is ;

[0024] The rotation factor at the eighth level is ;

[0025] The rotation factor at the tenth level is ;

[0026] The rotation factor at the twelfth level is ;

[0027] The rotation factor at the fourteenth level is ;

[0028] The rotation factor at the sixteenth level is .

[0029] A 256K - point fast Fourier transform device based on FPGA includes 18 butterfly calculation units, 8 rotation factor generation units, and delay units with a depth of 2 i where i takes integer values from 0 to 17;

[0030] The butterfly calculation unit is a radix - 2 butterfly calculation unit, which is used to implement the butterfly operation of data and complete the interleaving of data.

[0031] The 8 rotation factor generation units are respectively located in the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th - level calculations. Among them,

[0032] The second - level rotation factor generation unit is used to generate 1024 - point rotation factors with precisions of 16 bits or 32 bits;

[0033] The fourth - level rotation factor generation unit and the twelfth - level rotation factor generation unit are both used to generate 256 - point rotation factors with precisions of 16 - bit or 32 - bit respectively;

[0034] The sixth - level rotation factor generation unit and the fourteenth - level rotation factor generation unit are both used to generate 64 - point rotation factors with precisions of 16 - bit or 32 - bit respectively;

[0035] The eighth - level rotation factor generation unit and the sixteenth - level rotation factor generation unit are both used to generate 16 - point rotation factors with precisions of 16 - bit or 32 - bit respectively;

[0036] The tenth - level rotation factor generation unit is used to generate 256k - point rotation factors with precisions of 16 - bit or 32 - bit respectively;

[0037] The delay unit includes a memory and an address control unit to achieve data delay of different lengths; the memory is used to store the data input of this level and the output of the butterfly operation subtraction; the address control unit is used to control the read - write address of the memory and the control signal of the memory to achieve the delay function.

[0038] A computer - readable storage medium stores a program, which when executed by a processor, is used to implement the above - mentioned FPGA - based 256K - point fast Fourier transform method.

[0039] The beneficial effects of the present invention are as follows:

[0040] (1) The present invention decomposes the FFT as a whole according to 2 10 ×2 8 decomposition, which can reduce the storage occupancy of the rotation factors.

[0041] (2) The present invention can use logic to achieve delay under the condition of short delay, reducing the use of on - chip storage resources and improving the utilization rate of storage resources; at the same time, only 8 levels among the 18 - level processing units require multipliers, reducing the use of multipliers.

[0042] (3) The present invention can adapt to two different precisions of 16 - bit and 32 - bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is the overall architecture diagram of the FPGA - based 256K - point FFT according to the embodiment of the present invention;

[0044] Figure 2 is the schematic diagram of the calculation structure of each level according to the embodiment of the present invention;

[0045] Figure 3 is the schematic diagram of the butterfly calculation structure according to the embodiment of the present invention;

[0046] Figure 4 is a binary tree decomposition diagram, where Figure 4 (a) in is a binary tree decomposition diagram with base 2, Figure 4 (b) in is a binary tree decomposition diagram with base 2 2 of, Figure 4 (c) in is the binary tree decomposition diagram adopted in the embodiment of the present invention.

[0047] Figure 5 is a schematic diagram of a 256K-point fast Fourier transform device based on FPGA in the embodiment of the present invention. Specific embodiments

[0048] The present invention will be described in detail below according to the accompanying drawings and preferred embodiments. The purpose and effect of the present invention will become more apparent. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0050] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "the", and "said" used in the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0051] It should be understood that although the terms first, second, third, etc. may be used in the present invention to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to a determination".

[0052] The present invention will be described in detail below in conjunction with the accompanying drawings. Without conflict, the features in the following embodiments and implementation manners can be combined with each other.

[0053] As Figure 1As shown, the 256K-point fast Fourier transform method based on FPGA of the present invention is applied to astronomical signal processing in this embodiment, and includes the following steps:

[0054] Step 1: Determine the calculation precision to be 16 bits or 32 bits. Calculate and store the rotation factors of 16, 64, 256, 1024, and 256K points in the storage unit in advance. Calculate the two precisions of 16 bits and 32 bits, and select the rotation factor storage unit with different bit widths according to the precision. That is, if the precision is 16 bits, instantiate the rotation factor storage unit with a precision of 16; if the precision is 32 bits, instantiate the rotation factor storage unit with a precision of 32.

[0055] Step 1 includes the following sub-steps:

[0056] (1.1) Calculate , and amplify the calculation results by 2 15 and 2 31 respectively to obtain the results with 16-bit precision and 32-bit precision, and store them in the register;

[0057] (1.2) Calculate , and amplify the calculation results by 2 15 and 2 31 respectively to obtain the results with 16-bit precision and 32-bit precision, and store them in the register;

[0058] (1.3) Calculate , and amplify the calculation results by 2 15 and 2 31 respectively to obtain the results with 16-bit precision and 32-bit precision, and store them in the register;

[0059] (1.4) Calculate , and amplify the calculation results by 2 15 and 2 31 respectively to obtain the results with 16-bit precision and 32-bit precision, and store them in the read-only memory (ROM);

[0060] (1.5) Calculate , and amplify the calculation results by 2 15 and 2 31 respectively to obtain the results with 16-bit precision and 32-bit precision, and store them in the ROM;

[0061] (1.6) Determine that the calculation precision is 16 bits or 32 bits, and instantiate the rotation factor storage unit with different bit widths according to the precision.

[0062] Step 2: Adopt the radix-2 2 butterfly basic processing unit, and decompose the 256K-point data stream into 2 10×2 8 , then decompose 2 10 into 2 2 ×2 8 , decompose 2 8 into 2 2 ×2 6 , then decompose 2 6 into 2 2 ×2 4 , then decompose 2 4 into 2 2 ×2 2 , finally decompose 2 2 into 2×2, perform 18 - stage delay and butterfly calculations, that is, the rotation factor bases of 18 stages are successively 2 2 , 2 10 , 2 2 , 2 8 , 2 2 , 2 6 , 2 2 , 2 4 , 2 2 , 2 18 , 2 2 , 2 8 , 2 2 , 2 6 , 2 2 , 2 4 , 2 2 , 2 0 .

[0063] The overall structure is as shown in Figure 1 , divided into 18 - stage calculation units, and the size of the delay unit decreases gradually. The calculation structure of each stage is as shown in Figure 2 , and the butterfly calculation architecture is as shown in Figure 3 . Figure 4 In (a) of it is the binary tree decomposition diagram of radix - 2, (b) is the binary tree decomposition diagram of radix - 2 2 , and (c) is the binary tree decomposition diagram adopted by the present invention. The numbers in the figure represent the powers of 2. The decomposition method in the present invention can reduce the number of multipliers compared with the radix - 2 decomposition, and compared with the traditional radix - 2 2 decomposition, it reduces the number of large values of the subscripts of the large rotation factors, thus reducing the storage requirement of the rotation factors, as shown in Table 1 and Table 2 below.

[0064] Table 1 Figure 4 The number of adders required for three different binary tree decomposition methods in

[0065]

[0066] Table 2 Figure 4 The storage requirement of the rotation factors for three different binary tree decomposition methods in

[0067]

[0068] Step 2 specifically includes the following sub-steps:

[0069] (2.1) The first stage performs the following operations: Cache the first 128K points of the input data using on-chip RAM. When the last 128K points are input, read out the first 128K points in sequence. For every two points separated by 128K, perform butterfly operations in pairs, with a total of 128K pairs, 1 group. For the nth pair of butterflies, add the two data to get the output of the nth point, subtract the two data to get the output of the (n + 128K)th point. Directly output the result of adding the two data to the second stage, and write the result of subtracting the two data back to the storage unit in place. After the 128Kth butterfly calculation is complete, read out from the first storage address to the second stage in sequence. At the same time, multiply the last 64K output data by -j (j*j = -1), that is, reverse the sign bit of the real part to become the imaginary part, and the imaginary part becomes the real part, without using multiplier resources.

[0070] (2.2) The second stage performs the following operations: The second stage is divided into 2 group operations. Taking 128K points as a group in sequence, cache the first 64K points of the input data using on-chip RAM. When the last 64K points are input, read out the first 64K points in sequence. For every two points separated by 64K, perform butterfly operations in pairs, with a total of 64K pairs, 2 groups. For the nth pair of butterflies in the mth group, add the two data to get the output of the (n + 128K×(m - 1))th point, subtract the two data to get the output of the (n + 128K×(m - 1)+64K)th point. Directly output the result of adding the two data, and write the result of subtracting the two data back to the storage unit in place. After the 64Kth butterfly calculation is complete, read out from the first storage address in sequence; then calculate the second group of data in the same way. Multiply the 256K output points by the rotation factors respectively. The output sequence number index is represented by 18-bit binary index[17:0], and the rotation factor is , calculate , the address read from the rotation factor storage unit is W addr , the read result is , the actual rotation factor is , according to different intervals of addr, the result is as shown in Equation 1. The calculated data is truncated to keep the high-order data according to the precision configuration while maintaining the bit width unchanged.

[0071] (1)

[0072] The complex multiplication with the rotation factor is implemented using three multiplications and five additions to reduce the use of multipliers, specifically as follows:

[0073] ;

[0074] (2.3) The third stage performs the following operations: The third stage is divided into 4 group operations. Taking 64K points as a group in sequence, the first 32K points of the input data are cached using on-chip RAM. When the last 32K points are input, the first 32K points are read out in sequence. Two points separated by 32K are grouped in pairs for butterfly operations, with a total of 32K pairs and 4 groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 64K×(m - 1))th point, and the difference between the two data gives the output at the (n + 64K×(m - 1)+32K)th point. The result of adding the two data is directly output, and the result of subtracting the two data is written back to the storage unit in place. After the 32Kth butterfly calculation is complete, they are read out sequentially starting from the first storage address; then the subsequent group data is calculated in the same way. The last 16K points of each group of data are multiplied by -j (j*j = -1).

[0075] (2.4) The fourth stage performs the following operations: The fourth stage is divided into 8 group operations. Taking 32K points as a group in sequence, the first 16K points of the input data are cached using on-chip RAM. When the last 16K points are input, the first 16K points are read out in sequence. Two points separated by 16K are grouped in pairs for butterfly operations, with a total of 16K pairs and 8 groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 32K×(m - 1))th point, and the difference between the two data gives the output at the (n + 32K×(m - 1)+16K)th point. The result of adding the two data is directly output, and the result of subtracting the two data is written back to the storage unit in place. After the 16Kth butterfly calculation is complete, they are read out sequentially starting from the first storage address; then the subsequent group data is calculated in the same way. The 256K output points are each multiplied by a rotation factor. The output sequence number index is represented by 18-bit binary as index[17:0], and the rotation factor is , calculate , the address read from the rotation factor storage unit is W addr , the result read out is , the actual rotation factor is , according to different intervals of addr, the result is as shown in Equation 2. The calculated data is truncated to keep the high-order data according to the precision configuration while maintaining the bit width unchanged.

[0076] (2)

[0077] (2.5) The fifth stage performs the following operations: The fifth stage is divided into 16 group operations in total. Taking 16K points as a group in sequence, the first 8K points of the input data are cached using on-chip RAM. When the last 8K points are input, the first 8K points are read out in sequence. Two points with an interval of 8K are grouped in pairs for butterfly operations, with a total of 8K pairs and 16 groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 16K×(m - 1))th point, and the difference between the two data gives the output at the (n + 16K×(m - 1)+8K)th point. The result of adding the two data is directly output, and the result of subtracting the two data is written back to the storage unit in place. After the 8Kth butterfly calculation is complete, it is read out sequentially from the first storage address; then the subsequent group data is calculated in the same way. The last 4K points of each group of data are multiplied by -j (j*j = -1);

[0078] (2.6) The sixth stage performs the following operations: The sixth stage is divided into 32 group operations in total. Taking 8K points as a group in sequence, the first 4K points of the input data are cached using on-chip RAM. When the last 4K points are input, the first 4K points are read out in sequence. Two points with an interval of 4K are grouped in pairs for butterfly operations, with a total of 4K pairs and 32 groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 8K×(m - 1))th point, and the difference between the two data gives the output at the (n + 8K×(m - 1)+4K)th point. The result of adding the two data is directly output, and the result of subtracting the two data is written back to the storage unit in place. After the 4Kth butterfly calculation is complete, it is read out sequentially from the first storage address; then the subsequent group data is calculated in the same way. The 256K output points are each multiplied by a rotation factor. The output sequence number index is represented by 18-bit binary index[17:0], and the rotation factor is , and the calculation method is as above. The calculated data is truncated to keep the high-order data according to the precision configuration while maintaining the bit width unchanged;

[0079] (2.7) The seventh stage performs the following operations: The seventh stage is divided into 64 group operations in total. Taking 4K points as a group in sequence, the first 2K points of the input data are cached using on-chip RAM. When the last 2K points are input, the first 2K points are read out in sequence. Two points with an interval of 2K are grouped in pairs for butterfly operations, with a total of 2K pairs and 64 groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 4K×(m - 1))th point, and the difference between the two data gives the output at the (n + 4K×(m - 1)+2K)th point. The result of adding the two data is directly output, and the result of subtracting the two data is written back to the storage unit in place. After the 2Kth butterfly calculation is complete, it is read out sequentially from the first storage address; then the subsequent group data is calculated in the same way. The last 1K points of each group of data are multiplied by -j (j*j = -1);

[0080] (2.8) The eighth stage performs the following operations: The eighth stage is divided into 128 group operations. Taking 2K points as a group in sequence, the first 1K points of the input data are cached using on-chip RAM. When the last 1K points are input, the first 1K points are read out in sequence, and two points separated by 1K are grouped in pairs for butterfly operations, with a total of 1K pairs and 128 groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 2K×(m - 1))th point, and the difference between the two data gives the output at the (n + 2K×(m - 1)+1K)th point. The result of adding the two data is directly output, and the result of subtracting the two data is written back to the storage unit in-place. After the calculation of the 1Kth butterfly is complete, it is read out sequentially starting from the first storage address; then the subsequent group data is calculated in the same way. The 256K output points are multiplied by the twiddle factors respectively. The output sequence number index is represented by 18-bit binary as index[17:0], and the twiddle factor is , and the calculation method is as above. After calculation, the high-order data of the calculated data is intercepted according to the precision configuration to keep the bit width unchanged;

[0081] (2.9)The ninth stage performs the following operations: The ninth stage is divided into 256 group operations. Taking 1K points as a group in sequence, the first 512 points of the input data are cached using on-chip RAM. When the last 512 points are input, the first 512 points are read out in sequence, and two points separated by 512 are grouped in pairs for butterfly operations, with a total of 512 pairs and 256 groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 1K×(m - 1))th point, and the difference between the two data gives the output at the (n + 1K×(m - 1)+512)th point. The result of adding the two data is directly output, and the result of subtracting the two data is written back to the storage unit in-place. After the calculation of the 512th butterfly is complete, it is read out sequentially starting from the first storage address; then the subsequent group data is calculated in the same way. The last 256 points of each group of data are multiplied by -j (j*j=-1);

[0082] (2.10) The tenth stage performs the following operations: The tenth stage is divided into 512 group operations in total. Taking 512 points as a group in sequence, the first 256 points of the input data are input into the delay unit for caching. The on-chip RAM is used for caching. When the last 256 points are input, the first 256 points are read out in sequence. Two points with an interval of 256 are grouped in pairs for butterfly operations, a total of 256 pairs and 512 groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 512×(m - 1))th point, and the difference between the two data gives the output at the (n + 512×(m - 1)+256)th point. The result of adding the two data is directly output, and the result of subtracting the two data is written into the storage unit in place. After the 256th butterfly calculation is complete, it is read out sequentially from the first storage address; then the subsequent group data is calculated in the same way. The 256K output points are multiplied by the rotation factors respectively. The output serial number index is represented by 18-bit binary as index[17:0], and the rotation factor is , calculated as above, and the calculated data intercepts the high-order data according to the precision configuration to keep the bit width unchanged;

[0083] (2.11) The eleventh stage performs the following operations: The eleventh stage is divided into 1K group operations in total. Taking 256 points as a group in sequence, the first 128 points of the input data are input into the delay unit. The delay unit uses internal logic to implement a delay of 128 beats. When the last 128 points are input, they are grouped in pairs with the first 128 points for butterfly operations, a total of 256 pairs and 1K groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 256×(m - 1))th point, and the difference between the two data gives the output at the (n + 256×(m - 1)+128)th point. The result of adding the two data is directly output, and the result of subtracting the two data is input into the delay unit. After the 128th butterfly calculation is complete, the data output of the delay unit is valid; then the subsequent group data is calculated in the same way. The last 64 points of each group of data are multiplied by -j (j*j = -1);

[0084] (2.12) The twelfth stage performs the following operations: The twelfth stage is divided into 2K group operations in total. Taking 128 points as a group in sequence, the first 64 points of the input data are input into the delay unit. The delay unit uses internal logic to implement a delay of 64 beats. When the last 64 points are input, they are grouped in pairs with the first 64 points for butterfly operations, a total of 64 pairs and 2K groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 128×(m - 1))th point, and the difference between the two data gives the output at the (n + 128×(m - 1)+64)th point. The result of adding the two data is directly output, and the result of subtracting the two data is input into the delay unit. After the 64th butterfly calculation is complete, the data output of the delay unit is valid; then the subsequent group data is calculated in the same way. The 256K output points are multiplied by the rotation factors respectively. The output serial number index is represented by 18-bit binary as index[17:0], and the rotation factor is , the calculation method is as above, and the calculated data intercepts the high-order data according to the precision configuration to keep the bit width unchanged;

[0085] (2.13) The following operations are performed at the thirteenth level: The thirteenth level is divided into 4K group operations. In order, 64 points are in a group. The first 32 points of the input data are input into the delay unit. The delay unit uses internal logic to implement a delay of 32 beats. When the last 32 points are input, they are paired with the first 32 points one by one for butterfly operations, a total of 32 pairs, 4K groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 64×(m - 1))th point, and the difference between the two data gives the output at the (n + 64×(m - 1) + 32)th point. The result of adding the two data is directly output, and the result of subtracting the two data is input into the delay unit. After the 32nd butterfly calculation is complete, the data output of the delay unit is valid; then the subsequent group data is calculated in the same way. The last 16 points of each group of data are multiplied by -j (j*j = -1);

[0086] (2.14) The following operations are performed at the fourteenth level: The fourteenth level is divided into 8K group operations. In order, 32 points are in a group. The first 16 points of the input data are input into the delay unit. The delay unit uses internal logic to implement a delay of 16 beats. When the last 16 points are input, they are paired with the first 16 points one by one for butterfly operations, a total of 16 pairs, 8K groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 32×(m - 1))th point, and the difference between the two data gives the output at the (n + 32×(m - 1) + 16)th point. The result of adding the two data is directly output, and the result of subtracting the two data is input into the delay unit in place. After the 16th butterfly calculation is complete, the data output of the delay unit is valid; then the subsequent group data is calculated in the same way. The 256K output points are multiplied by the rotation factor respectively. The output serial number index is represented by 18-bit binary as index[17:0], and the rotation factor is , the calculation method is as above, and the calculated data intercepts the high-order data according to the precision configuration to keep the bit width unchanged;

[0087] (2.15) The following operations are performed at the fifteenth level: The fifteenth level is divided into 16K group operations. In order, 16 points are in a group. The first 8 points of the input data are input into the delay unit. The delay unit uses internal logic to implement a delay of 8 beats. When the last 8 points are input, they are paired with the first 8 points one by one for butterfly operations, a total of 8 pairs, 16K groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 16×(m - 1))th point, and the difference between the two data gives the output at the (n + 16×(m - 1) + 8)th point. The result of adding the two data is directly output, and the result of subtracting the two data is input into the delay unit in place. After the 8th butterfly calculation is complete, the data output of the delay unit is valid; then the subsequent group data is calculated in the same way. The last 4 points of each group of data are multiplied by -j (j*j = -1);

[0088] (2.16) The sixteenth stage performs the following operations: The sixteenth stage is divided into 32K group operations in total. In the order of 8 points as a group, the first 4 points of the input data are input into the delay unit. The delay unit uses internal logic to implement a delay of 4 beats. When the last 4 points are input, they are paired with the first 4 points one by one for butterfly operations, a total of 4 pairs, 32K groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 8×(m - 1))th point, and the subtraction of the two data gives the output at the (n + 8×(m - 1) + 4)th point. The result of adding the two data is directly output, and the result of subtracting the two data is input into the delay unit in place. After the 4th butterfly calculation is completed, the data output of the delay unit is valid; then the second group of data is calculated in the same way. The 256K output points are multiplied by the rotation factors respectively. The output sequence number index is represented by an 18-bit binary number index[17:0], and the rotation factor is , and the calculation method is as above. The calculated data intercepts the high-order data according to the precision configuration to keep the bit width unchanged;

[0089] (2.17) The seventeenth stage performs the following operations: The seventeenth stage is divided into 64K group operations in total. In the order of 4 points as a group, the first 2 points of the input data are input into the delay unit. The delay unit uses internal logic to implement a delay of 2 beats. When the last 2 points are input, they are paired with the first 2 points one by one for butterfly operations, a total of 2 pairs, 64K groups. For the nth pair of butterflies in the mth group, the sum of the two data gives the output at the (n + 4×(m - 1))th point, and the subtraction of the two data gives the output at the (n + 4×(m - 1) + 2)th point. The result of adding the two data is directly output, and the result of subtracting the two data is input into the delay unit in place. After the 32Kth butterfly calculation is completed, the data output of the delay unit is valid; then the subsequent groups of data are calculated in the same way. The last 1 point data of each group is multiplied by -j (j*j = -1);

[0090] (2.18) The eighteenth stage performs the following operations: The eighteenth stage is divided into 128K group operations in total. In the order of 2 points as a group, the first 1 point of the input data is input into the delay unit. The delay unit uses internal logic for 1-beat buffering. When the subsequent points are input, they just form a group of butterflies with the previous point for operation. There is a total of 1 pair, 128K groups. The sum of the two data in the mth group gives the output at the (2m - 1)th point, and the subtraction of the two data gives the output at the (2m - 1)th point. The result of adding the two data is directly output, and the result of subtracting the two data is buffered for 1 beat and then output. The final FFT result is obtained.

[0091] In addition, the embodiment of the present invention also provides a 256K-point fast Fourier transform device based on FPGA, including 18 butterfly calculation units, 8 rotation factor generation units, and delay units with depths of 2 i respectively, where i takes integer values from 0 to 17;

[0092] The butterfly computing unit is a radix-2 butterfly computing unit, which is used to implement the butterfly operation of data and complete the interleaving of data;

[0093] Eight rotation factor generation units are respectively located in the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th level computations. Among them,

[0094] The second-level rotation factor generation unit is used to generate 1024-point rotation factors with precisions of 16 bits or 32 bits respectively;

[0095] Both the fourth-level rotation factor generation unit and the twelfth-level rotation factor generation unit are used to generate 256-point rotation factors with precisions of 16 bits or 32 bits respectively;

[0096] Both the sixth-level rotation factor generation unit and the fourteenth-level rotation factor generation unit are used to generate 64-point rotation factors with precisions of 16 bits or 32 bits respectively;

[0097] Both the eighth-level rotation factor generation unit and the sixteenth-level rotation factor generation unit are used to generate 16-point rotation factors with precisions of 16 bits or 32 bits respectively;

[0098] The tenth-level rotation factor generation unit is used to generate 256k-point rotation factors with precisions of 16 bits or 32 bits respectively;

[0099] The delay unit includes a memory and an address control unit, and realizes data delays of different lengths; the memory is used to store the data input of this level and the output of the subtraction in the butterfly operation; the address control unit is used to control the read / write address of the memory and the control signal of the memory to realize the delay function.

[0100] As Figure 1 shown, 128k, 64k, 32k, 16k, 8k, 4k, 2k, 1k, 512, 256, 128, 64, 32, 16, 8, 4, 2, 1 represent delay units with different depths, BF2 represents the butterfly computing unit, and W represents the rotation factor base.

[0101] The fast Fourier transform device with 256K points based on FPGA according to an embodiment of the present invention further includes one or more processors for implementing the fast Fourier transform method with 256K points based on FPGA. The fast Fourier transform device with 256K points based on FPGA according to an embodiment of the present invention can be applied to any device with data processing capabilities, and the device with data processing capabilities can be a device or apparatus such as a computer. The device embodiment can be implemented by software, or by hardware or a combination of software and hardware. Taking software implementation as an example, as a logically meaningful device, it is formed by reading the corresponding computer program instructions in the non-volatile memory into the memory and running them through the processor of any device with data processing capabilities where it is located. From the hardware level, as Figure 5 shown, it is a hardware structure diagram of any device with data processing capabilities where the fast Fourier transform device with 256K points based on FPGA of the present invention is located. In addition to Figure 5 the processor, memory, network interface, and non-volatile memory shown, any device with data processing capabilities where the device in the embodiment is located usually further includes other hardware according to the actual functions of the device with data processing capabilities, which will not be elaborated here.

[0102] The specific implementation processes of the functions and roles of each unit in the above device can be specifically seen in the implementation processes of the corresponding steps in the above method, which will not be elaborated here.

[0103] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present invention. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0104] An embodiment of the present invention further provides a computer-readable storage medium, on which a program is stored. When the program is executed by a processor, it implements the fast Fourier transform method with 256K points based on FPGA in the above embodiment.

[0105] The computer-readable storage medium may be an internal storage unit of any device with data processing capabilities described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium may also be an external storage device, such as a plug-in hard disk, a SmartMedia card (SMC), an SD card, a Flash card, etc. equipped on the device. Further, the computer-readable storage medium may also include both an internal storage unit of any device with data processing capabilities and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by any device with data processing capabilities, and may also be used to temporarily store the data that has been output or is to be output.

[0106] Those of ordinary skill in the art can understand that the above are only preferred examples of the invention and are not used to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, for those skilled in the art, they can still modify the technical solutions described in the foregoing examples, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, etc. made within the spirit and principles of the invention shall be included within the protection scope of the invention.

Claims

1. A fast Fourier transform method for 256K points based on FPGA, characterized in that, It includes the following steps: Step 1: Determine the calculation precision to be 16 bits or 32 bits, calculate and store the rotation factors of 16, 64, 256, 1024, and 256K points in advance in the storage unit respectively; instantiate the rotation factor storage units with different bit widths according to the calculation precision. Step 2: Using the radix-2 2 butterfly basic processing unit, in the way of frequency extraction, the 256K-point data stream is first decomposed into 2 10 ×2 8 . Then, 2 10 is decomposed into 2 2 ×2 8 . Next, 2 8 is decomposed into 2 2 ×2 6 . Then, 2 6 is decomposed into 2 2 ×2 4 . Then, 2 4 is decomposed into 2 2 ×2 2 . Finally, 2 2 is decomposed into 2×2, and 18 levels of delay and butterfly calculations are performed. That is, the rotation factor bases for the 18 levels are 2 2 , 2 10 , 2 2 , 2 8 , 2 2 , 2 6 , 2 2 , 2 4 , 2 2 , 2 18 , 2 2 , 2 8 , 2 2 , 2 6 , 2 2 , 2 4 , 2 2 , 2 0 ; When performing 18 levels of delay and butterfly calculations, the multiplier only appears at the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th levels; The rotation factors of the even levels are obtained as follows: The 256K points obtained from each level of butterfly calculation are multiplied by the rotation factors respectively, and the output serial number index is represented by 18-bit binary as index[17:0]. The second-level rotation factor is ; The fourth-level rotation factor is ; The sixth-level rotation factor is ; The eighth-order rotation factor is ; The tenth-order rotation factor is ; The twelfth-stage rotation factor is ; The fourteenth rotation factor is ; The sixteenth rotation factor is .

2. The fast Fourier transform method based on FPGA with 256K points according to claim 1, wherein In Step 2, 18 levels of delay and butterfly calculation are performed, where The specific operations of the odd-level decomposition in the 18 levels are as follows: The S-level is divided into 2 S-1 group operations. S represents the level, and S takes odd numbers from 1 to 18; in order, 2 19-S points are a group, and the first 2 18-S points of the input data are cached; when the last 2 18-S points are input, the first 2 18-S points are read out in order, and every other 2 18-S points are grouped in pairs for butterfly operations; the sum of the two data of the nth pair of butterflies in the mth group gives the output of the (n + 2 19-S ×(m - 1))th point, and the difference between the two data of the nth pair of butterflies in the mth group gives the output of the (n + 2 19-S ×(m - 1)+ 2 18-S th point; the result of adding the two data is directly output; the result of subtracting the two data is written in place into the storage unit. After the 2 18-S butterfly calculations are complete, they are read out sequentially starting from the first storage address; then the subsequent group data is calculated in the same way; the last 2 17-S points of each group of output data are multiplied by -j, where j*j = -1, that is, the sign bit of the real part is inverted to become the imaginary part, and the imaginary part becomes the real part; The specific operations of the even-level decomposition in the 18 levels are as follows: The S-level is divided into 2 S-1 group operations. S represents the level, and S takes even numbers from 1 to 18. In order, 2 19-S points are taken as a group, and the first 2 18-S points of the input data are cached. When the last 2 18-S points are input, the first 2 18-S points are read out in order, and every other 2 18-S points are grouped in pairs for butterfly operations. For the nth pair of butterflies in the mth group, the sum of the two data gives the output of the (n + 2 19-S ×(m - 1))th point, and the difference between the two data gives the output of the (n + 2 19-S ×(m - 1)+ 2 18-S th point. The result of adding the two data is directly output. The result of subtracting the two data is written in place into the storage unit. After all 2 18-S butterfly calculations are completed, they are read out in sequence starting from the first storage address. Then, subsequent group data is calculated in the same way. The 256K points output by the first sixteen levels are multiplied by the calculated rotation factors respectively. The calculated data is truncated to the high-order data according to the precision configuration, and the bit width remains unchanged. The data of the eighteenth level is directly output to obtain the final FFT result.

3. The fast Fourier transform method based on FPGA with 256K points according to claim 1, characterized in that, In Step 1, the rotation factors of 16, 64, and 256 points are calculated and stored in the register in advance; the rotation factors of 1024 and 256K points are calculated and stored in the ROM in advance.

4. The fast Fourier transform method based on FPGA with 256K points according to claim 1, wherein When the depth of the delay unit for performing delay calculation is not less than 256, use the memory to implement the delay; otherwise, use the on-chip logic unit to implement the delay.

5. The fast Fourier transform method based on FPGA with 256K points according to claim 1, wherein, When the multiplier performs complex multiplication, it is implemented by 3 real multiplications and 5 real additions.

6. The fast Fourier transform method based on FPGA with 256K points according to claim 3, characterized in that, Only 1 / 8 of the length of the rotation factor is stored.

7. A 256K-point fast Fourier transform device based on FPGA, characterized in that, The device is used to implement the fast Fourier transform method based on FPGA with 256K points described in claim 1. The device includes 18 butterfly calculation units, 8 rotation factor generation units, and delay units with depths of 2 i respectively, where i takes integer values from 0 to 17; The butterfly calculation unit is a radix-2 butterfly calculation unit, which is used to implement the butterfly operation of data and complete the interleaving of data. Eight rotation factor generation units are respectively located in the calculations of the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th levels. Among them, the second-level rotation factor generation unit is used to generate the rotation factors of 1024 points with precisions of 16 bits or 32 bits respectively. Both the fourth-level rotation factor generation unit and the twelfth-level rotation factor generation unit are used to generate the rotation factors of 256 points with precisions of 16 bits or 32 bits respectively. Both the sixth-level rotation factor generation unit and the fourteenth-level rotation factor generation unit are used to generate the rotation factors of 64 points with precisions of 16 bits or 32 bits respectively. Both the eighth-level rotation factor generation unit and the sixteenth-level rotation factor generation unit are used to generate the rotation factors of 16 points with precisions of 16 bits or 32 bits respectively. The tenth-level rotation factor generation unit is used to generate the rotation factors of 256k points with precisions of 16 bits or 32 bits respectively. The delay unit includes a memory and an address control unit to implement data delay of different lengths; the memory is used to store the data input of this level and the output of the subtraction in the butterfly operation; the address control unit is used to control the read and write addresses of the memory and the control signal of the memory to implement the delay function.

8. A computer-readable storage medium, characterized in that, A program is stored thereon, and when the program is executed by a processor, it is used to implement the FPGA-based 256K-point fast Fourier transform method described in any one of claims 1-6.

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