45 results about "Fixed point computation" patented technology

The invention discloses an FPGA (Field Programmable Gate Array)-based general matrix fixed-point multiplier. An internal structure of the multiplier consists of a control module, a conversion module, an operation module and a storage module. The control module is used for generating a control signal according to dimension of a to-be-operated matrix. The conversion module is responsible for performing conversion between a fixed-point number and a floating-point number during operation. The operation module is used for reading operation data from the storage module and the conversion module, performing fixed-point multiplication and fixed-point accumulating operation and storing a result in the storage module. The storage module is used for caching to-be-operated matrix data and result matrix data, providing an interface compatible with a bus signal and allowing access of other components on a bus. The characteristic of high fixed-point calculation efficiency in hardware is fully utilized; by using a unique operation structure, simultaneous conversion and operation of the data are realized to improve the overall operation speed, and a plurality of matrix fixed-point multipliers can be simultaneously used to perform parallel calculation; thus the fixed-point multiplication of an arbitrary dimension matrix can be supported, and meanwhile extremely high calculation efficiency is guaranteed. Compared with matrix multiplication performed by using the floating-point number, the multiplier has the advantage that the calculation efficiency is greatly improved.

An efficient approach for SAT-based quantifier elimination and pre-image computation using unrolled designs that significantly improves the performance of pre-image and fix-point computation in SAT-based unbounded symbolic model checking.

The embodiment of the invention provides a computing method based on a neural network. The method comprises the steps of receiving an original image; extracting a feature tensor of the original image; and processing the feature tensor based on a trained fixed-point neural network to generate an image thermodynamic diagram. The embodiment of the invention provides the computing method in which the neural network is achieved by a fixed-point method, as fixed-point computation is adopted, a computation amount is small, fewer resources are occupied, and thus requirements on hardware is low.

This invention discloses a fix point divider, which comprises character generator, absolute generator, judger, difference generator and product generator. This invention also discloses one method of the fix point computation, which comprises the following steps: getting divider and divided absolute value to get product character for memory according to divider and divided; judging whether the divided value is larger or equal to divider absolute; if yes, then computing divided value highest valid bit and that of divider to get the different; getting the divided and divider product according to product bit, absolute value, otherwise output as zero.

The invention discloses a three-dimensional line of sight estimation method based on an iris projection matching function. The method firstly calculates human eye parameters and establishes a human eye model by letting a user look at a plurality of standard points on a screen. Then, the spatial position and orientation of the iris are located by the matching function of the eye rotation model andthe iris projection, and the three-dimensional optical axis direction is obtained. Finally, the polynomial correction method is used to correct the optical axis and calculate the direction of the three-dimensional axis of view. This method uses depth camera to estimate 3D line of sight, which provides a fast, accurate and robust solution for 3D line of sight tracking in natural environment.

A method for applying division of solving fixed-point number in video code flow rate control uses fixed-point processor to realize fixed-point division by utilizing NEWTON-RAPHSON iteration algorithm of Xi +1=Xi ( 2-DXi ). The method can raise operation speed of division in calculation course maximally under condition that minimum accurate requirement of video compression flow rate control is satisfied.

The invention belongs to the field of general in-memory computing, in particular to an in-memory computing system supporting general computing based on a magnetic random access memory. The in-memory computing system comprises a GCIM architecture, and the GCIM architecture comprises a spin transfer torque magnetic random access memory array, a shifter, a connector, a row decoder, a column decoder,a bit line driver, a calculation word line digital-to-analog converter, a pre-charging induction amplifier, a fifth-generation reduced instruction set processor, an instruction parser and a register.According to the invention, storage can be realized in the memory, and calculation operation can be carried out in the memory. Moreover, the method can effectively support general calculation (including logic calculation, fixed-point calculation, floating-point calculation and the like), fully utilizes a plurality of sub-array structures and improved shifters and connectors, improves the reconfigurability and calculation parallelism of the architecture, and improves the calculation efficiency.

The invention discloses a fixed-point type human face detection method. According to the method, fixed-point number conversion can be realized for parameters of a relevant training floating-point model of a waterfall cascaded classifier in an AdaBoost human face detection algorithm, and fixed-point calculation and conversion can be performed on a relevant floating-point calculation process. The method specifically comprises the steps of: (1) effective separation of relevant parameters of a strong classifier from relevant parameters of a weak classifier from the calibration perspective according to classified calculation characteristics of the strong classifier and the weak classifier in the waterfall cascaded classifier; (2) conversion of the floating-point number of the parameter theta into the fixed-point number, calculation of Harr features and fixed-point calculation of integral image calculation according to the classified calculation characteristics of the weak classifier; (3) conversion of the floating-point number of at and a_th in the strong classifier into the fixed-point number according to the classified calculation characteristics of the strong classifier and parameter definitions; and (4) conversion of floating-point calculation of the AdaBoost human face detection algorithm into fixed-point calculation.

A client device receives streamed encoded content data, such as encoded video data, which has been encoded at a constant perceptual quality. Several different versions of the content are available to be streamed to the device, at different perceptual quality levels. In order to decide which quality level to request from a content server at intervals the device calculates the delivery rates that would be required for each level of quality. The delivery rates are calculated in dependence on so-called critical points, which are points at which a piecewise constant bit rate delivery schedule is just equal to the decoding schedule. There are two classes of critical points, being a first class of critical points, referred to herein as “additional critical points”, which are points on the decoding schedule where, for any particular other point on the decoding schedule before an additional critical point, and assuming that a minimum threshold amount of data is buffered when delivery occurs from the particular point, a constant bit rate delivery schedule that is calculated for the particular point taking into account the buffered minimum amount of data and of such a rate such that buffer underflow does not occur is substantially equal to the decoding schedule. A second class of critical points, referred to herein as “downstairs critical points”, is also defined, which are derived from the decoding schedule as a whole, and which are the points at which a piecewise monotonically decreasing constant bit rate delivery schedule (the so-called “downstairs” schedule), which is calculated such that when delivering the encoded content data from the start buffer underflow does not occur, is substantially equal to the decoding schedule of the encoded content data. When the actual delivery rate received is ahead of the so-called “downstairs” schedule, then the delivery rate required for a particular quality level can be calculated from the second class of critical points. However, when the actual delivery rate received is behind the downstairs schedule, then the delivery rate required is calculated from the first class of critical points.

The invention discloses a method for color space conversion from HSL to RGB. The method includes the steps that standardization is carried out on the HSL, and the scope ranges from 0 to 240; if S equals to zero, the R, G and B are equal, fixed-point calculation standardization is carried out, and the scope of the RGB ranges from 0 to 255; if the S is not equal to zero, fixed-point calculation is carried out on p, q and hk; fixed-point initialization is carried out on t R, t G and t B; the fixed-point calculation is carried out on tc corresponding to each color; the corresponding colors are calculated according to the tc, the p and the q; standardization is carried out on the RGB, and the scope of the RGB ranges from 0 to 255. The method has the advantages that fixed-pointed processing is adopted, the method can be used in embedded 8-bit, 16-bit and 32-bit single-chip microcomputer systems and X86 systems, so the application scope is broadened greatly; some applications can be achieved on the single-chip microcomputers, so the system cost is reduced greatly; in addition, the efficiency of the floating point arithmetic mode is also improved.

The invention discloses a neural network interaction system and method based on AXI-APB, a server and a storage medium, and the system comprises the following parts: a receiving unit which is used forreceiving a plurality of first excitation signals transmitted by a plurality of pieces of main equipment; a conversion unit that is used for converting the first excitation signal into a second excitation signal according to the first conversion bridge; an analysis unit that is used for analyzing the plurality of second excitation signals according to a first preset channel and the plurality of APB interfaces so as to obtain a plurality of pieces of first identification information corresponding to the plurality of second excitation signals; an arbitration unit that is used for determining the priority of each corresponding second excitation signal according to the plurality of pieces of first identification information; an execution unit that is used for executing a plurality of corresponding second excitation signals according to the priorities; and a feedback module that is used for feeding back the execution result to the corresponding main equipment. According to the invention, through AXI-APB conversion, a plurality of AXI master devices are supported to access one APB slave device through a fixed-point computing rotation training arbitration method, and clock domain crossing and high-frequency requirements are flexibly met according to actual requirements.

Method for automatically restoring a calibrated state of a projection system, allowing simple and error-free alignment of a projection system in an original error-free state of the system. A calibrated state of a projection system is automatically restored by calculating a position and orientation of at least one camera within the projection system, using fixed points, subsequently m times n markers (9′) are projected onto the projection area, using the markers by cameras to determine a reduced number, compared with the calibration, of second measurement points (QI′) that have one X, Y and Z coordinate each, the reduced number of second measurement points (QI′) is used to perform a calculation of the differences between the second measurement points (QI′) and the associated first measurement points (QI′), a displacement vector is formed, the association between the projector coordinates and 3D coordinates is adapted with the displacement vector.

The invention discloses a method in an electronic communication device for processing a digital signal within a wireless communication network in order to transform the digital signal from a first domain representation to a second domain representation in a communication device, comprising the steps of: transforming (86, 98) the signal from the first domain to the second domain resulting in a signal of a first order of values with quantization noise in at least one area of the second domain, and performing (88, 100) a cyclic shift on the transformed signal to move the quantization noise in the second domain, resulting in a first shifted signal.

The invention discloses a hardware acceleration method for a long short-term memory neural network and a computing system for executing the method, the method comprises the following steps: firstly, quantizing parameters of the long short-term memory neural network, performing floating-point computation on floating-point data input into the long short-term memory neural network to obtain output floating-point data, and performing quantization according to the output floating-point data; and performing fixed-point calculation in the long short-term memory neural network to output fixed-point data. Then full-connection calculation is executed, specifically, weights in a full-connection layer in any long short-term memory unit in the long short-term memory neural network are rearranged, similar items are combined to execute less-order full-connection layer calculation, and then a specific nonlinear function is calculated by using a simplified instruction vector instruction set; after the steps are repeated, the matrix multiply-accumulate operation of the long-short-term memory neural network can be completed.