A fixed-point divider and operational method thereof

Abstract

This invention discloses a fix point divider, which comprises character generator, absolute generator, judger, difference generator and product generator. This invention also discloses one method of the fix point computation, which comprises the following steps: getting divider and divided absolute value to get product character for memory according to divider and divided; judging whether the divided value is larger or equal to divider absolute; if yes, then computing divided value highest valid bit and that of divider to get the different; getting the divided and divider product according to product bit, absolute value, otherwise output as zero.

Description

technical field [0001] The invention relates to digital circuit technology, in particular to a fixed-point divider and a method for realizing operation thereof. Background technique [0002] In digital signal processing, division operation circuits are often involved. However, there is no synthesizable division statement in the high-level hardware description language, such as VHDL and Verilog HDL, neither provide division-related statements. At present, one of the fixed-point division circuit devices includes a multiplication unit, the circuit structure is very complex, consumes more logic gate circuits, and has a larger delay; the other division circuit uses redundant codes composed of two-level operations. The redundant code addition unit mixed with binary forms a division array, and uses a selector to form an array conversion circuit that directly converts the quotient of redundant codes into binary form. The circuit structure is also more complicated and consumes more ...

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Problems solved by technology

However, there are no synthesizable division statements in high-level hardware description languages, such as VHDL and Verilog HDL, which do not provide division-related statements

At present, one of the fixed-point division circuit devices includes a multiplication unit, the circuit structure is very complex, consumes more logic gate circuits, and has a larger delay; the other division circuit uses redundant codes composed of two-level operations. The redundant code addition unit mixed with binary forms a division array, and uses a selector to form an array conversion circuit that directly converts the quotient of redundant codes into binary form. The circuit structure is also m

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