Method for repairing and improving power supply electromigration introduced by power switch unit

Abstract

The invention belongs to the field of integrated circuit design, and particularly relates to a method for repairing and improving power supply electromigration introduced by a power switch unit in an integrated circuit. A power supply layout above a power supply switch unit is arranged by adopting the following scheme: one or more power supply VDD wires are arranged and are arranged on M3 and M5 layers; on the M3 and M5 longitudinal metal layers, one or more gating power supply longitudinal VDDgated nets are distributed on the left side and the right side by taking the normally open power supply VDD as the center; a VSS wire is arranged near each VDD gate wire in a matching manner; and the M2 layer is provided with a transverse VDDgated net, and the transverse VDDgated net of the M2 layer and the longitudinal VDDgated net of the M3 layer are connected through a through hole V23. According to the method provided by the invention, the EM phenomenon above the power switch unit is directly improved, the EM violation of this kind is prevented from the power supply layout, the robustness of the power supply is also improved, and the whole power supply network is more robust.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular relates to a method for repairing and improving power electromigration introduced by a power switch unit in an integrated circuit. Background Art

[0002] When electrons move in a metal conductor, they collide with metal atoms. This collision causes the metal atoms to move, which is also called displacement of metal atoms. As time goes by, a large number of metal atoms on the metal interconnects move, which in turn causes the accumulation or loss of local metal atoms, which manifests itself as deformation and fracture of the metal interconnects on a macro scale. A large loss of metal atoms on the metal interconnects will cause a short circuit at the location where the atoms are lost; and the lost metal atoms will accumulate at other locations of the metal interconnects, and the interconnects at the accumulation location will become wider or deformed. At this time, if they come into contact with other metal interconnects, a short circuit will be formed. This atomic displacement caused by electron migration and the series of phenomena caused by atomic displacement are called electromigration.

[0003] As long as the chip is in use, there will be electron migration, that is, the EM phenomenon. Obviously, the deformation of the metal interconnect caused by the EM phenomenon is irreversible. Therefore, the longer the chip is used, the more the EM effect accumulates, and the more serious the metal deformation will be, that is, the greater the possibility of the metal interconnect being broken or shorted. When the EM cumulative effect is large enough, it eventually causes the metal interconnect to be broken or shorted, and the chip becomes ineffective. Therefore, the EM phenomenon is deeply related to the life and stability of the chip. That is why, theoretically speaking, the life of the chip is limited.

[0004] According to the difference in the carriers of EM phenomena, it is divided into PEM and SEM. Electromigration occurring on PG (Power & Ground) interconnects is called PEM, and electromigration occurring on signal lines is called SEM.

[0005] Low power consumption is an important performance target of digital chips. The pursuit of low power consumption of chips is endless. Power Shut Off (PSO) is one of the low power consumption technologies. This technology achieves the purpose of reducing power consumption by shutting down the power supply voltage of a certain area or a submodule that is not needed temporarily in the chip. Among them, one of the special standard units required for power shutdown technology is the power switch cell. The input of the power switch cell is a normally open voltage, and the output is a shutdown control voltage. Since the current output by the power switch cell is very large, the power electromigration (PEM) phenomenon caused by it is extremely obvious, and EM violations are easy to occur. Therefore, the power structure or strategy above the power switch cell is very important. If the power structure is unreasonable, PEM violations are likely to occur, and the number is large, making it difficult to repair in the later stage and the repair efficiency is low.

[0006] Existing solutions to EM violations mainly repair them by widening the violating net to increase the maximum current density carrying capacity, inserting buffer units to reduce the actual current density on the violating net, and then using program automation to improve repair efficiency and reduce manual repair workload, and mainly focus on solving SEM problems on signal nets.

[0007] For these common EM improvement and repair methods in the industry, although they can certainly improve and repair EM violations in theory, the number of EM violations on the low-level metal M2 caused by the large current characteristics of the power switch unit is large and difficult to repair. In the later stage of physical implementation, it is impossible to implement script repair, and it is difficult to implement manual repair one by one. Even if forced repair, the efficiency is extremely low, which will seriously affect the progress of the project. Secondly, manual repair cannot be reproduced quickly. If the physical implementation is re-performed due to some force majeure factors, all EM repair actions have to be repeated again, which is undoubtedly quite cumbersome and inefficient. In the end, they can only be repaired one by one, but generally it takes several rounds of iterations to truly repair them, which undoubtedly further increases the design cycle. Summary of the invention

[0008] In view of the problems existing in the prior art, the present invention proposes a method for repairing and improving the power electromigration introduced by the power switch unit, which mainly solves the power electromigration violation problem caused by the introduction of the power switch unit in the low-power physical implementation, and improves the power electromigration phenomenon on the low-layer metal above the power switch unit. The present invention is suitable for repairing the PEM problem above the power switch unit.

[0009] Technical Solution A method for repairing and improving power electromigration introduced by a power switch unit, wherein the power layout above the power switch unit is arranged by the following scheme: The power supply VDD wiring is one or more wires, arranged on the M3 and M5 layers; VSS wiring is arranged near each VDD_gated wiring to form a VDD_gated and VSS power supply pair to make the voltage network evenly distributed; On the vertical metal layers M3 and M5, with the normally open power supply VDD as the center, one or more gated power supply vertical VDD_gated nets are distributed on the left and right sides; The M2 layer arranges a horizontal VDD_gated net, and connects the horizontal VDD_gated net of the M2 layer and the vertical VDD_gated net of the M3 layer through a via V23; The output current is output to the left and right sides from the horizontal M2 above the center of the power switch unit; The layout of the power network is carried out according to the above scheme where there are power switch units. Where there are no power switch units, follow the conventional layout.

[0010] Furthermore, the above power layout implementation process is as follows: Step 1: First, locate all power switch units by unit type; Step 2: Then, based on the physical position of the switch unit, power layout is performed according to the power structure of the power switch unit proposed by the present invention.

[0011] Step 3: After completing the layout of all power switch units, based on the physical location of the switch units, place route blockages on top of all switch units to prohibit subsequent tools from routing here.

[0012] Step 4: Then, for the remaining areas, perform power layout according to the conventional power pairs (VDD_gated, VSS) with the same intervals.

[0013] Step 5: After all areas are powered on, remove all wiring obstacles to avoid affecting subsequent signal layout and routing behaviors.

[0014] Beneficial Effects The repair and improvement scheme for EM violations proposed by the present invention is also aimed at current density. Its advantage lies in that by changing the power structure above the power switch unit, current diversion is achieved through the change of the power structure, so as to achieve the effect of rapidly reducing the current density, thereby significantly improving the EM phenomenon on the voltage net. By changing the power structure, the EM phenomenon on the low-level metal M2 above all the power switch units is directly improved, and this type of EM violation is prevented from the power layout. After the layout and wiring are completed, there is no corresponding EM violation, which greatly reduces the ECO burden in the later stage of the design and accelerates the design cycle. In addition, this power structure also improves the robustness of the power supply, making the overall power network more robust. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the conventional PG layout of the power switch unit; Figure 2 This is an overall schematic diagram of the principle of the repair method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the layout of the power input and output pins of the power switch cell at the M1 layer according to an embodiment of the present invention; Figure 4 Schematic diagram of power layout M1, VIA12, M2 above the power switch unit according to an embodiment of the present invention; Figure 5 Schematic diagram of power layout M2, VIA23, M3 above the power switch unit according to an embodiment of the present invention; Figure 6 A schematic diagram of a power supply layout M3 above a power switch unit according to an embodiment of the present invention; Figure 7 Schematic diagram of power layout M3, VIA34, M4 above the power switch unit according to an embodiment of the present invention; Figure 8 Schematic diagram of power layout M4, VIA45, M5 above the power switch unit according to an embodiment of the present invention; Fig. 9 This is a schematic diagram of a power layout M5 above a power switch unit according to an embodiment of the present invention; Fig.10 It is a schematic diagram of the power supply layout process of the present invention. DETAILED DESCRIPTION

[0016] The technical solution provided by the present application will be further described below in conjunction with specific embodiments and accompanying drawings. The advantages and features of the present application will become more apparent with the following description.

[0017] IC physical implementation often requires multiple layers of metal. To distinguish different metal layers, M n Represents the metal nth layer, VIA n,n+1Represents the vias connecting the metal layers n and n+1. For example, M1 represents the first metal layer, M2 represents the second metal layer, VIA23 represents the vias connecting metal M2 and metal M3, and so on. The conventional power structure is connected layer by layer from the top layer to the PG pin of the bottom layer unit through vias, and starting from the third layer, the main direction of the winding of every two adjacent metal layers is crisscrossed, that is, the main direction of the winding of the odd-numbered layers is longitudinal, and the main direction of the winding of the even-numbered layers is transverse. The layout of the power structure is generally that each layer of the middle and upper metal is evenly distributed throughout the design area, and the adjacent layers form a crisscross power network. The middle and lower layers are penetrated through the power rails or power pins of the M2 and M1 layers (M2 and M1 are both transverse) through power short lines or direct vias. Therefore, the power structure is actually a network shape in three-dimensional space, so the power structure is also called the power network layout.

[0018] like Figure 1 The figure shows the conventional power network layout of the power switch cell. In low-power design, the power switch cell is used to control the on / off of the VDD power supply to the output power supply VDD_gated. The power network layout near the power switch cell has a great influence on IREM (voltage drop, electromigration).

[0019] Based on the input power supply VDD pin position of the power switch unit and the IREM consideration of the normally open power supply VDD, it is chosen to place the VDD power supply above the VDD pin position as much as possible. Figure 1 The output power supply VDD_gated is arranged (left side in the middle).

[0020] The input end of the power switch unit is connected to VDD, and the connection line between VDD_gated and the power switch unit is VDD_gatednet, including a horizontal VDD_gated net and a vertical VDD_gated net; Specifically, the VDD is one or more, arranged in the M3 and M5 layers; The lateral VDD_gated net is arranged on the M2 layer; The longitudinal VDD_gated net is one or more, and is arranged longitudinally on the M3 and M5 layers; When the power switch unit is turned on, the output current flows to the output power supply VDD_gated through the VDD_gated net of the M2 layer. Since the current output by the power switch unit is large and is output from the narrow low-level metal M2, a large amount of output current flows along the VDD_gated net of the M2 layer toward the VDD_gated high-level power supply on the left. Therefore, this small section of the VDD_gated net is prone to PEM violations. Even if the vertical VDD_gated net of M3 and M5 is arranged very wide, it is still difficult to improve this type of PEM violation.

[0021] In view of the above design scenario, this embodiment adopts the following processing method: (such as Figure 2 ) The power layout above the power switch unit is arranged in a symmetrical structure, specifically: The power supply VDD wiring is one or more wires, arranged on the M3 and M5 layers; On the vertical metal layers M3 and M5, with the normally open power supply VDD as the center, one or more gated power supply vertical VDD_gated nets are distributed on the left and right sides; VSS wiring is arranged near each VDD_gated wiring to form a VDD_gated and VSS power supply pair to make the voltage network evenly distributed; The M2 layer arranges a horizontal VDD_gated net, and connects the horizontal VDD_gated net of the M2 layer and the vertical VDD_gated net of the M3 layer through a via V23.

[0022] The output current is output to the left and right sides from the horizontal M2 at the upper center of the power switch unit. The layout of the power network is carried out according to the above scheme where there are power switch units. Where there are no power switch units, follow the conventional layout.

[0023] Furthermore, the VDD / vertical VDD_gated nets of the M3 layer and the M5 layer are parallel and aligned; in the wiring direction, through holes V34 and V45 are added at intervals, and the through holes V34 and V45 are connected by a short horizontal M4 line.

[0024] Furthermore, the local horizontal power lines above the power switch unit are widened: M2 is selected with a double line width, and M4 is selected with a short width line. Only local widening is performed above the power switch unit to reduce the use of winding resources and reduce the probability of DRC violations.

[0025] In the non-power switch unit area, the low-layer power interconnection line M2 to the middle-layer power M5 is directly connected through a through hole to reduce the use of wiring resources.

[0026] Furthermore, the wiring on the M3 layer (including VSS, VDD and VDD gated) uses a combination of multiple wider power lines, and the combined width is consistent with the width and coordinate position of the upper M5.

[0027] The M3 layer is the main wiring layer for signal wiring and also a low-level wiring layer (the minimum line width allowed by the manufacturing process is small). The use of multiple power lines is conducive to the disassembly of the power supply. When the signal line wiring resources are tight here, a few M3 thin wires PG net can be appropriately cut off. This solves the shortage of wiring resources without causing too much impact on IR and EM. This arrangement can reserve wiring resources for later ECO or resources to resolve DRC violations.

[0028] In summary, the layout of each layer of the power network near the chip power switch unit is as follows: Figure 3~Figure 9 ) like Figure 3 The figure shows the layout of the metal M1 layer, including all pins of the power switch unit: the input power VDD pin, output power VDD_gated pin and ground power VSS pin layout of the power switch unit. All output pins of the unit are located on the metal M1 layer.

[0029] like Figure 4 Layout for M2: M2 is the same as M1, the main routing layer direction is horizontal, M1 and M2 are parallel to each other, and are connected by many through holes VIA12 in the middle.

[0030] Starting from the M3 layer, the main routing directions of adjacent layers are alternating vertically and horizontally.

[0031] The M2 and M3 layers of the power network above the power switch unit are as follows Figure 5 As shown, the VDD_gated of the M2 layer uses a local width doubled (without introducing additional DRC violations) to increase the maximum current density carrying capacity; the current output by the power switch cell flows along the VDD_gated net of the M2 layer and flows toward the VDD_gated high-level power supplies on the left and right sides at the same time, and the current is divided into two to achieve the effect of reducing the current density; like Figure 6As shown in the figure, the M3 layer has a wide combination of multiple power supplies, and the combination width is consistent with the width and coordinate position of the M5 above. The M3 layer is the main wiring layer for signal wiring, and it is also a low-level wiring layer (the minimum line width allowed by the manufacturing process is small). The use of multiple power supply combinations is conducive to the disassembly of the power supply. When the signal line wiring resources are tight here, a few M3 thin wire PG nets can be reduced. This solves the shortage of wiring resources without causing too much impact on IR and EM, which is equivalent to reserving some wiring resources for later ECO or resources for solving DRC violations.

[0032] like Figure 7 As shown, M4 adopts short horizontal line layout, and the width is widened to two or three times the line width, which can not only reduce the use of M4 wiring resources, but also ensure the robustness of the power structure above the power switch unit. Through many VIA34, M3 and M4 are connected as much as possible.

[0033] like Figure 8 , Fig. 9 As shown in the figure, a wider vertical PG power supply is arranged on the M5 layer to further strengthen the power interconnection. The width is consistent with the combined width and coordinate position of the PG net of the M3 below. The M5 layer belongs to the middle wiring layer. Compared with M3, the signal line needs to be wound with relatively less resources, and a single wider power PG can be used.

[0034] Since only the M3 and M5 power supplies are strengthened above the power switch cell (wider power net combination or wider power net), and the total area of ​​the power switch cell only occupies a very small part of the total design area, the winding resources consumed by this PG strengthening will not be too much.

[0035] By changing the power PG structure to reduce the current density, strengthening the PG of M2, M3, and M5 to increase the upper limit of the allowable current density, Figure 1 The mentioned PEM improvements can produce immediate results.

[0036] The power layout implementation process is as follows: Step 1: First, locate all power switch units by unit type; Step 2: Then, based on the physical position of the switch unit, power layout is performed according to the power structure of the power switch unit proposed by the present invention.

[0037] Step 3: After completing the layout of all power switch units, based on the physical location of the switch units, place route blockages on top of all switch units to prohibit subsequent tools from routing here.

[0038] Step 4: Then, for the remaining areas, perform power layout according to the conventional power pairs (VDD_gated, VSS) with the same intervals.

[0039] Step 5: After all areas are powered on, remove all wiring obstacles to avoid affecting subsequent signal layout and routing behaviors.

[0040] When physically implementing a memory subsystem, use Figure 1 The power layout structure shown in the figure was subjected to IREM inspection and analysis, and it was found that there were a large number of power EM violations related to the gated power supply VDD_gated on the low-level metal M2 above the power switch unit, with the worst violation being as high as 200% (EM is measured by the percentage of actual current to maximum carrying current, and less than or equal to 100% meets the requirements; greater than 100% exceeds the standard and an EM violation occurs, and the larger the percentage, the more serious the violation).

[0041] After adopting the scheme described in the present invention, the EM of the relevant power supplies are reduced to less than 80%, which not only fixes all PEM violations, but also greatly improves the PEM of the entire PG network and enhances the robustness of the power supply network.

[0042] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any changes or modifications made by any person skilled in the art based on the above disclosed technical contents shall be deemed as equivalent effective embodiments and shall fall within the scope of protection of the technical solution of the present application.

[0043] Appendix: Terminology Explanation:

Claims

1. A method for repairing and improving power electromigration introduced by a power switch unit, characterized in that: The power layout above the power switch unit is arranged as follows: The power supply VDD wiring is one or more wires, arranged on the M3 and M5 layers; On the vertical metal layers M3 and M5, with the normally open power supply VDD as the center, one or more gated power supply vertical VDD_gated nets are distributed on the left and right sides; VSS wiring is arranged near each VDD_gated wiring to form a VDD_gated and VSS power supply pair to make the voltage network evenly distributed; The M2 layer arranges a horizontal VDD_gated net, and connects the horizontal VDD_gated net of the M2 layer and the vertical VDD_gated net of the M3 layer through a via V23; The output current is output to the left and right sides from the horizontal M2 above the center of the power switch unit; The layout of the power supply network is carried out according to the above scheme where there are power switch units; and according to the conventional layout where there are no power switch units.

2. A method for repairing and improving power electromigration introduced by a power switch unit as claimed in claim 1, characterized in that: The local horizontal power line above the power switch unit is widened: M2 selects 2 times the line width, and M4 selects a short width line; only the local widening is performed above the power switch unit.

3. A method for repairing and improving power electromigration introduced by a power switch unit as claimed in claim 2, characterized in that: In the non-power switch unit area, the low-layer power interconnection line M2 to the middle-layer power M5 is directly connected through a through hole to reduce the use of wiring resources.

4. A method for repairing and improving power electromigration introduced by a power switch unit as claimed in claim 1, characterized in that: The wiring on the M3 layer uses a combination of wider power lines, and the combined width is consistent with the width and coordinate position of the M5 above.

5. A method for repairing and improving power electromigration introduced by a power switch unit as claimed in claim 1, characterized in that: The VDD / vertical VDD_gated nets of the M3 and M5 layers are parallel and aligned. In the wiring direction, through holes V34 and V45 are added at intervals, and through holes V34 and V45 are connected by a short horizontal M4 line.

6. A method for repairing and improving power electromigration introduced by a power switch unit as claimed in any one of claims 1 to 5, characterized in that: The power layout implementation process is as follows: Step 1: First, locate all power switch units by unit type; Step 2, then based on the physical position of the switch unit, power layout is performed according to the power switch unit power structure proposed by the present invention; Step 3: After all power switch units are laid out, based on the physical location of the switch units, place wiring obstacles above all switch units to prevent subsequent tools from wiring there. Step 4, then for the remaining areas, perform power layout at the same intervals according to the conventional power pairs; Step 5: After all areas are powered on, remove all wiring obstacles to avoid affecting subsequent signal layout and routing behaviors.

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