Write compensation circuit and memory

Abstract

The present disclosure provides a write compensation circuit and a memory, wherein the write compensation circuit comprises a decoding circuit and a compensation circuit; the decoding circuit determines a compensation amount corresponding to a current working mode according to a mode selection signal and a mode register instruction, and outputs a parity indication signal and a plurality of enable signals; the compensation circuit compensates an internal write command obtained based on an external write command according to the parity indication signal and the plurality of enable signals in a corresponding compensation amount when an automatic precharge enable signal is valid, so that the external write command completes a preset delay amount delay in different modes. The present scheme can realize flexible write compensation.

Description

Technical Field

[0001] This disclosure relates to memory technology, and more particularly to a write compensation circuit and a memory. Background Technology

[0002] With the development of memory technology, memory has been widely used in many fields. For example, Dynamic Random Access Memory (DRAM) is widely used.

[0003] In practical applications, the memory performs sampling and decoding based on the input signals from the command / address pins to implement relevant command operations. In this design, when the chip is in a write (WriteAutoPrecharge) command operation, delay compensation is needed for the internal write command. The required compensation time varies depending on the operating mode, thus necessitating a flexible write compensation scheme. Summary of the Invention

[0004] Embodiments of this disclosure provide a write compensation circuit and a memory.

[0005] According to some embodiments, a first aspect of this disclosure provides a write compensation circuit, including: a decoding circuit and a compensation circuit; the decoding circuit receives a mode selection signal and a mode register instruction, and is configured to determine the compensation amount corresponding to the current operating mode according to the mode selection signal and the mode register instruction, and output an odd / even indicator signal and multiple enable signals, wherein different enable signals correspond to different offsets; wherein, only the enable signal corresponding to the offset corresponding to the compensation amount corresponding to the current operating mode is valid, and the odd / even indicator signal indicates that the compensation amount corresponding to the current operating mode is an odd multiple or an even multiple of the external clock cycle; the compensation circuit is coupled to the decoding circuit, and is configured to compensate the internal write command obtained based on the external write command according to the corresponding compensation amount according to the odd / even indicator signal and multiple enable signals when the automatic precharge enable signal is valid, so that the external write command completes a preset delay amount in different modes, and the compensation amount is obtained by superimposing an odd offset or an even offset on the offset corresponding to the compensation amount.

[0006] According to some embodiments, a second aspect of this disclosure provides a memory including: a memory array, and write compensation circuitry as in any of the preceding examples.

[0007] The write compensation circuit and memory provided in this embodiment include a decoding circuit and a compensation circuit. The decoding circuit determines the compensation amount based on the mode selection signal and the mode register instruction, and outputs an odd / even indicator signal indicating that the compensation amount is an odd or even multiple of the external clock cycle, as well as an enable signal corresponding to each offset. Only the enable signal corresponding to the offset of the current operating mode is valid. When the automatic precharge enable signal is valid, the compensation circuit performs delay compensation on the internal write command according to the compensation amount based on the odd / even indicator signal and the enable signal. Specifically, the compensation applies a delay of the offset corresponding to the current operating mode to the internal write command, and then further adds a delay of the odd or even offset. This solution compensates for the delay of the internal write command by applying an odd or even offset to the corresponding offset for different operating modes, thereby meeting the signal timing requirements when the chip is performing a write command operation including automatic precharge, and realizing a flexible write compensation scheme. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of the embodiments of this disclosure.

[0009] Figure 1 An example diagram of a memory architecture;

[0010] Figure 2 Here is a structural example diagram of a sample storage unit;

[0011] Figure 3 A timing diagram for a write command operation that includes automatic precharge;

[0012] Figure 4 This is a schematic diagram of an example write compensation circuit;

[0013] Figure 5 Here is a structural example diagram of a write compensation circuit;

[0014] Figure 6 Here is a structural example diagram of a processing circuit;

[0015] Figure 7 Here is a structural example diagram of a processing circuit;

[0016] Figure 8 Here is a structural example diagram of an output circuit;

[0017] Figure 9 Here is a schematic diagram of the structure of an example clock generation circuit;

[0018] Figure 10Here is a structural example diagram of an output circuit;

[0019] Figure 11 This is a schematic diagram of an example decoding circuit.

[0020] Figure 12 This is a schematic diagram of an example decoding circuit.

[0021] Figure 13 Here is a structural example diagram of a timing matching circuit;

[0022] Figure 14 An example diagram of the structure of a memory;

[0023] Figure 15 This is a timing diagram for an example.

[0024] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0026] The terms "comprising" and "having" in this disclosure are used to indicate an open-ended meaning of inclusion, and refer to the existence of additional elements / components / etc. besides those listed; the logical symbol " / " is used to indicate the logical meaning of "or"; the terms "first" and "second," etc., are used only as markings or distinctions, and are not intended to limit the order or quantity of the objects. Furthermore, the different elements and areas in the accompanying drawings are only schematic and are therefore not limited to the dimensions or distances shown in the drawings. The term "connection" in this disclosure can refer to a direct connection or an indirect connection.

[0027] The technical solution will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0028] Figure 1 An example memory architecture diagram, such as... Figure 1As shown, taking DRAM as an example, it includes a data input / output buffer, row decoder, column decoder, sense amplifier, and memory array. The data input / output buffer belongs to the peripheral circuitry, while the sense amplifier, row decoder, column decoder, and memory array belong to the array circuitry. The memory array mainly consists of word lines, bit lines, and memory cells. Word lines in the memory array extend along the row direction, and bit lines extend along the column direction. The intersection of word lines and bit lines forms the memory cell of the memory array.

[0029] Each storage unit is used to store one bit of data. For example... Figure 2 As shown, Figure 2 This is a structural example of a memory cell, which mainly consists of a transistor switch M and a capacitor C. The capacitor stores data, and the transistor switch is used to turn the cell off or on depending on its selected state.

[0030] Access to a memory cell can be achieved by controlling word lines and bit lines. Taking a read scenario as an example: when data needs to be read from a memory cell, the word line of the row containing that memory cell can be selected using a row decoder. Correspondingly, transistor M in the diagram turns on, and the state of capacitor C can be detected by sensing and amplifying the bit line signal. For example, if the bit data stored in the memory cell is 1, then after transistor M turns on, 1 will be read from the bit line of the memory cell, and vice versa. Furthermore, taking a write scenario as an example: when writing bit data to a memory cell, such as writing 1, the word line of the row containing that memory cell can be selected using a row decoder. Correspondingly, transistor M in the diagram turns on, and by setting the logic level of the bit line to 1, capacitor C is charged, thus writing 1 to the memory cell. Conversely, to write 0, the logic level of the bit line is set to 0, causing capacitor C to discharge, thus writing 0 to the memory cell.

[0031] In practical applications, the memory performs sampling and decoding based on the input signal from the command / address (CA) pin to implement relevant command operations. Taking a write (WriteAutoPrecharge) command operation with automatic precharge as an example, after completing the write leveling internal cycle alignment through the memory's mode register (e.g., data OP<3:0> in MR3), timing delay compensation is also required for the internal write command obtained based on the external write command. This ensures that the chip performs automatic precharge only after a certain time requirement has elapsed since the external write command. This time requirement includes the column address strobe write latency (CWL), the data transfer time (i.e., half the burst length (BL), and the write recovery time (tWR). To better understand the above timing, Figure 3 A timing diagram for a write command operation that includes automatic precharge, such as... Figure 3 As shown, taking the design of Double Data Rate Synchronous Dynamic Random Access Memory (DDR) as an example, after the activation command (ACT in the figure), after the delay time from row strobe to column strobe (RowtoColumnDelay, tRCD), in response to the external write command (auto-precharge write command, WR in the figure), after the delay CWL, the write data (DATA in the figure) is stored in the memory array for BL / 2 clock cycles. After that, after tWR, in response to the precharge command (PRE in the figure) to perform precharge, after the row precharge time (RowPre-chargeTime, tRP), the execution of a write command operation including auto-precharge is completed.

[0032] Based on the aforementioned technical background, and considering the need to ensure timing consistency between the clock and the Data Strobe Signal (DQS signal) of each memory, write leveling is performed. Specifically, after the external write leveling training operation is completed, the data select pulse and clock signal are aligned at the pins. Then, during internal write leveling, a negative offset is applied to the data select pulse. For example, this can be achieved by setting the memory's mode register MR3OP<3:0> to align the reference point of the internal write leveling pulse, increasing the negative offset to reduce the delay from the write command to the internal write pulse, until the data select pulse and the internal write pulse are aligned. After completing the write leveling process, the internal write command needs to compensate for the negative offset during write leveling to meet the delay required by the aforementioned external write command, i.e., CWL+BL / 2. After a tWR time delay, the chip automatically performs a pre-charge operation. Therefore, to ensure that external write commands meet the aforementioned latency, compensation is needed for the internal write commands of the memory. The internal write command is the signal obtained after the external write command has undergone a corresponding internal delay. This internal delay varies under different modes and different MR3 settings. Therefore, the duration of compensation required differs in different operating modes, and the amount of compensation may be an odd or even multiple of the external clock cycle. Thus, a flexible write compensation scheme is needed. Some aspects of the embodiments of this disclosure relate to the above considerations. The following examples illustrate the scheme.

[0033] In some embodiments, Figure 4 Here is a schematic diagram of an example write compensation circuit, as shown below. Figure 4 As shown, the write compensation circuit includes: a decoding circuit 11 and a compensation circuit 12;

[0034] Decoding circuit 11 receives mode selection signal D4_P<…> and mode register instruction MR3<…>. Based on the mode selection signal D4_P<…> and mode register instruction MR3<…>, it determines the compensation amount corresponding to the current operating mode and outputs a parity indicator signal SW and multiple enable signals P<…>. Different enable signals P<…> correspond to different offsets. Among the enable signals P<…>, only the enable signal corresponding to the offset of the compensation amount corresponding to the current operating mode is valid. The parity indicator signal SW indicates that the compensation amount corresponding to the current operating mode is an odd or even multiple of the external clock cycle.

[0035] The compensation circuit 12, coupled to the decoding circuit 11, is used to compensate the internal write command INT_WRCMD obtained based on the external write command according to the parity indicator signal SW and multiple enable signals P<…> when the automatic precharge enable signal AP_EN is valid, so that the external write command completes the preset delay in different modes. The compensation amount is obtained by superimposing an odd offset or an even offset on the offset corresponding to the compensation amount.

[0036] In practical applications, the circuit provided in this embodiment can be used in various memories. For example, it can be applied to, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR DRAM). The automatic precharge enable signal AP_EN is obtained based on the fact that "the second cycle of the CA10 signal under the Write command is low (i.e., AP = L)," meaning that the CA10 pin receives the signal during the second cycle of the Write command. The mode selection signal is used to determine the current operating mode. Furthermore, in conjunction with the foregoing, the internal delay duration differs under different operating modes. For example, the operating mode of the memory can be determined based on the memory's transmission frequency. For instance, the example operating modes may include a first mode, a second mode, and a third mode; the first mode corresponds to a transmission rate no greater than a preset value and a data strobe signal preamble of 4 external clock cycles; the second mode corresponds to a transmission rate no greater than a preset value and a data strobe signal preamble of 2 or 3 external clock cycles; and the third mode corresponds to a transmission frequency greater than a preset value. Referring to the example in Table 1, which shows the time delay under different operating modes for an example, including D4TYPE_PRE4 mode, D4TYPE_PRE2 / 3 mode, and D5TYPE mode, the time delay in Table 1 represents the time difference between external write commands and internal write commands. Similarly, the object of compensation in this scheme is the internal write command mentioned in this scheme. Specifically, the memory transfer rate in D4TYPE_PRE4 operating mode is no greater than 3200Mbps (Mbps is megabits per second) and the preamble of the data strobe signal is 4 external clock cycles; the memory transfer rate in D4TYPE_PRE2 / 3 operating mode is also no greater than 3200Mbps and the preamble of the data strobe signal is 2 or 3 external clock cycles; the memory transfer rate in D5TYPE operating mode is greater than 3200Mbps. In practical applications, the current operating mode can be determined based on the memory transfer rate and preamble.

[0037] Table 1

[0038]

[0039] In D4TYPE_PRE4 and D4TYPE_PRE2 / 3 modes, no internal write leveling is required, while D5TYPE mode does involve internal write leveling. It can be understood that the time difference between the external write command and the internal write command differs in different operating modes. For example, in D4TYPE_PRE4 mode it is CWL+2, in D4TYPE_PRE2 / 3 it is CWL+3, and in D5TYPE it is CWL+4-MR3. It should be noted that the numbers in the table above represent the duration equivalent to that number of times the external clock cycle. For example, CWL+2 indicates that the time delay is the sum of CWL and twice the external clock cycle. MR3 represents the absolute value of the offset represented by the parameter value in the mode register MR3, which is determined through internal write leveling. Based on the time delay amount in the example above, it means that the memory has already delayed the external write command by the aforementioned time delay amount to obtain the internal write command. Therefore, this solution needs to further compensate for the delay of the internal write command to ensure that the time difference between the compensated internal write command and the external write command is CWL+BL / 2. Specifically, this solution can be applied to compensate for the internal write command in different operating modes. The amount to be compensated for the internal write command can be determined based on the time difference between the external write command and the decoded internal write command in different operating modes. Taking the D4TYPE_PRE4 mode as an example, the time delay amount is CWL+2, and the total delay time is CWL+BL / 2. Therefore, the amount to be compensated for the internal write command is CWL+BL / 2-(CWL+2). Taking BL as 16 as an example, it can be determined that in D4TYPE_PRE4 mode, the amount to be compensated for the internal write command is 6 external clock cycles. For another example, in D4TYPE_PRE2 / 3 mode, the amount to be compensated for the internal write command is 5 external clock cycles. In D5TYPE mode, the amount to be compensated for the internal write command is the sum of 4 external clock cycles and the offset represented by the parameter value in MR3. The offset represented by the parameter value in MR3 can also be represented by external clock cycles, for example, an odd or even number of external clock cycles. Combining the above, in one example, the preset delay is the sum of the number of external clock cycles corresponding to the column address strobe pulse write delay and half the burst length; the compensation amount corresponding to the first mode is six external clock cycles; the compensation amount corresponding to the second mode is five external clock cycles; and the compensation amount corresponding to the third mode is the sum of four external clock cycles and the absolute value of the offset represented by the mode register instruction.

[0040] In practical applications, the above-mentioned operating modes can be determined by the mode selection signal D4_P<…>. As an example, Table 2 provides a functional description of the different mode selection signals. As shown in Table 2, D4_P… <0> The value is used to select either D4TYPE mode or D5TYPE mode. D4TYPE mode includes D4TYPE_PRE4 mode and D4TYPE_PRE2 / 3 mode. As an example, D4_P... <0> A value of 0 indicates the use of D5TYPE mode, D4_P <0> A value of 1 indicates that the D4TYPE mode is used. Furthermore, D4_P <0> When it is 1, D4_P <1> A value of 1 indicates the use of D4TYPE_PRE2 / 3 mode, D4_P <1> A value of 0 indicates that the D4TYPE_PRE4 mode is in use. This enables the determination of the current operating mode based on the mode selection signal.

[0041] Table 2

[0042] Mode selection signal Function Description D4_P <0> Select D4 / D5TYPE; when D4_P0=1, select D4_TYPE. D4_P <1> Select Preamble mode; when D4_P1=1, select Preamble2 / 3.

[0043] In this scheme, a two-stage compensation method is used to compensate the internal write command according to the compensation amount required by the current operating mode. Specifically, to compensate the internal write command, the decoding circuit 11 determines the current operating mode based on the current mode selection signal D4_P<…> and the mode register instruction MR3<…> (containing the parameter values ​​set in the mode register), thereby determining the amount of delay that the internal write command (INT_WRCMD) has been delayed relative to the external write command. Combined with the total delay required by the external write command, it determines how much further delay is needed for the internal write command to reach the total delay amount, which is the amount of compensation required for the internal write command in this scheme, and also the compensation amount corresponding to the current operating mode. Accordingly, the decoding circuit 11 outputs a parity indicator signal SW and multiple enable signals P<…>. The compensation amount may be an odd or even multiple of the external clock cycle. For example, referring to the previous example, the compensation amount corresponding to the D4TYPE_PRE4 mode is 6 external clock cycles, which is an even multiple; the compensation amount corresponding to the D4TYPE_PRE2 / 3 mode is 5 external clock cycles, which is an odd multiple.

[0044] Combining the two-stage compensation scheme, the multiple enable signals P<…> output by the decoding circuit 11 are used to indicate the base delay applied by the compensation circuit 12 to the internal write command, i.e., the offset corresponding to the compensation amount of the current operating mode. This base delay is an even multiple of the external clock cycle, such as 2, 4, 6, … 10, 12 external clock cycles. Different enable signals correspond to different offsets; for example, enable signals can have base delays of 2, 4, 6, … 10, 12 external clock cycles, respectively, represented by P<…>. <0> P <2> P <4> ...P <8> P <10> After applying the base delay, the compensation circuit 12 further superimposes either an odd or even offset. This depends on whether the compensation amount corresponding to the current operating mode is an odd or even multiple of the external clock cycle. For example, if the compensation amount is an even number of external clock cycles, an even offset is superimposed; if the compensation amount is an odd number of external clock cycles, an odd offset is superimposed. For instance, for the D4TYPE_PRE4 mode, the compensation amount corresponding to this mode is 6 external clock cycles. The offset (i.e., the base delay) corresponding to the compensation amount for the D4TYPE_PRE4 mode can be set to 4 external clock cycles. Accordingly, the enable signal output by the decoding circuit 11 only contains P. <2> In the active state, the compensation circuit 12 applies a base delay of 4 external clock cycles to the internal write command INT_WRCMD obtained based on the external write command, and then further superimposes an even offset (2 external clock cycles) in a two-stage compensation method to achieve the compensation amount corresponding to D4TYPE_PRE4, i.e., a delay of 6 external clock cycles. For D4TYPE_PRE2 / 3 mode, the enable signal output by the decoding circuit 11 also only contains P. <2> The system is active, applying a base delay of 4 external clock cycles. This means the offset corresponding to the compensation amount in the D4TYPE_PRE2 / 3 mode is also 4 external clock cycles. Then, a two-stage compensation method with an odd offset (1 external clock cycle) is added to achieve the compensation amount corresponding to the D4TYPE_PRE2 / 3 mode, i.e., a delay of 5 external clock cycles. This two-stage compensation scheme allows for flexible control of the delay compensation amount according to the needs of the operating mode. Even if the compensation amount differs for different operating modes, potentially being an odd or even multiple of the external clock cycles, this scheme can still achieve accurate and flexible delay compensation.

[0045] In practical applications, after the external clock CK is received by the memory, it is divided into an internal odd clock PCLK_O and an internal even clock PCLK_E. The clock periods of the internal odd clock PCLK_O and the internal even clock PCLK_E are both twice the external clock period tCK, and the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O is one external clock period tCK.

[0046] As an example, Figure 5 Here is an example diagram of the structure of a write compensation circuit, as shown below. Figure 5 As shown, based on any example, the compensation circuit 12 may specifically include: two processing circuits, referred to as the first processing circuit 21 and the second processing circuit 22, and an output circuit 23;

[0047] The first processing circuit 21 and the second processing circuit 22 are respectively used to offset the corresponding write command RMW_E / O according to the offset corresponding to the valid enable signal when the automatic precharge enable signal AP_EN is valid, so as to obtain the corresponding offset signal CMD2_E / O. The write command RMW_E / O corresponding to the first processing circuit 21 and the second processing circuit 22 is obtained by sampling the internal write command INT_WRCMD based on the internal even clock PCLK_E and the internal odd clock PCLK_O. The offset corresponding to the enable signal P<...> is an even number of external clock cycles, the clock cycles of the internal even clock PCLK_E and the internal odd clock PCLK_O are twice the external clock cycle tCK, and the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O is one external clock cycle tCK.

[0048] The output circuit 23 is connected to the decoding circuit 11, the first processing circuit 21, and the second processing circuit 22. It is used to offset the offset signals CMD2_E / O corresponding to the first processing circuit 21 and the second processing circuit 22 according to the odd / even indicator signal SW, and perform OR logic operation on the offset signals to obtain the compensated internal write command.

[0049] The first processing circuit 21 and the second processing circuit 22 function similarly, namely, to perform a basic delay offset on the input signal. Subsequently, the output circuit further applies an odd or even offset based on this basic offset. The basic offset applied by the first processing circuit 21 and the second processing circuit 22 to their respective delay objects is the same, corresponding to the offset of the currently valid enable signal. However, the difference lies in the delay object: specifically, it is the signal sampled based on the internal even clock PCLK_E and the internal odd clock PCLK_O for the internal write command INT_WRCMD. It can be understood that since the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O is one external clock cycle, the phase difference between the write commands corresponding to the first processing circuit 21 and the second processing circuit 22 is also one external clock cycle. Furthermore, the write commands corresponding to the first processing circuit 21 and the second processing circuit 22 are obtained by applying the same delay to the first processing circuit 21 and the second processing circuit 22, respectively, resulting in offset signals corresponding to the first processing circuit 21 and the second processing circuit 22. That is, there is also a phase difference of one external clock cycle between CMD2_E and CMD2_O. For differentiation, Figure 5 The example assumes that the write command corresponding to the first processing circuit is RMW_E, the write command corresponding to the second processing circuit is RMW_O, and the offset signal corresponding to the first processing circuit 21 is CMD2_E, and the offset signal corresponding to the second processing circuit 22 is CMD2_O.

[0050] Specifically, when the current parity indicator signal SW indicates that the compensation amount corresponding to the current operating mode is an even multiple of the external clock cycle, the output circuit 23 delays the offset signals CMD2_E / O corresponding to the first and second processing circuits by an even offset (e.g., two external clock cycles), and performs an OR operation on the two delayed signals to obtain a write signal that is delayed by an even multiple of the external clock cycle compared to the internal write signal. Conversely, when the current parity indicator signal SW indicates that the compensation amount corresponding to the current operating mode is an odd multiple of the external clock cycle, the output circuit 23 delays the offset signals CMD2_E / O corresponding to the first and second processing circuits by an odd offset (e.g., one external clock cycle), and performs an OR operation on the two delayed signals to obtain a write signal that is delayed by an odd multiple of the external clock cycle compared to the internal write signal.

[0051] In this example, the internal write command signal is sampled using the internal odd clock and internal even clock. The first and second processing circuits then apply a fundamental delay to the two sampled signals to obtain corresponding offset signals for each circuit. The subsequent output circuit, based on these two offset signals, applies either an odd or even offset and performs an OR operation to obtain the compensated write signal. The advantage of this approach is that the subsequent output circuit can easily utilize the sampling method using the internal even and odd clocks, and then superimpose the delay offset using an OR operation. This eliminates the need to generate a dedicated clock signal for delay; the memory's own internal clock signal is sufficient to compensate for the delay of the internal write command.

[0052] In one example Figure 6 Here is an example diagram of the structure of a processing circuit, such as... Figure 6 As shown, each processing circuit 21 / 22 may include: multiple cascaded offset sub-circuits 31, each corresponding to a multiple enable signals P<…>;

[0053] The first-level offset sub-circuit 31 receives the write command RMW_E / O corresponding to the processing circuit and the enable signal P<…> corresponding to the offset sub-circuit; each offset sub-circuit 31 other than the first level receives the write command RMW_E / O corresponding to the processing circuit and the enable signal P<…> corresponding to the offset sub-circuit, and is connected to the output terminal of the previous level offset sub-circuit.

[0054] Each offset sub-circuit 31 is used to delay the received write command RMW_E / O before outputting it when the enable signal P<...> corresponding to the offset sub-circuit is valid; and when its own enable signal P<...> is invalid, it delays the signal output by the previous offset sub-circuit before outputting it; the last offset sub-circuit 31 is used to output the offset signal CMD2_E / O corresponding to the processing circuit it is in; wherein, the total delay amount of the offset sub-circuit corresponding to the valid enable signal and all subsequent offset sub-circuits is the offset amount corresponding to the valid enable signal.

[0055] It should be noted that, Figure 6 Only the specific structure of a single processing circuit is shown. The circuit illustrated can be considered as either the first processing circuit 21 or the second processing circuit 22. The input signals in the diagram are represented by RMW_E / O to indicate the write command of the first / second processing circuit, and CMD2_E / O to indicate the corresponding offset signal output by the first / second processing circuit. In practical applications, the structures of the two processing circuits can be identical; therefore, only a single circuit diagram is shown here.

[0056] Reference Figure 6As shown, each offset sub-circuit 31 is used to delay the signal input to that offset sub-circuit for a certain duration. Optionally, this duration can be preset. The delay duration of each offset sub-circuit can be the same or different. In one example, for ease of circuit design and layout, the delay duration of each offset sub-circuit is the same. For example, the delay duration of each offset sub-circuit can be two external clock signals. As an example, Figure 6 The diagram shows a six-stage offset sub-circuit, with the enable signal for the first-stage offset sub-circuit shown as P. <10> The enable signal corresponding to the second-stage offset sub-circuit is shown as P. <8> And so on, the enable signal corresponding to the last stage offset sub-circuit is shown as P. <0> Specifically, in the processing circuit, the enable signal P<…> is used to control which offset sub-circuit the write command RMW_E / O corresponding to the processing circuit is input from, that is, to determine how many offset sub-circuits the write command will pass through for delay. This affects the base offset applied to the write command, that is, the offset corresponding to the compensation amount of the current working cycle.

[0057] Referring to the foregoing example, for the D4TYPE_PRE4 mode, the internal write commands are sampled based on the internal even clock and internal odd clock to obtain the write commands corresponding to the first processing circuit 21 and the second processing circuit 22. The first processing circuit 21 and the second processing circuit 22 respectively apply a base delay of 4 external clock cycles to the corresponding write commands, outputting CMD2_E / O. Then, the output circuit 23 applies an even offset (e.g., 2 external clock cycles) to CMD2_E / O, thereby achieving the compensation amount (6 external clock cycles) corresponding to the D4TYPE_PRE4 mode. Figure 6 In the circuit shown, among the enable signals P<...> output by the decoding circuit 11, only P... <2> When the current enable signal is active (e.g., high level), all other enable signals are inactive (e.g., low level). Therefore, the first four offset sub-circuits and the sixth stage will not receive RMW_E / O, but will instead receive the output signal of the previous offset sub-circuit. For the first four offset sub-circuits, since their previous offset sub-circuit did not output a valid output signal, they also cannot output a valid output signal until the fifth offset sub-circuit receives RMW_E / O and outputs RMW_E / O delayed by 2 external clock cycles to the next offset sub-circuit. Correspondingly, the sixth offset sub-circuit receives the output signal of the fifth offset sub-circuit, further adds a delay of 2 external clock cycles, and outputs the final CMD2_E / O. At this point, CMD2_E / O has a delay of 4 external clock cycles compared to RMW_E / O, realizing the basic delay for internal write commands in D4TYPE_PRE4 mode.

[0058] The circuit structure of the offset sub-circuit is not limited. As an example, Figure 7Here is an example diagram of the structure of a processing circuit, such as... Figure 7 As shown, the first-stage offset sub-circuit 31 includes: a first NAND gate 311, a seventh NOT gate 312, and a first flip-flop 313; the first input terminal of the first NAND gate 311 receives the enable signal of the first-stage offset sub-circuit (P in the example in the figure). <10> The second input of the first NAND gate 311 receives the write command RMW_E / O corresponding to the processing circuit 21 / 22; the input of the seventh NOT gate 312 is connected to the output of the first NAND gate 311, the output of the seventh NOT gate 312 is connected to the input of the first flip-flop 313, and the clock terminal of the first flip-flop 313 receives the first clock signal PCLK_E1 / O1 corresponding to the processing circuit 21 / 22.

[0059] Each offset sub-circuit 31, excluding the first stage, includes: a second NAND gate 314, a third NAND gate 315, a fourth NAND gate 316, and a second flip-flop 317. The first input of the second NAND gate 314 receives the enable signal of the offset sub-circuit, and the second input of the second NAND gate 314 receives the write command corresponding to the processing circuit 21 / 22. The first input of the third NAND gate 315 receives the inverted signal P<…>B of the enable signal of the offset sub-circuit, and the second input of the third NAND gate 315 is connected to the output of the previous stage offset sub-circuit. The first input of the fourth NAND gate 316 is connected to the output of the second NAND gate 314, the second input of the fourth NAND gate 316 is connected to the output of the third NAND gate 315, and the output of the fourth NAND gate 316 is connected to the input of the second flip-flop 317. The clock terminal of the second flip-flop 317 receives the first clock signal PCLK_E1 / O1 corresponding to the processing circuit 21 / 22.

[0060] Wherein, the period of the first clock signal PCLK_E1 / O1 is the sub-offset, and the phase difference between the first clock signal PCLK_E1 corresponding to the first processing circuit 21 and the first clock signal PCLK_O1 corresponding to the second processing circuit 22 is the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O.

[0061] Specifically, the sub-offset refers to the delay offset applied by each offset sub-circuit. For example, taking the write command corresponding to the first processing circuit 21 as RMW_E and the first clock signal corresponding to the first processing circuit 21 as PCLK_E1, and the write command corresponding to the second processing circuit 22 as RMW_O and the first clock signal corresponding to the second processing circuit 22 as PCLK_O1, the clock periods of PCLK_E1 and PCLK_O1 are both sub-offsets. For example, the sub-offset can be two external clock cycles, and correspondingly, the clock periods of PCLK_E1 and PCLK_O1 are two external clock cycles. Simultaneously, to ensure that the two processing circuits apply the same basic delay to their respective write commands, the phase difference between PCLK_E1 and PCLK_O1 is consistent with the phase difference between PCLK_E and PCLK_O, which can be, for example, one external clock cycle. It can be understood that the flip-flop in each offset circuit responds to the effective edge (e.g., rising edge) of the first clock signal PCLK_E1 / O1 received at the clock terminal and outputs the currently received input signal. The input signal of the flip-flop may be the write command RMW_E / O corresponding to the processing circuit, or it may be the output signal of the previous stage flip-flop, depending on whether the enable signal P<…> received by the first NAND gate 311 / second NAND gate 314 of this offset circuit is in a valid state. For example, an enable signal being valid can mean that the enable signal is in a high-level state, while an enable signal being in a low-level state indicates that the enable signal is invalid. As an example, when the enable signal is in a high-level state, the write command RMW_E / O can pass normally through the first NAND gate 311 / second NAND gate 314. At this time, the inverted signal of the enable signal is in a low-level state, the output signal of the previous stage flip-flop is blocked, the third NAND gate 315 maintains a high-level output signal, so the signal received at the first input terminal of the fourth NAND gate 316, i.e., RMW_E / O, is transmitted to the input terminal of this stage flip-flop. Conversely, when the enable signal is low, the write command RMW_E / O is blocked by the first NAND gate 311 / the second NAND gate 314. The first NAND gate 311 / the second NAND gate 314 maintains a high-level output signal. At this time, the inverted signal of the enable signal is high, and the output signal of the previous stage flip-flop can pass normally through the third NAND gate 315. Therefore, the signal received at the second input of the fourth NAND gate 316, that is, the output signal of the previous stage flip-flop, is transmitted to the input of this stage flip-flop.

[0062] The processing circuit described above can perform basic delay compensation on the write command corresponding to the currently valid enable signal based on the offset, ensuring that the basic delay compensation amounts of the two processing circuits are consistent. This results in two offset signals with a phase difference consistent with the phase difference of the internal odd and even clock signals. The subsequent output circuit can then use these two offset signals to achieve a superimposed odd or even offset delay, thereby realizing write compensation. Furthermore, this example is implemented using conventional components, which simplifies the manufacturing process and reduces costs.

[0063] Subsequently, based on the offset signals output by the first processing circuit 21 and the second processing circuit 22, the output circuit 23 further applies an odd offset or even offset delay to achieve write compensation in the current operating mode. In one example, Figure 8 Here is an example diagram of the structure of an output circuit, such as... Figure 8 As shown, the output circuit 23 includes: a first output sub-circuit 41, a second output sub-circuit 42, and an integrated circuit 43;

[0064] The first output sub-circuit 41 is connected to the first processing circuit 21 and the second processing circuit 22, and is used to sample and output the offset signal CMD2_O corresponding to the second processing circuit based on the second clock signal PCLK_E2 corresponding to the first processing circuit in response to the parity indicator signal SW in the first state; and to sample and output the offset signal CMD2_E corresponding to the first processing circuit based on the second clock signal PCLK_E2 corresponding to the first processing circuit in response to the parity indicator signal SW in the second state.

[0065] The second output sub-circuit 42 is connected to the first processing circuit 21 and the second processing circuit 22, and is used to sample and output the offset signal CMD2_E corresponding to the first processing circuit based on the second clock signal PCLK_O2 corresponding to the second processing circuit in response to the parity indicator signal SW in the first state; and to sample and output the offset signal CMD2_O corresponding to the second processing circuit based on the second clock signal PCLK_O2 corresponding to the second processing circuit in response to the parity indicator signal in the second state.

[0066] The integrated circuit 43 is connected to the first output sub-circuit 41 and the second output sub-circuit 42, and is used to perform OR logic operation on the output signals of the first output sub-circuit 41 and the second output sub-circuit 42 to output a compensated internal write command; wherein, the second clock signal PCLK_E2 corresponding to the first processing circuit and the second clock signal PCLK_O2 corresponding to the second processing circuit have the same period, and the phase difference between them is the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O.

[0067] Specifically, the above example uses RMW_E as the write command for the first processing circuit and RMW_O as the write command for the second processing circuit. The second clock signals for both processing circuits have the same clock period, and their phase difference is consistent with the phase difference between the first clock signals for the two processing circuits, i.e., the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O. For example, the phase difference between the second clock signals for the two processing circuits can be one external clock cycle. Specifically, a certain phase delay can be set between the first and second clock signals for each processing circuit. This is to ensure timing matching so that the output circuit can accurately capture the valid command window in the offset signal output by the processing circuit based on its respective first clock signal, and obtain the compensated internal write command through an OR logic operation.

[0068] In one example, the write compensation circuit also includes a clock generation circuit for generating the individual clock signals, as an example. Figure 9 Here is a schematic diagram of the structure of an example clock generation circuit, such as... Figure 9 As shown, the clock generation circuit may include a first generation circuit 51 and a second generation circuit 52. As an example, the first generation circuit 51 is used to output a first clock signal and a second clock signal corresponding to the first processing circuit, and the second generation circuit 52 is used to output a first clock signal and a second clock signal corresponding to the second processing circuit. The specific structures of the first generation circuit 51 and the second generation circuit 52 are not limited; their specific circuits may be the same or different. In one example, the first generation circuit 51 and the second generation circuit 52 adopt similar circuit structures to facilitate circuit design and fabrication.

[0069] like Figure 9As shown, the first generation circuit package 51 includes: a first AND operation unit 511, a second AND operation unit 512, a first NOR operation unit 513, a first delay unit 514, and a second delay unit 515. The first input terminal of the first AND operation unit 511 receives a first cycle mode instruction EN_1N, and the second input terminal receives an internal even clock PCLK_E; the first input terminal of the second AND operation unit 512 receives a second cycle mode instruction EN_2N, and the second input terminal receives an internal odd clock PCLK_O; the first NOR operation unit 514... The first input terminal is connected to the output terminal of the first AND operation unit 511, and the second input terminal is connected to the output terminal of the second AND operation unit 512; the input terminal of the first delay unit 514 is connected to the output terminal of the first NOR operation unit 513, and the output terminal of the first delay unit 514 is used to output the first clock signal PCLK_E1 corresponding to the first processing circuit 21; the input terminal of the second delay unit 515 is connected to the output terminal of the first delay unit 514, and the output terminal of the second delay unit 515 is used to output the second clock signal PCLK_O corresponding to the first processing circuit 21. 1; The second generation circuit package 52 includes: a third AND operation unit 521, a fourth AND operation unit 522, a second NOR operation unit 523, a third delay unit 524, and a fourth delay unit 525. The first input terminal of the third AND operation unit 521 receives the first cycle mode instruction EN_1N, and the second input terminal receives the internal odd clock PCLK_0; the first input terminal of the fourth AND operation unit 522 receives the second cycle mode instruction EN_2N, and the second input terminal receives the internal even clock PCLK_E; the first input terminal of the second NOR operation unit 523 ... third even clock PCLK_E; the first input terminal of the second NOR operation unit 523 receives the second cycle mode instruction EN_2N, and the second input terminal of the fourth NOR operation unit 524 receives the second cycle mode instruction EN_2N, and the second input terminal of the fourth NOR operation unit 525 receives the second cycle mode instruction EN_2N, and the second input terminal of the fourth NOR operation unit 525 receives the second cycle mode instruction EN_2N, and the second input terminal of the fourth NOR operation unit 524 receives the second cycle mode instruction EN_2N, and the second input terminal of the fourth NOR operation unit 525 receives the second cycle mode instruction EN_2N, and the second NOR operation unit 524 receives the second NOR operation unit EN_2N, and the second NOR operation unit 525 receives the second NOR operation unit EN_2N, and the second NOR operation unit 525 receives the second NOR operation unit EN The input terminal is connected to the output terminal of the third AND operation unit 521, and the second input terminal is connected to the output terminal of the fourth AND operation unit 522. The input terminal of the third delay unit 524 is connected to the output terminal of the second NOR operation unit 523, and the output terminal of the third delay unit 524 is used to output the first clock signal PCLK_O1 corresponding to the second processing circuit 22. The input terminal of the fourth delay unit 525 is connected to the output terminal of the third delay unit 524, and the output terminal of the fourth delay unit 525 is used to output the second clock signal PCLK_O2 corresponding to the second processing circuit 22. Through the example clock generation circuit, the operating clock of each circuit module can be provided, matching the signal sampling timing requirements, thereby achieving write compensation. Furthermore, the clock generation scheme in this example also considers different operating modes of the memory. In practical applications, the memory operating modes include 1N mode and 2N mode, and the memory processes instructions at different speeds in different operating modes.

[0070] With the coordination of various clock signals, the output circuit 23, based on the parity indicator signal SW, offsets the offset signals corresponding to the first processing circuit 21 and the second processing circuit 22 according to either an odd or even offset, and performs an OR logic operation on the offset signals to obtain a compensated internal write command. It can be understood that the offset signal CMD2_E corresponding to the first processing circuit and the offset signal CMD2_O corresponding to the second processing circuit differ by one external clock cycle, and the second clock signal PCLK_E2 corresponding to the first processing circuit and the second clock signal PCLK_O2 corresponding to the second processing circuit differ by one external clock cycle. Furthermore, the periods of both the first and second clock signals are two external clock cycles.

[0071] Based on the above signal timing relationship, when the required write compensation amount is an even multiple of the external clock cycle, the first output sub-circuit 41 uses the second clock signal PCLK_E2 corresponding to the first processing circuit to sample the offset signal CMD2_E corresponding to the first processing circuit, that is, delaying the offset signal CMD2_E by two tCK. Similarly, the second output sub-circuit 42 uses the second clock signal PCLK_O2 corresponding to the second processing circuit to sample the offset signal CMD2_O corresponding to the second processing circuit, that is, delaying the offset signal CMD2_O by two tCK. Finally, the integration circuit sums the output signals of the first output sub-circuit and the second output sub-circuit. The final signal is equivalent to further delaying by two tCK on the basis of the first stage delay (even multiple delay), thereby achieving a compensation amount equivalent to an even multiple of the external clock cycle.

[0072] When the required write compensation amount is an odd multiple of the external clock cycle, the first output sub-circuit 41 samples the offset signal CMD2_O corresponding to the second processing circuit using the second clock signal PCLK_E2 corresponding to the first processing circuit, that is, the offset signal CMD2_O is delayed by only one tCK. Similarly, the second output sub-circuit 42 samples the offset signal CMD2_E corresponding to the first processing circuit using the second clock signal PCLK_O2 corresponding to the second processing circuit, that is, the offset signal CMD2_E is delayed by one tCK. Finally, the integration circuit sums the output signals of the first and second output sub-circuits. The final signal is equivalent to a further delay of only one tCK on the basis of the first-stage delay (even-times delay), thereby achieving a compensation amount equivalent to an odd multiple of the external clock cycle. In practical applications, the level of the parity indicator signal can be used to characterize whether the compensation amount is an odd or even multiple of the external clock cycle. For example, when the parity indicator signal is high, it indicates that the compensation amount is an odd multiple of the external clock cycle, and a low level indicates an even multiple.

[0073] The specific structures of the first output sub-circuit, the second output sub-circuit, and the integrated circuit are not limited. As an example, Figure 10Here is an example diagram of the structure of an output circuit, such as... Figure 10 As shown, the first output sub-circuit 41 includes: a first AND gate 411, a second AND gate 412, a first NOR gate 413, and a third flip-flop 414; the first input terminal of the first AND gate 411 receives the offset signal CMD2_E corresponding to the first processing circuit 21, and the second input terminal receives the inverted signal SWB of the indication signal SW; the first input terminal of the second AND gate 412 receives the offset signal CMD2_O corresponding to the second processing circuit, and the second input terminal receives the indication signal SW; the input terminals of the first NOR gate 413 are connected to the output terminals of the first AND gate 411 and the second AND gate 412 respectively, and the output terminal of the first NOR gate 413 is connected to the input terminal of the third flip-flop 414; the clock terminal of the third flip-flop 414 receives the second clock signal PCLK_E2 corresponding to the first processing circuit; the output terminal of the third flip-flop 414 is connected to the first input terminal of the integrated circuit 43. The connection includes a second output sub-circuit 42, comprising a third AND gate 421, a fourth AND gate 422, a second NOR gate 423, and a fourth flip-flop 424. The first input of the third AND gate 421 receives the offset signal CMD2_O corresponding to the second processing circuit, and the second input receives the inverted signal SWB of the indicator signal SW. The first input of the fourth AND gate 422 receives the offset signal CMD2_E corresponding to the first processing circuit, and the second input receives the indicator signal SW. The inputs of the second NOR gate 423 are connected to the outputs of the third AND gate 421 and the fourth AND gate 422, respectively. The output of the second NOR gate 423 is connected to the input of the fourth flip-flop 424. The clock terminal of the fourth flip-flop 424 receives the second clock signal PCLK_O2 corresponding to the second processing circuit. The output of the fourth flip-flop 424 is connected to the second input of the integrated circuit 43. The integrated circuit 43 includes a third NOR gate 431 and a first NOT gate 432. The first input terminal of the third NOR gate 431 is connected to the output terminal of the first output sub-circuit 41, the second input terminal of the third NOR gate 431 is connected to the output terminal of the second output sub-circuit 42, and the output terminal of the third NOR gate 431 is connected to the input terminal of the first NOT gate 432. The output terminal of the first NOT gate 432 is used to output the internal write command after write compensation.

[0074] Based on the foregoing example, the processing circuits 21 / 22 consist of multiple offset sub-circuits 31. Each offset sub-circuit 31 receives a corresponding enable signal P<…> provided by the decoding circuit 21 based on the mode selection signal D4_P<…> and the mode register instruction MR3<…>, to perform basic delay compensation on the corresponding write command according to the enable signal. In conjunction with the foregoing example, the mode selection signal D4_P<…> may include a first selection signal D4_P. <0> Second selection signal D4_P <1> First selection signal D4_P <0> The second selection signal, D4_P, is used to indicate whether the current operating mode is the third mode (D5TYPE). <1> This is used to indicate whether the current operating mode is the first mode D4TYPE_PRE4 or the second mode D4TYPE_PRE2 / 3. The mode register instruction MR3<…> may include the indicator bit MDF_MR3. <0> and encoding bit MR3<n:1> Specifically, the MR3 encoding bit<n:1> To write the leveling encoding result MR3<n:1> The data segment excluding the last bit. Among them, MR3<n:1> It utilizes the binary representation of the absolute value of the offset actually required for internal writing and leveling, MDF_MR3<3:0>, plus the indicator bit MDF_MR3. <0> The purpose of this is to combine the internal write leveling offset MR into even and odd values, allowing for flexible write leveling offsets that are even or odd multiples of the external clock cycle. Referring to the example in Table 3, which shows the example mode register instructions...

[0075] Table 3

[0076]

[0077] In Table 3, the encoding bit MR3<n:1> The data length is four bits for example, i.e., n=3. In practical applications, the data length of the encoded bits can be determined according to the write leveling requirements. As an example, the indicator bit MDF_MR3 <0> This can be the least significant bit of the offset MDF_MR3<3:0>. This encoding method simplifies the data structure of the mode register instruction and enables parity merging of the internal write-leveling offset MR. It can be understood that, based on the above encoding method, the indicator bit MDF_MR3... <0> A value of 0 indicates that the write leveling offset is an even multiple of the external clock cycle, while a value of 1 indicates that the write leveling offset is an odd multiple of the external clock cycle. Based on the mode selection signal D4_P<…> and the mode register instruction MR3<…>, the decoding circuit 11 outputs a parity indicator signal SW and multiple enable signals P<…>. As an example, Figure 11 Here is a schematic diagram of an example decoding circuit, such as... Figure 11 As shown, the decoding circuit 11 includes: an odd / even decoding circuit 61 and a compensation decoding circuit 62;

[0078] Parity decoding circuit 61 receives the second selection signal D4_P <1> and the instruction pointer bit MDF_MR3 in the mode register <0> Used according to the second selection signal D4_P <1> and the instruction pointer bit MDF_MR3 in the mode register <0> The compensation amount is determined to be an odd multiple or an even multiple of the number of external clock cycles. When the compensation amount is an odd multiple of the number of external clock cycles, an odd / even indicator signal SW in the first state is output; and when the compensation amount is an even multiple of the number of external clock cycles, an odd / even indicator signal SW in the second state is output.

[0079] Compensation decoding circuit 62 receives the mode selection signal D4_P<…> and the encoded bits MR3 of the mode register instruction.<n:1> MR3 is used to encode the mode selection signal D4_P<…> and the mode register instruction.<n:1> The algorithm analyzes the data and outputs multiple enable signals P<…>.

[0080] The parity indicator signal, in different states, represents a compensation amount that is an odd or even multiple of the external clock cycle. Based on the foregoing, the first selection signal D4_P... <0> The different states indicate whether the current working mode is D5TYPE mode, for example, the first selection signal D4_P. <0> A value of 0 indicates D5TYPE mode, D4_P <0> A value of 1 indicates that it is not in D5TYPE mode. Further, the second selection signal D4_P... <1> The different states indicate the current operating mode as either D4TYPE_PRE2 / 3 mode or D4TYPE_PRE4 mode. In one example, when the first selection signal D4_P... <0> When the value is 0, the default design selects the second selection signal D4_P. <1> It is 0.

[0081] For example, as mentioned above, the compensation amount in D4TYPE_PRE2 / 3 mode is 5 external clock cycles, which is an odd multiple of the external clock cycle. In D4TYPE_PRE2 / 3 mode, the second selection signal D4_P... <1> Since the value is 1, the parity decoding circuit 61 should output a parity indicator signal SW in the first state, for example, a high-level state. As another example, the first selection signal D4_P... <0> When the value is 0, the operating mode is D5TYPE mode. The parity of the compensation amount depends on whether the write leveling offset is an odd or even multiple of the external clock cycle. Combined with the above, it can be seen that the indicator bit MDF_MR3... <0> Different states can characterize the parity of the write leveling offset. For example, when the indicator bit MDF_MR3 <0> When the value is 1, it indicates that the write leveling offset is an odd multiple of the external clock cycle, and the parity decoding circuit 61 outputs a parity indicator signal SW in the first state, such as a high-level signal. Conversely, when the indicator bit MDF_MR3 is 1, it indicates that the parity is 1. <0> When the value is 0, the parity decoding circuit 61 outputs a parity indication signal SW in the second state, such as a low-level signal. Therefore, in one example, the parity decoding circuit 61 is used if the second selection signal D4_P... <1> and the instruction pointer bit MDF_MR3 in the mode register <0> When any one of these values ​​is 1, the output is a high-level parity indicator signal SW; otherwise, the output is a low-level parity indicator signal SW. For example, Figure 12 Here is a schematic diagram of an example decoding circuit, such as... Figure 12 As shown, the parity decoding circuit 61 may include a fourth NOR gate 611 and a second NOT gate 612; the first input terminal of the fourth NOR gate 611 receives the second selection signal D4_P. <1> The second input terminal receives the indicator bit MDF_MR3 <0> The output of the fourth NOR gate 611 is connected to the input of the second NOT gate 612, and the output of the second NOT gate 612 is used to output the parity indicator signal SW. It should be noted that the figure is only an example, and the parity decoding circuit 61 can also be implemented by an OR gate structure. The specific method is not limited here.

[0082] Combining the aforementioned example, a two-stage compensation approach is adopted: a basic compensation is superimposed with an odd / even offset to achieve the complete compensation amount. Specifically, the compensation decoding circuit 62 outputs multiple enable signals based on the mode selection signal and the encoded bits. The enable signal corresponding to the currently required basic compensation amount is active, while the other enable signals are inactive. This allows each processing circuit 21 / 22 to apply a delay of the basic compensation amount to its respective input signal according to the enable signal. As an example, such as... Figure 12 As shown, the compensation decoding circuit 62 includes: multiple decoding sub-circuits 621, which correspond one-to-one with multiple offset sub-circuits 31;

[0083] Each decoding sub-circuit 621 receives the encoded bits of the mode register instruction and uses them to detect whether the current value of the encoded bits of the mode register instruction is consistent with the valid value corresponding to the decoding sub-circuit 621. If they are consistent, a valid enable signal P<…> is output; otherwise, an invalid enable signal P<…> is output.

[0084] The decoding sub-circuit 621 corresponding to the last-stage offset sub-circuit 31 also receives a mode selection signal D4_P<…>, which is used to output an invalid enable signal P<…> when the current working mode is the first mode or the second mode, and to detect whether the current value of the encoded bit of the mode register instruction is consistent with the valid value corresponding to the decoding sub-circuit 621 when the current working mode is the third mode. If they are consistent, a valid enable signal P<…> is output; otherwise, an invalid enable signal P<…> is output.

[0085] The decoding sub-circuit 621 corresponding to the previous level offset sub-circuit 31 of the last level also receives the mode selection signal D4_P<…>, which is used to output a valid enable signal P<…> when the current working mode is the first mode or the second mode according to the mode selection signal D4_P<…>; and when the mode selection signal D4_P<…> indicates that the current mode is the third mode, it detects whether the current value of the encoding bit of the mode register instruction is consistent with the valid value corresponding to the decoding sub-circuit 621. If they are consistent, it outputs a valid enable signal P<…>; otherwise, it outputs an invalid enable signal P<…>.

[0086] Specifically, this example utilizes decoding principles to output multiple enable signals based on the encoded bits of the mode register instruction. Different valid enable signals correspond to different base delays. Referring to the previous example, for the first and second modes, the base delay is fixed. For instance, in one example with a burst length of 16, the base delay for both D4TYPE_PRE4 and D4TYPE_PRE2 / 3 modes is 4 external clock cycles. Then, for D4TYPE_PRE4 mode, an even offset is added to achieve a compensation of 6 external clock cycles, while for D4TYPE_PRE2 / 3 mode, an odd offset is added to achieve a compensation of 5 external clock cycles. Given the fixed base delays of these two operating modes, this example, for the decoding sub-circuits corresponding to the last and penultimate offset sub-circuits, further designs their decoding functions for the first and second modes, based on their ability to decode the base delay in the third mode according to the encoded bits. Taking the first and second modes, both corresponding to a base delay of 4 external clock cycles, as an example, assuming each offset sub-circuit is delayed by 2 external clock cycles, the decoding sub-circuit corresponding to the penultimate offset sub-circuit, upon detecting the current mode as the first / second, outputs a valid enable signal to the penultimate offset sub-circuit of each processing circuit. Correspondingly, the penultimate offset sub-circuit in each processing circuit, with its own enable signal valid, outputs the received write command after a 2-external clock cycle delay to the last offset sub-circuit. Specifically, the decoding sub-circuit corresponding to the last offset sub-circuit, upon detecting the current mode as the first / second, outputs an invalid enable signal to the last offset sub-circuit of each processing circuit. Correspondingly, the last offset sub-circuit in each processing circuit delays the signal output by the previous offset sub-circuit (i.e., the penultimate offset sub-circuit) by 2 external clock cycles and outputs it as the corresponding offset signal, thus completing the application of the 4-external clock cycle base delay. In other words, when the current mode is the first or second mode, the enable signals output by the latter two levels of the encoding sub-circuit are fixed and independent of the value of the encoding bit of the mode register instruction. This enables the application of a fixed base delay to the write command in the first or second mode, which is independent of the encoding bit of the mode register instruction.

[0087] Taking the example of processing circuits 21 / 22 including a six-stage offset sub-circuit 31, for instance, still as Figure 12As shown, the decoding sub-circuit 621 corresponding to the last stage offset sub-circuit includes: a first multi-input NOR gate 71, a third NOT gate 72, a second multi-input NOR gate 73, and a fourth NOT gate 74; the input terminal of the first multi-input NOR gate 71 receives the encoded bits MR3<3:1> of the mode register instruction, and the output terminal of the first multi-input NOR gate 71 is connected to the input terminal of the third NOT gate 72; the first input terminal of the second multi-input NOR gate 73 is connected to the output terminal of the third NOT gate 72, and the second input terminal of the second multi-input NOR gate 73 receives the mode signal D4_P. <0> and D4_P <1> The output of the second multi-input NOR gate 73 is used to output the enable signal P of the last stage offset sub-circuit. <0> The input of the fourth NOT gate 74 is connected to the output of the second multi-input NOR gate 73, and the output of the fourth NOT gate 74 is used to output the enable signal P of the last stage offset circuit. <0> The inverted signal P <0> B;

[0088] The decoding sub-circuit 621 corresponding to the previous stage offset sub-circuit of the last stage includes: a first multi-input NAND gate 75, a second multi-input NAND gate 76, and a fifth NOT gate 77; the input terminal of the first multi-input NAND gate 75 receives multiple corresponding input signals (illustrated as MR3). <1> MR3 <2> B and MR3 <3> B) The output of the first multi-input NAND gate 75 is connected to the first input of the second multi-input NAND gate 76, and the second input of the second multi-input NAND gate 76 receives the inverted signal D4_P of the mode signal. <0> B and D4_P <1> B, the output of the second multi-input NAND gate 76 is used to output the enable signal P of the previous stage offset sub-circuit of the last stage. <2> The input of the fifth NOT gate 77 is connected to the output of the second multi-input NAND gate 76. The output of the fifth NOT gate 77 is used to output the inverted signal P of the enable signal of the previous stage offset circuit of the last stage. <2> B;

[0089] The decoding sub-circuit 621 corresponding to each offset sub-circuit except the last two stages includes: a third multi-input AND gate 78 and a sixth NOT gate 79; the third multi-input AND gate 78 receives multiple corresponding input signals, and the output terminal of the third multi-input AND gate 78 is connected to the input terminal of the sixth NOT gate 79; the output terminal of the sixth NOT gate 79 is used to output the enable signal corresponding to the offset sub-circuit.

[0090] The decoding sub-circuit includes multiple input signals such as the first input signal, the second input signal, ..., the i-th input signal, ..., the n-th input signal. If the i-th bit of the effective value corresponding to the decoding sub-circuit is high, the i-th input signal is the i-th bit of the encoding bit of the mode register instruction; if the i-th bit of the effective value corresponding to the decoding sub-circuit is low, the i-th input signal is the inverted signal of the i-th bit of the encoding bit of the mode register instruction, where 1 ≤ i ≤ n, and i is an integer. It should be noted that the above is only an example. As long as the enable signal required to control the basic delay of the processing circuit can be output in the first, second, and third modes, the specific implementation of the decoding circuit is not limited here. Taking the example of the processing circuit 21 / 22 including a six-level offset sub-circuit 31, the enable signals corresponding to each offset sub-circuit include P... <0> P <2> …P <8> P <10> As an example, P <4> The corresponding input signals for the decoding sub-circuit 621 include MR3. <1> B, MR3 <2> and MR3 <3> B; P <6> The corresponding input signals for the decoding sub-circuit 621 include MR3. <1> MR3 <2> and MR3 <3> B; P <8> The corresponding input signals for the decoding sub-circuit 621 include MR3. <1> B, MR3 <2> B and MR3 <3> ;P <10> The corresponding input signals for the decoding sub-circuit 621 include P <8> B, and MR3 <3> By using other enable signals as input signals to the decoding sub-circuit corresponding to a certain enable signal, the number of input signals can be effectively reduced, further simplifying the circuit structure.

[0091] In practical applications, considering timing matching, a timing matching circuit can be set up to perform timing matching processing on the internal write commands, and then the compensation circuit will perform compensation. As an example, such as... Figure 13 As shown, Figure 13 The following is a structural example diagram of a timing matching circuit. The write compensation circuit also includes a timing matching circuit 24. The timing matching circuit 24 includes an even number of first inverters 241 (two are used as an example in the figure), an even number of second inverters 244 (two are used as an example in the figure), a delay unit 242, and a fifth NOR gate 243.

[0092] An even number of first inverters 241 are connected in series, with the first inverter receiving the inverted signal of the internal write command. The even number of first inverters 241 are connected in series to the input of the delay unit 242. The output of the delay unit 242 is connected to the first input of the fifth NOR gate 243. The second input of the fifth NOR gate 243 receives the automatic precharge enable signal AP_EN. The output of the fifth NOR gate 243 is connected in series with an even number of second inverters 244. The timing matching circuit 24 is used to output the internal write command after timing matching processing.

[0093] Based on the previous example, two timing matching circuits can be set up to perform timing matching processing on the inverted signals of INT_WRCMD_E and INT_WRCMD_O, namely INT_WRCMD_EB and INT_WRCMD_OB, respectively. These signals are then used as the write commands RMW_E and RMW_O corresponding to the first processing circuit 21 and the second processing circuit 22, respectively, and input to the first processing circuit 21 and the second processing circuit 22 for base offset. Correspondingly, as... Figure 7 As shown, a third inverter 318 needs to be set at the output of the last stage offset sub-circuit 31 in the first processing circuit 21 and the second processing circuit 22 to output offset signals CMD2_E and CMD2_O. Specifically, in this example, the inverted signal of the write command is offset by a basic value and then inverted again. It is then input to the first output word circuit 41 and the second output sub-circuit 42 of the output circuit 23, respectively, and finally the internal write command with write compensation is output by the output circuit 23.

[0094] The write compensation circuit provided in this embodiment includes a decoding circuit and a compensation circuit. The decoding circuit determines the compensation amount based on the mode selection signal and the mode register instruction, and outputs an odd / even indicator signal indicating that the compensation amount is an odd or even multiple of the external clock cycle, as well as an enable signal corresponding to each offset. Only the enable signal corresponding to the offset of the current operating mode is valid. When the automatic precharge enable signal is valid, the compensation circuit performs delay compensation on the internal write command according to the odd / even indicator signal and the enable signal, based on the compensation amount. Specifically, the compensation applies a delay of the offset corresponding to the current operating mode to the internal write command, and then further adds a delay of the odd or even offset. This solution compensates for the delay of the internal write command by applying an odd or even offset to the corresponding offset for different operating modes, thereby meeting the signal timing requirements of the chip when performing a write command operation including automatic precharge, and realizing a flexible write compensation scheme.

[0095] Figure 14 Here is an example diagram of the structure of a memory, such as Figure 14 As shown, the memory includes: a storage array 1, and a write compensation circuit 2 as in any of the preceding examples.

[0096] Combining the aforementioned scheme, for example, the external clock CK_t / CK_c, after passing through the memory receiver, is divided into an internal odd clock PCLK_O and an internal even clock PCLK_E for sampling. That is, each DFF stage will shift the input signal by 2T CK for output. Figure 15 Here is a timing diagram for an example, such as Figure 15As shown, assuming the current D4_P <0> and D4_P <1> A signal of 0 indicates that the current operating mode is D5TYPE. Assuming a burst length of 16 bits, MR3...<n:1> =011, and MDF_MR3 <0> =1 indicates that the original write leveling encoding result MR3<3:0> was -5tCK, but it was changed to -6tCK after parity merging encoding. Therefore, in this example, the shift added to the internal write signal is CWL+4-MR3, which needs to be compensated to CWL+8. Thus, the amount to be compensated is CWL+8-(CWL+4-MR3)=4+5=9, which is 9 external clock cycles tCK.

[0097] After processing by decoding circuit 11, assuming that among the multiple enable signals output by decoding circuit 11, P <6> If the signal is valid, then combine Figure 7 The example circuit, taking the write signal RMW_E corresponding to the first processing circuit 21 as an example, the RMW_E signal is actually generated by P <6> The corresponding input to the offset sub-circuit 31, assuming a delay of 2 tCK for each stage of the offset sub-circuit, then after P <6> The corresponding offset sub-circuit 31, P <4> The corresponding offset sub-circuit 31, P <2> The corresponding offset sub-circuit 31 and P <0> The corresponding offset sub-circuit 31 outputs an offset signal CMD2_E from the first processing circuit 21, which is compensated by 8 tCK compared to the RMW_E signal. Furthermore, since the amount to be compensated is an odd multiple of the external clock cycle, if the SW signal is valid (e.g., high level), it means that only 1 tCK of compensation needs to be superimposed through the output circuit 23. Combined with... Figure 10 In the output circuit shown, if the SW signal is not activated, for example, is low, then CMD2_E should continue to be sampled by the first output sub-circuit 41 based on the second clock signal PCLK_E2 corresponding to the first processing circuit, that is, after realizing the superposition compensation of 2tCK, it should be output to the integrated circuit. However, now SW is high and SWB is low, so if... Figure 10As shown, the CMD2_E signal is sampled by the second output sub-circuit 42 based on the second clock signal PCLK_O2 corresponding to the second processing circuit. Since the PCLK_E2 and PCLK_O2 signals differ by 1tCK, the second output sub-circuit 42 samples CMD2_E at this time, and the output signal is only shifted by 1tCK compared to CMD2_E. Finally, after integration processing by the integration circuit 43, the output compensated INT_WRCMD signal is compensated by 8+1=9TCK compared to the original INT_WRCMD, achieving an odd multiple compensation. It can be understood that the above is only an example. For example, if the amount to be compensated is an even multiple of the external clock, SW is at a low level. Therefore, the offset signals output by the first processing circuit and the second processing circuit continue to be sampled by the first output sub-circuit and the second output sub-circuit based on their respective second clock signals, that is, 2tCK is superimposed. Finally, after passing through the integration circuit, the write signal compensated by an even multiple of tCK is obtained.

[0098] In the memory provided in this embodiment, the write compensation circuit includes a decoding circuit and a compensation circuit. The decoding circuit determines the compensation amount based on the mode selection signal and the mode register instruction, and outputs an odd / even indicator signal indicating that the compensation amount is an odd or even multiple of the external clock cycle, as well as an enable signal corresponding to each offset. Only the enable signal corresponding to the offset of the current operating mode is valid. When the automatic precharge enable signal is valid, the compensation circuit performs delay compensation on the internal write command according to the compensation amount based on the odd / even indicator signal and the enable signal. Specifically, the compensation applies a delay of the offset corresponding to the current operating mode to the internal write command, and then further adds a delay of the odd or even offset. This solution compensates for the delay of the internal write command by applying an odd or even offset to the corresponding offset for different operating modes, thereby meeting the signal timing requirements when the chip is performing a write command operation including automatic precharge, and realizing a flexible write compensation scheme.

[0099] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only.

[0100] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A write back compensation circuit, characterized by, The application relates to a decoding circuit and a compensation circuit. The decoding circuit receives a mode selection signal and a mode register instruction, determines a compensation amount corresponding to a current working mode according to the mode selection signal and the mode register instruction, and outputs a parity indication signal and a plurality of enable signals, wherein different enable signals correspond to different offset amounts; only the enable signal corresponding to the offset amount corresponding to the compensation amount of the current working mode is valid in the enable signals, and the parity indication signal represents whether the compensation amount corresponding to the current working mode is an odd multiple or an even multiple of an external clock period. The compensation circuit is coupled to the decoding circuit, and when an automatic precharge enable signal is valid, the compensation circuit compensates an internal write command based on an external write command according to the parity indication signal and the plurality of enable signals according to the corresponding compensation amount, so that the external write command completes a preset delay amount delay in different modes, and the compensation amount is obtained by superimposing an odd offset amount or an even offset amount on the offset amount corresponding to the compensation amount. The working mode includes a first mode, a second mode and a third mode.

2. The write compensation circuit of claim 1, wherein, The transmission rate corresponding to the first mode is not greater than a preset value, and the preamble of a data strobe signal is four external clock periods; the transmission rate corresponding to the second mode is not greater than the preset value, and the preamble of the data strobe signal is two or three external clock periods; and the transmission frequency corresponding to the third mode is greater than the preset value. The preset delay amount is the sum of the number of external clock periods corresponding to a column address strobe pulse write delay and half of a burst length.

3. The write compensation circuit of claim 2, wherein, The compensation amount corresponding to the first mode is six external clock periods; the compensation amount corresponding to the second mode is five external clock periods; and the compensation amount corresponding to the third mode is the sum of four external clock periods and the absolute value of an offset amount represented by a mode register instruction. The compensation circuit comprises two processing circuits, namely a first processing circuit and a second processing circuit, and an output circuit.

4. The write compensation circuit according to claim 2 or 3, characterized in that, The first processing circuit and the second processing circuit are respectively used for, when the automatic precharge enable signal is valid, offsetting a corresponding write command according to the offset amount corresponding to the enable signal in a valid state to obtain a corresponding offset signal according to the plurality of enable signals; wherein the first processing circuit and the second processing circuit sample the internal write command based on an internal even clock and an internal odd clock to obtain the corresponding write command; wherein the offset amount corresponding to the enable signal is an even number of external clock periods, the clock period of the internal even clock and the internal odd clock is twice the clock period of the external clock, and the phase difference between the internal even clock and the internal odd clock is one external clock period. The output circuit is connected with the decoding circuit, the first processing circuit and the second processing circuit, and is used for offsetting the offset signals corresponding to the first processing circuit and the second processing circuit according to an odd offset amount or an even offset amount according to the parity indication signal, and performing or logical operation on the offset signals to obtain a compensated internal write command. ​ 5. The write compensation circuit of claim 4, wherein, Each processing circuit comprises a plurality of cascaded offset sub-circuits corresponding to the plurality of enable signals one by one; The first-stage offset sub-circuit receives a write command corresponding to the processing circuit and an enable signal corresponding to the offset sub-circuit; each offset sub-circuit other than the first-stage offset sub-circuit receives a write command corresponding to the processing circuit and an enable signal corresponding to the offset sub-circuit, and is connected to an output terminal of the offset sub-circuit at the previous stage; Each offset sub-circuit is configured to output the received write command after time delay when the enable signal corresponding to the offset sub-circuit is valid, and output a signal output by the offset sub-circuit at the previous stage after time delay when the enable signal corresponding to the offset sub-circuit is invalid; and the last-stage offset sub-circuit is configured to output an offset signal corresponding to the processing circuit; wherein a total time delay amount of the offset sub-circuit corresponding to the enable signal in the valid state and all offset sub-circuits after the offset sub-circuit is an offset amount corresponding to the enable signal in the valid state.

6. The write compensation circuit of claim 5, wherein, The mode selection signal comprises a first selection signal and a second selection signal; the first selection signal is used to indicate whether the current working mode is the third mode, and the second selection signal is used to indicate whether the current working mode is the first mode or the second mode; the mode register instruction comprises an indication bit and an encoding bit; The decoding circuit comprises a parity decoding circuit and a compensation decoding circuit. The parity decoding circuit receives the second selection signal and the indication bit of the mode register instruction, and is configured to determine whether the compensation amount is an odd multiple or an even multiple of a number of external clock cycles according to the second selection signal and the indication bit of the mode register instruction, output the parity indication signal in the first state when the compensation amount is the odd multiple of the number of external clock cycles, and output the parity indication signal in the second state when the compensation amount is the even multiple of the number of external clock cycles. The compensation decoding circuit receives the mode selection signal and the encoding bit of the mode register instruction, and is configured to parse the mode selection signal and the encoding bit of the mode register instruction, and output the plurality of enable signals.

7. The write compensation circuit of claim 6, wherein, The compensation decoding circuit comprises a plurality of decoding sub-circuits corresponding to the plurality of offset sub-circuits one by one; Each decoding sub-circuit receives the encoding bit of the mode register instruction, and is configured to detect whether a current value of the encoding bit of the mode register instruction is consistent with a valid value corresponding to the decoding sub-circuit, output a valid enable signal if the current value is consistent with the valid value, or output an invalid enable signal if the current value is not consistent with the valid value; The decoding sub-circuit corresponding to the last-stage offset sub-circuit further receives the mode selection signal, and is configured to output an invalid enable signal when the current working mode is the first mode or the second mode according to the mode selection signal, and detect whether a current value of the encoding bit of the mode register instruction is consistent with a valid value corresponding to the decoding sub-circuit when the current working mode is the third mode, output a valid enable signal if the current value is consistent with the valid value, or output an invalid enable signal if the current value is not consistent with the valid value. The decoding sub-circuit corresponding to the last-stage offset sub-circuit further receives the mode selection signal, and outputs a valid enable signal when the current working mode is the first mode or the second mode according to the mode selection signal; and when the mode selection signal indicates that the current working mode is the third mode, the decoding sub-circuit detects whether the current value of the encoding bit of the mode register instruction is consistent with the valid value corresponding to the decoding sub-circuit, and outputs a valid enable signal if consistent, or outputs an invalid enable signal otherwise.

8. The write compensation circuit of claim 7, wherein, the decoding sub-circuit corresponding to the last-stage offset sub-circuit comprises a first multi-input NOR gate, a third NOT gate, a second multi-input NOR gate and a fourth NOT gate; the first multi-input NOR gate receives the encoding bit of the mode register instruction at an input terminal, and an output terminal of the first multi-input NOR gate is connected to an input terminal of the third NOT gate; a first input terminal of the second multi-input NOR gate is connected to an output terminal of the third NOT gate, a second input terminal of the second multi-input NOR gate receives the mode selection signal, and an output terminal of the second multi-input NOR gate is used to output the enable signal of the last-stage offset sub-circuit; an input terminal of the fourth NOT gate is connected to an output terminal of the second multi-input NOR gate, and an output terminal of the fourth NOT gate is used to output an inverted signal of the enable signal of the last-stage offset sub-circuit; the decoding sub-circuit corresponding to the last-but-one-stage offset sub-circuit comprises a first multi-input AND gate, a second multi-input AND gate and a fifth NOT gate; the first multi-input AND gate receives corresponding multiple input signals at input terminals, an output terminal of the first multi-input AND gate is connected to a first input terminal of the second multi-input AND gate, a second input terminal of the second multi-input AND gate receives an inverted signal of the mode selection signal, and an output terminal of the second multi-input AND gate is used to output the enable signal of the last-but-one-stage offset sub-circuit; an input terminal of the fifth NOT gate is connected to an output terminal of the second multi-input AND gate, and an output terminal of the fifth NOT gate is used to output an inverted signal of the enable signal of the last-but-one-stage offset sub-circuit; the decoding sub-circuit corresponding to each offset sub-circuit except the last two stages comprises a third multi-input AND gate and a sixth NOT gate; the third multi-input AND gate receives corresponding multiple input signals, and an output terminal of the third multi-input AND gate is connected to an input terminal of the sixth NOT gate; and an output terminal of the sixth NOT gate is used to output the enable signal corresponding to the offset sub-circuit; wherein the multiple input signals corresponding to the decoding sub-circuit comprise a first input signal, a second input signal, an i-th input signal (1≤i≤n, i is an integer), and an n-th input signal; if an i-th bit of the valid value corresponding to the decoding sub-circuit is high, the i-th input signal is an i-th bit of the encoding bit of the mode register instruction; if the i-th bit of the valid value corresponding to the decoding sub-circuit is low, the i-th input signal is an inverted signal of the i-th bit of the encoding bit of the mode register instruction.

9. The write compensation circuit of claim 5, wherein, the first stage offset sub-circuit comprises a first NAND gate, a seventh NAND gate and a first flip-flop, a first input terminal of the first NAND gate receives an enable signal of the first stage offset sub-circuit, a second input terminal of the first NAND gate receives a write command corresponding to the processing circuit, an input terminal of the seventh NAND gate is connected with an output terminal of the first NAND gate, an output terminal of the seventh NAND gate is connected with an input terminal of the first flip-flop, and a clock terminal of the first flip-flop receives a first clock signal corresponding to the processing circuit; each stage offset sub-circuit except the first stage offset sub-circuit comprises a second NAND gate, a third NAND gate, a fourth NAND gate and a second flip-flop, a first input terminal of the second NAND gate receives an enable signal of the offset sub-circuit, a second input terminal of the second NAND gate receives a write command corresponding to the processing circuit, a first input terminal of the third NAND gate receives an inverted signal of the enable signal of the offset sub-circuit, a second input terminal of the third NAND gate is connected with an output terminal of an upper stage offset sub-circuit, a first input terminal of the fourth NAND gate is connected with an output terminal of the second NAND gate, a second input terminal of the fourth NAND gate is connected with an output terminal of the third NAND gate, and an output terminal of the fourth NAND gate is connected with an input terminal of the second flip-flop, and a clock terminal of the second flip-flop receives a first clock signal corresponding to the processing circuit; wherein a period of the first clock signal is a sub-offset, and a phase difference between the first clock signal corresponding to the first processing circuit and the first clock signal corresponding to the second processing circuit is a phase difference between the internal even clock and the internal odd clock.

10. The write compensation circuit of claim 6, wherein, the output circuit comprises a first output sub-circuit, a second output sub-circuit and an integration circuit; the first output sub-circuit is connected with the parity decoding circuit, the first processing circuit and the second processing circuit, and is configured to, in response to the parity indication signal being in a first state, sample and output the offset signal corresponding to the second processing circuit based on a second clock signal corresponding to the first processing circuit, and in response to the parity indication signal being in a second state, sample and output the offset signal corresponding to the first processing circuit based on the second clock signal corresponding to the first processing circuit; the second output sub-circuit is connected with the parity decoding circuit, the first processing circuit and the second processing circuit, and is configured to, in response to the parity indication signal being in a first state, sample and output the offset signal corresponding to the first processing circuit based on a second clock signal corresponding to the second processing circuit, and in response to the parity indication signal being in a second state, sample and output the offset signal corresponding to the second processing circuit based on the second clock signal corresponding to the second processing circuit. The integration circuit is connected with the first output sub-circuit and the second output sub-circuit, and is configured to perform an OR logical operation on output signals of the first output sub-circuit and the second output sub-circuit, and output the compensated internal write command; wherein a period of the second clock signal corresponding to the first processing circuit and a period of the second clock signal corresponding to the second processing circuit are the same, and a phase difference between the two is the same as a phase difference between the internal even clock and the internal odd clock.

11. A memory, comprising: Comprising: a memory array, and a write compensation circuit as claimed in any of claims 1-10.

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