Test system, method and device of memory chip, electronic equipment and medium

Abstract

The invention discloses a memory chip testing system, method and device, electronic equipment and a medium, and particularly relates to the field of electronic chip testing. The temperature control box is used for heating the test assembly to enable the environment temperature of the memory chip to reach the preset test temperature, and the radiator is used for radiating the system-on-chip module, so that the temperature of the system-on-chip module is reduced, and the situation that the system-on-chip module cannot operate due to too high temperature is avoided. Since the memory chip is directly mounted on the test circuit board through the connecting seat and does not need to be connected through a transmission line, signal attenuation caused by the transmission line can be avoided, the signal transmission rate between the test circuit board and the memory chip is ensured, the accuracy of a test result is ensured, and the test efficiency is improved. And the limit performance of the memory chip can be tested at a relatively high signal transmission rate.

Description

Technical Field

[0001] The present application relates to the field of electronic chip testing, and in particular to a memory chip testing system, method, device, electronic equipment and medium. Background Art

[0002] During the production process of memory chips, the memory chips need to be tested. In order to test the performance of memory chips under extreme conditions, the memory chips need to be tested at a higher signal transmission rate and in a higher temperature environment. In current memory chip testing equipment, a test circuit board is usually used to test the memory chip. Since the system-on-chip module on the test circuit board cannot withstand high temperatures, the test circuit board is usually placed outside the temperature control box, and the memory chip is placed inside the temperature control box. The test circuit board and the memory chip are electrically connected through a transmission line of a certain length. Due to the limitations of the transmission line, the signal transmission rate between the test circuit board and the memory chip is reduced, thereby reducing the accuracy of the test results. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a memory chip test system, method, device, electronic equipment and medium, where a test circuit board and the memory chip do not need to be connected by a transmission line, so that the signal transmission rate between the test circuit board and the memory chip can be guaranteed, thereby ensuring the accuracy of the test result.

[0004] A memory chip testing system according to a first aspect of the present application includes:

[0005] Temperature control box;

[0006] A test assembly, the test assembly is installed inside the temperature control box, the test assembly includes a test circuit board, a first thermal insulation pad and a radiator, the first thermal insulation pad is provided with a through groove, the radiator is arranged on the test circuit board through the thermal insulation pad, a system-on-chip module is arranged on a side of the test circuit board opposite to the radiator, and the system-on-chip module is located in the through groove; a connection seat is arranged on a side of the test circuit board opposite to the radiator, the connection seat is used to install a memory chip to be tested, and the memory chip is electrically connected to the system-on-chip module through the test circuit board;

[0007] A host computer, the host computer is located outside the temperature control box, the host computer is electrically connected to the temperature control box, and the host computer is electrically connected to the test circuit board through a connecting line; the host computer is used to send test instructions to the test circuit board and receive test data sent by the test circuit board; the temperature control box is used to heat the test component so that the ambient temperature of the memory chip reaches a preset test temperature.

[0008] According to the memory chip test system of the embodiment of the present application, at least the following beneficial effects are achieved: the test system includes a temperature control box, a test assembly and a host computer. The test assembly includes a test circuit board, a first thermal insulation pad and a radiator. The first thermal insulation pad is provided with a through groove. The radiator is arranged on the test circuit board through a thermal insulation pad. The side of the test circuit board opposite to the radiator is provided with a system-on-chip module, and the system-on-chip module is located in the through groove. The side of the test circuit board opposite to the radiator is provided with a connection seat, and the connection seat is used to install the memory chip to be tested, and the memory chip is electrically connected to the system-on-chip module through the test circuit board. The host computer is used to send test instructions to the test circuit board and receive test data sent by the test circuit board to obtain test results. The temperature control box is used to heat the test assembly so that the ambient temperature of the memory chip reaches the preset test temperature, and the radiator is used to dissipate heat from the system-on-chip module, reduce the temperature of the system-on-chip module, and avoid the situation where the system-on-chip module cannot operate due to excessive temperature. Since the memory chip is directly mounted on the test circuit board through the connecting socket without being connected through a transmission line, signal attenuation caused by the transmission line can be avoided, thereby ensuring the signal transmission rate between the test circuit board and the memory chip, thereby ensuring the accuracy of the test results, and being able to test the extreme performance of the memory chip at a higher signal transmission rate.

[0009] According to some embodiments of the first aspect of the present application, the test assembly further includes a second thermal insulation pad, which is disposed on a side of the heat sink away from the first thermal insulation pad, and the heat sink is located between the first thermal insulation pad and the second thermal insulation pad.

[0010] According to some embodiments of the first aspect of the present application, the test assembly is provided with a first temperature sensor and a second temperature sensor, the first temperature sensor and the second temperature sensor are installed on the test circuit board, and the first temperature sensor is located in the through groove; the second temperature sensor is arranged on one side of the connecting seat.

[0011] According to some embodiments of the first aspect of the present application, a heat dissipation component is further included, which includes a water pump, an expansion valve and a water storage tank. The water pump and the water storage tank are both arranged outside the temperature control box, the output end of the water pump is connected to the input end of the radiator through the expansion valve, the input end of the water pump is connected to the water storage tank, and the output end of the radiator is connected to the water storage tank; the host computer is electrically connected to the water pump and the expansion valve, respectively.

[0012] A second aspect of the present application provides a method for testing a memory chip, which is applied to a host computer of a test system of the first aspect of the present application, and the method includes:

[0013] Obtain the limit transmission rate and limit ambient temperature range;

[0014] Based on the extreme ambient temperature range, the temperature control box is controlled to heat the test component; during the heating process, the water pump is started, and the first detection temperature in the through groove is obtained through the first temperature sensor, and the second detection temperature of the connecting seat is obtained through the second temperature sensor, and the expansion valve is controlled based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than the first preset temperature, and the second detection temperature is within the extreme ambient temperature range; wherein the first preset temperature is the upper limit value of the temperature range of normal operation of the system-on-chip module;

[0015] When it is detected that the first detected temperature is lower than the first preset temperature and the second detected temperature is within the extreme ambient temperature range, a performance test is performed on the memory chip to be tested based on the extreme transmission rate through the test circuit board to obtain a test result.

[0016] According to some embodiments of the second aspect of the present application, obtaining a first detected temperature in the through groove by the first temperature sensor, obtaining a second detected temperature of the connecting seat by the second temperature sensor, and controlling the expansion valve based on the first detected temperature and the second detected temperature so that the first detected temperature is lower than a first preset temperature and the second detected temperature is within the extreme ambient temperature range, includes:

[0017] Adjusting the opening of the expansion valve to a preset opening;

[0018] periodically acquiring a first detected temperature through the first temperature sensor and acquiring a second detected temperature through the second temperature sensor;

[0019] Calculating a first temperature difference between a first detected temperature and the first preset temperature;

[0020] When it is detected that the first detected temperature is lower than the first preset temperature, the first temperature difference is lower than or equal to the first preset difference, and the second detected temperature is within the extreme ambient temperature range, the opening of the expansion valve is increased.

[0021] According to some embodiments of the second aspect of the present application, after periodically acquiring the first detected temperature through the first temperature sensor and acquiring the second detected temperature through the second temperature sensor, the method further includes:

[0022] Calculating a second temperature difference between the second detected temperature and a lower limit of the extreme ambient temperature interval;

[0023] When it is detected that the first detected temperature is lower than the first preset temperature, the first temperature difference is greater than the first preset difference, the second detected temperature is within the extreme ambient temperature range, and the second temperature difference is less than the second preset difference, the opening of the expansion valve is reduced.

[0024] A third aspect of the present application provides a memory chip test device, which is applied to a host computer of a test system of the first aspect of the present application, and includes:

[0025] An acquisition module is configured to acquire a limit transmission rate and a limit ambient temperature range;

[0026] The heating module is configured to control the temperature control box to heat the test component based on the extreme ambient temperature range; during the heating process, the water pump is started, and the first detection temperature in the through groove is obtained through the first temperature sensor, and the second detection temperature of the connecting seat is obtained through the second temperature sensor, and the expansion valve is controlled based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than the first preset temperature, and the second detection temperature is within the extreme ambient temperature range; wherein the first preset temperature is the upper limit value of the temperature range of normal operation of the system-on-chip module;

[0027] The detection module is configured to perform a performance test on the memory chip to be tested through a test circuit board based on the limit transmission rate to obtain a test result when it is detected that the first detection temperature is lower than the first preset temperature and the second detection temperature is within the limit ambient temperature range.

[0028] A fourth aspect of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the memory chip testing method described in any one of the second aspect embodiments when executing the computer program.

[0029] The fifth aspect of the present application provides a computer-readable storage medium, which stores a computer program, and is characterized in that when the computer program is executed by a processor, it implements the memory chip testing method described in any one of the second aspect embodiments.

[0030] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0032] Figure 1 A schematic diagram of the structure of a memory chip test system according to an embodiment of the present application;

[0033] Figure 2 A schematic diagram of the steps of the memory chip testing method according to an embodiment of the present application;

[0034] Figure 3 for Figure 2 A specific flow chart of step S320;

[0035] Figure 4 A schematic diagram of a sub-flow chart after step S420 of the memory chip testing method according to an embodiment of the present application;

[0036] Figure 5 A schematic diagram of the structure of a memory chip testing device according to an embodiment of the present application;

[0037] Figure 6 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application.

[0038] Reference numerals:

[0039] Temperature control box 100; test circuit board 110; connection seat 111; system-on-chip module 112; first thermal insulation pad 120; radiator 130; second thermal insulation pad 140; host computer 150; water storage tank 160; expansion valve 170; water pump 180; thermal pad 190. DETAILED DESCRIPTION

[0040] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0041] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0042] In the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0043] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0044] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0045] Since the system-on-chip module 112 on the test circuit board cannot withstand high temperatures, the test circuit board is usually placed outside the temperature control box, and the memory chip is placed inside the temperature control box. The test circuit board and the memory chip are electrically connected through a transmission line of a certain length. Due to the limitations of the transmission line, the signal transmission rate between the test circuit board and the memory chip is reduced, thereby reducing the accuracy of the test results. Moreover, due to the limitations of the transmission line, the memory chip cannot be tested at a higher signal transmission rate, that is, the memory chip cannot be tested for extreme performance.

[0046] Based on this, the embodiments of the present application provide a memory chip test system, method, device, electronic device and medium, where there is no need to use a transmission line to connect the test circuit board and the memory chip, so the signal transmission rate between the test circuit board and the memory chip can be guaranteed, thereby ensuring the accuracy of the test results. And the extreme performance of the memory chip can be tested at a higher signal transmission rate.

[0047] The first aspect of the present application provides a memory chip testing system. Figure 1 , Figure 1 The following is a schematic diagram of the structure of a memory chip test system according to an embodiment of the present application. The memory chip test system includes:

[0048] Temperature control box 100;

[0049] A test assembly is installed inside the temperature control box 100. The test assembly includes a test circuit board 110, a first thermal insulation pad 120 and a heat sink 130. The first thermal insulation pad 120 is provided with a through groove. The heat sink 130 is provided on the test circuit board 110 through a thermal insulation pad. A system-on-chip module 112 is provided on a side of the test circuit board 110 opposite to the heat sink 130, and the system-on-chip module 112 is located in the through groove. A connection seat 111 is provided on a side of the test circuit board 110 opposite to the heat sink 130. The connection seat 111 is used to install a memory chip to be tested, and the memory chip is electrically connected to the system-on-chip module 112 through the test circuit board 110.

[0050] The host computer 150 is located outside the temperature control box 100, and is electrically connected to the temperature control box 100. The host computer 150 is electrically connected to the test circuit board 110 through a connecting line; the host computer 150 is used to send test instructions to the test circuit board 110, and receive test data sent by the test circuit board 110; the temperature control box 100 is used to heat the test component so that the ambient temperature of the memory chip reaches a preset test temperature.

[0051] According to the memory chip test system of the embodiment of the present application, there are at least the following beneficial effects: the host computer 150 is used to send test instructions to the test circuit board 110, and receive test data sent by the test circuit board 110 to obtain test results. The temperature control box 100 is used to heat the test component so that the ambient temperature of the memory chip reaches the preset test temperature, and the radiator 130 is used to dissipate heat from the system-on-chip module 112, reduce the temperature of the system-on-chip module 112, and avoid the situation where the system-on-chip module 112 cannot operate due to excessive temperature. Since the memory chip is directly mounted on the test circuit board 110 through the connection socket 111, there is no need to connect through a transmission line, so the signal attenuation caused by the transmission line can be avoided, thereby ensuring the signal transmission rate between the test circuit board 110 and the memory chip, thereby ensuring the accuracy of the test results, and being able to test the extreme performance of the memory chip at a higher signal transmission rate.

[0052] It should be noted that the memory chip is an LPDDR (Low Power Double Data Rate SDRAM) chip. The LPDDR chip is a memory technology designed for low-power devices. It is a branch of DDR SDRAM and its standards are set by the JEDEC Solid State Technology Association. The LPDDR series of chips are known for their low power consumption and high performance. They are mainly used in mobile devices, tablets, and thin and light notebooks, which are sensitive to power consumption and volume. The operating temperature range of ordinary LPDDR chips is -40℃ to 95℃, while the operating temperature range of some industrial-grade LPDDR chips is -40℃ to 105℃. Therefore, when producing LPDDR chips, it is usually necessary to perform performance tests on LPDDR chips at the upper limit of the operating temperature range.

[0053] It should be noted that the system-on-chip module 112 refers to a system-on-chip or system-level chip (System on Chip, SoC), which is a highly integrated integrated circuit technology that integrates all components required for a complete electronic system into a single chip. These components include processor cores, memories, input / output interfaces, communication modules, power management units, etc. The design goal of SoC is to achieve high performance, low power consumption, small size and high reliability. The operating temperature range of a general system-on-chip module 112 is between 0°C and 70°C. If the system-on-chip module 112 is exposed to a high temperature environment for a long time, it is prone to damage. The present application uses a first thermal insulation pad 120 for insulation and a heat sink 130 for heat dissipation, which can reduce the temperature around the system-on-chip module 112, thereby ensuring that the system-on-chip module 112 can operate normally and ensure the service life of the system-on-chip module 112.

[0054] It should be noted that the memory chip is mounted on the test circuit board 110 through the connector 111 and is electrically connected to the test circuit board 110 through the connector 111. Compared with the transmission line, the test circuit board 110 can send test instructions to the memory chip through the connector 111 at a higher data transmission rate.

[0055] It should be noted that the host computer 150 can be a terminal device such as a desktop computer, a laptop computer, a tablet computer, a mobile phone, an embedded device, etc., and this application does not make specific limitations on this. The temperature control box 100 can adopt the temperature control box 100 in the prior art, which can heat the test component and control the heating temperature.

[0056] It should be noted that the side wall of the temperature control box 100 is provided with a plurality of through holes for the connection wires to pass through.

[0057] In one embodiment, the first thermal insulation pad 120 is glued to the test circuit board 110 , and the shape of the through groove is cylindrical.

[0058] In one embodiment, referring to Figure 1 The test assembly further includes a second thermal insulation pad 140, which is disposed on a side of the heat sink 130 away from the first thermal insulation pad 120, and the heat sink 130 is located between the first thermal insulation pad 120 and the second thermal insulation pad 140. The second thermal insulation pad 140 is used to insulate the heat sink 130 to prevent the heat inside the temperature control box 100 from affecting the heat sink 130, so that the heat sink 130 can dissipate heat for the system-on-chip module 112.

[0059] In one embodiment, the test component also includes a thermal pad 190, which is disposed in the through slot, and one side of the thermal pad 190 is in contact with the heat sink 130, and the other side is in contact with the system-on-chip module 112. The thermal pad 190 is used to guide the heat of the system-on-chip module 112 to the heat sink 130, which helps to reduce the temperature in the through slot.

[0060] In one embodiment, the test assembly is provided with a first temperature sensor (not shown in the figure) and a second temperature sensor (not shown in the figure), the first temperature sensor and the second temperature sensor are installed on the test circuit board 110, and the first temperature sensor is located in the through groove; the second temperature sensor is arranged on one side of the connection seat 111. The temperature around the system-on-chip module 112 is detected by the first temperature sensor, and the temperature around the memory chip to be tested is detected by the second temperature sensor, so that the host computer 150 can control the heat sink 130 and the temperature control box 100 according to the temperature around the system-on-chip module 112 and the temperature around the memory chip, so that the ambient temperature around the memory chip reaches the preset test temperature, and the temperature around the system-on-chip module 112 is lower than the preset threshold temperature. Those skilled in the art can set the preset test temperature and the preset threshold temperature according to actual needs.

[0061] In one embodiment, referring to Figure 1 The test system also includes a heat dissipation component, which includes a water pump 180, an expansion valve 170 and a water tank 160. The water pump 180 and the water tank 160 are both arranged outside the temperature control box 100. The output end of the water pump 180 is connected to the input end of the radiator 130 through the expansion valve 170, the input end of the water pump 180 is connected to the water tank 160, and the output end of the radiator 130 is connected to the water tank 160; the host computer 150 is electrically connected to the water pump 180 and the expansion valve 170 respectively. When the system-on-chip module 112 needs to be cooled, the water in the water tank 160 is input to the radiator 130 through the expansion valve 170, and the water after passing through the radiator 130 enters the water tank 160 again, and the heat of the radiator 130 is taken away during the flow of water, so as to achieve the heat dissipation effect. In addition, the host computer 150 can adjust the heat dissipation effect by adjusting the opening of the expansion valve 170.

[0062] The second embodiment of the present application provides a memory chip testing method, which is applied to the host computer 150 in the test system of the first embodiment. Figure 2 , Figure 2 The following is a flow chart of the steps of the memory chip testing method according to the embodiment of the present application. The memory chip testing method according to the embodiment of the present application may include but is not limited to the following steps:

[0063] Step S310, obtaining the limit transmission rate and the limit ambient temperature range;

[0064] In one embodiment, the operating temperature range of the memory chip is -40°C to 95°C, and the extreme ambient temperature range is set to 90°C to 95°C. Specifically, the user can input the extreme transmission rate and the extreme ambient temperature range on the host computer 150 through a device such as a mouse, keyboard, or touch screen. The maximum data transmission rate of the memory chip is 4266MT / s, and 4266MT / s is used as the extreme transmission rate.

[0065] Step S320, based on the extreme ambient temperature range, the temperature control box is controlled to heat the test component; during the heating process, the water pump is started, and the first detection temperature in the through groove is obtained by the first temperature sensor, and the second detection temperature of the connecting seat is obtained by the second temperature sensor, and the expansion valve is controlled based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than the first preset temperature, and the second detection temperature is within the extreme ambient temperature range; wherein the first preset temperature is the upper limit value of the temperature range of normal operation of the system-on-chip module 112;

[0066] Step S330, when it is detected that the first detected temperature is lower than the first preset temperature and the second detected temperature is within the extreme ambient temperature range, a performance test is performed on the memory chip to be tested through a test circuit board based on the extreme transmission rate to obtain a test result.

[0067] In one embodiment, the operating environment of the system-on-chip module 112 is generally within a temperature range of 0° C. to 70° C., and the first preset temperature is set to 70° C. When the first preset temperature is the ambient temperature lower than 70° C., the system-on-chip module 112 can operate normally. Those skilled in the art can set the first preset temperature according to actual needs.

[0068] It is worth noting that the test method of the memory chip of the embodiment of the present application is to control the temperature control box 100 to heat through step S310 to step S330, and adjust the heat dissipation effect of the radiator 130 by adjusting the opening of the expansion valve 170. When the first detection temperature is lower than the first preset temperature, it indicates that the system-on-chip module 112 can operate normally. When the second detection temperature is within the extreme ambient temperature range, it means that the memory chip can be tested at the extreme transmission rate at this time. In this way, the memory chip is directly installed on the test circuit board 110 through the connection seat 111, without the need to be connected through a transmission line, so that the signal attenuation caused by the transmission line can be avoided, thereby ensuring the signal transmission rate between the test circuit board 110 and the memory chip, thereby ensuring the accuracy of the test results, and being able to test the extreme performance of the memory chip at a higher signal transmission rate.

[0069] In one embodiment, referring to Figure 3 , Figure 3 for Figure 2 A specific flow chart of step S320 in FIG. 1 is shown in FIG. 1 . Step S320 may include the following steps:

[0070] Step S410, adjusting the opening of the expansion valve to a preset opening;

[0071] Specifically, those skilled in the art may set the preset opening according to actual needs, for example, the preset opening may be set to 30%.

[0072] Step S420, periodically acquiring a first detected temperature through a first temperature sensor, and acquiring a second detected temperature through a second temperature sensor;

[0073] Step S430, calculating a first temperature difference between the first detected temperature and the first preset temperature;

[0074] Step S440, when it is detected that the first detected temperature is lower than the first preset temperature, the first temperature difference is lower than or equal to the first preset difference, and the second detected temperature is within the extreme ambient temperature range, the opening of the expansion valve is increased.

[0075] In the embodiment of the present application, through the above steps S410 to S440, when the second detected temperature is within the extreme ambient temperature range, it means that the performance test of the memory chip to be tested can be performed based on the extreme transmission rate, and the first detected temperature is lower than the first preset temperature, and the first temperature difference is lower than or equal to the first preset difference, which means that the temperature around the system-on-chip module 112 has gradually approached the first preset temperature. In order to prevent the temperature around the system-on-chip module 112 from reaching the first preset temperature, the opening of the expansion valve 170 is increased to improve the heat dissipation efficiency, so as to ensure that the temperature around the system-on-chip module 112 is lower than the first preset temperature.

[0076] It should be noted that those skilled in the art can set the first temperature difference according to actual needs.

[0077] In one embodiment, referring to Figure 4 , Figure 4 A schematic diagram of a sub-flow chart of the memory chip testing method according to an embodiment of the present application after step S420. The following steps are included after step S420:

[0078] Step S510, calculating a second temperature difference between the second detected temperature and the lower limit of the extreme ambient temperature range;

[0079] Step S520, when it is detected that the first detected temperature is lower than the first preset temperature, the first temperature difference is greater than the first preset difference, the second detected temperature is within the extreme ambient temperature range, and the second temperature difference is less than the second preset difference, reduce the opening of the expansion valve.

[0080] For example, when the extreme ambient temperature interval is 90°C to 95°C, 90°C is the lower limit of the extreme ambient temperature interval, and the difference between 90°C and the second detected temperature is calculated. When the second temperature difference is detected to be less than the second preset difference, it means that the heat dissipation efficiency of the radiator 130 is too high, which affects the temperature around the memory chip, causing the temperature around the memory chip to drop below the lower limit of the extreme ambient temperature interval. Therefore, at this time, the opening of the expansion valve 170 is reduced to reduce the heat dissipation efficiency of the radiator 130, so as to avoid the temperature around the memory chip from dropping below the lower limit of the extreme ambient temperature interval, so as to ensure that the memory chip can perform performance testing in a high temperature environment normally. Moreover, at this time, the first detected temperature is less than the first preset temperature, and the first temperature difference is greater than the first preset difference, indicating that the risk of the temperature around the system-on-chip module 112 reaching the first preset temperature is small, and even if the heat dissipation efficiency is reduced, the temperature around the system-on-chip module 112 will not reach the first preset temperature.

[0081] In this way, through steps S410 to S440, combined with steps S510 to S520, the opening of the expansion valve 170 is adjusted based on the first detection temperature and the second detection temperature, so as to adjust the heat dissipation efficiency of the radiator 130 to ensure that the first detection temperature is lower than the first preset temperature and the second detection temperature is within the extreme ambient temperature range, so as to facilitate performance testing of the memory chip in a high temperature environment.

[0082] The third aspect of the present application provides a memory chip test device, which is applied to the host computer 150 of the test system of the first aspect of the present application. Figure 5 , Figure 5The schematic diagram of the structure of the memory chip test device of the embodiment of the present application is as follows. The test device includes:

[0083] An acquisition module 510 is configured to acquire a limit transmission rate and a limit ambient temperature range;

[0084] The heating module 520 is configured to control the temperature control box 100 to heat the test component based on the extreme ambient temperature range; during the heating process, the water pump 180 is started, and the first detection temperature in the through groove is obtained through the first temperature sensor, and the second detection temperature of the connecting seat 111 is obtained through the second temperature sensor, and the expansion valve 170 is controlled based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than the first preset temperature, and the second detection temperature is within the extreme ambient temperature range; wherein the first preset temperature is the upper limit value of the temperature range of normal operation of the system-on-chip module 112;

[0085] The detection module 530 is configured to perform a performance test on the memory chip to be tested through the test circuit board 110 based on the extreme transmission rate to obtain a test result when it is detected that the first detection temperature is lower than the first preset temperature and the second detection temperature is within the extreme ambient temperature range.

[0086] Specifically, the memory chip testing device is used to execute the memory chip testing method of the second embodiment of the present application. When executing the memory chip testing method, the temperature control box 100 is controlled to heat, and the heat dissipation effect of the radiator 130 is adjusted by adjusting the opening of the expansion valve 170. When the first detection temperature is lower than the first preset temperature, it indicates that the system-on-chip module 112 can operate normally. When the second detection temperature is within the extreme ambient temperature range, it indicates that the memory chip can be tested at the extreme transmission rate. In this way, the memory chip is directly mounted on the test circuit board 110 through the connection seat 111, without the need to be connected through a transmission line, so that the signal attenuation caused by the transmission line can be avoided, thereby ensuring the signal transmission rate between the test circuit board 110 and the memory chip, thereby ensuring the accuracy of the test results, and being able to test the extreme performance of the memory chip at a higher signal transmission rate.

[0087] It should be noted that the specific implementation of the memory chip testing device is basically the same as the specific implementation of the memory chip testing method in the above-mentioned embodiment, and will not be repeated here. On the premise of meeting the requirements of the embodiments of the present application, the memory chip testing device can also be provided with other functional modules to implement the memory chip testing method in the above-mentioned embodiment.

[0088] The fourth aspect of the present application provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the memory chip test method of the above embodiment when executing the computer program. The electronic device can be any smart terminal including a tablet computer, a car computer, etc.

[0089] In one embodiment, referring to Figure 6 , Figure 6 The hardware structure of the electronic device of the embodiment of the present application is illustrated, and the electronic device includes:

[0090] The processor 601 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0091] The memory 602 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 602, and the processor 601 calls and executes the test method of the memory chip in the embodiment of this application;

[0092] Input / output interface 603, used to implement information input and output;

[0093] Communication interface 604, used to realize communication interaction between the device and other devices, which can be realized by wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);

[0094] Bus 605 , which transmits information between various components of the device (e.g., processor 601 , memory 602 , input / output interface 603 , and communication interface 604 );

[0095] The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0096] The fifth aspect of the present application is a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the memory chip testing method of the first aspect of the present application is implemented.

[0097] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0098] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0099] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0100] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0102] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0103] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0104] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0105] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0106] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0107] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0108] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A memory chip testing system, characterized in that: include: Temperature control box; A test assembly, the test assembly is installed inside the temperature control box, the test assembly includes a test circuit board, a first thermal insulation pad and a radiator, the first thermal insulation pad is provided with a through groove, the radiator is arranged on the test circuit board through the thermal insulation pad, a system-on-chip module is arranged on a side of the test circuit board opposite to the radiator, and the system-on-chip module is located in the through groove; a connection seat is arranged on a side of the test circuit board opposite to the radiator, the connection seat is used to install a memory chip to be tested, and the memory chip is electrically connected to the system-on-chip module through the test circuit board; A host computer, the host computer is located outside the temperature control box, the host computer is electrically connected to the temperature control box, and the host computer is electrically connected to the test circuit board through a connecting line; the host computer is used to send test instructions to the test circuit board and receive test data sent by the test circuit board; the temperature control box is used to heat the test component so that the ambient temperature of the memory chip reaches a preset test temperature.

2. The memory chip testing system according to claim 1, characterized in that: The test assembly further includes a second thermal insulation pad, which is disposed on a side of the heat sink away from the first thermal insulation pad, and the heat sink is located between the first thermal insulation pad and the second thermal insulation pad.

3. The memory chip testing system according to claim 1, characterized in that: The test assembly is provided with a first temperature sensor and a second temperature sensor. The first temperature sensor and the second temperature sensor are installed on the test circuit board, and the first temperature sensor is located in the through slot; the second temperature sensor is arranged on one side of the connecting seat.

4. The memory chip testing system according to claim 3, characterized in that: It also includes a heat dissipation component, which includes a water pump, an expansion valve and a water storage tank. The water pump and the water storage tank are both arranged outside the temperature control box. The output end of the water pump is connected to the input end of the radiator through the expansion valve, the input end of the water pump is connected to the water storage tank, and the output end of the radiator is connected to the water storage tank; the host computer is electrically connected to the water pump and the expansion valve respectively.

5. A method for testing a memory chip, characterized in that: A host computer used in the test system as claimed in claim 4; The method comprises: Obtain the limit transmission rate and limit ambient temperature range; Based on the extreme ambient temperature range, the temperature control box is controlled to heat the test component; during the heating process, the water pump is started, and the first detection temperature in the through groove is obtained through the first temperature sensor, and the second detection temperature of the connecting seat is obtained through the second temperature sensor, and the expansion valve is controlled based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than the first preset temperature, and the second detection temperature is within the extreme ambient temperature range; wherein the first preset temperature is the upper limit value of the temperature range of normal operation of the system-on-chip module; When it is detected that the first detected temperature is lower than the first preset temperature and the second detected temperature is within the extreme ambient temperature range, a performance test is performed on the memory chip to be tested based on the extreme transmission rate through the test circuit board to obtain a test result.

6. The memory chip testing method according to claim 5, characterized in that: The method of obtaining a first detected temperature in the through groove by the first temperature sensor, obtaining a second detected temperature of the connecting seat by the second temperature sensor, and controlling the expansion valve based on the first detected temperature and the second detected temperature so that the first detected temperature is lower than a first preset temperature and the second detected temperature is within the extreme ambient temperature range includes: Adjusting the opening of the expansion valve to a preset opening; periodically acquiring a first detected temperature through the first temperature sensor and acquiring a second detected temperature through the second temperature sensor; Calculating a first temperature difference between a first detected temperature and the first preset temperature; When it is detected that the first detected temperature is lower than the first preset temperature, the first temperature difference is lower than or equal to the first preset difference, and the second detected temperature is within the extreme ambient temperature range, the opening of the expansion valve is increased.

7. The memory chip testing method according to claim 6, characterized in that: After periodically acquiring the first detected temperature through the first temperature sensor and acquiring the second detected temperature through the second temperature sensor, the method further includes: Calculating a second temperature difference between the second detected temperature and a lower limit of the extreme ambient temperature interval; When it is detected that the first detected temperature is lower than the first preset temperature, the first temperature difference is greater than the first preset difference, the second detected temperature is within the extreme ambient temperature range, and the second temperature difference is less than the second preset difference, the opening of the expansion valve is reduced.

8. A memory chip testing device, characterized in that: A host computer used in the test system as claimed in claim 4; The device comprises: An acquisition module is configured to acquire a limit transmission rate and a limit ambient temperature range; The heating module is configured to control the temperature control box to heat the test component based on the extreme ambient temperature range; during the heating process, the water pump is started, and the first detection temperature in the through groove is obtained through the first temperature sensor, and the second detection temperature of the connecting seat is obtained through the second temperature sensor, and the expansion valve is controlled based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than the first preset temperature and the second detection temperature is within the extreme ambient temperature range; wherein the first preset temperature is the upper limit value of the temperature range of the normal operation of the system-on-chip module; The detection module is configured to perform a performance test on the memory chip to be tested based on the limit transmission rate through the test circuit board to obtain a test result when it is detected that the first detection temperature is lower than the first preset temperature and the second detection temperature is within the extreme ambient temperature range.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the memory chip testing method according to any one of claims 5 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the memory chip testing method according to any one of claims 5 to 7 is implemented.

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