Memory chip testing system, method, device, electronic equipment and medium

Abstract

The application discloses a memory chip testing system, method, device, electronic equipment and medium, and particularly relates to the field of electronic chip testing. The temperature control box is used for heating the testing assembly, so that the ambient temperature of the memory chip reaches the preset testing temperature, and the heat sink is used for dissipating heat for the system-on-chip module, reducing the temperature of the system-on-chip module, and avoiding the situation that the system-on-chip module cannot run due to the excessively high temperature. Since the memory chip is directly installed on the testing circuit board through the connecting seat and does not need to be connected through a transmission line, signal attenuation caused by the transmission line can be avoided, the signal transmission rate between the testing circuit board and the memory chip is ensured, the accuracy of the testing result is ensured, and the limit performance of the memory chip can be tested at a high signal transmission rate.

Description

Technical Field

[0001] This application relates to the field of electronic chip testing, and in particular to a testing system, method, apparatus, electronic device, and medium for memory chips. Background Technology

[0002] During the manufacturing process of memory chips, testing is required. To test the performance of memory chips under extreme conditions, they need to be tested at high signal transmission rates and in high-temperature environments. Current memory chip testing equipment typically uses test circuit boards. Since the on-chip modules on the test circuit board cannot withstand high temperatures, the test circuit board is usually placed outside a temperature-controlled chamber, while the memory chip is placed inside. The test circuit board and the memory chip are electrically connected via a transmission line of a certain length. Due to the limitations of the transmission line, the signal transmission rate between the test circuit board and the memory chip is reduced, thus decreasing the accuracy of the test results. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a testing system, method, apparatus, electronic device, and medium for memory chips. No transmission line is required between the test circuit board and the memory chip, thus ensuring the signal transmission rate between the test circuit board and the memory chip, thereby guaranteeing the accuracy of the test results.

[0004] A test system for a memory chip according to a first aspect embodiment of this application includes:

[0005] Temperature control box;

[0006] The test assembly is installed inside the temperature control chamber. The test assembly includes a test circuit board, a first heat insulation pad, and a heat sink. The first heat insulation pad has a through groove. The heat sink is mounted on the test circuit board via the heat insulation pad. A system-on-a-chip (SoC) module is located on the side of the test circuit board opposite to the heat sink, and the SoC module is situated within the through groove. A connector is located on the side of the test circuit board opposite to the heat sink. The connector is used to mount a memory chip to be tested, and the memory chip is electrically connected to the SoC module via the test circuit board.

[0007] The host computer is located outside the temperature control chamber and is electrically connected to the temperature control chamber. The host computer is also electrically connected to the test circuit board via a connecting cable. The host computer is used to send test commands to the test circuit board and receive test data sent by the test circuit board. The temperature control chamber is used to heat the test components so that the ambient temperature of the memory chip reaches the preset test temperature.

[0008] The memory chip testing system according to embodiments of this application has at least the following beneficial effects: The testing system includes a temperature control chamber, a testing component, and a host computer. The testing component includes a test circuit board, a first heat insulation pad, and a heat sink. The first heat insulation pad has a through slot. The heat sink is mounted on the test circuit board via the heat insulation pad. A system-on-a-chip (SoC) module is located on the side of the test circuit board opposite to the heat sink, and the SoC module is located within the through slot. A connector is provided on the side of the test circuit board opposite to the heat sink. The connector is used to mount the memory chip to be tested, and the memory chip is electrically connected to the SoC module via the test circuit board. The host computer is used to send test commands to the test circuit board and receive test data sent by the test circuit board to obtain test results. The temperature control chamber is used to heat the testing component to bring the ambient temperature of the memory chip to a preset test temperature, while the heat sink is used to dissipate heat from the SoC module, reducing its temperature and preventing it from malfunctioning due to excessive temperature. Since the memory chip is directly mounted on the test circuit board via a connector, without the need for a transmission line, signal attenuation caused by the transmission line can be avoided, thus ensuring the signal transmission rate between the test circuit board and the memory chip, thereby ensuring the accuracy of the test results, and enabling the testing of the memory chip's extreme performance at a high signal transmission rate.

[0009] According to some embodiments of the first aspect of this application, the test assembly further includes a second heat insulation pad disposed on the side of the heat sink away from the first heat insulation pad, and the heat sink is located between the first heat insulation pad and the second heat insulation pad.

[0010] According to some embodiments of the first aspect of this application, the test assembly is provided with a first temperature sensor and a second temperature sensor, the first temperature sensor and the second temperature sensor are mounted on the test circuit board, and the first temperature sensor is located in the through slot; the second temperature sensor is located on one side of the connector.

[0011] According to some embodiments of the first aspect of this application, a heat dissipation assembly is also included, which includes a water pump, an expansion valve, and a water storage tank. The water pump and the water storage tank are both located outside the temperature control box. The output end of the water pump is connected to the input end of the radiator through the expansion valve. The input end of the water pump is connected to the water storage tank, and the output end of the radiator is connected to the water storage tank. The host computer is electrically connected to the water pump and the expansion valve respectively.

[0012] A second aspect of this application provides a method for testing a memory chip, applied in the host computer of the testing system of the first aspect embodiment. The method includes:

[0013] Obtain the maximum transmission rate and the maximum ambient temperature range;

[0014] The temperature control chamber is used to heat the test component based on the extreme ambient temperature range. During the heating process, the water pump is started, and the first temperature in the channel is obtained through the first temperature sensor, and the second temperature of the connector is obtained through the second temperature sensor. The expansion valve is controlled based on the first and second temperature to ensure that the first temperature is lower than the first preset temperature and the second temperature is within the extreme ambient temperature range. The first preset temperature is the upper limit of the normal operating temperature range of the system-on-a-chip module.

[0015] If the first detection temperature is lower than the first preset temperature and the second detection temperature is within the extreme ambient temperature range, the memory chip under test is subjected to performance testing through the test circuit board based on the extreme transmission rate, and the test results are obtained.

[0016] According to some embodiments of the second aspect of this application, the step of obtaining a first detected temperature in the channel through the first temperature sensor, obtaining a second detected temperature of the connector through the second temperature sensor, and controlling the expansion valve based on the first and second detected temperatures to make the first detected temperature lower than a first preset temperature and the second detected temperature within the extreme ambient temperature range includes:

[0017] Adjust the opening degree of the expansion valve to the preset opening degree;

[0018] A first detection temperature is periodically obtained through the first temperature sensor, and a second detection temperature is obtained through the second temperature sensor;

[0019] Calculate the first temperature difference between the first detection temperature and the first preset temperature;

[0020] When the first detected temperature is lower than the first preset temperature, and the first temperature difference is less than or equal to the first preset difference, and the second detected temperature is within the extreme ambient temperature range, the opening degree of the expansion valve is increased.

[0021] According to some embodiments of the second aspect of this application, after periodically acquiring a first detection temperature through the first temperature sensor and acquiring a second detection temperature through the second temperature sensor, the method further includes:

[0022] Calculate the second temperature difference between the second detection temperature and the lower limit of the extreme ambient temperature range;

[0023] If the first detected temperature is lower than the first preset temperature and the first temperature difference is greater than the first preset difference, and the second detected temperature is within the extreme ambient temperature range and the second temperature difference is less than the second preset difference, the opening degree of the expansion valve is reduced.

[0024] A third aspect of this application provides a testing apparatus for a memory chip, which is applied to the host computer of the testing system of the first aspect embodiment. The apparatus includes:

[0025] The acquisition module is configured to acquire the extreme transmission rate and extreme ambient temperature range;

[0026] The heating module is configured to control the temperature control chamber to heat the test components based on the extreme ambient temperature range. During the heating process, a water pump is started, and a first detection temperature in the through slot is obtained through a first temperature sensor, and a second detection temperature of the connector is obtained through a second temperature sensor. An expansion valve is controlled based on the first and second detection temperatures to ensure that the first detection temperature is lower than a first preset temperature and the second detection temperature is within the extreme ambient temperature range. The first preset temperature is the upper limit of the normal operating temperature range of the on-chip system module.

[0027] The detection module is configured to perform performance testing on the memory chip under test through a test circuit board based on the extreme transmission rate when the first detection temperature is lower than the first preset temperature and the second detection temperature is within the extreme ambient temperature range, and to obtain the test results.

[0028] A fourth aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the testing method for the memory chip described in any of the second aspects of the embodiment.

[0029] A fifth aspect of this application provides a computer-readable storage medium storing a computer program, characterized in that, when executed by a processor, the computer program implements the testing method for the memory chip described in any one of the second aspects of the embodiment.

[0030] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0031] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0032] Figure 1 This is a simplified structural diagram of a test system for a memory chip according to an embodiment of this application;

[0033] Figure 2 This is a flowchart illustrating the steps of a testing method for a memory chip according to an embodiment of this application.

[0034] Figure 3 for Figure 2 A detailed flowchart of step S320;

[0035] Figure 4 This is a schematic diagram of a sub-process of the memory chip testing method according to an embodiment of this application, following step S420.

[0036] Figure 5 This is a schematic diagram of the structure of a testing apparatus for a memory chip according to an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application.

[0038] Figure label:

[0039] Temperature control box 100; test circuit board 110; connector 111; on-chip system module 112; first heat insulation pad 120; heat sink 130; second heat insulation pad 140; host computer 150; water storage tank 160; expansion valve 170; water pump 180; thermal conductive pad 190. Detailed Implementation

[0040] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0041] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0042] In the description of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0043] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0044] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0045] Because the system-on-a-chip module 112 on the test circuit board cannot withstand high temperatures, the test circuit board is usually placed outside the temperature-controlled chamber, while the memory chip is placed inside. The test circuit board and the memory chip are electrically connected via a transmission line of a certain length. Due to the limitations of the transmission line, the signal transmission rate between the test circuit board and the memory chip is reduced, thus decreasing the accuracy of the test results. Moreover, due to the limitations of the transmission line, it is impossible to test the memory chip at a high signal transmission rate, i.e., it is impossible to perform extreme performance tests on the memory chip.

[0046] Based on this, embodiments of this application provide a testing system, method, apparatus, electronic device, and medium for memory chips. No transmission line is required between the test circuit board and the memory chip, thus ensuring the signal transmission rate between the test circuit board and the memory chip, thereby guaranteeing the accuracy of the test results. Furthermore, it enables testing the extreme performance of the memory chip at a high signal transmission rate.

[0047] The first aspect of this application provides a testing system for a memory chip. (Refer to...) Figure 1 , Figure 1 This is a simplified structural diagram of a memory chip testing system according to an embodiment of this application. The memory chip testing system includes:

[0048] Temperature control box 100;

[0049] The test assembly is installed inside the temperature control chamber 100. The test assembly includes a test circuit board 110, a first heat insulation pad 120, and a heat sink 130. The first heat insulation pad 120 has a through groove. The heat sink 130 is mounted on the test circuit board 110 through a heat insulation pad. On the side of the test circuit board 110 opposite to the heat sink 130, there is a system-on-a-chip module 112, and the system-on-a-chip module 112 is located in the through groove. On the side of the test circuit board 110 opposite to the heat sink 130, there is a connector 111. The connector 111 is used to mount the memory chip to be tested, and the memory chip is electrically connected to the system-on-a-chip module 112 through the test circuit board 110.

[0050] The host computer 150 is located outside the temperature control chamber 100 and is electrically connected to the temperature control chamber 100. The host computer 150 is also electrically connected to the test circuit board 110 via a connecting cable. The host computer 150 is used to send test commands to the test circuit board 110 and to receive test data sent by the test circuit board 110. The temperature control chamber 100 is used to heat the test components so that the ambient temperature of the memory chip reaches the preset test temperature.

[0051] The memory chip testing system according to the embodiments of this application has at least the following beneficial effects: The host computer 150 is used to send test commands to the test circuit board 110 and receive test data sent by the test circuit board 110 to obtain test results. The temperature control chamber 100 is used to heat the test components to bring the ambient temperature of the memory chip to a preset test temperature, while the heat sink 130 is used to dissipate heat from the system-on-a-chip module 112, reducing the temperature of the system-on-a-chip module 112 and preventing it from failing to operate due to excessive temperature. Since the memory chip is directly mounted on the test circuit board 110 via the connector 111 without the need for a transmission line, signal attenuation caused by the transmission line can be avoided, thus ensuring the signal transmission rate between the test circuit board 110 and the memory chip, thereby ensuring the accuracy of the test results, and enabling testing of the memory chip's extreme performance at a higher signal transmission rate.

[0052] It's important to note that the memory chip is an LPDDR (Low Power Double Data Rate) chip. LPDDR is a memory technology specifically designed for low-power devices, a branch of DDR SDRAM, and its standard is set by the JEDEC Solid State Technology Association. LPDDR chips are known for their low power consumption and high performance, and are mainly used in power- and size-sensitive applications such as mobile devices, tablets, and thin and light laptops. The operating temperature range of ordinary LPDDR chips is -40℃ to 95℃, while some industrial-grade LPDDR chips operate within this range of -40℃ to 105℃. Therefore, during LPDDR chip manufacturing, performance testing is typically performed at the upper limit of the operating temperature range.

[0053] It should be noted that the System-on-Chip (SoC) module 112 refers to a System-on-Chip or SoC, a highly integrated integrated circuit technology that integrates all the components required for a complete electronic system onto a single chip. These components include a processor core, memory, input / output interfaces, communication modules, power management units, etc. The design goals of an SoC are to achieve high performance, low power consumption, small size, and high reliability. Generally, the operating temperature range of a typical SoC module 112 is 0°C to 70°C. If the SoC module 112 is exposed to a high-temperature environment for a long period, it is prone to damage. This application uses a first thermal insulation pad 120 for heat insulation and a heat sink 130 for heat dissipation, which can reduce the temperature around the SoC module 112, thereby ensuring the normal operation of the SoC module 112 and guaranteeing its lifespan.

[0054] It should be noted that the memory chip is mounted on the test circuit board 110 via connector 111, and is electrically connected to the test circuit board 110 via connector 111. Compared with a transmission line, the test circuit board 110 can send test commands to the memory chip at a higher data transmission rate via connector 111.

[0055] It should be noted that the host computer 150 can be a desktop computer, laptop computer, tablet computer, mobile phone, embedded device, or other terminal device; this application does not make any specific limitations on it. The temperature control chamber 100 can be any existing temperature control chamber 100, as long as it can heat the test components and control the heating temperature.

[0056] It should be noted that the side wall of the temperature control box 100 has multiple perforations for connecting wires to pass through.

[0057] In one embodiment, the first heat insulation pad 120 is glued to the test circuit board 110, and the through groove is cylindrical in shape.

[0058] In one embodiment, reference is made to Figure 1 The test assembly also includes a second heat insulation pad 140, which is disposed on the side of the heat sink 130 away from the first heat insulation pad 120. The heat sink 130 is located between the first heat insulation pad 120 and the second heat insulation pad 140. The second heat insulation pad 140 is used to insulate the heat sink 130, preventing the heat inside the temperature control box 100 from affecting the heat sink 130, so that the heat sink 130 can dissipate heat from the system-on-a-chip module 112.

[0059] In one embodiment, the test assembly further includes a thermal pad 190 disposed in the through slot, with one side of the thermal pad 190 contacting the heat sink 130 and the other side contacting the system-on-a-chip module 112. The thermal pad 190 is used to guide the heat of the system-on-a-chip module 112 to the heat sink 130, which helps to reduce the temperature in the through slot.

[0060] In one embodiment, the test assembly includes a first temperature sensor (not shown) and a second temperature sensor (not shown). The first and second temperature sensors are mounted on a test circuit board 110, with the first temperature sensor located within a through slot; the second temperature sensor is located on one side of the connector 111. The first temperature sensor detects the temperature around the system-on-chip module 112, and the second temperature sensor detects the temperature around the memory chip under test. This allows the host computer 150 to control the heat sink 130 and the temperature control chamber 100 based on the temperatures around the system-on-chip module 112 and the memory chip, ensuring that the ambient temperature around the memory chip reaches a preset test temperature and that the temperature around the system-on-chip module 112 is below a preset threshold temperature. Those skilled in the art can set the preset test temperature and preset threshold temperature according to actual needs.

[0061] In one embodiment, reference is made to Figure 1 The testing system also includes a heat dissipation assembly, which comprises a water pump 180, an expansion valve 170, and a water storage tank 160. Both the water pump 180 and the water storage tank 160 are located outside the temperature control box 100. The output of the water pump 180 is connected to the input of the radiator 130 via the expansion valve 170, and the input of the water pump 180 is connected to the water storage tank 160. The output of the radiator 130 is connected to the water storage tank 160. The host computer 150 is electrically connected to both the water pump 180 and the expansion valve 170. When heat dissipation is required for the on-chip system module 112, the water pump 180 is started. Water from the storage tank 160 is input to the radiator 130 through the expansion valve 170. After passing through the radiator 130, the water returns to the storage tank 160. During the water flow, the heat from the radiator 130 is carried away, thus achieving the heat dissipation effect. Furthermore, the host computer 150 can adjust the heat dissipation effect by adjusting the opening of the expansion valve 170.

[0062] A second aspect of this application provides a method for testing a memory chip, applied to the host computer 150 in the testing system of the first aspect embodiment. (Refer to...) Figure 2 , Figure 2 This is a schematic flowchart illustrating the steps of a testing method for a memory chip according to an embodiment of this application. The testing method for a memory chip according to an embodiment of this application may include, but is not limited to, the following steps:

[0063] Step S310: Obtain the maximum transmission rate and the maximum ambient temperature range;

[0064] In one embodiment, the operating temperature range of the memory chip is -40°C to 95°C, so the extreme ambient temperature range is set to 90°C to 95°C. Specifically, the user can input the extreme transmission rate and extreme ambient temperature range on the host computer 150 using a mouse, keyboard, or touchscreen. Since the memory chip's maximum data transmission rate is 4266MT / s, 4266MT / s is used as the extreme transmission rate.

[0065] Step S320: The temperature control chamber is used to heat the test component based on the extreme ambient temperature range. During the heating process, the water pump is started, and the first detection temperature in the channel is obtained through the first temperature sensor, and the second detection temperature of the connector is obtained through the second temperature sensor. The expansion valve is controlled based on the first detection temperature and the second detection temperature to make the first detection temperature lower than the first preset temperature and the second detection temperature within the extreme ambient temperature range. The first preset temperature is the upper limit of the normal operating temperature range of the on-chip system module 112.

[0066] In step S330, when the first detection temperature is lower than the first preset temperature and the second detection temperature is within the extreme ambient temperature range, the performance of the memory chip under test is performed on the test circuit board based on the extreme transmission rate, and the test results are obtained.

[0067] In one embodiment, the operating environment of the system-on-a-chip module 112 is typically within a temperature range of 0°C to 70°C. Therefore, a first preset temperature is set to 70°C. When the ambient temperature is below 70°C, the system-on-a-chip module 112 can operate normally. Those skilled in the art can set the first preset temperature according to actual needs.

[0068] It is worth noting that the memory chip testing method in this embodiment of the application, through steps S310 to S330, involves controlling the temperature control chamber 100 to heat the chip and adjusting the opening of the expansion valve 170 to adjust the heat dissipation effect of the heat sink 130. When the first detection temperature is lower than the first preset temperature, it indicates that the on-chip system module 112 can operate normally. When the second detection temperature is within the extreme ambient temperature range, it indicates that the memory chip can be tested at its maximum transmission rate. Thus, the memory chip is directly mounted on the test circuit board 110 via the connector 111, without the need for a transmission line. This avoids signal attenuation caused by transmission lines, ensuring the signal transmission rate between the test circuit board 110 and the memory chip, thereby guaranteeing the accuracy of the test results and enabling the testing of the memory chip's extreme performance at a high signal transmission rate.

[0069] In one embodiment, reference is made to Figure 3 , Figure 3 for Figure 2 A detailed flowchart of step S320 is provided. Step S320 may include the following steps:

[0070] Step S410: Adjust the opening of the expansion valve to the preset opening.

[0071] Specifically, those skilled in the art can set a preset opening degree according to actual needs, for example, the preset opening degree can be set to 30%.

[0072] Step S420: Periodically obtain a first detection temperature through a first temperature sensor and a second detection temperature through a second temperature sensor;

[0073] Step S430: Calculate the first temperature difference between the first detection temperature and the first preset temperature;

[0074] Step S440: When the first detection temperature is lower than the first preset temperature, the first temperature difference is less than or equal to the first preset difference, and the second detection temperature is within the extreme ambient temperature range, the opening degree of the expansion valve is increased.

[0075] In this embodiment of the application, through the above steps S410 to S440, when the second detected temperature is within the extreme ambient temperature range, it means that the performance test of the memory chip to be tested can be performed based on the extreme transmission rate. When the first detected temperature is less than the first preset temperature and the first temperature difference is less than or equal to the first preset difference, it means that the temperature around the on-chip system module 112 has gradually approached the first preset temperature. In order to prevent the temperature around the on-chip system module 112 from reaching the first preset temperature, the opening of the expansion valve 170 is increased to improve the heat dissipation efficiency, so as to ensure that the temperature around the on-chip system module 112 is less than the first preset temperature.

[0076] It should be noted that those skilled in the art can set the first temperature difference value according to actual needs.

[0077] In one embodiment, reference is made to Figure 4 , Figure 4 This is a schematic diagram of a sub-process of the memory chip testing method according to an embodiment of this application, following step S420. The steps following step S420 are as follows:

[0078] Step S510: Calculate the second temperature difference between the second detection temperature and the lower limit of the extreme ambient temperature range;

[0079] Step S520: When the first detected temperature is lower than the first preset temperature and the first temperature difference is greater than the first preset difference, and the second detected temperature is within the extreme ambient temperature range and the second temperature difference is less than the second preset difference, the opening degree of the expansion valve is reduced.

[0080] For example, if the extreme ambient temperature range is 90℃ to 95℃, then 90℃ is the lower limit of the extreme ambient temperature range. The difference between 90℃ and the second detected temperature is calculated. If the second temperature difference is less than the second preset difference, it indicates that the heat dissipation efficiency of the heat sink 130 is too high, affecting the temperature around the memory chip and potentially causing the temperature around the memory chip to drop below the lower limit of the extreme ambient temperature range. Therefore, the opening of the expansion valve 170 is reduced to decrease the heat dissipation efficiency of the heat sink 130, preventing the temperature around the memory chip from dropping below the lower limit of the extreme ambient temperature range, thus ensuring that the memory chip can perform normal performance testing under high-temperature conditions. Furthermore, if the first detected temperature is less than the first preset temperature and the first temperature difference is greater than the first preset difference, it indicates that the risk of the temperature around the on-chip system module 112 reaching the first preset temperature is low. Even with reduced heat dissipation efficiency, the temperature around the on-chip system module 112 will not reach the first preset temperature.

[0081] Thus, through steps S410 to S440, combined with steps S510 to S520, the opening of the expansion valve 170 is adjusted based on the first and second detected temperatures, thereby adjusting the heat dissipation efficiency of the heat sink 130 to ensure that the first detected temperature is lower than the first preset temperature and the second detected temperature is within the extreme ambient temperature range, which facilitates performance testing of the memory chip in a high-temperature environment.

[0082] A third aspect of this application provides a testing apparatus for memory chips, applied to a host computer 150 of the testing system of the first aspect of this application. (Refer to...) Figure 5 , Figure 5This is a schematic diagram of the structure of a testing apparatus for a memory chip according to an embodiment of this application. The testing apparatus includes:

[0083] The acquisition module 510 is configured to acquire the extreme transmission rate and the extreme ambient temperature range;

[0084] Heating module 520 is configured to control the temperature control chamber 100 to heat the test component based on the extreme ambient temperature range. During the heating process, water pump 180 is started, and a first detection temperature in the channel is obtained through a first temperature sensor, and a second detection temperature of the connector 111 is obtained through a second temperature sensor. Based on the first and second detection temperatures, expansion valve 170 is controlled to ensure that the first detection temperature is lower than a first preset temperature and the second detection temperature is within the extreme ambient temperature range. The first preset temperature is the upper limit of the normal operating temperature range of on-chip system module 112.

[0085] The detection module 530 is configured to perform performance testing on the memory chip under test through the test circuit board 110 based on the extreme transmission rate when the first detection temperature is lower than the first preset temperature and the second detection temperature is within the extreme ambient temperature range, and obtain the test results.

[0086] Specifically, the memory chip testing apparatus is used to execute the memory chip testing method of the second aspect embodiment of this application. When executing the memory chip testing method, the temperature control chamber 100 is heated, and the heat dissipation effect of the heat sink 130 is adjusted by adjusting the opening of the expansion valve 170. When the first detection temperature is lower than the first preset temperature, it indicates that the on-chip system module 112 can operate normally. When the second detection temperature is within the extreme ambient temperature range, it indicates that the memory chip can be tested at its maximum transmission rate. Thus, the memory chip is directly mounted on the test circuit board 110 via the connector 111, without the need for a transmission line. This avoids signal attenuation caused by transmission lines, ensuring the signal transmission rate between the test circuit board 110 and the memory chip, thereby ensuring the accuracy of the test results and enabling testing of the memory chip's extreme performance at a high signal transmission rate.

[0087] It should be noted that the specific implementation of the memory chip testing device is basically the same as the specific implementation of the memory chip testing method in the above embodiments, and will not be repeated here. Under the premise of meeting the requirements of the embodiments of this application, the memory chip testing device may also be equipped with other functional modules to realize the memory chip testing method in the above embodiments.

[0088] A fourth aspect of this application provides an electronic device including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the testing method for the memory chip described in the above embodiment. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0089] In one embodiment, reference is made to Figure 6 , Figure 6 The hardware structure of an electronic device according to an embodiment of this application is illustrated. The electronic device includes:

[0090] The processor 601 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0091] The memory 602 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 602 and is called and executed by the processor 601 to execute the test method of the memory chip in the embodiments of this application.

[0092] The input / output interface 603 is used to implement information input and output;

[0093] The communication interface 604 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0094] Bus 605 transmits information between various components of the device (e.g., processor 601, memory 602, input / output interface 603, and communication interface 604);

[0095] The processor 601, memory 602, input / output interface 603, and communication interface 604 are connected to each other within the device via bus 605.

[0096] According to a fifth aspect of this application, a computer-readable storage medium stores a computer program that, when executed by a processor, implements the testing method for a memory chip according to a first aspect embodiment.

[0097] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0098] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0099] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0100] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0102] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0103] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0104] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0105] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0107] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0108] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method of testing a memory chip, characterized by, The application is applied to a host computer of a test system, the test system further comprises a temperature control box, a test assembly and a heat dissipation assembly, the test assembly is installed in the temperature control box, the test assembly comprises a test circuit board, a first heat insulation pad and a heat sink, the first heat insulation pad is provided with a through slot, the heat sink is arranged on the test circuit board through the first heat insulation pad, one side of the test circuit board opposite to the heat sink is provided with a system on chip module, and the system on chip module is located in the through slot; one side of the test circuit board opposite to the heat sink is provided with a connecting seat, the connecting seat is used for mounting a memory chip to be tested, and the memory chip is electrically connected with the test circuit board and the system on chip module; the host computer is located outside the temperature control box, the host computer is electrically connected with the temperature control box, and the host computer is electrically connected with the test circuit board through a connecting line; the host computer is used for sending a test instruction to the test circuit board and receiving test data sent by the test circuit board; the temperature control box is used for heating the test assembly to make the ambient temperature of the memory chip reach a preset test temperature; the test assembly is provided with a first temperature sensor and a second temperature sensor, the first temperature sensor and the second temperature sensor are installed on the test circuit board, and the first temperature sensor is located in the through slot; the second temperature sensor is arranged on one side of the connecting seat; the heat dissipation assembly comprises a water pump, an expansion valve and a water storage tank, the water pump and the water storage tank are arranged outside the temperature control box, the output end of the water pump is communicated with the input end of the heat sink through the expansion valve, the input end of the water pump is communicated with the water storage tank, and the output end of the heat sink is communicated with the water storage tank; the host computer is electrically connected with the water pump and the expansion valve respectively; the method comprises: obtaining a limit transmission rate and a limit ambient temperature interval; controlling the temperature control box to heat the test assembly based on the limit ambient temperature interval; during the heating process, starting the water pump, obtaining a first detection temperature in the through slot through the first temperature sensor, obtaining a second detection temperature of the connecting seat through the second temperature sensor, and controlling the expansion valve based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than a first preset temperature, and the second detection temperature is within the limit ambient temperature interval; wherein the first preset temperature is an upper limit value of a temperature range in which the system on chip module normally works; based on the limit transmission rate, performing performance test on the memory chip to be tested through the test circuit board to obtain a test result, when the first detection temperature is lower than the first preset temperature and the second detection temperature is within the limit ambient temperature interval.

2. The method of testing memory chips according to claim 1, wherein, The first detection temperature in the through groove is acquired by the first temperature sensor, the second detection temperature of the connecting seat is acquired by the second temperature sensor, and the expansion valve is controlled based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than the first preset temperature, and the second detection temperature is in the extreme environment temperature range, comprising: The opening of the expansion valve is adjusted to a preset opening; The first detection temperature is periodically acquired by the first temperature sensor, and the second detection temperature is acquired by the second temperature sensor; The first temperature difference between the first detection temperature and the first preset temperature is calculated; In the case that the first detection temperature is less than the first preset temperature, the first temperature difference is less than or equal to the first preset difference, and the second detection temperature is in the extreme environment temperature range, the opening of the expansion valve is increased.

3. The method of testing memory chips according to claim 2, wherein, After the first detection temperature is periodically acquired by the first temperature sensor, and the second detection temperature is acquired by the second temperature sensor, further comprising: The second temperature difference between the second detection temperature and the lower limit value of the extreme environment temperature range is calculated; In the case that the first detection temperature is less than the first preset temperature, the first temperature difference is greater than the first preset difference, the second detection temperature is in the extreme environment temperature range, and the second temperature difference is less than the second preset difference, the opening of the expansion valve is reduced.

4. An apparatus for testing a memory chip, characterized by An upper computer applied to a test system; the test system further comprises a temperature control box, a test assembly and a heat dissipation assembly, the test assembly is installed inside the temperature control box, the test assembly comprises a test circuit board, a first heat insulation pad and a heat sink, the first heat insulation pad is provided with a through groove, the heat sink is provided on the test circuit board through the first heat insulation pad, one side of the test circuit board opposite to the heat sink is provided with a system on chip module, and the system on chip module is located in the through groove; one side of the test circuit board opposite to the heat sink is provided with a connecting seat, the connecting seat is used for mounting a memory chip to be tested, and the memory chip is electrically connected with the test circuit board and the system on chip module; The upper computer is located outside the temperature control box, the upper computer is electrically connected with the temperature control box, and the upper computer is electrically connected with the test circuit board through a connecting line; the upper computer is used for sending test instructions to the test circuit board and receiving test data sent by the test circuit board; the temperature control box is used for heating the test assembly, so that the environment temperature of the memory chip reaches a preset test temperature; The test assembly is provided with a first temperature sensor and a second temperature sensor, the first temperature sensor and the second temperature sensor are installed on the test circuit board, and the first temperature sensor is located in the through groove; the second temperature sensor is arranged on one side of the connecting seat; The heat dissipation assembly comprises a water pump, an expansion valve and a water storage tank, the water pump and the water storage tank are arranged outside the temperature control box, an output end of the water pump is communicated with an input end of the radiator through the expansion valve, an input end of the water pump is communicated with the water storage tank, and an output end of the radiator is communicated with the water storage tank; The upper computer is electrically connected with the water pump and the expansion valve respectively; The device comprises: An acquisition module configured to acquire a limit transmission rate and a limit environmental temperature interval; A heating module configured to control the temperature control box to heat the test assembly based on the limit environmental temperature interval; during the heating process, the water pump is started, a first detection temperature in the through slot is acquired through the first temperature sensor, a second detection temperature of the connecting seat is acquired through the second temperature sensor, the expansion valve is controlled based on the first detection temperature and the second detection temperature, so that the first detection temperature is lower than a first preset temperature, and the second detection temperature is within the limit environmental temperature interval; wherein the first preset temperature is an upper limit value of a temperature range in which the system on chip module normally works; A detection module configured to, when the first detection temperature is lower than the first preset temperature and the second detection temperature is within the limit environmental temperature interval, perform performance testing on the memory chip to be tested through the test circuit board based on the limit transmission rate, and obtain a test result.

5. An electronic device, comprising: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the memory chip testing method of any one of claims 1 to 3 when executing the computer program.

6. A computer readable storage medium, the storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the memory chip testing method of any one of claims 1 to 3.

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