Structure and method for providing connections across channels

Abstract

The disclosure relates to structures and methods to provide connections across channels. The present disclosure provides novel tools and techniques for implementing semiconductor or chip packages, and more particularly, methods, systems, and apparatus for implementing semiconductor or chip packages including one or more channel vias. In various embodiments, an apparatus includes a first layer including a channel and a first via extending through the first layer to a first surface of a first ridge of the first channel. The apparatus may further include a second layer coupled to the first layer. The second layer may be a first outer layer of the first substrate. The apparatus may also include a first line coupled to the first via and extending along the first ridge of the first channel and embedded in the second layer.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 63 / 606,657 filed on December 6, 2023 by Jeremy Theil, entitled “Structure for reducing pressure drop requirements in a fluid filled heatsink and enabling electrical connections” (“the '657 application”), the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0003] Copyright Notice

[0004] A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0005] The present disclosure generally relates to methods, systems, and apparatus for implementing a semiconductor device including a channel and one or more vias. Background Art

[0006] When dealing with semiconductor devices that have channels, cavities, or apertures therein, there are some limitations on the routing of traces or vias due to the presence of engineered channels, cavities, or apertures within the semiconductor device. Examples of situations where the semiconductor device includes channels, cavities, or apertures include: the semiconductor device includes one or more cold plates (e.g., fluid cold plates, heat sinks, etc.) that need to be crossed to pass signals (e.g., electrical signals, etc.) or one or more vacuum cavities for sensors and transducers.

[0007] Through substrate vias (TSVs) are commonly used to pass signals through a semiconductor device from or to one or more layers or dies. However, the number, amount, or density of TSVs may be limited in a semiconductor device or in one or more regions of a semiconductor device where one or more channels, cavities, or voids are formed.

[0008] Therefore, there is a need for a more robust and scalable solution for implementing semiconductor packages and chip packages having a channel.Accordingly, methods, systems and apparatus are provided for implementing a semiconductor package or chip package including one or more lines extending across a ridge of a channel. Summary of the invention

[0009] In one aspect, the present disclosure relates to a semiconductor device, comprising: a first substrate, comprising: a first layer, comprising a first channel; a first through-hole, extending through the first layer to a first surface of a first ridge of the first channel; a second layer, coupled to the first layer, wherein the second layer is a first outer layer of the first substrate; and a first line, coupled to the first through-hole and extending along the first ridge of the first channel and embedded in the second layer.

[0010] In another aspect, the present disclosure relates to a semiconductor device, comprising: a first substrate, comprising: a first layer, comprising a first channel; a first through-hole, extending to a first surface of the first layer, wherein the first surface is a surface of a first ridge of the first channel; a second layer, coupled to the first layer, wherein the second layer is a first outer layer of the first substrate; and a first line, connected to the first through-hole and extending across the first ridge of the first channel; and a second substrate, comprising: a third layer, comprising a second channel; a second through-hole, extending to a second surface of the third layer, wherein the second surface is a surface of a second ridge of the second channel; a fourth layer, coupled to the third layer, wherein the fourth layer is a second outer layer of the second substrate; and a connector, coupled to the second through-hole and the first line.

[0011] In yet another aspect, the present disclosure relates to a method for manufacturing a semiconductor device, the method comprising: forming a first substrate, comprising: forming a first layer; forming a first channel in the first layer; forming a first through hole in the first layer extending to a first ridge of the first channel; forming a first line extending along the first ridge of the first channel and connected to the first through hole; and forming a second layer on the first ridge of the first channel and around the first line. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and to the drawings, in which like reference numbers are used to refer to similar components. In some instances, a sub-label is associated with a reference number to denote one of multiple similar components. When a reference number is mentioned without specific reference to an existing sub-label, it is intended to refer to all such multiple similar components.

[0013] Figure 1 is a schematic perspective view of an embodiment of a semiconductor device according to various embodiments;

[0014] Figure 2 According to various embodiments Figure 1 A top view of a semiconductor device;

[0015] Figure 3 According to various embodiments, a second substrate having a transparent Figure 1 A top view of an embodiment of a semiconductor device;

[0016] Figure 4 According to various embodiments, a second substrate having a transparent Figure 1 A top view of another embodiment of a semiconductor device;

[0017] Figure 5 is taken along line AA according to various embodiments Figure 4 A cross-sectional view of a semiconductor device;

[0018] Figure 6 is taken along line BB according to various embodiments Figure 4 A cross-sectional view of a semiconductor device;

[0019] Figure 7 is taken along line CC according to various embodiments Figure 4 A cross-sectional view of a semiconductor device;

[0020] Figure 8 is a flow chart of a method of fabricating a semiconductor device according to various embodiments. DETAILED DESCRIPTION

[0021] Various embodiments are described herein that provide tools and techniques for implementing semiconductor packages or chip packages that include one or more channels.

[0022] In a first aspect, a semiconductor device may include a first substrate, the first substrate comprising: a first layer having a first channel; a first via extending through the first layer to a first surface of a first ridge of the first channel; a second layer coupled to the first layer; and a first line coupled to the first via and extending along the first ridge of the first channel and embedded in the second layer. The second layer may be a first outer layer of the first substrate. The first line may be directly or indirectly coupled to the first surface of the first ridge.

[0023] In some cases, the first line may be located between the first layer and the second layer. In various examples, the second layer may be a dielectric layer. In some embodiments, the first line may be connected to a bonding pad, and the bonding pad may be connected to at least one of a second via, a pad, or a bonding pad located on a second substrate.

[0024] In various examples, the semiconductor device may further include a second substrate, the second substrate including: a third layer including a second channel; a second via extending through the third layer to a second surface of a second ridge of the second channel; a fourth layer coupled to the third layer; and a connector connected to the second via and the first line and embedded in the fourth layer. In some cases, the fourth layer may be a second outer layer of the second substrate.

[0025] In some embodiments, the connector may be a second wire extending across the second ridge of the second channel. In some cases, the first wire may be connected to the second wire by a bonding pad. In various examples, the connector may be a pad or a bonding pad. In some cases, the second ridge of the second channel may be offset relative to the first ridge of the first channel. In various embodiments, the second ridge of the second channel may be approximately perpendicular to the first ridge of the first channel. In some cases, the first through hole may be located above the second channel. In some examples, the second substrate includes one or more inlet or outlet ports configured to receive a fluid, and the fluid may be received in the first channel and the second channel.

[0026] In another aspect, a semiconductor device may include a first substrate, the first substrate including: a first layer including a first channel; a first via extending to a first surface of the first layer, the first surface may be a surface of a first ridge of the first channel; a second layer coupled to the first layer, the second layer may be a first outer layer of the first substrate; and a first line connected to the first via and extending across the first ridge of the first channel. The semiconductor device may further include a second substrate. The second substrate may include: a third layer including a second channel; a second via extending to a second surface of the third layer, the second surface may be a surface of a second ridge of the second channel; a fourth layer coupled to the third layer, the fourth layer may be a second outer layer of the second substrate; and a connector coupled to the second via and the first line.

[0027] In some cases, the connector can include a second wire extending across the second ridge of the second channel.

[0028] In various examples, a ratio of the thickness of the second layer to the thickness of the first line may be between about 1:1 and about 30:1.

[0029] In another aspect, a method for manufacturing a semiconductor device may include forming a first substrate, including: forming a first layer; forming a first channel in the first layer; forming a first through hole in the first layer extending to a first ridge of the first channel; forming a first line extending along the first ridge of the first channel and connected to the first through hole; and forming a second layer on the first ridge of the first channel and around the first line.

[0030] The method may further include forming a second substrate, including: forming a third layer; forming a second channel in the third layer; forming a second through hole in the third layer extending to a second ridge of the second channel; forming a connector coupled to the third layer and connected to the second through hole and the first line; and forming a fourth layer on the second ridge of the second channel and around the connector.

[0031] In some cases, the connector includes a second wire extending along the second spine and connected to the first wire.

[0032] In various embodiments, the second layer may be formed in one or more first selected positions based on one or more first positions where the first lines are formed, and the fourth layer may be formed in one or more second selected positions based on one or more second positions where the connectors are formed.

[0033] In the following description, for purposes of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be appreciated by those skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it will be appreciated that features described with respect to one embodiment may also be combined with other embodiments. However, by the same token, any single feature or multiple features of any described embodiment should not be considered essential to every embodiment of the invention, as other embodiments of the invention may omit such features.

[0034] When an element is referred to herein as being "connected," "coupled," or "attached" to another element, it is understood that the element may be directly connected or coupled to the other element, or that there may be an intermediary element between the elements. In contrast, when an element is referred to as being "directly connected," "directly coupled," or "directly attached" to another element, it is understood that there may be no intermediary element in the "direct" connection or coupling between the elements. However, the presence of a direct connection or coupling does not exclude other connections or couplings in which there may be an intermediary element. As used throughout this disclosure, "connect," "connected," and the like may refer to a connection (e.g., an electrical connection) between one or more elements, while "couple," "coupled," and the like may refer to a connection (e.g., a mechanical or physical connection, link, or engagement) between one or more elements.

[0035] When an element is referred to herein as being "positioned" or "located" in some manner relative to another element (e.g., positioned on, between, below, adjacent to, or positioned in some other relative manner), it is understood that the element may be directly positioned or located relative to the other element (e.g., directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly positioned" or "directly located" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct positioning does not exclude other instances in which there may be intervening elements.

[0036] Likewise, when an element is referred to herein as a "layer", it is understood that the layer may be a single layer or include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or a plurality of different conductive materials or a dielectric and conductive material combination layer or a dielectric or conductive layer combination, etc., and a dielectric layer may include a plurality of dielectric materials or a plurality of dielectric materials or a dielectric and conductive material combination layer or a dielectric or conductive layer combination, etc. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intermediary element present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there is no intermediary element between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which an intermediary element may be present.

[0037] Furthermore, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Rather, they are used only to indicate the relative position and / or direction between various components of an object and / or assembly. Additionally, unless otherwise expressly stated, terms such as first, second, third, etc. are used only to distinguish elements or components from one another and are not intended to imply an order, sequence, or amount.

[0038] In addition, the methods and processes described herein may be described in a particular order for ease of description. However, it should be understood that unless the context dictates otherwise, intervening processes may occur before and / or after any portion of the described process, and other various processes may be reordered, added, and / or omitted according to various embodiments.

[0039] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, and the like are to be understood as being modified in all instances by the term "approximately." As used herein, the term "substantially" or "approximately" means a variation within ±20% or less (e.g., ±20%, ±15%, ±10%, ±5%, etc.) (including the endpoints of the range) relative to a reference value or ratio.

[0040] In this application, unless specifically stated otherwise, the use of the singular includes the plural; and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "including" and "having" and other forms (such as "includes", "included", "has", "have" and "had") should be considered non-exclusive. Also, unless specifically stated otherwise, terms such as "element" or "component" encompass both elements and components that include one unit and elements and components that include more than one unit.

[0041] As used herein, the phrase "at least one of" following a list of items (where any of the items are separated by the terms "and" or "or") modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of" does not require selection from at least one of each of the listed items; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where selection is intended from "at least one of each of A, B, and C," or alternatively "at least one of A, at least one of B, and at least one of C," it will be explicitly described as such.

[0042] In existing semiconductor or chip packages, through holes are often used to pass signals through a semiconductor device from or to one or more layers, substrates, components or assemblies. However, the number, amount or density of through holes may be limited in a semiconductor device or in one or more regions of a semiconductor device in which one or more channels, cavities or pores are formed. In a non-limiting example, for certain types of heat sinks, it is possible to reduce the voltage drop by inserting a second substrate, the second substrate including one or more second channels that continue perpendicular to the one or more first channels of the first substrate. However, due to the way the first substrate overlaps the second substrate and the need to prevent liquid from interfering with the electrical connection, it is difficult to extend the electrical connection through the first substrate to the second substrate.

[0043] The present technology includes a semiconductor or chip device (e.g., an integrated circuit (IC), a chip or other semiconductor device or module) or an interposer (e.g., an interface for routing one or more electrical connections between at least two layers, etc.) that provides one or more channels (e.g., channels, cavities, pores, openings, etc.). The semiconductor device may include one or more vias (e.g., ridge vias, ridge through substrate vias (TSVs), etc.) extending through one or more layers to the top surface of a ridge (e.g., ridge, fin, etc.) of the channel. The vias can be used to route one or more electrical connections through one or more layers and can be used to ensure electrical contact across an interface (e.g., an interface where two layers are coupled together, an interface where a die is coupled to a substrate, an interface where two substrates are coupled together, an interface where a die is coupled to a cold plate (e.g., one or more layers including a channel configured to contain a nanofluid), or any other interface where two components of a semiconductor device are coupled together, etc.). However, providing only ridge vias that extend through one or more layers to the top surface of the ridge of a trench, cavity, or void may limit the density and number of vias that may be formed within a semiconductor device.

[0044] Thus, the present technology may further provide a first substrate comprising one or more through holes extending to the top surface of the first ridge of the first channel and one or more wires extending along the first ridge of the first channel configured to couple to one or more other connectors located on the second substrate. In various cases, the one or more through holes may be located above (e.g., above, below, etc.) the second channel of the second substrate. Thus, by routing the one or more wires along the first ridge of the first channel, the one or more through holes may be coupled to one or more connectors located at the second ridge of the second substrate. In this way, an electrical path may be formed through portions of the first and second substrates, wherein the ridges of the first and second substrates do not overlap. Additionally, by providing a zero-gap bonding surface between the first and second substrates, the zero-gap bonding surface may insulate the one or more wires, thereby preventing fluid from interfering with the one or more through holes, the one or more wires, the one or more connectors, and the like.

[0045] Figure 1 is a schematic perspective view of an embodiment of a semiconductor device 100 according to various embodiments. Figure 2 yes Figure 1 FIG. 1 is a top view of a semiconductor device 100 . Figure 3 yes Figure 1 FIG. 1 is a top view of an embodiment of a semiconductor device 100 . Figure 4 The second substrate 300 has a transparent Figure 1 FIG. 1 is a top view of another embodiment of a semiconductor device 100. For illustrative purposes, the second substrate 300 is Figure 4 The substrate 200 is transparent in order to show one or more vias, lines or connections, etc. between the first substrate 200 and the second substrate 300. However, the second substrate 300 is generally not transparent. Figures 5 to 7 It is taken along various lines Figure 4 FIG. 1 is a cross-sectional view of a semiconductor device 100 .

[0046] Semiconductor device 100 may include a packaging substrate 102 (e.g., a support material on or within which elements of a semiconductor device are fabricated or attached). In various cases, packaging substrate 102 may be formed of one or more layers. The one or more layers may include, but are not limited to, one or more dielectric layers, one or more device layers, one or more conductive layers, one or more insulating layers, one or more redistribution layers, and / or the like. In some cases, packaging substrate 102 may be formed of silicon, glass, ceramic, or other substrate materials. In some cases, packaging substrate 102 may be coupled to a circuit board (e.g., a printed circuit board, etc.) or may be a circuit board.

[0047] In some embodiments, the semiconductor device 100 may further include a first substrate 200. The first substrate 200 may include one or more first intermediate or outer layers 202, the one or more first intermediate or outer layers including one or more first channels 204 (e.g., channels, cavities, pores, etc.) and one or more first ridges 206. In various cases, the one or more first intermediate or outer layers 202 may be one or more layers of the first substrate 200 that are indirectly coupled to the second substrate 300. In some cases, the first substrate 200 may be a cold plate or heat sink including one or more channels, a component or substrate including one or more vacuum cavities, or another component or substrate including one or more channels, etc. In some cases, when the first substrate 200 includes one or more vacuum cavities, the one or more vacuum cavities may include one or more sensors, one or more transducers, etc. In some cases, for example, when the first substrate 200 is a cold plate or heat sink, the one or more first channels 204 may contain or may be configured to contain a liquid. In a non-limiting example, the liquid may be a liquid configured to cool the semiconductor device 100, one or more active devices (e.g., transistors, diodes, etc.) located on or within the semiconductor device 100, one or more device dies of the semiconductor device 100, etc. In some cases, the liquid may be water or other liquid configured to cool the semiconductor device 100, the one or more active devices, the one or more device dies, etc.

[0048] The first substrate 200 may further include one or more second surface layers 208 (eg, one or more bonding layers, etc.), such as Figures 5 to 7 The one or more second surface layers 208 may be one or more outer layers of the first substrate 200 that are directly coupled to the second substrate 300. The one or more second surface layers 208 will be described in more detail below. In some cases, a first ratio of a first thickness T1 of a first layer of the one or more first intermediate or outer layers 202 to a second thickness T2 of a second layer of the one or more second surface layers 208 is between about 250:1 and 10:1, such as Figure 6 However, other ratios are possible and within the scope of the present disclosure. In some cases, one or more insulating or dielectric layers may be included between the one or more second surface layers 208 and the one or more first layers 202.

[0049] In various embodiments, the semiconductor device 100 may further include a second substrate 300. The second substrate 300 may include one or more third intermediate or outer layers 302, the one or more third intermediate or outer layers including one or more second channels 304 (e.g., channels, cavities, pores, etc.) and one or more second ridges 306. In various cases, the one or more third intermediate or outer layers 302 may be one or more layers of the second substrate 300 that are indirectly coupled to the first substrate 200. In various cases, the second substrate 300 may be a cold plate or heat sink including one or more channels, a component or substrate including one or more vacuum cavities, or another component or substrate including one or more channels, etc. In some cases, when the second substrate 300 includes one or more vacuum cavities, the vacuum cavity may include one or more sensors, one or more transducers, etc. In some cases, for example, when the second substrate 300 is a cold plate or heat sink, the one or more second channels 304 may contain or may be configured to contain a liquid (eg, similar to the liquid described above with respect to the first substrate 200 ).

[0050] In some cases, the liquid may be configured to enter the one or more first channels 204 of the first substrate 200 or the one or more second channels 304 of the second substrate 300 through the one or more inlet ports 308 of the second substrate 300 and exit the first substrate 200 or the second substrate 300 through the one or more outlet ports 310 of the second substrate 300, such as Figures 1 to 3 In some examples, one or more inlet ports 308 or one or more outlet ports 310 may be configured to allow liquid to enter or exit through a side 312 of the second substrate 300. In other cases, one or more inlet ports 308 or one or more outlet ports 310 may be configured to allow liquid to enter or exit through a top (or bottom) 314 of the second substrate 300. In various cases, the first substrate 200 or the second substrate 300 may have more or fewer inlet ports 308 or outlet ports 310 than those shown.

[0051] In various cases, the one or more second channels 304 may be offset (e.g., at least partially spaced apart, at least partially angled, misaligned, displaced, etc.) relative to the one or more first channels 204. In other words, the one or more second channels 304 may not completely overlap or align with the one or more first channels 204. In some cases, the one or more second channels 304 may be approximately perpendicular to the one or more first channels 204, such as Figures 1 to 3In some cases, the one or more second ridges 306 may be offset (e.g., at least partially spaced apart, at least partially angled, etc.) relative to the one or more first ridges 206. In other words, the one or more second ridges 306 may not completely overlap or align with the one or more first ridges 206. In some cases, the one or more second ridges 306 may be approximately perpendicular to the one or more first ridges 206, such as Figures 1 to 3 In some cases, at least one first channel 204 may extend below or to an edge 309 of one or more connected second ridges 307 connected to one or more second ridges 306, such as Figure 3 Alternatively, in other cases, one or more first channels 204 may not extend below one or more connected second ridges 307 or extend to their edges 309, such as Figure 2 Various other configurations of one or more channels and one or more ridges are possible and within the scope of the present disclosure.

[0052] The second substrate 300 (on Figures 2 to 7 The surface layer 310 (shown by the light grey shaded area in FIG. 1 ) may further include one or more fourth surface layers 316 (e.g., one or more bonding layers, etc.), such as Figures 5 to 7 In some cases, the one or more fourth surface layers 316 may be one or more outer layers of the second substrate 300 that are directly coupled to the first substrate 200 or the one or more second surface layers 208. The one or more fourth surface layers 316 will be described in more detail below. In some cases, the second ratio of the third thickness T3 of the third layer of the one or more third intermediate layers or outer layers 302 to the fourth thickness T4 of the fourth layer of the one or more fourth surface layers 316 is between about 250:1 and about 10:1, such as Figure 6 However, other ratios are possible and within the scope of the present disclosure. In some cases, one or more insulating or dielectric layers may be included between the one or more fourth surface layers 316 and the one or more third layers 302.

[0053] In some examples, the semiconductor device 100 may be configured to include a cold plate or heat sink including a first substrate 200 and a second substrate 300. The first substrate 200 may be a microchannel plate including one or more first channels 204 configured to receive a fluid. The second substrate 300 may be a manifold structure configured to distribute a fluid through the one or more second channels 304 and the one or more first channels 204. Each of the first substrate 200 or the second substrate 300 may be formed of silicon or other substrate materials or combinations of substrate materials, etc. The cold plate or heat sink may be configured to dissipate heat from the package substrate 102 or one or more device dies of the semiconductor device 100, etc.

[0054] In various cases, the semiconductor device 100 may further include one or more device dies (not shown). The one or more device dies may include, but are not limited to, one or more circuits configured to perform a function, one or more active devices (e.g., transistors, etc.), or one or more passive devices (e.g., wiring, etc.). In various cases, the one or more device dies may include, but are not limited to, one or more microprocessors, one or more switches, one or more memory circuits, or other components or circuits configured to perform a function. In various cases, one or more first channels 204 or second channels 304 may be located near the device die and configured to dissipate or transfer heat from the device die. In some cases, the package substrate 102, the first substrate 200, or the second substrate 300 may be directly coupled to the device die. In various cases, the package substrate 102 may include a device die or may be a device die.

[0055] In some examples, the first substrate 200 may further include one or more first through holes 210 and the second substrate 300 may include one or more second through holes 318 (eg, Figures 3 to 7 ). One or more first through holes 210 may extend through one or more first intermediate or outer layers 202 of the first substrate 200 to a first surface 212 of the one or more first ridges 206. The first surface 212 may be located between the one or more first intermediate or outer layers 202 and the one or more second surface layers 208. One or more second through holes 318 may extend through one or more third intermediate or outer layers 302 of the second substrate 300 to a second surface 320 of the one or more second ridges 306. The second surface 320 may be located between the one or more third intermediate or outer layers 302 and the one or more fourth surface layers 316.

[0056] The one or more through-vias 210 or 318 may include, but are not limited to, one or more through-silicon vias and / or one or more through-substrate vias (TSVs). The one or more through-vias 210 or 318 may be configured to extend completely through the one or more first intermediate or outer layers 202 of the substrate 200 or one or more third intermediate or outer layers 302 of the substrate 300 (e.g., "through" vias) or at least partially through the substrate 200 or 300, and may be formed of a conductive material. The conductive material of the one or more through-vias 210 or 318 may include a metal (e.g., copper, tungsten, nickel, aluminum, gold, silver, tin) or a combination of metals / alloys, or may be formed of other conductive materials or combinations of conductive materials. The one or more through-vias 210 or 318 may be configured to form one or more electrical connections to allow power or one or more signals to travel or be transmitted through the semiconductor device 100, the package substrate 102, the first substrate 200, the second substrate 300, the device die, and / or the like.

[0057] In some cases, the semiconductor device 100 may further include one or more first lines 214 or one or more second lines 322. One or more lines 214 or 322 may include but are not limited to conductive lines, conductive strips, conductive strips, conductive traces, conductive wires, conductive strips, etc. In some examples, one or more first lines 214 or one or more second lines 322 may be formed of a metal (e.g., copper, aluminum, gold, silver, tin, nickel) or a combination of metals / alloys, or may be formed of other conductive materials or combinations of materials. In some cases, one or more first lines 214 or one or more second lines 322 may be formed of one or more layers. In various cases, the one or more layers may include one or more conductive material layers, one or more dielectric material layers, or one or more conductive material and dielectric material combination layers, etc. In addition, in some cases, two or more lines may be formed in two or more layers in one or more second surface layers or the fourth surface layer.

[0058] The one or more first wires 214 may be configured to connect to one or more first connectors (e.g., one or more first conductive surfaces or pads 216, one or more second conductive surfaces or pads 324, one or more second wires 322, one or more bonding pads 104, etc.). The one or more second wires may be configured to connect to one or more second connectors (e.g., one or more first wires 214, one or more first pads 216, one or more second pads 324, or one or more bonding pads 104, etc.).

[0059] One or more first pads 216 may be configured to connect to one or more first vias 210, and one or more second pads 324 may be configured to connect to one or more second vias 318. One or more bonding pads 104 may be configured to couple one or more first wires 214 to corresponding one or more second wires 322, may be configured to couple one or more first wires 214 to corresponding pads 216 or 324 or vias 210 or 318, may be configured to couple one or more second wires 322 to corresponding pads 216 or 324 or vias 210 or 318, or may be configured to couple to another bonding pad. One or more first pads 216, one or more second pads 324, or one or more bonding pads 104 may include one or more conductive elements, one or more conductive wires, one or more bonding pads or bonding surfaces, one or more via pads, and the like. In some examples, one or more first gaskets 216 may surround (eg, at least partially or completely surround) a surface of one or more first through holes 210 , and one or more second gaskets 324 may surround a surface of one or more second through holes 318 .

[0060] Alternatively, in some cases, one or more first wires 214 may be configured to connect directly to one or more first vias 210 or one or more second vias 318 , and one or more second wires 322 may be configured to connect directly to one or more first vias 210 or one or more second vias 318 .

[0061] Steering Figure 3 , one or more first through holes 210, one or more second through holes 318, one or more first gaskets 216, or one or more second gaskets 324 can be arranged on one or more first ridges 206 or one or more second ridges 306, respectively, in various ways. In various cases, one or more first through holes 210, one or more second through holes 318, one or more first gaskets 216, or one or more second gaskets 324 can be arranged along the center or around the center axis of one or more ridges 206 and 306 (such as in Example A by Figure 3 In some examples, one or more first through holes 210, one or more second through holes 318, one or more first shims 216, or one or more second shims 324 may be arranged in one or more rows or columns on one or more ridges 206 and 306 (as shown by Figure 3 In some examples, a two-dimensional orthogonal or non-orthogonal array of one or more first through holes 210, one or more second through holes 318, one or more first shims 216, or one or more second shims 324 may be formed on one or more ridges 206 and 306. In some cases, one or more first through holes 210, one or more second through holes 318, one or more first shims 216, or one or more second shims 324 may be arranged in one or more staggered columns or rows or offset from each other (as shown in Example C by Figure 3 By arranging one or more first through holes 210, one or more second through holes 318, one or more first shims 216, or one or more second shims 324 in one or more rows or columns on the ridges 206 and 306, a higher number or density of through holes 210 or 318 can be obtained.

[0062] Once the one or more first through holes 210, the one or more second through holes 318, the one or more first wires 214, the one or more second wires 322, the one or more first pads 216, or the one or more second pads 324 are formed, the one or more second surface layers 208 may be formed on the first layer 202 of the first substrate 200 or the one or more fourth surface layers 316 may be formed on the third layer 302 of the second substrate 300. The one or more second surface layers may be configured to surround (e.g., at least partially or completely) one or more of the one or more first wires 214, the one or more first pads 216, or the one or more bonding pads 104, etc. The one or more fourth surface layers may be configured to surround (e.g., at least partially or completely) one or more of the one or more second wires 322, the one or more second pads 324, or the one or more bonding pads 104, etc.

[0063] The one or more second surface layers 208 or the one or more fourth surface layers 316 may be one or more bonding layers formed between the first substrate 200 and the second substrate 300 and configured to couple the first substrate 200 to the second substrate 300. In various cases, the one or more second surface layers 208 and the one or more fourth surface layers 316 may be directly coupled together to form a seal (e.g., complete seal, substantial seal, partial seal, etc.) between the first substrate 200 and the second substrate 300. In various cases, one or more second surface layers 208 and one or more fourth surface layers 316 may prevent (e.g., completely, substantially, or partially) liquid in one or more first channels 204 or one or more second channels 304 from leaking from coupling between the first substrate 200 or the second substrate 300 or from contact with one or more first through holes 210, one or more second through holes 318, one or more first wires 214, one or more second wires 322, one or more first gaskets 216, one or more second gaskets 324, or one or more bonding gaskets 104 or other conductive elements contained within the first substrate 200 or the second substrate 300.

[0064] The one or more second surface layers 208 or the one or more fourth surface layers 316 may include one or more zero-gap bonding layers, such as one or more hybrid bonding surfaces, one or more direct bonding surfaces, one or more surface-activated bonding surfaces, and the like. The one or more hybrid bonding surfaces may include one or more surfaces having more than one material (e.g., a combination of an insulator or a dielectric material and a conductive material, and the like). The one or more direct bonding surfaces may include directly bonding two surfaces (e.g., two layers) together without an intermediate layer between the two surfaces. The one or more surface-activated bonding surfaces may include the one or more surfaces that have been chemically treated or treated with a plasma process to enhance the bonding energy between the one or more surfaces. By using the one or more zero-gap bonding layers, the one or more conductive elements or conductive materials contained in the one or more zero-gap bonding layers may be sealed (e.g., completely, substantially, or partially) relative to the liquid in the one or more first channels 204 or the one or more second channels 304. In each of the zero gap bonding scenarios described above, the zero gap bonding surface or layer may be bump-free (e.g., no solder bumps, etc.), which allows the surfaces of one or more second surface layers 208 or one or more fourth surface layers 316 to be set to be substantially or completely flush relative to each other (e.g., there is no gap or mostly no gap between one or more second surface layers 208 or one or more fourth surface layers 316).

[0065] In various cases, the one or more second surface layers 208 or the one or more fourth surface layers 316 may include one or more layers that combine a dielectric material (e.g., silicon oxide, etc.) with an embedded (e.g., at least partially, substantially, or completely embedded in the one or more second surface layers 208 or the one or more fourth surface layers 316) metal (e.g., one or more first lines 214 or second lines 322, one or more first pads 216 or second pads 324, or one or more bonding pads 104, etc.) to form one or more interconnects (e.g., an interconnect between the first substrate 200 and the second substrate 300 or an interconnect between other components or elements of the semiconductor device 100, etc.). The second thickness T2 (shown in FIG. 1 ) of the dielectric material (e.g., the second layer 208 or the fourth layer 316, etc.) Figure 6 ) and the fifth thickness T5 (shown in Figure 7 The third ratio of (in) may be between about 1: 1 and about 30: 1. However, other ratios are possible and within the scope of the present disclosure.

[0066] In some examples, the embedded metal of one of the one or more second surface layers 208 or the one or more fourth surface layers 316 may be located on (e.g., coupled to or directly coupled to) the surface 212 or 320 of the one or more ridges 206 or 306. The embedded metal may be configured to connect to one or more corresponding connectors (e.g., one or more first lines 214 or second lines 322, one or more first pads 216 or second pads 324, or one or more bonding pads 104, etc.) on the other of the one or more second surface layers 208 or the one or more fourth surface layers 316 or other components or connectors of the semiconductor device 100.

[0067] In various cases, the one or more first wires 214 may be configured to extend along the surface 212 of the first ridge 206 of the channel 204 and be connected to the one or more first vias 210, to the one or more first pads 216, etc. In various cases, the one or more first wires 214 may be configured to extend around the center of the first ridge 206. Alternatively, the one or more first wires 214 may be configured to be offset relative to the center of the first ridge 206. In some cases, two or more first wires 214 may be configured to extend along the first ridge 206 adjacent to each other. The one or more first wires 214 may further be configured to couple to one or more second vias 318, one or more second wires 322, or one or more second pads 324 located on or in the second substrate 300, or one or more bonding pads 104 located on or in the first substrate 200 or the second substrate 300.

[0068] In some cases, the one or more second wires 322 may be configured to extend along the surface 320 of the second ridge 306 of the second channel 304 and be connected to the one or more second vias 318, to the one or more second pads 324, etc. In various cases, the one or more second wires 322 may be configured to extend around the center of the second ridge 306. Alternatively, the one or more second wires 322 may be configured to be offset relative to the center of the second ridge 306. In some cases, two or more second wires 322 may be configured to extend along the second ridge 306 adjacent to each other. The one or more second wires 322 may further be configured to couple to the one or more first vias 210, the one or more first wires 214, or the one or more first pads 216 located on or in the first substrate 200, or the one or more bonding pads 104 located on or in the first substrate 200 or the second substrate 300.

[0069] One or more first through-holes 210 or second through-holes 218, one or more first pads 216 or second pads 324, one or more first wires 214 or second wires 322, and one or more bonding pads 104 may be arranged in various ways within or on the first substrate 200 and the second substrate 300. The following paragraphs set forth some non-limiting examples of various arrangements of one or more elements within the first substrate 200 and the second substrate 300. However, these examples are only some of the possible arrangements, and many other arrangements are possible and within the scope of the present disclosure.

[0070] For example, if Figure 4 and 5 As shown in Example D of FIG. 1 , the first via 210 d can be connected (e.g., electrically connected, etc.) to the second via 318 d via the first shim 216 d embedded in the second layer 208 and located on the ridge 206 d and the second shim 324 d embedded in the fourth layer 316 and located on the ridge 306 d. In some cases, the first shim 216 d and the second shim 324 d can be one or more bonding shims 104, or a combination of one or more of the first shim 216 d, the second shim 324 d, and the one or more bonding shims 104.

[0071] In some cases, such as Figure 4 and 5 As shown in Example E of FIG. 1 , a second through hole 318e located above a first channel 204e of the first substrate 200 may be connected to the first through hole 210e via a second pad 324e, a second wire 322e, and a bonding pad 104e embedded in the fourth layer 316. The second wire 322e may extend along the ridge 306d between the third layer 302 and the fourth layer 316 until it reaches the first ridge 206e of the first substrate 200. Once the second wire 322e reaches the first ridge 206e, the second wire 322e may be connected to the bonding pad 104e, which may then be connected to the first pad 216e, which is connected to the first through hole 210e. Alternatively, in some cases, the second wire 322e may be directly connected to the first pad 216e. The first pad 216e may be embedded in the second layer 208 of the first substrate 200.

[0072] In some embodiments, Figure 4 , 5As shown in Example F of 6, the second through hole 318f located above the first channel 204f of the first substrate 200 can be connected to the first through hole 210f located above the second channel 304f through the second shim 324f embedded in the fourth surface layer 316, the second line 322f and the bonding pad 104f. In some cases, the second line 322f can be directly connected to the second through hole 318f without the help of the second shim 324f. The second line 322f can extend along the ridge 306d between the third layer 302 and the fourth layer 316 until it reaches the first ridge 206f of the first substrate 200. Once the second line 322f reaches the first ridge 206f, the second line 322f can be connected to the bonding pad 104f, which can then be connected to another bonding pad 104ff. The bonding pad 104ff may then be connected to the first line 214f, which may extend along the first ridge 206f and be coupled to the first pad 216f connected to the first via 210f. In some cases, the second line 322f may be directly coupled to the first line 214f ​​without the aid of any bonding pads. In some cases, the first line 214f ​​may be directly connected to the first via 210f without the aid of the first pad 216f. The bonding pad 104ff, the first line 214f, and the first pad 216f may be embedded within the second layer 208 of the first substrate 200.

[0073] In some embodiments, Figure 4 , 5 As shown in Example G of 7, a second through hole 318g located above the first channel 204g of the first substrate 200 can be connected to the second through hole 318gg and the first through hole 210g located above the second channel 304g by a second wire 322g embedded in the fourth layer 316 and a bonding pad 104g. The second wire 322g can extend along the ridge 306d between the third layer 302 and the fourth layer 316 until it reaches the first ridge 206g of the first substrate 200. Once the second wire 322f reaches the first ridge 206g, the second wire 322g can be connected to the bonding pad 104g, which can then be connected to another bonding pad 104gg. The bonding pad 104gg can then be connected to the first wire 214g, which can extend along the first ridge 206g and be coupled to the first through hole 210g. In some cases, the second wire 322g can be directly coupled to the first wire 214g without the aid of any bonding pads. The bonding pad 104 gg and the first wire 214 g may be embedded within the second layer 208 of the first substrate 200 .

[0074] In some cases, such as Figure 4 and 6As shown in Example H of , the second through hole 318h can be connected to the first through hole 210h offset relative to the second through hole 318h via the second wire 322h and the bonding pad 104h embedded in the fourth layer 316. The second wire 322h can extend between the third layer 302 and the fourth layer 316 until the second wire 322h reaches the bonding pad 104h. Once the second wire 322h reaches the bonding pad 104h, the second wire 322h can be connected to the bonding pad 104h, which can then be connected to the bonding pad 104hh, which is connected to the first wire 214h. The first wire can then extend between the first layer 202 and the second layer 208 until it reaches and connects to the first through hole 210h. The bonding pad 104hh and the first wire 214h can be embedded in the second layer 208.

[0075] In some cases, such as Figure 4 and 6 As shown in Example 1 of , the first through hole 210i located above the second channel 304i of the second substrate 300 can be connected to the second through hole 318i via the first wire 214i, which is embedded in the second layer 208 or coated with the second surface layer 208 to prevent the fluid from contacting the first wire 214i. In some cases, the width of the second ridge 306i can also be increased to cover the first wire 214i. The first wire 214i can extend along the ridge 206g between the first layer 202 and the second layer 208 until it reaches the second ridge 306i of the second substrate 300. Once the first wire 214i reaches the second ridge 306i, the first wire 214i can be directly connected to the second pad 324i, which is connected to the second through hole 318i. Alternatively, in some cases, the first wire 214i can be indirectly connected to the second pad 324i or the second through hole 318i via a bonding pad (not shown). The second spacer 324 i may be embedded in the fourth layer 316 of the second substrate 300 .

[0076] In some cases, such as Figure 4 and 7As shown in Example J of , a first through hole 210j located above a second channel 304j of the second substrate 300 may be connected to a second through hole 318j located on a ridge 306j not adjacent to the second channel 304j. The connection may be formed via a first wire 214j and a bonding pad 104j embedded in the second layer 208. The first wire 214j may extend along the ridge 206g between the first layer 202 and the second layer 208 until it reaches the second ridge 306j of the second substrate 300. Once the first wire 214j reaches the second ridge 306j, the first wire 214j may be connected to the bonding pad 104j, which may then be connected to a second pad 324j, which is connected to the second through hole 318j. Alternatively, in some cases, the first wire 214j may be directly connected to the second pad 324j or the second through hole 318j. The second pad 324j may be embedded in the fourth layer 316 of the second substrate 300.

[0077] These are only some of the possible arrangements for one or more first through holes 210 or second through holes 218, one or more first pads 216 or second pads 324, one or more first wires 214 or second wires 322, and one or more bonding pads 104, and many other arrangements are possible and within the scope of the embodiments. In various cases, one or more wires 214 or 322 may be routed between, around, over, along, or across ridges and connected to one or more first through holes 210 or second through holes 218, one or more first pads 216 or second pads 324, one or more first wires 214 or second wires 322, and one or more bonding pads 104, etc., in any arrangement desired by the design (without limitation).

[0078] In some embodiments, Figures 5 to 7, one or more second surface layers 208 or one or more fourth surface layers 316 may be optionally deposited below and / or on top of one or more first vias 210 or second vias 218, one or more first pads 216 or second pads 324, one or more first wires 214 or second wires 322, and one or more bonding pads 104, etc. The one or more layers 208 and 316 may be one or more dielectric layers or insulating layers. The one or more layers 208 and 316 may be formed of an inorganic material (e.g., silicon dioxide, silicon nitride, silicon carbonitride) or an organic material (e.g., a photodefinable or non-photodefinable polymer) and / or another other material suitable for use as a dielectric layer or insulating layer. The one or more layers 208 and 316 may be selectively located at locations where one or more first vias 210 or second vias 218, one or more first pads 216 or second pads 324, one or more first wires 214 or second wires 322, and one or more bonding pads 104 are formed, etc. In a non-limiting example, the one or more layers 208 or 316 may be deposited where one or more wires 214 or 322 extend along one or more ridges 206 or 306 and not deposited in one or more locations where no wires 214 or 322 or other conductive elements are present (e.g., on a portion of the ridge 306d located above the channel 204k, etc.).

[0079] By selectively positioning one or more layers 208 and 316 at locations where one or more first vias 210 or second vias 218, one or more first pads 216 or second pads 324, one or more first wires 214 or second wires 322, and one or more bonding pads 104, etc. are formed, heat transfer between the first substrate 200, the second substrate 300, another component (e.g., a device die), etc. at locations where one or more layers 208 and 316 are not formed can be increased. However, the one or more layers 208 and 316 may completely cover any metal portion that would otherwise be in contact with the fluid contained within the one or more channels 204 or 304. By covering one or more first vias 210 or second vias 218 , one or more first pads 216 or second pads 324 , one or more first lines 214 or second lines 322 , and one or more bonding pads 104 , etc., with one or more layers 208 and 316 , corrosion or other unwanted chemical reactions may be prevented.

[0080] Figure 8 is a flow chart of a method of manufacturing a semiconductor device according to various embodiments. Figure 8 The method described in the Figures 1 to 7 However, other methods may be used to manufacture Figure 1-7 components.

[0081] Steering Figure 8, method 800 may begin at box 805 by providing or forming a first substrate (e.g., substrate 200, or other component of a semiconductor device including one or more channels, etc.). The first substrate may include one or more first intermediate layers or outer layers (e.g., first layer 202, etc.). Next, one or more first vias (e.g., first via 210, etc.) may be formed within the first substrate at box 810. In some cases, one or more first channels (e.g., first channel 204, etc.) may then be formed in the first substrate at box 815. One or more first ridges (e.g., first ridge 206, etc.) may be used to separate one or more first channels from another of the one or more first channels. Method 800 may further include forming one or more first lines (e.g., first line 214, etc.) on or connecting one or more first lines to the top surface of the one or more first ridges at box 820. The one or more first wires may be configured to extend along a surface of a corresponding first ridge of the one or more first ridges.In some cases, the one or more first wires may be connected to the one or more first through-holes.

[0082] In some cases, method 800 may include forming one or more bonding pads (e.g., bonding pad 104, etc.) connected to the one or more first wires at optional block 825. The one or more bonding pads may be used to connect the one or more first wires to one or more connectors located on another substrate or component of the semiconductor device. Method 800 may further include forming one or more second surface layers (e.g., second layer 208, etc.) on one or more first intermediate or outer layers of the first substrate at block 830. The one or more second surface layers may encapsulate (e.g., at least partially, substantially, or completely) the one or more first wires and the optional bonding pads.

[0083] The method may continue at block 835 by providing or forming a second substrate (e.g., second substrate 300, or other component of a semiconductor device including one or more channels, etc.). The second substrate may be formed at the same time or at the same location as the first substrate, or at a different time or at a different location than the first substrate. The second substrate may include one or more third intermediate or outer layers (e.g., third layer 302, etc.). Next, one or more second through holes (e.g., second through hole 318, etc.) may be formed within the second substrate at block 840. In some cases, one or more second channels (e.g., second channel 304, etc.) may then be formed in the second substrate at block 845. One or more second ridges (e.g., second ridge 306, etc.) may be used to separate one or more second channels from another of the one or more second channels. The method 800 may further include forming or connecting one or more connectors (e.g., one or more second wires 322, one or more second pads 324, one or more bonding pads 104, or other connectors, etc.) on or to the top surface of the one or more second ridges at block 850. The one or more connectors may be connected to the one or more second vias.

[0084] In some cases, method 800 may include forming one or more fourth surface layers (e.g., fourth layer 316, etc.) on one or more third intermediate layers or outer layers of the second substrate at block 855. The one or more fourth surface layers may encapsulate (e.g., at least partially, substantially, or completely) the one or more connectors.

[0085] The method may then continue at frame 860 by coupling one or more second surface layers of the first substrate to one or more fourth surface layers of the second substrate and coupling the first through hole of the first substrate to the second through hole of the second substrate via one or more of one or more wires, through hole pads, or bonding pads. One or more zero-gap bonding techniques (e.g., hybrid bonding, direct bonding, or surface-activated bonding, etc.) may be used to couple the first substrate to the second substrate. The interface between the first substrate and the second substrate may be bump-free and substantially flat to ensure that liquid does not leak from the one or more first channels or the one or more second channels.

[0086] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. In addition, although the processes of the methods and processes described herein are described in a particular order for ease of description, various processes may be reordered, added, and / or omitted according to various embodiments unless the context otherwise dictates. In addition, the processes described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to a system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although those embodiments are described as having or not having some features for ease of description and for illustrating various aspects of various embodiments, various components and / or features described herein with respect to a particular embodiment may be replaced, added, and / or deleted among other described embodiments unless the context otherwise dictates. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalent forms within the scope of the appended claims.

Claims

1. A semiconductor device comprising: A first substrate comprising: a first layer including a first channel; a first through hole extending through the first layer to a first surface of a first ridge of the first channel; a second layer coupled to the first layer, wherein the second layer is a first outer layer of the first substrate; and A first line coupled to the first via and extending along the first ridge of the first channel is embedded in the second layer. 2 . The semiconductor device according to claim 1 , wherein the first line is located between the first layer and the second layer. The semiconductor device according to claim 1 , wherein the second layer is a dielectric layer. The semiconductor device according to claim 1 , wherein the first line is connected to a bonding pad. 5 . The semiconductor device of claim 4 , wherein the bonding pad is connected to at least one of a second via, a pad, or another bonding pad located on a second substrate.

6. The semiconductor device according to claim 1, further comprising: A second substrate comprising: a third layer including a second channel; a second through hole extending through the third layer to a second surface of a second ridge of the second channel; a fourth layer coupled to the third layer, wherein the fourth layer is a second outer layer of the second substrate; and A connection member is connected to the second via and the first line and is embedded in the fourth layer. 7 . The semiconductor device of claim 6 , wherein the connection is a second line extending across the second ridge of the second channel. 8 . The semiconductor device according to claim 7 , wherein the first line is connected to the second line through a bonding pad.

9. The semiconductor device according to claim 6, wherein the connection member is a pad. 10 . The semiconductor device of claim 6 , wherein the second ridge portion of the second channel is offset with respect to the first ridge portion of the first channel. 11 . The semiconductor device of claim 6 , wherein the second ridge of the second channel is approximately perpendicular to the first ridge of the first channel. 12 . The semiconductor device according to claim 6 , wherein the first through hole is located above the second channel.

13. The semiconductor device of claim 6, wherein the second substrate comprises one or more inlet or outlet ports configured to receive a fluid, wherein the fluid is received in the first channel and the second channel.

14. A semiconductor device comprising: A first substrate comprising: a first layer including a first channel; a first through hole extending to a first surface of the first layer, wherein the first surface is a surface of a first ridge of the first channel; a second layer coupled to the first layer, wherein the second layer is a first outer layer of the first substrate; and a first line connected to the first via and extending across the first ridge of the first channel; and A second substrate comprising: a third layer including a second channel; a second through hole extending to a second surface of the third layer, wherein the second surface is a surface of a second ridge of the second channel; a fourth layer coupled to the third layer, wherein the fourth layer is a second outer layer of the second substrate; and A connector is coupled to the second via and the first line. 15 . The semiconductor device of claim 14 , wherein the connector comprises a second line extending across the second ridge of the second channel. 16 . The semiconductor device of claim 14 , wherein a ratio of a thickness of the second layer to a thickness of the first line is between about 1:1 and about 30:

1.

17. A method for manufacturing a semiconductor device, the method comprising: Forming a first substrate, comprising: forming a first layer; forming a first channel in the first layer; forming a first through hole in the first layer extending to a first ridge of the first channel; forming a first line extending along the first ridge of the first channel and connected to the first via; and A second layer is formed on the first ridge of the first channel and around the first line.

18. The method according to claim 17, further comprising: forming a second substrate, comprising: Forming the third layer; forming a second channel in the third layer; forming a second through hole in the third layer extending to a second ridge of the second channel; forming a connector coupled to the third layer and connected to the second via and the first line; and A fourth layer is formed on the second ridge of the second channel and around the connecting member.

19. The method of claim 18, wherein the connector comprises a second wire extending along the second spine and connected to the first wire.

20. The method of claim 18, wherein the second layer is formed in one or more first selected positions based on one or more first positions where the first lines are formed, and wherein the fourth layer is formed in one or more second selected positions based on one or more second positions where the connectors are formed.

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