Semiconductor package having lead frame with metallized bonding region

Abstract

A semiconductor package includes a semiconductor die having a first surface and a second surface opposite the first surface. A die pad is disposed at a first surface of the semiconductor die. The lead frame includes a carrier section on which the semiconductor die is mounted, where the semiconductor die is solder bonded to the carrier section, where the second surface faces the carrier section. A metallized bonding region is provided on a carrier section of the lead frame, wherein the metal of the metallized bonding region is different from the metal of the lead frame. An electrical conductor is connected to the die pad and bonded to the metallized bonding region. The metallized bonding region has a substantially triangular shape.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor die packaging, and in particular to the field of semiconductor packages having lead frames with metallized bonding areas. Background Art

[0002] Semiconductor device manufacturers are constantly striving to improve the performance of their products while reducing their manufacturing costs. A cost and device performance sensitive area in the manufacture of semiconductor devices is the packaging of the semiconductor die. Packaging involves encapsulating the semiconductor die and forming interconnections from the die pads to the package terminals. Packaging concepts and interconnection technologies should provide high electrical and thermal performance and reliability of semiconductor devices. They should further support package scalability and die shrinkage.

[0003] Some types of packages use so-called spot-plated leadframes. Spot-plated leadframes provide plated metal bonding areas (spots) that allow the leadframe to be connected to a semiconductor die mounted on the leadframe via conductors (eg, bond wires).

[0004] Providing a metallized bonding area can increase the size of the lead frame. In order to keep this increase in size small, the metallized bonding area should be placed as close to the die (semiconductor chip) as possible. On the other hand, if the metallized bonding area is placed too close to the die, it may interfere with the die attach process. Summary of the invention

[0005] According to an embodiment of a semiconductor package, the semiconductor package comprises: a semiconductor die having a first surface and a second surface opposite to the first surface. A die pad is arranged at the first surface of the semiconductor die. A lead frame comprises: a carrier section on which the semiconductor die is mounted, wherein the semiconductor die is solder-bonded to the carrier section, wherein the second surface faces the carrier section. A metallized bonding area is provided on the carrier section of the lead frame, wherein the metal of the metallized bonding area is different from the metal of the lead frame. An electrical conductor is connected to the die pad and bonded to the metallized bonding area. The metallized bonding area has a substantially triangular shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The elements of the drawings are not necessarily drawn to scale relative to each other. Similar reference numerals designate corresponding similar parts. The features of the various illustrated examples may be combined unless they are mutually exclusive and / or may be selectively omitted if not described as being required. The examples are exemplarily detailed in the drawings and in the following description.

[0007] Figure 1is a schematic plan view illustrating a carrier section of a lead frame on which a semiconductor die is mounted and metallized bonding areas are provided.

[0008] Figure 2A is a schematic cross-sectional view of an example of a reduced metallized bonding area.

[0009] Figure 2B is a schematic cross-sectional view of an example of an elevated metallized bonding area.

[0010] Figure 3 is a schematic plan view illustrating a barrier to solder creep disposed between a metallized bonding area and a semiconductor die.

[0011] Figure 4A is a schematic cross-sectional view of a first example of a barrier to solder creep.

[0012] Figure 4B is a schematic cross-sectional view of a second example of a barrier to solder creep.

[0013] Figure 5 is a schematic cross-sectional partial view of an example of a molded semiconductor package using a lead frame having metallized bonding areas.

[0014] Figure 6 is a schematic plan view of an example of a semiconductor package including a leadframe having a carrier section on which a semiconductor die is mounted and on which a metallized bonding area is provided.

[0015] Figure 7 is a schematic diagram of a semiconductor die package including a GaN dual-gate bidirectional switch.

[0016] Figure 8 is a perspective view of a semiconductor die package including a GaN dual-gate bidirectional switch.

[0017] Fig. 9 is with Figure 6 A schematic plan view of an example of a semiconductor package similar to that of a semiconductor package, in which two metallized bonding areas are provided on a carrier section. DETAILED DESCRIPTION

[0018] The words “on…” or “on…” or “below…” may be used herein with respect to a part, element, or material layer formed or positioned or arranged or placed “on” or “under” a surface to mean that the part, element, or material layer is “directly” positioned (e.g., placed, formed, arranged, arranged, placed, etc.) “on” or “under” the implied surface (e.g., in direct contact with it). However, the words “on…” or “on…” or “below…” may be used herein with respect to a part, element, or material layer formed or positioned or arranged or placed “on” or “under” a surface to mean that the part, element, or material layer is “indirectly” positioned (e.g., placed, formed, arranged, deposited, etc.) “on” or “under” the implied surface, with one or more additional parts, elements, or layers being arranged between the implied surface and the part, element, or material layer.

[0019] As used in this specification, the term "electrically connected" or "electrically coupled" or similar terms are not intended to mean that: elements are directly in contact together; intervening elements may be provided between the "electrically connected" or "electrically coupled" elements, respectively. However, according to the present disclosure, the above-mentioned and similar terms may optionally also have the specific meaning that elements are directly in contact together (i.e., no intervening elements are provided between the "electrically connected" or "electrically coupled" elements, respectively).

[0020] Figure 1 The lead frame (in Figure 1 The semiconductor die 150 is mounted on the carrier section 110. The semiconductor die 150 has a first surface 150A. A die pad 155 is disposed at the first surface 150A of the semiconductor die 150. The semiconductor die 150 is solder-bonded to the carrier section 110, wherein a second surface of the semiconductor die 150 opposite to the first surface 150A faces the carrier section 110.

[0021] The carrier section 110 is provided with a metallized bonding area 120. The metallized bonding area 120 comprises or is made of a metal that allows the lead frame (or more specifically, the carrier section 110 of the lead frame) to be connected to the electrical conductor 130. To this end, the metallized bonding area 120 is different from the metallized lead frame (or more specifically, the metallized lead frame carrier section 110). The electrical conductor 130 is connected to a die pad 155 of the semiconductor die 150.

[0022] like Figure 1 As shown in , the metallized bonding area 120 has a substantially triangular shape.

[0023] "Substantially triangular in shape" means that the shape is a triangle (i.e., has three sides) or is a triangle with one or two or three cut or rounded edges, i.e., a "truncated" triangle. Further, the sides of the triangle need not be straight lines, but may undulate or oscillate. In other words, the phrase "substantially triangular in shape" may include some deviation from an "ideal" triangle.

[0024] Hereinafter, the shape of the metallized bonding area 120 is referred to as a triangular shape, keeping in mind that this term encompasses both the triangular and truncated triangular shapes as described above.

[0025] The triangular shape consumes less space than a square, rectangular, circular, or other shape. Thus, the size of the carrier section 110 can be kept small. Furthermore, the triangular shape can be oriented relative to the outline of the semiconductor die 150 so that the corners of the die face the sides (e.g., the longest sides) of the triangular shape. That way, interference between the metallized bonding area 120 and the semiconductor die 150 can be minimized during die attachment.

[0026] The metallized bonding area 120 may be arranged close to the corner 110C of the carrier segment 110. The triangular shape of the metallized bonding area 120 may be aligned with the corner 110C. For example, two sides of the triangular shape may be arranged substantially parallel to the proximal edge of the carrier segment 110.

[0027] The metallized bonding region 120 may be disposed close to a corner of the semiconductor die 150. For example, the corner of the semiconductor die close to the metallized bonding region 120 may face the longest side of the triangular shape of the metallized bonding region 120.

[0028] A variety of different triangular shapes can be used. For example, the triangular shape can be a right triangle shape. In this case, typically, the hypotenuse of the triangle faces the corner of the semiconductor die 150 that is closest to the metallized bonding area 120.

[0029] For example, if the triangle is right-angled in shape, an imaginary line between the right-angled corners of the triangle and the corners of semiconductor die 150 may intersect the hypotenuse of the triangle at or near its center. Additionally, two sides of a right or non-right triangle may have the same length.

[0030] For example, the carrier section 110 and thus the lead frame may include or be of copper or a copper alloy. The upper surface 110A of the carrier section 110 may be solderable. The semiconductor die 150 may be soldered to the (solderable) surface 110A of the carrier section 110 using soft solder.

[0031] The metallized bonding region 120 may include a bondable metal material configured to allow the electrical conductor 130 to be bonded to the carrier segment 110. The material of the metallized bonding region 120 may be different from the material forming the solderable surface 110A of the carrier segment 110. For example, the material of the metallized bonding region 120 may include or be a precious metal, such as silver or a silver alloy.

[0032] The material of the metallized bonding area 120 may depend on the type of electrical conductor 130, the material of the electrical conductor 130 and / or the process used for bonding. For example, the electrical conductor 130 may be a bonding wire. For example, the electrical conductor may be made of or include copper or a copper alloy, aluminum or an aluminum alloy, or gold or a gold alloy. If the electrical conductor 130 is a bonding wire, all known wire bonding processes may be used.

[0033] In other examples, the electrical conductor 130 may be a clip. In this case, a clip bonding process is used to connect the clip to the metallized bonding area 120.

[0034] As is known in the art, there is a tendency for solder creep to the metallized bonding area 120 during die attach, especially with respect to large-sized semiconductor dies 150. Solder creep (also referred to as "solder oozing") of liquid solder during die attach is critical because it may result in the solder possibly covering the metallized bonding area 120 and thus compromising its ability to be used for bonding. Further, the semiconductor die 150 may tilt due to solder creep.

[0035] Figure 2A The carrier section 110 is shown along Figure 1 A cross-sectional view of the section line BB. Figure 2A As shown in , the metallized bonding area 120 can be formed in the lowered portion 110_1 of the carrier segment 110. For example, the lowered portion 110_1 can be formed by stamping the carrier segment 110 in the area including the metallized bonding area 120. More specifically, the carrier segment 110 of the lead frame can be first spot-plated with the metal of the metallized bonding area 120, and then the carrier segment 110 of the lead frame can be stamped around the plated area. Thus, the following can be obtained: Figure 2A Good design as shown in .

[0036] The height of the wall measured from the upper surface 110A of the carrier segment 110 to the metal surface of the metallized bonding area 120 may be equal to or greater than or less than 0.15 mm or 0.25 mm or 0.35 mm. The width W of the wall may be, for example, equal to or greater than or less than 0.3 mm or 0.4 mm or 0.5 mm. For example, the area of ​​the metallized bonding area 120 may be equal to or greater than or less than 0.5 mm. 2, 0.75mm 2 , 1.0mm 2 , 1.25mm 2 or 1.5mm 2 .

[0037] Figure 2B Another example of a carrier segment 110 is illustrated. In this example, the metallized bonding region 120 is formed on an elevated region of the carrier segment 110. That is, the upper surface 110A of the carrier segment 110 is elevated in the region where the metallized bonding region 120 is carried.

[0038] For example, the metallized bonding region 120 may first be formed by spot-plating the carrier segment 110 with the metal of the metallized bonding region 120. The raised portion 110_2 of the carrier segment 110 may then be formed by a machining process such as, for example, embossing.

[0039] refer to Figure 3 In some examples, an obstacle 310 for solder creep can be arranged between the semiconductor die 150 and the metallized bonding area 120. The obstacle 310 can, for example, have a longitudinal and / or linear shape. The obstacle 310 can, for example, extend substantially parallel to the sides of the triangular shape of the metallized bonding area 120 (e.g., to the longest side (e.g., hypotenuse) of the triangle).

[0040] Refer to the diagram along Figure 3 A cross-sectional view of line AA Figure 4A , the obstacle 310 may include, for example, a wall 310_1 formed on the carrier segment 110. The wall 310_1 may be formed by machining (e.g., embossing). The wall 310_1 may have a height H equal to or greater than or less than 0.15 mm, 0.25 mm, or 0.35 mm. The width W of the wall 310_1 may be equal to or greater than or less than 0.3 mm, 0.4 mm, or 0.5 mm.

[0041] refer to Figure 4B , the obstacle 310 may include a groove 310_2 formed in the carrier segment 110. The groove 310_2 may be formed by machining (e.g., by stamping). For example, first, the metal of the metallized bonding area 120 is spot-plated on the carrier segment 110, and then, the groove 310_2 is formed by machining (e.g., by stamping).

[0042] The depth D of the groove 310_2 may be greater than the width W of the groove 310_2. For example, the depth D of the groove 310_2 may be equal to or greater than or less than 0.4 mm, 0.6 mm, or 0.8 mm. The width W of the groove 310_2 may be, for example, equal to or greater than or less than 0.05 mm, 0.1 mm, or 0.15 mm. The groove 310_2 may have a distance X from the metallized bonding area 120 that is equal to or greater than or less than, for example, 0.2 mm, 0.3 mm, or 0.4 mm.

[0043] The semiconductor die 150 includes or is a semiconductor material. Examples of such semiconductor materials include, but are not limited to, basic semiconductor materials such as silicon (Si) or germanium (Ge); IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP); and the like.

[0044] The semiconductor die 150 may have a die pad 155 (only) at its first surface 150A. In other examples, the semiconductor die 150 may have a die pad 155 at its first surface 150A and at its second surface 150B.

[0045] In some examples, semiconductor die 150 may be a transistor. For example, semiconductor die 150 (e.g., semiconductor chip) may be configured, for example, as: an IGBT (insulated gate bipolar transistor); a FET (field effect transistor), in particular a MOSFET (metal oxide semiconductor FET), such as, for example, a P-FET (P channel FET), an N-FET (N channel FET), an AFET (array FET), a JFET (junction gate FET); a planar gate transistor; a field plate trench transistor; or an SJ (super junction) transistor.

[0046] In some examples, semiconductor die 150 may be a power die. Semiconductor die 150 may, for example, be a vertical device in which the primary direction of the load current is in a perpendicular direction to the die plane. As an example, a power pad (e.g., a source or emitter pad) and a gate pad may be located at a first surface 150A of semiconductor die 150, while another power pad (e.g., a drain or collector pad) may be provided at a second surface 150B of semiconductor die 150.

[0047] In other examples, semiconductor die 150 may be, for example, a horizontal or lateral device, where the primary direction of the load current is in a horizontal or lateral direction with respect to the substrate plane. In this case, a first power pad (e.g., a source or emitter pad), a second power pad (e.g., a drain pad or a collector pad), and a gate pad may be located at a first surface 150A of semiconductor die 150, while no die pad is located at a second surface 150B of semiconductor die 150. The present disclosure is not limited to any particular FEOL (front end of line) integration, but a variety of different FEOL integrations (or device types) may benefit from the present disclosure.

[0048] As a specific example, semiconductor die 150 may be a GaN power transistor, in particular a GaN HEMT (High Electron Mobility Transistor), more particularly a bidirectional GaN transistor.

[0049] Figure 5 A partial cross-sectional view of a semiconductor package 500 is illustrated. The lead frame 510 may include a carrier section 110 (also referred to in the art as a "pad") and a package wiring contact section 512. The package wiring contact section 512 is connected to one or more die pads (not shown) of the semiconductor die 150 by package wiring 530 (e.g., bond wires or clips).

[0050] The semiconductor die 150 is mounted on the carrier section 110 by solder 520 (eg soft solder). The semiconductor package 500 may further include a molding compound 540 encapsulating the semiconductor die 150 , the electrical conductors 130 , the package wiring 530 , and at least partially encapsulating the lead frame 510 .

[0051] like Figure 5 As shown in FIG. 5 , package 500 may be, for example, a leadless package. Such a package is also referred to as a leadframe package without leads. In this type of package, package wiring contact section 512 may form, for example, a package terminal located at a footprint of semiconductor package 500 .

[0052] In other examples (see below), the semiconductor package 500 may have leads that protrude laterally outward from the package 500. In this case, the package wiring contact sections 512 may be designed as leads that protrude laterally outward from the mold compound 540. They may or may not be exposed at the footprint side of the semiconductor package 500.

[0053] In all examples, the carrier section 110 of the lead frame 510 may or may not be exposed at the periphery of the mold compound 540. Figure 5As shown in , in some examples, the carrier section 110 can be exposed at the footprint side of the semiconductor package. In other examples, the carrier section 110 can be exposed, for example, at the top side of the semiconductor package (see, for example Figure 8 ), while the package wiring contact section 512 is formed as a contact section at the footprint side of the semiconductor package 500, or is formed as a lead protruding laterally outward from the molding compound 540.

[0054] Figure 6 An example of a semiconductor package 600 is shown. Figure 6 , the mold compound 540 is shown as transparent to allow viewing into the package 600 .

[0055] Semiconductor package 600 is similar to semiconductor package 500 , and reference is made to the above description to avoid repetition. Figure 6 It is illustrated that a plurality of package wirings 530 and / or a plurality of package wiring contact sections 512 may be provided. For example, eight package wiring contact sections 512 (e.g., footprint terminals or leads) may be provided at one lateral side of the semiconductor package 600, and / or a plurality (e.g., eight) of package wiring contact sections 512 may also be provided at another lateral side (e.g., the opposite side). Further, Figure 6 A triangular shaped metallized bonding area 120 is illustrated that is bonded to a die pad 155 of a semiconductor die 150 .

[0056] Further references Figure 7 and 8 , the semiconductor package 600 may be, for example, a package including a semiconductor die 150, which is, for example, a GaN-HEMT (High Electron Mobility Transistor). More specifically, the semiconductor die 150 may be a dual-gate bidirectional switch. Such a switch uses the (unique) properties of the GaN-HEMT, i.e., allows bidirectional switching.

[0057] GaN dual-gate bidirectional switches can eliminate the need for half R DS(ON) Therefore, it can provide low cost and enable new topologies to gain application advantages.

[0058] refer to Figure 7 , a dual-gate bidirectional GaN-HEMT switch has two source terminals S1, S2 and two gate terminals G1, G2. For example, the two GaN transistors may have a common drain configuration (e.g., drains connected internally to the die). For example, the common drain may be floating and not accessible externally. Further, a Kelvin sense terminal (at Figure 7). The ground terminal may be provided, for example, by the carrier section 110 of the lead frame 510. That is, the carrier section 110 may be at the substrate ground potential during operation of the semiconductor package 500.

[0059] More specifically, here and in all other examples, the chip pad 155 may be used to ground the semiconductor die substrate. The die pad 155 may, for example, be connected to a substrate pinning circuit intended to pin the semiconductor die substrate to the respective source S1, S2 having a lower voltage.

[0060] Figure 6 An exemplary lead frame design and an exemplary assignment of package terminals (e.g., wiring contact segments 512) to die pads of semiconductor die 150 are illustrated. A first gate terminal is represented by G1, a second gate terminal is represented by G2, a first source terminal is represented by S1, and a second source terminal is represented by S2. Further, one package wiring contact segment 512 represented by KS1 is connected to a first Kelvin sense die pad of semiconductor die 150 through package wiring 530, and another package wiring contact segment 512 represented by KS2 is connected to a second Kelvin sense die pad of semiconductor die 150 through package wiring 530.

[0061] In this example, the die pad 155 connected to the metallized bonding area 120 is a ground die pad of the semiconductor die 150. However, as already mentioned, substantially any die pad of the semiconductor die 150 may be connected to the metallized bonding area 120 of the carrier section 110 via the electrical conductor 130. More specifically, the die pad connected to the metallized bonding area 120 may alternatively be, for example, a gate pad or a sense Kelvin pad or a load current pad.

[0062] Figure 8 A semiconductor package 800 is shown, which can be similar to a semiconductor package 800 in terms of packaged devices, internal package wiring, and package terminals. Figure 6 The semiconductor package 600 is the same as shown in FIG. Figure 6 As in the semiconductor package 600 of the embodiment of the present invention, the package wiring contact section 512 (e.g., one or more of the package terminals S1, KS1, G1, S2, KS2, G2) can be formed, for example, by leads that protrude laterally outward from the mold compound 540. The semiconductor package 800 can be distinguished from the semiconductor packages 500 and / or 600 in that it is a top-side cooled package. That is, the carrier section 110 of the lead frame 510 can be exposed, for example, at the top side (non-footprint side) of the semiconductor package 800.

[0063] Fig. 9 An example of a semiconductor package 900 is shown. Figure 6As in , mold compound 540 is shown as transparent to allow viewing into package 900 .

[0064] Semiconductor package 900 is similar to semiconductor package 600 and reference is made to the above description to avoid repetition. In semiconductor package 900, a further metallized bonding area 920 may be provided, for example, on carrier section 110. The further metallized bonding area 920 may be arranged close to another corner of carrier section 110.

[0065] The further metallized bonding region 920 may be positioned and / or designed similarly or identically to the metallized bonding region 120. Although the further metallized bonding region 920 is illustrated for the example of a dual-gate bidirectional GaN-HEMT switch, it may be used in any of the semiconductor packages described herein.

[0066] This further metallized bonding area 920 may be used to sense the leadframe potential (i.e., the potential of the carrier section 110 of the leadframe, which may, for example, be the same as the substrate potential of the semiconductor die 150). To this end, the package wiring contact section 512, denoted by SS2, may be connected to this further metallized bonding area 920 by a conductor (e.g., a bonding wire).

[0067] Optionally, alternatively or additionally, the metallized bonding area 120 can also be used (in this example and / or in all other examples of semiconductor packages) for sensing the lead frame potential, for example. In this case, the package wiring contact section 512 represented by SS1 can be connected to the metallized bonding area 120 by a conductor (e.g., a bonding wire).

[0068] In the semiconductor packages 600, 900, a barrier to solder creep may be arranged between the semiconductor die 150 and the metallized bonding area 120 and / or the further metallized bonding area 920 (at Figure 6 and 9 For example, Figure 3 , 4A Reference is made to the description of obstacles 310 , 310_1 , 310_2 shown in 4B .

[0069] The semiconductor package 900 may be based on Figure 8 Referring to the semiconductor package 900 , for example, the package wiring contact section 512 may represent one or more of the package terminals S1 , KS1 , G1 , S2 , KS2 , G2 , SS1 , SS2 .

[0070] EXAMPLES The following examples relate to further aspects of the present disclosure: Example 1 is a semiconductor package, comprising: a semiconductor die having a first surface and a second surface opposite to the first surface. A die pad is disposed at the first surface of the semiconductor die. A lead frame comprises: a carrier section on which the semiconductor die is mounted, wherein the semiconductor die is solder-bonded to the carrier section, wherein the second surface faces the carrier section. A metallized bonding area is provided on the carrier section of the lead frame, wherein the metal of the metallized bonding area is different from the metal of the lead frame. An electrical conductor is connected to the die pad and bonded to the metallized bonding area. The metallized bonding area has a substantially triangular shape.

[0071] In Example 2, the subject matter of Example 1 can optionally include: wherein the metallized bonding area is disposed proximate to a corner of the carrier segment, the triangular shape being aligned with the corner.

[0072] In Example 3, the subject matter of Example 1 or 2 can optionally include wherein the metallized bonding region is disposed proximate to a corner of the semiconductor die, the corner of the semiconductor die facing a longest side of the triangular shape.

[0073] In Example 4, the subject matter of any of the preceding examples may optionally include: wherein the triangular shape is a right triangle shape.

[0074] In Example 5, the subject matter of any of the preceding examples can optionally further include: a barrier to solder creep disposed between the semiconductor die and the metallized bonding area.

[0075] In Example 6, the subject matter of Example 5 can optionally include wherein the obstacle comprises a wall formed on the carrier segment.

[0076] In Example 7, the subject matter of Example 5 or 6 can optionally include: wherein the obstacle comprises a groove formed in the carrier segment.

[0077] In Example 8, the subject matter of any of the preceding examples can optionally include wherein the metallized bonding region is formed on an elevated area of ​​the carrier segment.

[0078] In Example 9, the subject matter of any of the preceding examples can optionally include: wherein a distance between the semiconductor die and the metallized bonding area is equal to or less than 0.5 mm or 0.4 mm or 0.35 mm or 0.3 mm or 0.25 mm or 0.2 mm.

[0079] In Example 10, the subject matter of any of the preceding examples can optionally include wherein the electrical conductor comprises a bonding wire.

[0080] In Example 11, the subject matter of any of the preceding examples can optionally include: wherein the electrical conductor comprises a clip.

[0081] In Example 12, the subject matter of any of the preceding examples can optionally include: wherein the metal of the metallized bonding region comprises or is Ag or an Ag-based alloy.

[0082] In Example 13, the subject matter of any of the preceding examples can optionally include: wherein the semiconductor die comprises a wide bandgap semiconductor material, in particular GaN.

[0083] In Example 14, the subject matter of any of the preceding examples can optionally include wherein the semiconductor die is a power die.

[0084] In Example 15, the subject matter of any of the preceding examples can optionally include: wherein the semiconductor die includes a transistor, and the die pad is a gate pad or a sense Kelvin pad or a ground pad or a load current pad.

[0085] In Example 16, the subject matter of any of the preceding examples may optionally include: wherein the semiconductor die comprises a bidirectional GaN transistor, in particular a bidirectional GaN high electron mobility transistor.

[0086] Although specific examples have been illustrated and described herein, it will be appreciated by those skilled in the art that the specific examples shown and described may be replaced with a variety of alternative and / or equivalent implementations without departing from the scope of the invention. This application is intended to cover any adaptation or variation of the specific examples discussed herein. Therefore, it is intended that the present invention is limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: a semiconductor die having a first surface and a second surface opposite the first surface; a die pad disposed at a first surface of the semiconductor die; a lead frame comprising: a carrier section on which the semiconductor die is mounted, wherein the semiconductor die is solder bonded to the carrier section, wherein the second surface faces the carrier section; a metallized bonding area on a carrier section of the lead frame, wherein the metallized bonding area is of a different metal than the lead frame; and an electrical conductor connected to the die pad and bonded to the metallized bonding area; wherein The metallized joining area has a substantially triangular shape. 2 . The semiconductor package of claim 1 , wherein the metallized bonding area is disposed proximate to a corner of the carrier segment, the triangular shape being aligned with the corner.

3. The semiconductor package of claim 1 or 2, wherein the metallized bonding area is arranged close to a corner of the semiconductor die, the corner of the semiconductor die facing the longest side of the triangular shape.

4. The semiconductor package of any one of the preceding claims, wherein the triangular shape is a right triangle shape.

5. The semiconductor package as claimed in any one of the preceding claims, further comprising: A barrier to solder creep is disposed between the semiconductor die and the metallized bonding area. 6 . The semiconductor package of claim 5 , wherein the barrier comprises a wall formed on the carrier section.

7. A semiconductor package as claimed in claim 5 or 6, wherein the barrier comprises a groove formed in the carrier section.

8. The semiconductor package of any of the preceding claims, wherein the metallized bonding area is formed on a raised area of ​​the carrier section.

9. The semiconductor package of any one of the preceding claims, wherein the distance between the semiconductor die and the metallized bonding area is equal to or less than 0.5 mm or 0.4 mm or 0.35 mm or 0.3 mm or 0.25 mm or 0.2 mm.

10. The semiconductor package of any preceding claim, wherein the electrical conductor comprises a bond wire.

11. A semiconductor package as claimed in any preceding claim, wherein the electrical conductor comprises a clip.

12. The semiconductor package of any one of the preceding claims, wherein the metal of the metallized bonding area comprises or is Ag or an Ag-based alloy.

13. A semiconductor package as claimed in any one of the preceding claims, wherein the semiconductor die comprises a wide bandgap semiconductor material, in particular GaN.

14. The semiconductor package of any preceding claim, wherein the semiconductor die is a power die.

15. The semiconductor package of any one of the preceding claims, wherein the semiconductor die comprises a transistor and the die pad is a gate pad or a sense Kelvin pad or a ground pad or a load current pad. 16 . The semiconductor package of claim 13 , wherein the semiconductor die comprises a bidirectional GaN transistor, in particular a bidirectional GaN high electron mobility transistor.

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