Short circuit protection method and system for multi-thread integrated circuit

Abstract

The invention discloses a short-circuit protection method and system for a multi-thread integrated circuit, and particularly relates to the technical field of circuits, and the method comprises the steps: S1, multi-source data collection: collecting thread-level current waveform, voltage fluctuation and temperature gradient data in real time through a high-frequency sampling sensor integrated on each thread power supply pin, and synchronously obtaining a chip load state, constructing a multi-dimensional original data stream; an anti-noise coding technology and a fault-tolerant interpolation algorithm are adopted to ensure data integrity and robustness; according to the method, the multi-dimensional original data is collected in real time, the data influence coefficients of the current layer, the thread layer, the scheduling layer and the power supply network layer are calculated, and four types of core protection decision features are constructed, so that specific threads or core faults can be accurately positioned, forced interruption of non-fault areas is avoided, and fine protection is realized.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and more particularly to a short circuit protection method and system for a multi-threaded integrated circuit. Background Art

[0002] With the continuous development of integrated circuit technology, multi-threaded integrated circuits are increasingly used in various electronic devices. Multi-threaded integrated circuits can handle multiple tasks at the same time, greatly improving the operating efficiency of the system.

[0003] Short circuit failure is one of the common problems faced by integrated circuits. Once a short circuit occurs, it may cause damage to the integrated circuit or even cause failure of the entire electronic device. The traditional circuit short-circuit protection method is to connect a fuse in series in the circuit. When the current exceeds the rated value, the fuse will melt and cut off the circuit or monitor the current through a comparator to trigger a shutdown relay for circuit protection.

[0004] However, in actual use, it still has some shortcomings, such as the protection is not precise. The traditional method protects at the global or module level. The fuse will cut off the entire power network and cannot locate the specific thread or core, resulting in forced interruption of the non-fault area; the protection relies on static thresholds. The traditional method relies on fixed thresholds and cannot dynamically adapt to transient load changes in multi-threaded scenarios. It may misjudge normal peak current as a fault; the recovery capability is poor. Most of the protection actions are irreversible operations and require manual intervention to restart, and automatic recovery after a fault cannot be achieved.

[0005] Therefore, there is an urgent need to provide a short-circuit protection method and system for multi-threaded integrated circuits to solve the problems of existing circuit short-circuit protection methods, such as imprecise protection, protection dependence on static thresholds, and poor recovery capabilities. Summary of the invention

[0006] In order to overcome the above defects of the prior art, an embodiment of the present invention provides a short circuit protection method and system for a multi-threaded integrated circuit, and solves the problems raised in the above background technology through the following scheme.

[0007] To achieve the above object, the present invention provides the following technical solution: a short circuit protection method for a multi-threaded integrated circuit, comprising: S1. Multi-source data acquisition: Through the high-frequency sampling sensor integrated in each thread power supply pin, the thread-level current waveform, voltage fluctuation and temperature gradient data are collected in real time, the chip load status is obtained synchronously, and a multi-dimensional raw data stream is constructed; anti-noise coding technology and fault-tolerant interpolation algorithm are used to ensure data integrity and robustness; S2, indicator calculation, based on the multi-source raw data collected in S1, through physical coupling modeling and nonlinear function design, calculate the current layer data influence coefficient, thread layer data influence coefficient, scheduling layer data influence coefficient and power supply network layer data influence coefficient respectively, and construct four types of core protection decision-making characteristics; S3, short-circuit protection strategy generation, based on the four types of core protection decision-making characteristics obtained in S2, select the autonomous influence coefficient hierarchical trigger mechanism to avoid the comprehensive value blurring the risk characteristics of each level, and then generate the short-circuit protection strategy; S4, self-healing recovery and status feedback, short-circuit protection is performed according to the protection strategy generated in S3, and then progressive recovery and model iteration are performed, the short-circuit event-related data is fed back to the LSTM dynamic threshold model, the threshold parameters are updated, and multi-source data is collected again for the circuit system after short-circuit protection; S5. Data interaction: transmit the short-circuit event related data and the generated short-circuit protection strategy to the user information segment, providing the user with reference data for making adjustment measures.

[0008] Preferably, the multi-dimensional original data stream includes current layer data, thread layer data, scheduling layer data and power supply network layer data.

[0009] Preferably, the current layer data includes the power rail voltage drop, denoted as ΔVd; the effective value of the current, denoted as Ir; the measured impedance value at the resonant frequency, denoted as Z(fr); the duration of current exceeding the standard, denoted as To; the thread layer data includes the core temperature gradient, denoted as ▽T; the hot spot diffusion rate, denoted as vh; the number of shared resource contention times, denoted as C; the scheduling layer data includes the task deadline, denoted as Td; the on-chip network bandwidth utilization, denoted as Un; the CPU resource discreteness, denoted as σc; the GPU resource discreteness, denoted as σg; the voltage disturbance caused by migration, denoted as ΔV; the power supply network layer data includes the number of effective power supply paths, denoted as Np; the path impedance matching degree, denoted as ρZ; the total number of power supply paths, denoted as Nt; the short-circuit current propagation speed, denoted as vf; the voltage coupling coefficient, denoted as kc, and the duration of current exceeding the standard, denoted as To.

[0010] Preferably, the current layer data impact coefficient reflects instantaneous power anomalies through the product of voltage drop and current, the impedance attenuation exponential term amplifies the low impedance risk, and the time square root term balances the impact of short-term spikes and continuous overloads, thereby realizing multi-physical field coupling modeling of current-voltage-impedance-time, which is used to quantify the current layer short circuit risk.

[0011] Preferably, the thread-level data impact coefficient characterizes the urgency of thermal runaway through the product of temperature gradient and hotspot diffusion rate, the logarithmic function of resource contention times suppresses numerical explosion in high-concurrency scenarios, and thread-level risks are evaluated through the heat-time-resource ternary relationship.

[0012] Preferably, the scheduling layer data impact coefficient measures the scheduling urgency through the ratio of task deadline to bandwidth utilization, the square root of resource discreteness suppresses the impact of fragmentation, and the hyperbolic tangent function constrains the voltage disturbance amplitude, thereby achieving coordinated optimization of real-time-resource efficiency-power supply stability.

[0013] Preferably, the power supply network layer data impact coefficient evaluates the network redundancy capability by the product of the effective path proportion and the impedance matching degree, the coupling term of the fault propagation speed and the square root of time quantifies the diffusion risk, and the reconstruction success rate is predicted by the path-impedance-speed ternary model.

[0014] Preferably, the short circuit protection strategy generation step specifically includes the following steps: First, set the hierarchical thresholds and priorities, and generate four core thresholds based on historical data and experimental data, namely, the current layer data impact coefficient threshold, the thread layer data impact coefficient threshold, the scheduling layer data impact coefficient threshold, and the power supply network layer data impact coefficient threshold. Then, prioritize them according to the priority of power supply network layer > current layer > thread layer > scheduling layer. Then, perform real-time monitoring and parallel evaluation, and make parallel judgments based on the real-time values ​​of the current layer data impact coefficient, thread layer data impact coefficient, scheduling layer data impact coefficient, and power supply network layer data impact coefficient obtained by S2, and then generate a protection action strategy according to the priority. The current layer data impact coefficient threshold is calculated by building a test environment, injecting a step-by-step increasing short-circuit current, recording the CLIF value and the critical point of chip damage, taking 80% of the critical value to calculate the current layer data impact coefficient at this time, and then averaging it with the mean of the historical current layer data impact coefficient as the current layer data impact coefficient threshold; The thread layer data impact coefficient threshold is calculated by gradually increasing the core load in the high temperature aging test until a transistor leakage failure occurs, recording the TLIF critical value, calculating the thread layer data impact coefficient at this time, and then averaging it with the mean of the historical thread layer data impact coefficient as the thread layer data impact coefficient threshold; The scheduling layer data impact coefficient threshold is calculated by gradually increasing the task load in the resource fragmentation scenario until the task times out, recording the SLIF critical value, calculating the scheduling layer data impact coefficient at this time, and then averaging it with the mean of the historical scheduling layer data impact coefficient as the scheduling layer data impact coefficient threshold; The power supply network layer data impact coefficient threshold is obtained by artificially creating a power supply network short circuit, measuring the PLIF and system crash associated fuse trigger point, calculating the power supply network layer data impact coefficient at this time, and then averaging it with the mean of the historical power network layer data impact coefficient as the power supply network layer data impact coefficient threshold.

[0015] Preferably, the parallel judgment is specifically: When the power supply network layer data impact coefficient is less than the power supply network layer data impact coefficient threshold, the power supply of the faulty thread is cut off, a reverse current is injected, the global power supply of the chip is immediately cut off, and the coordinates of the faulty area are recorded through the non-volatile memory; an interrupt signal is sent to the external controller to wait for manual intervention; When the current layer data impact coefficient is greater than the current layer data impact coefficient threshold, cut off the power supply of the faulty thread, inject reverse current, and turn off the GaN switch of the faulty thread within ≤10ns; inject reverse current into the adjacent thread to offset the short-circuit current; mark the faulty thread as disabled, and continue to monitor the current layer data impact coefficient until it is less than 20% of the current layer data impact coefficient threshold; When the thread layer data impact coefficient is greater than the thread layer data impact coefficient threshold, migrate the thread to the spare core, start active cooling, suspend the faulty thread task, and migrate the context to the spare core through the silicon interposer high-speed link; after the migration is completed, reset the original core temperature sensor and release the shared resource lock; When the scheduling layer data impact coefficient is greater than the scheduling layer data impact coefficient threshold, the task scheduling priority is increased and resource allocation is optimized; task priority is dynamically increased and allocated to cores with resource discreteness < 0.2; and the bandwidth occupancy rate of non-real-time tasks is limited; In other cases, keep monitoring.

[0016] Preferably, the short circuit protection system for a multi-threaded integrated circuit specifically comprises: The multi-source data acquisition module collects thread-level current waveform, voltage fluctuation and temperature gradient data in real time through high-frequency sampling sensors integrated in each thread power supply pin, synchronously obtains chip load status, and constructs multi-dimensional raw data streams; it uses anti-noise coding technology and fault-tolerant interpolation algorithms to ensure data integrity and robustness; The indicator calculation module calculates the influence coefficient of current layer data, thread layer data, scheduling layer data and power supply network layer data respectively based on the multi-source original data collected by the multi-source data acquisition module through physical coupling modeling and nonlinear function design, and constructs four types of core protection decision-making features; The short-circuit protection strategy generation module selects the autonomous impact coefficient hierarchical trigger mechanism based on the four types of core protection decision-making characteristics obtained by the indicator calculation module to avoid the comprehensive value blurring the risk characteristics of each level, and then generates a short-circuit protection strategy; The self-healing recovery and state feedback module generates a protection strategy for short-circuit protection according to the short-circuit protection strategy generation module, and then performs progressive recovery and model iteration, feeds back short-circuit event-related data to the LSTM dynamic threshold model, updates the threshold parameters, and re-collects multi-source data for the circuit system after short-circuit protection; The data interaction module transmits the short-circuit event related data and the generated short-circuit protection strategy to the user information segment, providing the user with reference data for making adjustment measures.

[0017] Technical effects and advantages of the present invention: The present invention collects multi-dimensional raw data in real time, calculates the data influence coefficients of the current layer, thread layer, scheduling layer and power supply network layer, and constructs four types of core protection decision features, which can accurately locate specific thread or core faults, avoid forced interruption in non-fault areas, and achieve fine protection; The present invention adopts anti-noise coding technology and fault-tolerant interpolation algorithm to ensure data integrity and robustness. Based on the collected multi-source raw data, various influence coefficients are calculated through physical coupling modeling and nonlinear function design, and the short-circuit event-related data is fed back to the LSTM dynamic threshold model to update the threshold parameters. It can dynamically adapt to transient load changes in multi-threaded scenarios to avoid misjudging normal peak current as a fault. After performing short-circuit protection according to the short-circuit protection strategy, the present invention performs progressive recovery and simultaneously performs model iteration to achieve automatic recovery after a fault, reduce manual intervention, and improve circuit system recovery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the overall structure of the present invention.

[0019] Figure 2 It is a schematic diagram of the system structure of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] As attached Figure 1 The short circuit protection method for a multi-threaded integrated circuit is shown, including.

[0022] S1. Multi-source data acquisition: Through the high-frequency sampling sensor integrated in each thread power supply pin, the thread-level current waveform, voltage fluctuation and temperature gradient data are collected in real time, the chip load status is obtained synchronously, and a multi-dimensional raw data stream is constructed; anti-noise coding technology and fault-tolerant interpolation algorithm are used to ensure data integrity and robustness.

[0023] In this embodiment, it should be specifically explained that the multi-dimensional original data stream includes current layer data, thread layer data, scheduling layer data and power supply network layer data.

[0024] In this embodiment, it should be specifically noted that the current layer data includes the power rail voltage drop, denoted as ΔVd; the effective value of the current, denoted as Ir; the measured impedance value at the resonant frequency, denoted as Z(fr); the duration of current exceeding the standard, denoted as To; the thread layer data includes the core temperature gradient, denoted as ▽T; the hot spot diffusion rate, denoted as vh; the number of shared resource contention times, denoted as C; the scheduling layer data includes the task deadline, denoted as Td; the on-chip network bandwidth utilization, denoted as Un; the CPU resource discreteness, denoted as σc; the GPU resource discreteness, denoted as σg; the voltage disturbance caused by migration, denoted as ΔV; the power supply network layer data includes the number of effective power supply paths, denoted as Np; the path impedance matching degree, denoted as ρZ; the total number of power supply paths, denoted as Nt; the short-circuit current propagation speed, denoted as vf; the voltage coupling coefficient, denoted as kc, and the duration of current exceeding the standard, denoted as To.

[0025] In this embodiment, it is specifically necessary to explain that the power rail voltage drop is obtained by deploying a high-precision differential voltage probe on the chip power supply pin, collecting voltage signals in real time at a sampling rate of 2MS / s, synchronously recording the rated voltage feedback value of the power management unit, and calculating the deviation between the actual voltage and the rated value.

[0026] In this embodiment, it should be specifically noted that the effective value of the current is obtained by collecting the instantaneous current sequence using a high-frequency current sensor and then calculating it, specifically: ; Where I(t) represents the instantaneous current sequence and T represents the current running time.

[0027] In this embodiment, it should be specifically explained that the measured impedance value at the resonant frequency is directly collected by injecting a 1MHz-1GHz sweep frequency signal into the power supply network using an impedance analyzer, measuring the impedance amplitude-frequency characteristic curve, and extracting the impedance amplitude at the resonant frequency point.

[0028] In this embodiment, it is specifically necessary to explain that the duration of the current exceeding the standard is determined by starting the FPGA built-in hardware timer when the current sensor triggers an exceeding standard signal, and continuously timing until the current falls below the threshold, recording the time difference, and directly acquiring the data.

[0029] In this embodiment, it should be specifically noted that the core temperature gradient is obtained by deploying digital thermal sensors at the four corners of the chip core, with a sampling rate of 100 kS / s, recording the temperature, and then calculating, specifically: ; Where T i represents the core temperature of the ith sensor, T j represents the core temperature of the jth sensor, d ijThe distance between the i-th sensor and the j-th sensor.

[0030] In this embodiment, it should be specifically noted that the hot spot diffusion rate is obtained by collecting the chip surface temperature distribution image at a frame rate of 100 Hz by an infrared thermal imager, locating the hot spot coordinates, and then calculating and obtaining, specifically: ; Where (x(t), y(t)) represents the coordinates of the positioning hotspot, (x(t+Δt), y(t+Δt)) represents the coordinates of the positioning hotspot after Δt time, and Δt represents the time interval.

[0031] In this embodiment, it should be specifically explained that the number of shared resource contention is directly obtained by implanting hardware performance counters in the cache controller and the bus arbiter to count the number of access failures caused by resource conflicts within a unit time.

[0032] In this embodiment, it should be specifically explained that the task deadline is obtained by reading the real-time constraint parameters of the task from the real-time operating system scheduler or the hardware task management unit.

[0033] In this embodiment, it should be specifically noted that the bandwidth utilization of the on-chip network is calculated by deploying a hardware traffic monitor in the NoC router, counting the number of valid data packets per unit time, and combining the theoretical maximum bandwidth, and is specifically: ; Where Np represents the number of valid data packets, Lp represents the average data packet length, Bmax represents the theoretical maximum bandwidth, and Tz represents the statistical period.

[0034] In this embodiment, it should be specifically noted that the CPU resource discreteness and the GPU resource discreteness are obtained by recording the idle cycle proportion of each computing unit through a performance counter.

[0035] In this embodiment, it should be specifically explained that the voltage disturbance caused by the migration is obtained by using a high-speed voltage sensor to record the difference between the peak value and the steady-state value of the voltage fluctuation of the power supply network at the moment when the task migration is triggered.

[0036] In this embodiment, it should be specifically explained that the number of effective power supply paths is obtained by injecting a test current into each path and detecting the number of paths of voltage response by using a programmable power supply network scanning module using a power supply network scanner.

[0037] In this embodiment, it should be specifically noted that the path impedance matching is obtained by applying a constant current to each power supply path, measuring the voltage drop, calculating the impedance, and comparing it with the rated impedance, specifically: ; Where Z represents impedance and Zn represents rated impedance.

[0038] In this embodiment, it should be specifically noted that the total number of power supply paths is directly read according to the chip power supply network design specification.

[0039] In this embodiment, it should be specifically noted that the short-circuit current propagation speed is obtained by recording the short-circuit trigger timestamp and the abnormal voltage timestamp of the adjacent area, and obtaining the physical distance between the fault point and the affected area from the layout data, which is specifically: ; Where d represents the physical distance between the fault point and the affected area, t 0 Indicates the short circuit triggering timestamp, t 1 Indicates the timestamp of abnormal voltage in adjacent areas.

[0040] In this embodiment, it should be specifically noted that the voltage coupling coefficient is obtained by deploying voltage sensors in adjacent power supply areas, recording the voltage fluctuations in the two areas during a short circuit event, and then calculating, specifically: ; Where ΔV 1 Indicates the voltage fluctuation amplitude in the fault area, ΔV 2 Indicates the voltage fluctuation amplitude in adjacent areas.

[0041] S2, indicator calculation, based on the multi-source original data collected by S1, through physical coupling modeling and nonlinear function design, calculate the current layer data influence coefficient, thread layer data influence coefficient, scheduling layer data influence coefficient and power supply network layer data influence coefficient respectively, and construct four types of core protection decision-making characteristics.

[0042] In this embodiment, it should be specifically explained that the current layer data influence coefficient reflects the instantaneous power anomaly through the product of voltage drop and current, the impedance attenuation exponential term amplifies the low impedance risk, and the time square root term balances the impact of short-term spikes and continuous overloads, realizing the multi-physics field coupling modeling of current-voltage-impedance-time, which is used to quantify the current layer short circuit risk, specifically: ; Where ΔVd represents the current layer data including the power rail voltage drop, Ir represents the effective value of the current, Z(fr) represents the measured impedance value at the resonant frequency, To represents the duration of the current exceeding the standard, Vn represents the rated voltage, Zn represents the rated impedance, and Ts represents the maximum allowable safety time.

[0043] In this embodiment, it should be specifically explained that the thread-level data impact coefficient represents the urgency of thermal runaway through the product of temperature gradient and hot spot diffusion rate, the logarithmic function of resource contention times suppresses the numerical explosion of high concurrency scenarios, and the thread-level risk is evaluated through the heat-time-resource ternary relationship, specifically: ; Where ▽T represents the core temperature gradient, vh represents the hot spot diffusion rate, C represents the number of shared resource contention times, Ts represents the maximum safe temperature, τ represents the thermal diffusion time constant, and Ct represents the maximum allowed number of contention times.

[0044] In this embodiment, it should be specifically explained that the scheduling layer data impact coefficient measures the scheduling urgency by the ratio of the task deadline to the bandwidth utilization rate, the square root of the resource discreteness suppresses the fragmentation effect, and the hyperbolic tangent function constrains the voltage disturbance amplitude to achieve the coordinated optimization of real-time-resource efficiency-power supply stability, specifically: ; Where Td represents the task deadline; Un represents the on-chip network bandwidth utilization; σc represents the CPU resource discreteness; σg represents the GPU resource discreteness; ΔV represents the voltage disturbance caused by migration, and Vn represents the power supply noise tolerance; In this embodiment, it should be specifically noted that the power supply network layer data impact coefficient evaluates the network redundancy capability by multiplying the effective path proportion by the impedance matching degree, and the coupling term of the fault propagation speed and the square root of time quantifies the diffusion risk. The path-impedance-speed ternary model is used to predict the reconstruction success rate, which is specifically: ; Where Np represents the number of effective power supply paths, ρZ represents the path impedance matching, Nt represents the total number of power supply paths, vf represents the short-circuit current propagation speed, kc represents the voltage coupling coefficient, To represents the duration of current exceeding the standard, v max Indicates the maximum propagation speed.

[0045] S3, short-circuit protection strategy generation, based on the four types of core protection decision-making characteristics obtained in S2, select the autonomous influence coefficient hierarchical trigger mechanism to avoid the comprehensive value blurring the risk characteristics of each level, and then generate the short-circuit protection strategy.

[0046] In this embodiment, it should be specifically explained that the short circuit protection strategy generation step has the following specific steps: First, the hierarchical thresholds and priorities are set, and four sets of core thresholds are generated based on historical data and experimental data, namely, the current layer data impact coefficient threshold, the thread layer data impact coefficient threshold, the scheduling layer data impact coefficient threshold, and the power supply network layer data impact coefficient threshold. Then, the priorities are sorted according to the priority of power supply network layer > current layer > thread layer > scheduling layer. Then, real-time monitoring and parallel evaluation are carried out, and parallel judgments are made according to the real-time values ​​of the current layer data impact coefficient, thread layer data impact coefficient, scheduling layer data impact coefficient, and power supply network layer data impact coefficient obtained by S2, and then a protection action strategy is generated according to the priority.

[0047] In this embodiment, it is specifically necessary to explain that the current layer data impact coefficient threshold is obtained by setting up a test environment, injecting a step-by-step increasing short-circuit current, recording the CLIF value and the critical point of chip damage, taking 80% of the critical value to calculate the current layer data impact coefficient at this time, and then averaging it with the mean of the historical current layer data impact coefficient as the current layer data impact coefficient threshold.

[0048] In this embodiment, it is specifically necessary to explain that the thread layer data impact coefficient threshold is obtained by gradually increasing the core load in the high temperature aging test until transistor leakage failure occurs, recording the TLIF critical value, calculating the thread layer data impact coefficient at this time, and then averaging it with the mean of the historical thread layer data impact coefficient as the thread layer data impact coefficient threshold.

[0049] In this embodiment, it is specifically necessary to explain that the scheduling layer data impact coefficient threshold is calculated by gradually increasing the task load in the resource fragmentation scenario until the task times out, recording the SLIF critical value, calculating the scheduling layer data impact coefficient at this time, and then averaging it with the mean of the historical scheduling layer data impact coefficient as the scheduling layer data impact coefficient threshold.

[0050] In this embodiment, it is specifically necessary to explain that the power supply network layer data impact coefficient threshold is obtained by artificially creating a power supply network short circuit, measuring the PLIF and system collapse associated fuse trigger point, calculating the power supply network layer data impact coefficient at this time, and then averaging it with the mean of the historical power network layer data impact coefficient as the power supply network layer data impact coefficient threshold.

[0051] In this embodiment, it should be specifically explained that the parallel judgment is specifically: When the power supply network layer data impact coefficient is less than the power supply network layer data impact coefficient threshold, the power supply of the faulty thread is cut off, a reverse current is injected, the global power supply of the chip is immediately cut off, and the coordinates of the faulty area are recorded through the non-volatile memory; an interrupt signal is sent to the external controller to wait for manual intervention; When the current layer data impact coefficient is greater than the current layer data impact coefficient threshold, cut off the power supply of the faulty thread, inject reverse current, and turn off the GaN switch of the faulty thread within ≤10ns; inject reverse current into the adjacent thread to offset the short-circuit current; mark the faulty thread as disabled, and continue to monitor the current layer data impact coefficient until it is less than 20% of the current layer data impact coefficient threshold; When the thread layer data impact coefficient is greater than the thread layer data impact coefficient threshold, migrate the thread to the spare core, start active cooling, suspend the faulty thread task, and migrate the context to the spare core through the silicon interposer high-speed link; after the migration is completed, reset the original core temperature sensor and release the shared resource lock; When the scheduling layer data impact coefficient is greater than the scheduling layer data impact coefficient threshold, the task scheduling priority is increased and resource allocation is optimized; the task priority is dynamically increased and allocated to the core with resource discreteness <0.2; and the bandwidth occupancy rate of non-real-time tasks is limited.

[0052] In other cases, keep monitoring.

[0053] S4, self-healing recovery and status feedback, generates a protection strategy based on S3 for short-circuit protection, then performs progressive recovery and model iteration, feeds back short-circuit event-related data to the LSTM dynamic threshold model, updates the threshold parameters, and re-collects multi-source data for the circuit system after short-circuit protection.

[0054] In this embodiment, it should be specifically explained that the progressive recovery is to gradually restore the voltage in the fault area in 10% steps after the short circuit is eliminated, with each step interval being 1 μs.

[0055] S5. Data interaction: transmit the short-circuit event related data and the generated short-circuit protection strategy to the user information segment, providing the user with reference data for making adjustment measures.

[0056] As attached Figure 2 As shown, this embodiment provides a short circuit protection system for a multi-threaded integrated circuit, comprising: The multi-source data acquisition module collects thread-level current waveform, voltage fluctuation and temperature gradient data in real time through high-frequency sampling sensors integrated in each thread power supply pin, synchronously obtains chip load status, and constructs multi-dimensional raw data streams; it uses anti-noise coding technology and fault-tolerant interpolation algorithms to ensure data integrity and robustness; The indicator calculation module calculates the influence coefficient of current layer data, thread layer data, scheduling layer data and power supply network layer data respectively based on the multi-source original data collected by the multi-source data acquisition module through physical coupling modeling and nonlinear function design, and constructs four types of core protection decision-making features; The short-circuit protection strategy generation module selects the autonomous impact coefficient hierarchical trigger mechanism based on the four types of core protection decision-making characteristics obtained by the indicator calculation module to avoid the comprehensive value blurring the risk characteristics of each level, and then generates a short-circuit protection strategy; The self-healing recovery and state feedback module generates a protection strategy for short-circuit protection according to the short-circuit protection strategy generation module, and then performs progressive recovery and model iteration, feeds back short-circuit event-related data to the LSTM dynamic threshold model, updates the threshold parameters, and re-collects multi-source data for the circuit system after short-circuit protection; The data interaction module transmits the short-circuit event related data and the generated short-circuit protection strategy to the user information segment, providing the user with reference data for making adjustment measures.

[0057] Secondly: In the drawings of the embodiments disclosed in the present invention, only the structures related to the embodiments disclosed in the present invention are involved, and other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of the present invention can be combined with each other; Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A short circuit protection method for a multi-threaded integrated circuit, characterized in that: include: S1. Multi-source data acquisition: Through the high-frequency sampling sensor integrated in each thread power supply pin, the thread-level current waveform, voltage fluctuation and temperature gradient data are collected in real time, the chip load status is obtained synchronously, and a multi-dimensional raw data stream is constructed; anti-noise coding technology and fault-tolerant interpolation algorithm are used to ensure data integrity and robustness; S2, indicator calculation, based on the multi-source raw data collected in S1, through physical coupling modeling and nonlinear function design, calculate the current layer data influence coefficient, thread layer data influence coefficient, scheduling layer data influence coefficient and power supply network layer data influence coefficient respectively, and construct four types of core protection decision-making characteristics; S3, short-circuit protection strategy generation, based on the four types of core protection decision-making characteristics obtained in S2, select the autonomous influence coefficient hierarchical trigger mechanism to avoid the comprehensive value blurring the risk characteristics of each level, and then generate the short-circuit protection strategy; S4, self-healing recovery and status feedback, short-circuit protection is performed according to the protection strategy generated in S3, and then progressive recovery and model iteration are performed, the short-circuit event-related data is fed back to the LSTM dynamic threshold model, the threshold parameters are updated, and multi-source data is collected again for the circuit system after short-circuit protection; S5. Data interaction: transmit the short-circuit event related data and the generated short-circuit protection strategy to the user information segment, providing the user with reference data for making adjustment measures.

2. The short circuit protection method for a multi-threaded integrated circuit according to claim 1, characterized in that: The multi-dimensional original data stream includes current layer data, thread layer data, scheduling layer data and power supply network layer data.

3. The short circuit protection method for a multi-threaded integrated circuit according to claim 2, characterized in that: The current layer data includes the power rail voltage drop, denoted as ΔVd; the effective value of the current, denoted as Ir; the measured impedance value at the resonant frequency, denoted as Z(fr); the duration of current exceeding the standard, denoted as To; the thread layer data includes the core temperature gradient, denoted as ▽T; the hot spot diffusion rate, denoted as vh; the number of shared resource contention times, denoted as C; the scheduling layer data includes the task deadline, denoted as Td; the on-chip network bandwidth utilization, denoted as Un; the CPU resource discreteness, denoted as σc; the GPU resource discreteness, denoted as σg; the voltage disturbance caused by migration, denoted as ΔV; the power supply network layer data includes the number of effective power supply paths, denoted as Np; the path impedance matching degree, denoted as ρZ; the total number of power supply paths, denoted as Nt; the short-circuit current propagation speed, denoted as vf; the voltage coupling coefficient, denoted as kc, and the duration of current exceeding the standard, denoted as To.

4. The short circuit protection method for a multi-threaded integrated circuit according to claim 1, characterized in that: The current layer data impact coefficient reflects the instantaneous power anomaly through the product of voltage drop and current, the impedance attenuation exponential term amplifies the low impedance risk, and the time square root term balances the impact of short-term spikes and continuous overload, realizing multi-physical field coupling modeling of current-voltage-impedance-time, which is used to quantify the current layer short circuit risk.

5. The short circuit protection method for a multi-threaded integrated circuit according to claim 1, characterized in that: The thread-level data impact coefficient characterizes the urgency of thermal runaway through the product of temperature gradient and hotspot diffusion rate. The logarithmic function of resource contention times suppresses the numerical explosion in high-concurrency scenarios, and the thread-level risk is evaluated through the heat-time-resource ternary relationship.

6. The short circuit protection method for a multi-threaded integrated circuit according to claim 1, characterized in that: The scheduling layer data impact coefficient measures the scheduling urgency through the ratio of task deadline to bandwidth utilization, the square root of resource discreteness suppresses the impact of fragmentation, and the hyperbolic tangent function constrains the voltage disturbance amplitude, thereby achieving coordinated optimization of real-time performance, resource efficiency, and power supply stability.

7. The short circuit protection method for a multi-threaded integrated circuit according to claim 1, characterized in that: The power supply network layer data impact coefficient evaluates the network redundancy capability by multiplying the effective path proportion by the impedance matching degree, the coupling term of the fault propagation speed and the square root of time quantifies the diffusion risk, and the reconstruction success rate is predicted by the path-impedance-speed ternary model.

8. The short circuit protection method for a multi-threaded integrated circuit according to claim 1, characterized in that: The specific steps of the short-circuit protection strategy generation step are as follows: First, set the hierarchical thresholds and priorities, and generate four core thresholds based on historical data and experimental data, namely, the current layer data impact coefficient threshold, the thread layer data impact coefficient threshold, the scheduling layer data impact coefficient threshold, and the power supply network layer data impact coefficient threshold. Then, prioritize them according to the priority of power supply network layer > current layer > thread layer > scheduling layer. Then, perform real-time monitoring and parallel evaluation, and make parallel judgments based on the real-time values ​​of the current layer data impact coefficient, thread layer data impact coefficient, scheduling layer data impact coefficient, and power supply network layer data impact coefficient obtained by S2, and then generate a protection action strategy according to the priority. The current layer data impact coefficient threshold is calculated by building a test environment, injecting a step-by-step increasing short-circuit current, recording the CLIF value and the critical point of chip damage, taking 80% of the critical value to calculate the current layer data impact coefficient at this time, and then averaging it with the mean of the historical current layer data impact coefficient as the current layer data impact coefficient threshold; The thread layer data impact coefficient threshold is calculated by gradually increasing the core load in the high temperature aging test until a transistor leakage failure occurs, recording the TLIF critical value, calculating the thread layer data impact coefficient at this time, and then averaging it with the mean of the historical thread layer data impact coefficient as the thread layer data impact coefficient threshold; The scheduling layer data impact coefficient threshold is calculated by gradually increasing the task load in the resource fragmentation scenario until the task times out, recording the SLIF critical value, calculating the scheduling layer data impact coefficient at this time, and then averaging it with the mean of the historical scheduling layer data impact coefficient as the scheduling layer data impact coefficient threshold; The power supply network layer data impact coefficient threshold is obtained by artificially creating a power supply network short circuit, measuring the PLIF and system crash associated fuse trigger point, calculating the power supply network layer data impact coefficient at this time, and then averaging it with the mean of the historical power network layer data impact coefficient as the power supply network layer data impact coefficient threshold.

9. The short circuit protection method for a multi-threaded integrated circuit according to claim 8, characterized in that: The parallel judgment is specifically as follows: When the power supply network layer data impact coefficient is less than the power supply network layer data impact coefficient threshold, the power supply of the faulty thread is cut off, a reverse current is injected, the global power supply of the chip is immediately cut off, and the coordinates of the faulty area are recorded in a non-volatile memory; Send an interrupt signal to the external controller, waiting for human intervention; When the current layer data influence coefficient is greater than the current layer data influence coefficient threshold, the power supply of the faulty thread is cut off, a reverse current is injected, and the GaN switch of the faulty thread is turned off within ≤10ns; Inject reverse current into adjacent threads to offset short-circuit current; Mark the faulty thread as disabled and continue to monitor the current layer data impact coefficient until it is less than 20% of the current layer data impact coefficient threshold; When the thread layer data impact coefficient is greater than the thread layer data impact coefficient threshold, migrate the thread to the spare core, start active cooling, suspend the faulty thread task, and migrate the context to the spare core through the silicon interposer high-speed link; after the migration is completed, reset the original core temperature sensor and release the shared resource lock; When the scheduling layer data impact coefficient is greater than the scheduling layer data impact coefficient threshold, the task scheduling priority is increased and resource allocation is optimized; task priority is dynamically increased and allocated to cores with resource discreteness < 0.2; and the bandwidth occupancy rate of non-real-time tasks is limited; In other cases, keep monitoring.

10. A short circuit protection system for a multi-threaded integrated circuit, used to implement the short circuit protection method for a multi-threaded integrated circuit as claimed in any one of claims 1 to 9, characterized in that: include: The multi-source data acquisition module collects thread-level current waveform, voltage fluctuation and temperature gradient data in real time through high-frequency sampling sensors integrated in each thread power supply pin, synchronously obtains chip load status, and constructs multi-dimensional raw data streams; it uses anti-noise coding technology and fault-tolerant interpolation algorithms to ensure data integrity and robustness; The indicator calculation module calculates the influence coefficient of current layer data, thread layer data, scheduling layer data and power supply network layer data respectively based on the multi-source original data collected by the multi-source data acquisition module through physical coupling modeling and nonlinear function design, and constructs four types of core protection decision-making features; The short-circuit protection strategy generation module selects the autonomous impact coefficient hierarchical trigger mechanism based on the four types of core protection decision-making characteristics obtained by the indicator calculation module to avoid the comprehensive value blurring the risk characteristics of each level, and then generates a short-circuit protection strategy; The self-healing recovery and state feedback module generates a protection strategy for short-circuit protection according to the short-circuit protection strategy generation module, and then performs progressive recovery and model iteration, feeds back short-circuit event-related data to the LSTM dynamic threshold model, updates the threshold parameters, and re-collects multi-source data for the circuit system after short-circuit protection; The data interaction module transmits the short-circuit event related data and the generated short-circuit protection strategy to the user information segment, providing the user with reference data for making adjustment measures.

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