SVPWM Inverter Neutral Point Potential Balance and Low Common-Mode Voltage Modulation Method and System

Abstract

The present invention relates to the technical field of inverter pulse width modulation, and specifically to a modulation method and system for neutral point potential balance and low common mode voltage of an SVPWM inverter. The method includes: determining basic voltage vectors based on different switching states of an NPC three-level inverter; respectively determining the neutral point currents of each basic voltage vector, and determining the basic voltage vectors that cause neutral point potential offset; combining with large vectors and zero vectors to perform mode division of a single vector space region; determining an expected current according to the DC side capacitor voltage of the inverter, and constructing an objective function based on the expected current; performing region judgment according to the synthesized voltage vector output, determining the corresponding optimal division mode, obtaining each basic voltage vector of the synthesized voltage vector and the corresponding duty cycle, and determining the switching sequence to obtain a PWM wave. While achieving neutral point potential balance and common mode voltage suppression of the NPC three-level inverter, the switching frequency of the inverter is effectively reduced, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of inverter pulse width modulation, and in particular, to a modulation method and system for neutral point potential balance and low common-mode voltage of an SVPWM inverter. Background Art

[0002] Neutral Point Clamped (NPC) three-level inverters are widely used in renewable energy generation, motor drive and other applications because of their advantages such as small voltage stress on switching devices, high output efficiency, and low harmonic distortion rate of output voltage. However, NPC three-level inverters have problems of unbalanced neutral point potential and large common-mode voltage. At present, although some researchers use Space Vector Pulse Width Modulation (SVPWM) method to solve the neutral point potential and common-mode voltage problems of NPC three-level inverters, there are still the following defects:

[0003] For the problem of unbalanced neutral point potential of NPC three-level inverters, most traditional SVPWM strategies use redundant small vectors to adjust the neutral point potential. However, this method has insufficient ability to suppress the neutral point potential fluctuation under high modulation index and low power factor. Therefore, someone proposed the Virtual Space Vector Pulse Width Modulation (VSVPWM) strategy. This strategy synthesizes a virtual space vector by selecting appropriate basic voltage vectors, so that the average neutral point current during the action of the virtual vector is zero, thereby eliminating the neutral point potential fluctuation generated by the algorithm itself and achieving neutral point potential balance. However, the switching frequency of the inverter increases by 1 / 3, and the harmonic content also increases. Some people also proposed a hybrid modulation algorithm based on these two strategies to achieve complete control of the neutral point potential of NPC three-level inverters, and can obtain lower switching losses and harmonic content. However, the hybrid control algorithm is computationally complex and difficult to implement.

[0004] These solutions all use positive small vectors with large common-mode voltage, making the amplitude of the common-mode voltage output by the NPC three-level inverter 1 / 3 of the DC side voltage. For a motor, the large high-frequency common-mode voltage will generate a large motor bearing current through the capacitance coupling between the stator and the rotor, promoting the aging of the motor insulation, increasing the mechanical wear between the bearings, and shortening the service life of the motor. In addition, the high-frequency common-mode voltage will generate high-frequency leakage current, thereby generating electromagnetic interference and affecting the normal operation of surrounding electrical equipment. Summary of the Invention

[0005] To solve the above problems, the first aspect of the present invention provides a modulation method for neutral point potential balance and low common-mode voltage of an SVPWM inverter, including:

[0006] S1. Determine the basic voltage vectors based on the different switching states of the NPC three-level inverter, and divide the vector space according to the basic voltage vectors;

[0007] S2. Determine the midpoint current of the NPC three-level inverter in the independent switching state for each basic voltage vector respectively, and determine the basic voltage vectors that cause the midpoint potential offset based on the midpoint current;

[0008] S3. Take the basic voltage vectors that cause the midpoint potential offset in a single vector space region as independent switching states, and combine them with the large vectors and zero vectors to perform the mode division of a single vector space region;

[0009] S4. Determine the desired current according to the DC-side capacitor voltage of the NPC three-level inverter, and construct an objective function based on the desired current;

[0010] S5. Perform region judgment according to the synthesized voltage vector required to be output by the NPC three-level inverter, determine the corresponding optimal division mode based on the objective function, obtain each basic voltage vector of the synthesized voltage vector and the corresponding duty cycle, and determine the switching sequence to obtain the PWM wave.

[0011] In the implementation manner of the first aspect, the mode division of a single vector space region described in S3 is specifically as follows:

[0012] S3.1. Respectively take the end points of the large vectors in a single vector space region as vertices, connect the vertex with the end point of the small vector on the opposite side as the dividing line, and divide the single vector space region into two triangular regions to obtain the first division mode and the second division mode;

[0013] S3.2. Divide the single vector space region into two triangular regions with the medium vector as the dividing line to obtain the third division mode.

[0014] The specific formula of the objective function described in S4 is:

[0015] ,

[0016] In the formula, i X , d X represent the midpoint current and duty cycle corresponding to the voltage vector U X ; i NP * is the desired current; f is the objective function value.

[0017] The formula of the desired current is:

[0018] ,

[0019] Wherein, i NP * is the desired current, T s represents the switching period; u c1 and u c2 are the voltages across the DC-side capacitors c 1 c 2 respectively; C is c 1 c 2's capacitance value, and c1 and c2 are the same capacitor.

[0020] In the implementation of the first aspect, the region determination according to the synthesized voltage vector required to be output by the NPC three-level inverter in S5 is specifically as follows:

[0021] S5.1.1. Determine the vector space region to which the synthesized voltage vector of the NPC three-level inverter belongs;

[0022] S5.1.2. Perform coordinate transformation on the synthesized voltage vector to determine the coordinate value of the synthesized voltage vector in the 60° coordinate system;

[0023] S5.1.3. Perform region determination according to the division boundaries of the three division modes of the vector space region to which it belongs, and determine the region where the synthesized voltage vector is located under different division modes.

[0024] The method for determining the corresponding optimal division mode based on the objective function in S5 is specifically as follows:

[0025] S5.2.1. Determine the basic voltage vectors used for the synthesized voltage vector according to the regions where the synthesized voltage vector is located under different division modes;

[0026] S5.2.2. Calculate the duty ratios of the basic voltage vectors that have been determined under different division modes for synthesizing the voltage vector respectively;

[0027] S5.2.3. Substitute the basic voltage vectors and duty ratios obtained by calculation under different division modes into the objective function, and determine the optimal division mode according to the objective function values of each division mode.

[0028] The method for determining the optimal division mode according to the objective function values of each division mode is specifically as follows:

[0029] Multiply the duty ratios of the basic voltage vectors of each division mode by the corresponding midpoint current to obtain the offset values of the midpoint potential under different division modes in the same vector space region respectively;

[0030] Determine the difference mode value between the offset value of the midpoint potential and the expected current for the three partitioning modes in the same vector space region according to the objective function;

[0031] Compare the difference mode values of the three partitioning modes, and select the partitioning mode with the smallest difference mode value as the optimal partitioning mode.

[0032] In the implementation manner of the first aspect, the basic voltage vectors causing the midpoint potential offset are determined based on the midpoint current in S2, and the specific method is as follows:

[0033] Based on the independent switching states of the basic voltage vectors, determine the equivalent circuits of the switching states of the basic voltage vectors;

[0034] Based on the equivalent circuit diagrams of the basic voltage vectors, determine the corresponding midpoint currents;

[0035] According to the midpoint current, filter out the basic voltage vectors with non-zero midpoint current, that is, the basic voltage vectors causing the midpoint potential offset.

[0036] The second aspect provides a system for balancing the midpoint potential and modulating low common-mode voltage based on SVPWM inverters, which implements the method for balancing the midpoint potential and modulating low common-mode voltage based on SVPWM inverters as described above, including:

[0037] A basic vector module, which is used to determine basic voltage vectors based on different switching states of an NPC three-level inverter, and perform regional partitioning of the vector space according to the basic voltage vectors;

[0038] A midpoint potential module, which is used to determine the midpoint currents of the NPC three-level inverter in the independent switching states of the basic voltage vectors respectively, and determine the basic voltage vectors causing the midpoint potential offset based on the midpoint currents;

[0039] A mode partitioning module, which is used to take the basic voltage vectors causing the midpoint potential offset in a single vector space region as independent switching states, and combine them with large vectors and zero vectors to perform mode partitioning of a single vector space region;

[0040] A function construction module, which is used to determine the expected current according to the DC-side capacitor voltage of the NPC three-level inverter, and construct an objective function based on the expected current;

[0041] A modulation module, which is used to perform region judgment according to the synthesized voltage vector required to be output by the NPC three-level inverter, determine the corresponding optimal partitioning mode based on the objective function, obtain the basic voltage vectors and corresponding duty cycles of the synthesized voltage vector, and determine the switching sequence to obtain the PWM wave.

[0042] A third aspect provides a device for balancing the neutral point potential and modulating low common-mode voltage of an SVPWM inverter, including a processor and a memory. When the processor executes the program data saved in the memory, the method for balancing the neutral point potential and modulating low common-mode voltage of the SVPWM inverter as described above is implemented.

[0043] The beneficial effects are as follows: The method and system for balancing the neutral point potential and modulating low common-mode voltage of the SVPWM inverter provided by the present invention optimize the preselected basic voltage vectors, limit the amplitude of the common-mode voltage to 1 / 6 of the DC-side voltage. Secondly, by using the characteristics of the low common-mode voltage switching states with three neutral point potential deviations in each vector space region, three division modes of the vector space region are proposed, and by constructing the objective function of the neutral point current, a division mode with the neutral point current closest to the expected neutral point current is selected, thereby realizing the active regulation of the neutral point potential. At the same time, according to the region division mode of the present invention, the number of switching tube operations is only 6 or 8 times, while the number of switching operations of the traditional low common-mode voltage VSVPWM algorithm in any region is greater than or equal to 8 times. The present invention effectively reduces the switching frequency of the inverter and reduces the switching loss while achieving the neutral point potential balance and common-mode voltage suppression of the NPC three-level inverter. Description of the Drawings

[0044] Figure 1 It is a schematic flow chart of the method of this application;

[0045] Figure 2 It is a circuit diagram of an NPC three-level inverter;

[0046] Figure 3 It is a basic voltage space vector diagram of an NPC three-level inverter;

[0047] Figure 4 It is an equivalent circuit diagram of the independent switching states of each basic voltage vector. Among them, a is the equivalent circuit diagram of the large vector PNN; b is the equivalent circuit diagram of the zero vector OOO; c is the equivalent circuit diagram of the medium vector PON; d is the equivalent circuit diagram of the small vector OON;

[0048] Figure 5 It is a schematic diagram of the three division modes of this application;

[0049] Figure 6 It is a comparison schematic diagram of the average number of switchings in any switching period under multiple modulation degrees between the five-segment PWM modulation method of the present invention and the RCMV_VSVPWM algorithm based on virtual voltage vectors;

[0050] Figure 7 It is a schematic diagram of the steady-state waveform of the method of the present invention;

[0051] Figure 8Schematic diagram of the common-mode voltage waveform of the method of the present invention;

[0052] Figure 9 It is a schematic diagram of the dynamic process of eliminating the midpoint potential deviation of the present invention. Specific embodiments

[0053] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0054] See Figure 1 , this embodiment provides a method for midpoint potential balance and low common-mode voltage modulation based on an SVPWM inverter, and the specific implementation steps are as follows:

[0055] S1. Determine the basic voltage vectors based on the different switching states of the NPC three-level inverter, and divide the vector space according to the basic voltage vectors;

[0056] As Figure 2 , Figure 3 shown, the NPC three-level inverter determines the basic voltage vectors according to the switching states of the power devices of each phase leg. The basic voltage vectors include zero vectors, small vectors, medium vectors, and large vectors. Among them, the zero vectors are represented as PPP, OOO, NNN; the small vectors are represented as POO and ONN, PPO and OON, OPO and NON, OPP and NOO, OOP and NNO, POP and NON; the medium vectors are represented as PON, OPN, NPO, NOP, ONP, PNO; the large vectors are represented as PNN, PPN, NPN, NPP, NNP, PNP.

[0057] Divide the vector space according to the basic voltage vectors. With the zero vector as the center and the α-axis as the reference, there is one region between two adjacent large vectors, and it is divided into 6 regions in the counterclockwise direction, that is Figure 3 in which I, II, III, IV, V, and VI represent each vector space region respectively.

[0058] S2. Determine the midpoint current of the NPC three-level inverter in the independent switching state for each basic voltage vector, and determine the basic voltage vectors that cause the midpoint potential deviation based on the midpoint current;

[0059] As Figure 2 shown, the power devices of the NPC three-level inverter are provided with clamping diodes. Due to the existence of the clamping diodes, the NPC three-level inverter has the ability to output zero level, but at the same time, it also causes the charging and discharging phenomena of the DC-side capacitors, leading to the midpoint potential deviation.

[0060] The specific method for determining the basic voltage vectors that cause the midpoint potential deviation based on the midpoint current is as follows:

[0061] Determine the equivalent circuit of the switching states of each basic voltage vector based on the independent switching states of each basic voltage vector;

[0062] Determine the corresponding midpoint current based on the equivalent circuit diagrams of each basic voltage vector;

[0063] According to the midpoint current, filter out the basic voltage vectors with non-zero midpoint current, that is, the basic voltage vectors causing the midpoint potential offset.

[0064] This application takes the basic voltage vectors PNN, PON, OON, and OOO in the large sector region I as examples. As Figure 4 shown, Figure 4 In (a), the equivalent circuit of the large vector PNN Figure 3 None of the phases are connected to the midpoint potential, and the midpoint current is 0; Figure 4 In (b), it is the equivalent circuit diagram of the zero vector 000. Assuming a balanced three-phase load, the midpoint current i NP = i A + i B + i C = 0; Figure 4 In (c) and (d), they are the equivalent circuit diagrams of the medium vector PON and the small vector OON respectively. It can be seen from the figure that there is one or two phases connected to the midpoint potential, and the current flowing through the midpoint potential is not 0, which causes the charging and discharging phenomenon of the DC-side capacitor. According to the volt-ampere characteristic of the capacitor, the voltage across the capacitor will change. Therefore, the medium vector and the small vector affect the midpoint voltage offset.

[0065] At the same time, the common-mode voltage u CMV , and its definition is:

[0066] ,

[0067] In the formula, u AO , u BO , u CO respectively represent the voltage differences between phase A, phase B, phase C and the DC-side midpoint.

[0068] Combined with Figure 3 , taking the large sector region I as an example, the low common-mode voltage switching states that affect the midpoint voltage in the large sector region I are the small vectors POO, OON, and the medium vector PON. Similarly, there are also two small vectors and one medium vector in other large sector regions that affect the midpoint voltage offset.

[0069] S3. Take the basic voltage vectors that cause the midpoint potential shift in a single vector space region as independent switching states, and combine them with large vectors and zero vectors to perform the mode of a single vector space region, specifically as follows:

[0070] S3.1. Respectively take the ends of the large vectors in a single vector space region as vertices, connect the vertex with the end of the small vector on the opposite side as the dividing line, and divide the single vector space region into two triangular regions to obtain the first division mode and the second division mode;

[0071] S3.2. Take the medium vector as the dividing line to divide the single vector space region into two triangular regions to obtain the third division mode.

[0072] This application takes the vector space region Ⅰ as an example. As Figure 5 shown, in the vector space region Ⅰ, the basic voltage vectors that affect the midpoint potential are POO, PON, and OON, and the midpoint currents generated by them in the switching state are respectively -i A , i B , -i C . Therefore, the mode division of the vector space region Ⅰ is carried out according to the above method, and is respectively named mode 1, mode 2, and mode 3. Each mode contains a basic voltage vector for adjusting the midpoint potential, and it is combined with large vectors and zero vectors to realize the synthesis of the reference voltage.

[0073] S4. Determine the expected current according to the DC-side capacitor voltage of the NPC three-level inverter, and construct an objective function based on the expected current;

[0074] The formula for determining the expected current according to the DC-side capacitor voltage of the NPC three-level inverter is:

[0075] ,

[0076] where, i NP * is the expected current, T s represents the switching period; u c1 , u c2 are the voltages at both ends of the DC-side capacitors c 1, c 2 respectively; C is c 1, c 2's capacitance value, and c1 and c2 are the same capacitors.

[0077] When i NP* When < 0, u c2 > u c1 , it is necessary to reasonably increase u c1 and decrease u c2 , that is, remove the charge from the midpoint to reduce the deviation of the midpoint potential; when i NP * < 0, u c2 < u c1 , the midpoint charge quantity should be increased.

[0078] At the same time, a target function for midpoint potential control is constructed according to the expected current, and its formula is:

[0079] ,

[0080] In the formula, i X , d X represent the midpoint current and duty ratio corresponding to the voltage vector U X ; f is the target function value.

[0081] According to the constructed target function, the midpoint current and duty ratio under different division modes of a single vector space region are calculated respectively, and the difference is taken with the expected current. Based on the difference, the optimal division mode with the smallest difference between the midpoint current and the expected current is determined. The zero vector and large vector in this division mode are combined with the basic voltage vectors (small vectors or medium vectors) in the independent switch states and participate in modulation together to achieve optimal midpoint potential control.

[0082] S5. Determine the region according to the synthesized voltage vector required to be output by the NPC three-level inverter, and based on the target function, determine the corresponding optimal division mode, obtain each basic voltage vector of the synthesized voltage vector and the corresponding duty ratio, and determine the switching sequence to obtain the PWM (Pulse Width Modulation) wave;

[0083] The method for determining the region according to the synthesized voltage vector required to be output by the NPC three-level inverter is as follows:

[0084] S5.1.1. Determine the vector space region to which the synthesized voltage vector of the NPC three-level inverter belongs;

[0085] Determine the vector space region to which the synthesized voltage vector belongs according to the abscissa and ordinate of the synthesized voltage vector of the NPC three-level inverter in the rectangular coordinate system.

[0086] S5.1.2. Perform coordinate transformation on the synthesized voltage vector to determine the coordinate values of the synthesized voltage vector in the 60° coordinate system;

[0087] Taking vector space region I as an example in this application, perform coordinate transformation on the synthesized voltage vector. The components of the synthesized voltage vector on the g-h axes in the 60° coordinate system are:

[0088] ,

[0089] In the formula, u a , u b respectively represent the abscissa and ordinate of the synthesized voltage vector U ref in the rectangular coordinate system; u dc represents the DC side voltage value.

[0090] S5.1.3. Perform region judgment according to the division boundaries of the three division modes of the vector space region to which it belongs, and determine the region where the synthesized voltage vector is located under different division modes;

[0091] In vector space region I, the division boundaries of the three division modes l 1. l 2. l 3 are respectively expressed as:

[0092] ,

[0093] ,

[0094] ,

[0095] According to the division boundaries of the three division modes, the specific region position where the synthesized voltage vector is located can be judged. Similarly, other large sector regions can be obtained by rotating large sector region I.

[0096] According to the determined region where the synthesized voltage vector of the NPC three-level inverter is located, determine the corresponding optimal division mode based on the objective function. The specific method is as follows:

[0097] S5.2.1. Determine the basic voltage vectors used for the synthesized voltage vector according to the regions where the synthesized voltage vector is located under different division modes;

[0098] This application takes Figure 5Taking the three partitioning modes of the vector space region Ⅰ as an example, the synthesized voltage vector is partitioned into the region R1.1, and the basic voltage vectors of the region R1.1 include U OOO 、 U POO 、 U PPN ,

[0099] S5.2.2. Calculate the duty ratios of the synthesized voltage vectors for the determined basic voltage vectors under different partitioning modes respectively;

[0100] According to the volt-second balance principle, the equation can be established as:

[0101] ,

[0102] In the formula, d 1、 d 2、 d 3 respectively represent the duty ratios of the voltage vectors U OOO 、 U POO 、 U PPN ; U ref represents the synthesized voltage vector.

[0103] The above formula is expressed in the g-h coordinate system as:

[0104] ,

[0105] From the above formula, it can be obtained that:

[0106] 。

[0107] Similarly, the duty ratios of the basic voltage vectors when the reference vector is in the regions of other partitioning modes can be calculated.

[0108] S5.2.3. Substitute the calculated basic voltage vectors and duty ratios under different partitioning modes into the objective function, and determine the optimal partitioning mode according to the objective function values of each partitioning mode.

[0109] The specific method for determining the optimal partitioning mode according to the objective function values of each partitioning mode is as follows:

[0110] Multiply the duty ratios of the basic voltage vectors of each partitioning mode by the corresponding midpoint current to obtain the offset values of the midpoint potentials of different partitioning modes in the same vector space region respectively;

[0111] Determine the difference modulus values between the offset values of the midpoint potentials and the expected current for the three partitioning modes in the same vector space region according to the objective function;

[0112] The differential mode values of the three division modes are compared, and the division mode with the smallest differential mode value is selected as the optimal division mode.

[0113] According to the determined optimal division mode, the basic voltage vector and the corresponding duty cycle required for synthesizing the voltage vector are obtained, the switching sequence is determined, and the PWM wave is generated based on the switching sequence.

[0114] When determining the switching sequence, it also includes that the switch states P and N cannot be directly switched to prevent the upper and lower bridge arms from being directly connected, so as to improve the stability of the inverter system; and the number of power device switch tube actions of each phase bridge arm of the NPC three-level inverter is the least, thereby reducing switching losses. This application takes vector space region I as an example, and the optimal switching sequence of the vector space region I is shown in the following table:

[0115]

[0116] Once the duty cycle, optimal division mode and switching sequence of each synthetic voltage vector are determined, a PWM wave modulation signal can be generated.

[0117] Figure 6 It is a schematic diagram comparing the average number of switches in any switching cycle under multiple modulation indices between the five-segment PWM modulation method (FS_SVPWM) provided by the present invention and the RCMV_VSVPWM method based on a virtual voltage vector. It can be seen that the method of the present invention effectively reduces the number of switch tube actions of the inverter.

[0118] Figure 7 , Figure 8 and Figure 9 This is an experimental waveform diagram of the FS_SVPWM of the present invention when the DC side voltage is 200V. It can be seen that the present invention can well suppress the midpoint potential fluctuation of the NPC three-level inverter, effectively reduce the common-mode voltage amplitude, and can quickly eliminate the midpoint potential deviation.

[0119] In addition, the present invention also provides a SVPWM inverter midpoint potential balance and low common mode voltage modulation system, comprising:

[0120] A basic vector module is used to determine a basic voltage vector based on different switching states of the NPC three-level inverter, and to divide the vector space into regions according to the basic voltage vector;

[0121] A midpoint potential module is used to determine the midpoint current of the NPC three-level inverter of each basic voltage vector in an independent switching state, and determine the basic voltage vector causing the midpoint potential shift based on the midpoint current;

[0122] The mode division module is configured to use the basic voltage vectors that cause the midpoint potential offset in a single vector space region as independent switching states, and combine them with large vectors and zero vectors to perform mode division for a single vector space region;

[0123] The function construction module is configured to determine the desired current according to the DC-side capacitor voltage of the NPC three-level inverter, and construct an objective function based on the desired current;

[0124] The modulation module is configured to perform region judgment according to the synthesized voltage vector required to be output by the NPC three-level inverter, determine the corresponding optimal division mode based on the objective function, obtain each basic voltage vector of the synthesized voltage vector and the corresponding duty cycle, and determine the switching sequence to obtain the PWM wave.

[0125] Finally, a modulation device for midpoint potential balance and low common-mode voltage based on the SVPWM inverter is also provided, including a processor and a memory. Among them, when the processor executes the program data stored in the memory, the method for midpoint potential balance and low common-mode voltage modulation based on the SVPWM inverter as described above is implemented.

Claims

1. A modulation method for neutral point potential balance and low common mode voltage of an SVPWM inverter, characterized in that Including: S1. Determine the basic voltage vectors based on different switching states of the NPC three-level inverter, and divide the vector space according to the basic voltage vectors; S2. Determine the midpoint current of the NPC three-level inverter in the independent switching state for each basic voltage vector, and determine the basic voltage vectors that cause the midpoint potential offset based on the midpoint current; S3. Take the basic voltage vectors that cause the midpoint potential offset in a single vector space region as independent switching states, and combine them with the large vectors and zero vectors for pattern division of a single vector space region. Specifically: S3.

1. Take the ends of the large vectors in a single vector space region as vertices respectively, connect the vertex with the end of the small vector on the opposite side as the dividing line, divide the single vector space region into two triangular regions, and obtain the first division pattern and the second division pattern; S3.

2. Divide the single vector space region into two triangular regions with the medium vector as the dividing line to obtain the third division pattern; S4. Determine the desired current according to the DC-side capacitor voltage of the NPC three-level inverter, and construct an objective function based on the desired current. The formula of the objective function is: ， ， In the formula, i X , d X represent the voltage vectors U X corresponding midpoint current and duty cycle; i NP * is the desired current; f is the objective function value; T s represents the switching period; u c1 and u c2 are the voltages across the DC-link capacitors c 1 c and C is c 1 c and 2, respectively. c1 and c2 are the same capacitor; S5. Perform region judgment according to the synthesized voltage vector required to be output by the NPC three-level inverter, determine the corresponding optimal division pattern based on the objective function, obtain each basic voltage vector of the synthesized voltage vector and the corresponding duty cycle, and determine the switching sequence to obtain the PWM wave; The region judgment according to the synthesized voltage vector required to be output by the NPC three-level inverter is specifically: S5.1.

1. Determine the vector space region to which the synthesized voltage vector of the NPC three-level inverter belongs; S5.1.

2. Perform coordinate transformation on the synthesized voltage vector to determine the coordinate value of the synthesized voltage vector in the 60° coordinate system; S5.1.

3. Perform region judgment according to the division boundaries of the three division patterns of the vector space region to which it belongs, and determine the region where the synthesized voltage vector is located under different division patterns; The determination of the corresponding optimal division pattern based on the objective function is specifically: S5.2.

1. Determine the basic voltage vectors used for the synthesized voltage vector according to the region where the synthesized voltage vector is located under different division patterns; S5.2.

2. Calculate the duty cycle of the basic voltage vectors that have been determined under different division patterns for synthesizing the voltage vector respectively; S5.2.

3. Substitute the basic voltage vectors and duty cycles obtained by calculation under different division patterns into the objective function, multiply the duty cycle of the basic voltage vectors of each division pattern by the corresponding midpoint current, and respectively obtain the offset values of the midpoint potential under different division patterns in the same vector space region; determine the difference modulus value between the offset value of the midpoint potential and the desired current under the three division patterns in the same vector space region; compare the difference modulus values of the three division patterns, and select the division pattern with the smallest difference modulus value as the optimal division pattern.

2. The SVPWM inverter neutral point potential balance and low common mode voltage modulation method according to claim 1, characterized in that The specific method for determining the basic voltage vectors that cause the midpoint potential offset based on the midpoint current in S2: Based on the independent switching states of each basic voltage vector, determine the equivalent circuit of the switching state of each basic voltage vector; Based on the equivalent circuit diagram of each basic voltage vector, determine the corresponding midpoint current; According to the midpoint current, screen out the basic voltage vectors with non-zero midpoint current, that is, the basic voltage vectors causing the midpoint potential offset.

3. A SVPWM inverter midpoint potential balance and low common-mode voltage modulation system for implementing the SVPWM inverter midpoint potential balance and low common-mode voltage modulation method according to any one of claims 1-2, characterized in that, Including: A basic vector module, which is used to determine basic voltage vectors based on different switching states of an NPC three-level inverter, and perform regional division of the vector space according to the basic voltage vectors; A midpoint potential module, which is used to determine the midpoint current of the NPC three-level inverter in an independent switching state for each basic voltage vector respectively, and determine the basic voltage vectors causing the midpoint potential offset based on the midpoint current; A mode division module, which is used to use the basic voltage vectors causing the midpoint potential offset in a single vector space region as independent switching states, and combine them with large vectors and zero vectors to perform mode division of a single vector space region; A function construction module, which is used to determine the desired current according to the DC-side capacitor voltage of the NPC three-level inverter, and construct an objective function based on the desired current; A modulation module, which is used to perform regional judgment according to the synthesized voltage vector required to be output by the NPC three-level inverter, and determine the corresponding optimal division mode based on the objective function, obtain each basic voltage vector of the synthesized voltage vector and the corresponding duty cycle, and determine the switching sequence to obtain the PWM wave.

4. A device for balancing the neutral point potential and modulating low common-mode voltage of an SVPWM inverter, characterized in that, Including a processor and a memory. Among them, when the processor executes the program data stored in the memory, it implements the SVPWM inverter midpoint potential balance and low common-mode voltage modulation method according to any one of claims 1-2.

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