Charge pump phase-locked loop circuit, radar and charge pump phase-locked loop locking control method

Abstract

The invention relates to the technical field of integrated circuits, in particular to a charge pump phase-locked loop circuit, a radar and a charge pump phase-locked loop locking control method.The circuit comprises a charge pump, the charge pump comprises a first branch circuit, a second branch circuit, a third branch circuit and a fourth branch circuit, the frequency sweeping state refers to the state when the frequency of the signal output by the phase-locked loop is linearly changed; the at least one second branch is connected to the first branch under the condition that the hopping amplitude of the frequency of the signal output by the phase-locked loop is greater than or equal to a preset amplitude threshold value so as to increase the magnitude of the current output by the charge pump, and is disconnected with the first branch when the phase-locked loop enters a frequency sweeping state; the circuit can effectively shorten the locking time of the phase-locked loop when the phase-locked loop has relatively large frequency hopping, and is beneficial to improving the response speed and performance of a system.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a charge pump phase-locked loop circuit, a radar, and a charge pump phase-locked loop locking control method. Background Art

[0002] Charge Pump Phase-Locked Loop (CP-PLL) is used to generate frequency modulated waveforms and is widely used in speed and distance measurement. For example, in FMCW (Frequency Modulated Continuous Wave) radar, the charge pump phase-locked loop changes the frequency of the transmitted signal linearly over time to achieve accurate speed and distance measurement.

[0003] However, when the FMCW waveform has a large frequency jump (such as the frequency change of the sawtooth waveform, etc.), the phase-locked loop needs extra time to readjust and stabilize its phase lock state, which is the so-called stabilization time (locking time). This extra stabilization time causes the phase-locked loop to be unable to quickly recover to the desired frequency state after the frequency jump, thus affecting the response speed and performance of the system. Summary of the invention

[0004] The present invention provides a charge pump phase-locked loop circuit, a radar and a charge pump phase-locked loop locking control method to solve the problem in the prior art that the phase-locked loop cannot quickly recover to a desired frequency state after a frequency jump, resulting in the system response speed and performance being affected.

[0005] A charge pump phase-locked loop circuit provided by the present invention comprises: a charge pump, wherein the charge pump comprises:

[0006] A first branch, which outputs current when the phase-locked loop enters a frequency sweeping state, wherein the frequency sweeping state refers to a state in which the frequency of a signal output by the phase-locked loop changes linearly; and

[0007] At least one second branch is connected to the first branch to increase the current output by the charge pump when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, and is disconnected from the first branch when the phase-locked loop enters a frequency scanning state.

[0008] In one embodiment of the present invention, it further includes: a phase frequency detector, which is used to compare the phase difference and frequency difference between the input signal and the preset reference signal to output a positive pulse signal or a negative pulse signal;

[0009] The first branch includes: a first current source, a first switch, a second switch, and a second current source connected in sequence; one end of the second current source away from the second switch is grounded, and a connection point between the first switch and the second switch is an output end of the charge pump;

[0010] The first switch is turned on when receiving the positive pulse signal, and the second switch is turned on when receiving the negative pulse signal.

[0011] In one embodiment of the present invention, the second branch includes: a third current source, a third switch, a fourth switch, and a fourth current source connected in sequence;

[0012] A connection point between the third switch and the fourth switch is an output terminal of the charge pump, and both the third switch and the fourth switch are turned on when receiving a first control signal, and are turned off when receiving a second control signal;

[0013] The first control signal is sent by the external controller when it determines that the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, and the second control signal is sent by the external controller when it determines that the phase-locked loop enters a frequency sweep state.

[0014] In one embodiment of the present invention, the invention further comprises: a loop filter, which is used to reduce its own on-resistance to increase the loop bandwidth when receiving the first control signal, and restore its own on-resistance to the original state when receiving the second control signal;

[0015] The first control signal is sent by the external controller when it determines that the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, and the second control signal is sent by the external controller when it determines that the phase-locked loop enters a frequency sweep state.

[0016] In one embodiment of the present invention, the loop filter includes: a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth switch, and a sixth switch;

[0017] One end of the first capacitor is connected to the output end of the charge pump, and the other end of the first capacitor is grounded; one end of the second capacitor is connected to the output end of the charge pump, and the other end of the second capacitor is connected to one end of the first resistor, and the other end of the first resistor is grounded; the second resistor is connected in parallel with the first resistor, and the fifth switch is located between the second capacitor and the second resistor; one end of the third resistor is connected to the output end of the charge pump, and the other end of the third resistor is the output end of the loop filter; the fourth resistor is connected in parallel with the third resistor, and the sixth switch is located between the fourth resistor and the output end of the charge pump; one end of the third capacitor is connected to the third resistor, and the other end of the third capacitor is grounded;

[0018] The fifth switch and the sixth switch are both turned on when receiving the first control signal, and are turned off when receiving the second control signal.

[0019] In one embodiment of the present invention, the loop filter is further configured to reduce the resistance values ​​of the first resistor and the third resistor when receiving the first control signal, wherein the reduction range of the third resistor is greater than the reduction range of the first resistor;

[0020] When the second control signal is received, the resistance values ​​of the first resistor and the third resistor are restored to original resistance values.

[0021] In one embodiment of the present invention, it further includes:

[0022] A voltage-controlled oscillator, the input end of the voltage-controlled oscillator is connected to the output end of the loop filter, and is used to adjust its output frequency based on the voltage signal output by the loop filter, and output a signal of a corresponding frequency; the output end of the voltage-controlled oscillator is connected to the N-divider;

[0023] A signal generator, used to obtain a fractional frequency division ratio and an integer frequency division ratio, and transmit the fractional frequency division ratio to a signal modulator;

[0024] A signal modulator, configured to modulate the fractional frequency division ratio to obtain a corresponding integer sequence; the sum of the integer sequence and the integer frequency division ratio is a target frequency division ratio;

[0025] The frequency divider is used to perform a frequency division operation on the signal output by the voltage-controlled oscillator according to the target frequency division ratio to obtain a divided feedback signal, wherein the feedback signal is an input signal of a preset frequency detector and phase detector.

[0026] The present invention further provides a radar, comprising: a charge pump phase-locked loop circuit as described in any one of the above items.

[0027] The present invention also provides a charge pump phase-locked loop locking control method, comprising:

[0028] A charge pump is provided, the charge pump comprising: a first branch and at least one second branch;

[0029] When the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, the second branch is connected to the first branch to increase the current output by the charge pump, and when the phase-locked loop enters a frequency scanning state, the connection between the second branch and the first branch is disconnected.

[0030] In one embodiment of the present invention, the method further includes: when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, reducing the on-resistance of the preset loop filter to increase the loop bandwidth.

[0031] Beneficial effects of the present invention: The charge pump phase-locked loop circuit, radar and charge pump phase-locked loop locking control method provided by the present invention, the circuit is provided with a first branch and at least one second branch in the charge pump, the first branch is used to output current when the phase-locked loop enters the frequency sweeping state, the frequency sweeping state refers to the state when the signal frequency output by the phase-locked loop changes linearly; the second branch is used to connect to the first branch when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to the preset amplitude threshold, so as to increase the current output by the charge pump, and when the phase-locked loop enters the frequency sweeping state, disconnect the connection with the first branch. Through the above-mentioned setting, the locking time of the phase-locked loop with a large frequency jump can be effectively shortened, which is helpful to improve the system response speed and performance. It can be understood that by connecting the second branch to the first branch when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to the preset amplitude threshold, so as to increase the current output by the charge pump, the loop bandwidth of the phase-locked loop can be effectively increased and the locking time of the phase-locked loop can be reduced. Furthermore, during the period of increasing the current output by the charge pump, since the phase-locked loop is in a re-locking state, the output signal at this time will not be used by the system (such as a radar system, etc.) in which the charge pump phase-locked loop circuit is located, and the system performance will not be affected by the significant increase in the loop bandwidth. When the phase-locked loop is locked, that is, when the phase-locked loop enters the frequency sweeping state, the loop bandwidth can be restored to the original bandwidth by disconnecting the connection between the second branch and the first branch, thereby avoiding the phase noise caused by the increase in the loop bandwidth from affecting the system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a charge pump phase-locked loop circuit provided by an embodiment of the present invention;

[0033] Figure 2Another structural schematic diagram of a charge pump phase-locked loop circuit provided by an embodiment of the present invention;

[0034] Figure 3 A schematic diagram of the principle of locking control in a charge pump phase-locked loop circuit provided in one embodiment of the present invention;

[0035] Figure 4 A schematic diagram showing a time domain waveform comparison of the output frequencies of a charge pump phase-locked loop circuit provided by an embodiment of the present invention and a conventional charge pump phase-locked loop circuit;

[0036] Figure 5 This is a schematic structural diagram of an electronic device provided by the present invention. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0038] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0039] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0040] Combine the following Figures 1 to 5 , the charge pump phase-locked loop circuit, radar and charge pump phase-locked loop locking control method provided by the present invention are explained.

[0041] See also Figure 1 , Figure 1 A schematic diagram of a charge pump phase-locked loop circuit according to an embodiment of the present invention is shown in FIG. Figure 1 As shown, the charge pump phase-locked loop circuit includes:

[0042] A charge pump 120, wherein the charge pump 120 comprises:

[0043] A first branch, which outputs current when the phase-locked loop enters a frequency sweeping state, wherein the frequency sweeping state refers to a state in which the frequency of a signal output by the phase-locked loop changes linearly; and

[0044] At least one second branch is connected to the first branch to increase the current output by the charge pump when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, and is disconnected from the first branch when the phase-locked loop enters a frequency scanning state.

[0045] It should be noted that by performing the above-mentioned configuration in the charge pump 120, the locking time of the phase-locked loop can be effectively shortened when there is a large frequency jump, which helps to improve the system response speed and performance, has low cost, high flexibility, and strong real-time performance.

[0046] It should also be noted that the number of the second branches can be set according to actual needs, such as 1, 2, etc. The amplitude threshold can also be set according to actual conditions, which will not be described in detail here.

[0047] It is understandable that, in addition to the charge pump 120 , the charge pump phase-locked loop circuit may also include a phase frequency detector 110 (PFD), a loop filter 130 (LPF, Low-Pass Filter), and a voltage-controlled oscillator (VCO, Voltage-Controlled Oscillator) 140 and other devices.

[0048] Please refer to Figure 2 In some embodiments, the phase frequency detector 110 in the charge pump phase-locked loop circuit is used to compare the phase difference and frequency difference between the input signal (FB) and the preset reference signal (REF) to output a positive pulse signal (UP) or a negative pulse signal (DOWN);

[0049] The first branch includes: a first current source CS1, a first switch S1, a second switch S2, and a second current source CS2 connected in sequence; one end of the second current source CS2 away from the second switch S2 is grounded, and a connection point between the first switch S1 and the second switch S2 is an output end of the charge pump 120;

[0050] The first switch S1 is turned on when receiving the positive pulse signal, and the second switch S2 is turned on when receiving the negative pulse signal.

[0051] It can be understood that the first current source CS1 is used to output a positive current when the first switch S1 is turned on to increase the frequency of the VCO. The second current source CS2 is used to output a negative current when the second switch S2 is turned on to reduce the frequency of the VCO. Through the above settings, the frequency of the VCO can be flexibly adjusted, so that the signal output by the VCO is synchronized with the reference signal.

[0052] In some embodiments, the second branch includes: a third current source CS3, a third switch S3, a fourth switch S4, and a fourth current source CS4 connected in sequence;

[0053] The connection point between the third switch S3 and the fourth switch S4 is the output end of the charge pump. The third switch S3 and the fourth switch S4 are both turned on when receiving the first control signal, and are turned off when receiving the second control signal.

[0054] The first control signal is sent by the external controller when it determines that the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, and the second control signal is sent by the external controller when it determines that the phase-locked loop enters a frequency sweep state.

[0055] In some examples of this embodiment, the number of the third switch S3 and the fourth switch S4 can be one or more. If the number of the third switch S3 is multiple, the multiple third switches S3 are connected in series. If the number of the fourth switch S4 is multiple, the multiple fourth switches S4 are connected in series. Figure 2 Two third switches S3 and two fourth switches S4 are exemplarily shown in FIG.

[0056] It can be understood that the signal output by the phase-locked loop is the signal output by the VCO.

[0057] It should be noted that by setting the above structure in the second branch, it is easy to control the second branch, that is, when receiving the first control signal, the third switch S3 and the fourth switch S4 are turned on, so that the second branch is connected to the first branch, thereby increasing the output current Icp of the charge pump 120 and increasing the loop bandwidth. By increasing the loop bandwidth, the locking speed of the phase-locked loop is effectively improved.

[0058] It should be mentioned that after the second branch is connected to the first branch, the output current of the charge pump 120 increases significantly. The effect of the output current of the charge pump 120 on the loop bandwidth can be deduced. Assuming that the output current of the charge pump 120 increases from Icp to k*Icp, the change in the loop bandwidth is as follows:

[0059]

[0060] Wherein, k represents the increase multiple of the output current of the charge pump 120, LBW represents the loop bandwidth before the current increases, and LBW new It indicates the loop bandwidth after the current increases, and "*" indicates the multiplication sign. Assuming that Icp increases by 16 times, the loop bandwidth will usually increase by 8 to 10 times, etc.

[0061] In some embodiments, the loop filter 130 is used to reduce its own on-resistance to increase the loop bandwidth when receiving the first control signal, and restore its own on-resistance to the original state when receiving the second control signal.

[0062] It should be noted that by reducing the on-resistance of the loop filter 130 itself when receiving the first control signal, the loop bandwidth can be effectively increased, so that when the signal frequency output by the phase-locked loop changes drastically, the locking speed of the phase-locked loop can be effectively improved, thereby helping to improve the system response speed and performance.

[0063] In some embodiments, the loop filter 130 includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth switch S5, and a sixth switch S6;

[0064] One end of the first capacitor C1 is connected to the output end of the charge pump 120, and the other end of the first capacitor C1 is grounded; one end of the second capacitor C2 is connected to the output end of the charge pump 120, and the other end of the second capacitor C2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the second resistor R2 is connected in parallel with the first resistor R1, and the fifth switch S5 is located between the second capacitor C2 and the second resistor R2; one end of the third resistor R3 is connected to the output end of the charge pump 120, and the other end of the third resistor R3 is the output end of the loop filter 130; the fourth resistor R4 is connected in parallel with the third resistor R3, and the sixth switch S6 is located between the fourth resistor R4 and the output end of the charge pump 120; one end of the third capacitor C3 is connected to the third resistor R3, and the other end of the third capacitor C3 is grounded;

[0065] The fifth switch S5 and the sixth switch S6 are both turned on when receiving the first control signal, and are turned off when receiving the second control signal.

[0066] It should be noted that, through the above-mentioned setting, the loop filter 130 can be better controlled, that is, when the signal frequency output by the phase-locked loop changes drastically, the fifth switch S5 and the sixth switch S6 are closed, thereby reducing the overall on-resistance of the loop filter 130, thereby increasing the loop bandwidth and accelerating the locking time of the phase-locked loop.

[0067] In the above embodiment, when it is determined that the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to the preset amplitude threshold, that is, the signal frequency output by the phase-locked loop has a large jump, the loop bandwidth is increased by increasing the output current Icp of the charge pump 120 and reducing the on-resistance of the loop filter 130, thereby shortening the locking time of the phase-locked loop. However, the above method may lead to a reduction in the phase margin while increasing the loop bandwidth. In order to compensate for the decreased phase margin, the following embodiment reduces the size of the first resistor R1 and the second resistor R2 in the loop filter 130 to achieve compensation for the phase margin, as follows:

[0068] In some embodiments, the loop filter 130 is further configured to reduce the resistance values ​​of the first resistor R1 and the third resistor R3 upon receiving the first control signal, wherein the reduction amplitude of the third resistor R3 is greater than the reduction amplitude of the first resistor R1;

[0069] When the second control signal is received, the resistance values ​​of the first resistor R1 and the third resistor R3 are restored to their original resistance values.

[0070] It should be noted that, by reducing the resistance values ​​of the first resistor R1 and the third resistor R3 when the first control signal is received, the phase margin can be increased as much as possible while increasing the loop bandwidth. The principle is as follows:

[0071] For the charge pump phase-locked loop circuit provided in the above embodiment, the loop gain of the phase-locked loop is related to the output current of the charge pump 120, the frequency sensitivity of the VCO, and the transfer function of the loop filter 130. The mathematical expression of the loop gain of the phase-locked loop is:

[0072]

[0073] Wherein, G(s) represents loop gain, Kvco represents frequency sensitivity of VCO, Z(s) represents transfer function of loop filter 130, π represents pi, s is a variable in complex frequency domain, representing complex frequency, and N is a preset frequency division coefficient.

[0074] The mathematical expression of Z(s) is:

[0075]

[0076] Among them, A1=C1+C2+C3, A2=R1*C2*C3+R1*C1*C2+R3*C3*C1+R3*C3*C2, A3=C1*C2*C3*R1*R3. When the modulus of G(s) is 1, the corresponding loop frequency is the loop bandwidth, and the phase margin can also be defined as the value obtained by adding 180 degrees to the phase of G(s) at this time. On this basis, there is a non-zero negative zero point and two non-zero negative poles in G(s). The mathematical expressions of these three points are as follows:

[0077]

[0078] Zero represents a non-zero negative zero point, and Pole1 and Pole2 represent two non-zero negative poles. Since the capacitance of C2 is usually much larger than that of C1 and C3, and it is guaranteed that no complex poles will appear, A2 2 -4*A1*A3>0 always holds true.

[0079] From the above formula, we can know that when R1 decreases, the Zero frequency increases, A2 and A3 decrease, the ratio of A2 decreases is smaller than A3, and A1 remains unchanged. The frequency of Pole1 will also increase. When R3 decreases, the Zero frequency remains unchanged, A2 and A3 decrease, and the ratio of A2 decreases is smaller than A3. Therefore, it will only affect the frequency of Pole1 and Pole2, that is, it will cause the frequency of Pole1 and Pole2 to increase.

[0080] For loop bandwidth, due to the existence of the second-order pole at the origin, when the non-zero negative zero frequency increases, the loop bandwidth will decrease, because the modulus of G(s) will drop to 1 faster. When the pole (Pole1 and Pole2) frequency increases, the loop bandwidth will increase. For phase margin, the increase in the pole (Pole1 and Pole2) frequency will lead to an increase in phase margin, but the increase in zero frequency is not certain for the change in phase margin.

[0081] From the above analysis, it can be seen that when Icp increases, the reduction of R3 will increase the loop bandwidth and phase margin. Therefore, the above embodiment can increase the loop bandwidth and increase the phase margin by reducing the resistance of R3 when receiving the first control signal. Although the reduction of R1 will increase the phase margin, it will also reduce the loop bandwidth. Therefore, in the above embodiment, the decrease of R1 is less than the decrease of R3. In the above manner, the phase margin can be increased while increasing the loop bandwidth, thereby ensuring the performance of the phase-locked loop during relocking.

[0082] In some embodiments, the input end of the voltage-controlled oscillator 140 is connected to the output end of the loop filter 130, and is used to adjust its output frequency based on the voltage signal output by the loop filter 130, and output a signal of a corresponding frequency; the output end of the voltage-controlled oscillator 140 is connected to an N divider.

[0083] In some embodiments, the circuit further includes a signal generator 150, which is used to obtain a fractional frequency division ratio and an integer frequency division ratio, and transmit the fractional frequency division ratio to the signal modulator 160. In some examples of this embodiment, the signal generator 150 is a Chirp signal generator, and the Chirp signal is a signal whose frequency gradually changes over time.

[0084] In some embodiments, the circuit further includes a signal modulator 160 for modulating the fractional frequency division ratio to obtain a corresponding integer sequence; the sum of the integer sequence and the integer frequency division ratio is the target frequency division ratio. The signal modulator 160 may be a SDM (Sigma-Delta Modulator, Σ-Δ modulator).

[0085] In some embodiments, the circuit further includes a frequency divider 170, which is used to perform a frequency division operation on the signal output by the voltage-controlled oscillator 140 according to the target frequency division ratio to obtain a divided feedback signal, wherein the feedback signal is a preset input signal of the frequency detector 110. The frequency divider 170 may be an N frequency divider (N times frequency divider) or the like.

[0086] It should be noted that, by providing the above-mentioned devices, it can help the phase-locked loop to generate an FMCW signal. Figure 2 The FMCW OUT in the figure indicates the FMCW signal output by the phase-locked loop, which may be a sawtooth wave signal or the like.

[0087] Figure 3 FIG. 1 is a schematic diagram showing the principle of locking control in a charge pump phase-locked loop circuit provided in an embodiment of the present invention. Please refer to FIG. Figure 3 , Figure 3The Chirp waveform in is the signal waveform output by the phase-locked loop. Assuming that the Chirp waveform is a sawtooth waveform, when the signal frequency changes significantly, the external controller sends a first control signal to control the corresponding switch to be turned on, that is, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are closed. When the phase-locked loop enters the frequency sweep state, that is, when the signal frequency changes linearly, the external controller sends a second control signal to control the corresponding switch to be open, that is, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are disconnected. With the above control, the current size of Icp also changes accordingly. In the conduction stage (closed stage) of the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6, the size of Icp is I_bias+I_extra. In the open stage of the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6, the size of Icp is I_bias. I_bias represents the current output by the first branch of the charge pump 120 , and I_extra represents the current output by the second branch of the charge pump 120 .

[0088] In order to more intuitively demonstrate the difference between the locking speed of the charge pump phase-locked loop circuit in the above embodiment and the prior art, this embodiment also performs modeling simulation, and the simulation conditions are as follows:

[0089] Fref (reference frequency) = 100 MHz (megahertz), loop bandwidth 650 kHz (kilohertz), phase margin 60 degrees, Chirp rate = 100 MHz / us (megahertz / microsecond), Chirp bandwidth 1.5 GHz (gigahertz), start frequency 20 GHz, I_bias = 0.5 mA (milliamperes), Kvco of VCO is 2 GHz / V (gigahertz per volt). The configuration of the loop filter 130 is: C1 = 25 pF (picofarads), C2 = 950 pF, C3 = 18 pF, R2 = 825 Ω (ohms), R3 = 1150 Ω.

[0090] Under the above conditions, modeling and simulation are carried out, and the comparison of the time domain waveforms is as follows Figure 4 Please refer to Figure 4 At the frequency jump of the sawtooth wave signal, the corresponding locking time is 4us when the fast locking function is not enabled (existing technology), and the locking time is about 1.5us after the fast locking is enabled (using the locking method of the charge pump phase-locked loop circuit in the above embodiment). In the frequency sweeping stage, the fast locking function is turned off, and the waveforms of the two are basically the same, which means that the fast locking function of the charge pump phase-locked loop circuit in the above embodiment has basically no effect on the signal quality during linear frequency sweeping.

[0091] This embodiment further provides a radar, comprising: the charge pump phase-locked loop circuit as described in any one of the above items. The radar in this embodiment can achieve the technical effects achieved by any one of the above embodiments, which will not be described in detail here.

[0092] This embodiment also provides a charge pump phase-locked loop locking control method, including:

[0093] A charge pump is provided, the charge pump comprising: a first branch and at least one second branch;

[0094] When the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to the preset amplitude threshold, the second branch is connected to the first branch to increase the current output by the charge pump, and when the phase-locked loop enters the frequency sweep state, the connection between the second branch and the first branch is disconnected. The charge pump phase-locked loop locking control method in this embodiment can increase the loop bandwidth and effectively shorten the locking time of the phase-locked loop when the signal frequency output by the phase-locked loop jumps significantly.

[0095] The charge pump phase-locked loop locking control method in the above embodiment is performed based on any one of the charge pump phase-locked loop circuits described above.

[0096] In some embodiments, the method further includes: when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, reducing the on-resistance of the preset loop filter to increase the loop bandwidth.

[0097] In some embodiments, an electronic device is also provided, which may be a server, and its internal structure is shown in FIG. Figure 5 As shown. The electronic device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile and / or volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the electronic device is used to communicate with an external client via a network connection. When the computer program is executed by the processor, the functions or steps on the server side of the above method are implemented.

[0098] In some embodiments, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented: when the jump amplitude of the signal frequency output by a phase-locked loop is greater than or equal to a preset amplitude threshold, the second branch is connected to the first branch to increase the current output by the charge pump, and when the phase-locked loop enters a frequency sweep state, the connection between the second branch and the first branch is disconnected.

[0099] In some embodiments, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, the second branch is connected to the first branch to increase the current output by the charge pump, and when the phase-locked loop enters a sweeping frequency state, the connection between the second branch and the first branch is disconnected.

[0100] It should be noted that the above functions or steps that can be implemented by the computer-readable storage medium or electronic device can refer to the relevant descriptions on the server side and the client side in the aforementioned method embodiment. To avoid repetition, they will not be described one by one here.

[0101] The flow chart and block diagram in the accompanying drawings illustrate the possible implementation architecture, function and operation of the method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0102] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A charge pump phase-locked loop circuit, characterized in that: include: A charge pump, the charge pump comprising: The first branch outputs current when the phase-locked loop enters a frequency sweeping state, wherein the frequency sweeping state refers to a state in which the frequency of a signal output by the phase-locked loop changes linearly; as well as, At least one second branch is connected to the first branch to increase the current output by the charge pump when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, and is disconnected from the first branch when the phase-locked loop enters a frequency scanning state.

2. The charge pump phase-locked loop circuit according to claim 1, characterized in that: Also includes: A phase frequency detector, used to compare the phase difference and frequency difference between the input signal and a preset reference signal to output a positive pulse signal or a negative pulse signal; The first branch includes: a first current source, a first switch, a second switch, and a second current source connected in sequence; one end of the second current source away from the second switch is grounded, and a connection point between the first switch and the second switch is an output end of the charge pump; The first switch is turned on when receiving the positive pulse signal, and the second switch is turned on when receiving the negative pulse signal.

3. The charge pump phase-locked loop circuit according to claim 2, characterized in that: The second branch includes: a third current source, a third switch, a fourth switch, and a fourth current source connected in sequence; The connection point between the third switch and the fourth switch is the output end of the charge pump, and the third switch and the fourth switch are both turned on when receiving the first control signal, and are turned off when receiving the second control signal; The first control signal is sent by the external controller when it determines that the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, and the second control signal is sent by the external controller when it determines that the phase-locked loop enters a frequency sweep state.

4. The charge pump phase-locked loop circuit according to claim 1, characterized in that: Also includes: The loop filter is configured to reduce its own on-resistance to increase the loop bandwidth when receiving the first control signal, and restore its own on-resistance to an original state when receiving the second control signal; The first control signal is sent by the external controller when it determines that the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, and the second control signal is sent by the external controller when it determines that the phase-locked loop enters a frequency sweep state.

5. The charge pump phase-locked loop circuit according to claim 4, characterized in that: The loop filter comprises: a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth switch, and a sixth switch; One end of the first capacitor is connected to the output end of the charge pump, and the other end of the first capacitor is grounded; one end of the second capacitor is connected to the output end of the charge pump, and the other end of the second capacitor is connected to one end of the first resistor, and the other end of the first resistor is grounded; the second resistor is connected in parallel with the first resistor, and the fifth switch is located between the second capacitor and the second resistor; one end of the third resistor is connected to the output end of the charge pump, and the other end of the third resistor is the output end of the loop filter; the fourth resistor is connected in parallel with the third resistor, and the sixth switch is located between the fourth resistor and the output end of the charge pump; one end of the third capacitor is connected to the third resistor, and the other end of the third capacitor is grounded; The fifth switch and the sixth switch are both turned on when receiving the first control signal, and are turned off when receiving the second control signal.

6. The charge pump phase-locked loop circuit according to claim 5, characterized in that: The loop filter is further configured to reduce the resistance values ​​of the first resistor and the third resistor when receiving the first control signal, wherein the reduction amplitude of the third resistor is greater than the reduction amplitude of the first resistor; When the second control signal is received, the resistance values ​​of the first resistor and the third resistor are restored to original resistance values.

7. The charge pump phase-locked loop circuit according to claim 4, characterized in that: Also includes: A voltage-controlled oscillator, the input end of the voltage-controlled oscillator is connected to the output end of the loop filter, and is used to adjust its output frequency based on the voltage signal output by the loop filter, and output a signal of a corresponding frequency; the output end of the voltage-controlled oscillator is connected to the N-divider; A signal generator, used to obtain a fractional frequency division ratio and an integer frequency division ratio, and transmit the fractional frequency division ratio to a signal modulator; A signal modulator, configured to modulate the fractional frequency division ratio to obtain a corresponding integer sequence; the sum of the integer sequence and the integer frequency division ratio is a target frequency division ratio; The frequency divider is used to perform a frequency division operation on the signal output by the voltage-controlled oscillator according to the target frequency division ratio to obtain a divided feedback signal, wherein the feedback signal is an input signal of a preset frequency detector and phase detector.

8. A radar, characterized in that: include: A charge pump phase-locked loop circuit as claimed in any one of claims 1 to 7.

9. A charge pump phase-locked loop locking control method, characterized in that: include: A charge pump is provided, the charge pump comprising: a first branch and at least one second branch; When the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, the second branch is connected to the first branch to increase the current output by the charge pump, and when the phase-locked loop enters a frequency scanning state, the connection between the second branch and the first branch is disconnected.

10. The charge pump phase-locked loop locking control method according to claim 9, characterized in that: The method further includes: when the jump amplitude of the signal frequency output by the phase-locked loop is greater than or equal to a preset amplitude threshold, reducing the on-resistance of the preset loop filter to increase the loop bandwidth.

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