Signal processing circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a signal processing circuit, a chip and electronic equipment. The signal processing circuit comprises an analog-to-digital conversion module and a signal amplification module, the first chopping switch module is used for modulating the differential input signal to high frequency under the control of a preset clock signal and inputting the signal to the signal amplification module; the second chopping switch module is used for modulating the differential output signal output by the signal amplification module to a low frequency under the control of a preset control signal and inputting the low frequency to the analog-to-digital conversion module; and the second chopping switch module also enables the analog-to-digital conversion module to establish sampling under the control of a preset control signal. According to the application, the second chopping switch module is multiplexed as a sampling switch of the analog-to-digital conversion module, so that the problem that on-resistance is increased due to the fact that a chopping demodulation switch and the sampling switch are arranged at the same time can be avoided.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a signal processing circuit, a chip and an electronic device. Background Art

[0002] At present, a programmable gain amplifier (PGA) is usually used as a pre-stage circuit of an analog-to-digital converter to amplify the input signal and improve the signal-to-noise ratio of the signal processing system. In the related art, a programmable gain amplifier is usually combined with a chopping technology to eliminate the offset voltage and flicker noise of the operational amplifier. By setting a chopping switch at the input and output ends of the programmable gain amplifier, the input signal is modulated to a high frequency by the chopping switch at the input end, and the high-frequency signal is restored and demodulated to a low frequency by the chopping switch at the output end, the offset voltage and flicker noise of the operational amplifier can be modulated to a high frequency, and finally the offset voltage and flicker noise of the operational amplifier are eliminated by a post-stage filtering circuit.

[0003] However, after adopting the chopping technology, the on-resistance between the output of the programmable gain amplifier and the sampling capacitor in the analog-to-digital converter includes the on-resistance of the chopping switch and the sampling switch, which will cause the settling error of the sampling capacitor in the analog-to-digital converter to increase due to the increase of the on-resistance. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a signal processing circuit, a chip and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a signal processing circuit, including:

[0006] Analog-to-digital conversion module and signal amplification module;

[0007] A first chopping switch module, the first chopping switch module is used to modulate the differential input signal to a high frequency under the control of a preset clock signal and input the high frequency into the signal amplification module;

[0008] A second chopping switch module, which is used to modulate the differential output signal output by the signal amplification module to a low frequency under the control of a preset control signal and input the low frequency signal into the analog-to-digital conversion module;

[0009] The second chopping switch module also enables the analog-to-digital conversion module to establish sampling under the control of a preset control signal.

[0010] In a second aspect, an embodiment of the present application further provides a chip, comprising the above-mentioned signal processing circuit.

[0011] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or signal processing circuit.

[0012] The present application modulates the differential input signal to a high frequency through the first chopping switch module, and restores the high-frequency differential output signal to a low-frequency signal through the second chopping switch module and inputs it into the analog-to-digital conversion module, so that the signal measurement can be achieved while eliminating the offset voltage and flicker noise of the operational amplifier. Since the second chopping switch module can also enable the analog-to-digital conversion module to establish sampling under the control of a preset control signal, that is, the present application reuses the second chopping switch module as the sampling switch of the analog-to-digital conversion module, and the second chopping switch module can not only realize the chopping demodulation function, but also realize the sampling switch function of the sampling capacitor, and finally makes it unnecessary to set a sampling switch between the sampling capacitor and the second chopping switch module, thereby avoiding the problem of increasing the on-resistance due to setting the chopping demodulation switch and the sampling switch at the same time.

[0013] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic diagram of a signal processing circuit in the related art is shown.

[0016] Figure 2 A signal schematic diagram of a signal processing circuit in the related art is shown.

[0017] Figure 3 A schematic diagram of a signal processing circuit in an embodiment of the present application is shown.

[0018] Figure 4 Another schematic diagram of a signal processing circuit in an embodiment of the present application is shown.

[0019] Figure 5 Another schematic diagram of a signal processing circuit in an embodiment of the present application is shown.

[0020] Figure 6 Another schematic diagram of a signal processing circuit in an embodiment of the present application is shown.

[0021] Figure 7 A signal schematic diagram of a signal processing circuit in an embodiment of the present application is shown.

[0022] Among them, 10 analog-to-digital conversion module, 101 first sampling input terminal, 102 second sampling input terminal, 20 signal amplification module, 201 first input terminal, 202 second input terminal, 203 first output terminal, 204 second output terminal, 30 first chopping switch module, 40 second chopping switch module;

[0023] A first differential signal VIP, a second differential signal VIN, an operational amplifier OP, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first differential amplified signal VOP, a second differential amplified signal VON, sampling capacitors CS1 and CS2, and a reset switch SI;

[0024] A first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a first clock signal CLK1, a second clock signal CLK2, a reset clock signal CLKI, a first control signal CLKS1, and a second control signal CLKS2. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0026] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0027] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0028] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0029] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0030] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0031] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0032] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0033] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0034] Currently, programmable gain amplifiers are often combined with chopping technology to eliminate the offset voltage and flicker noise of the operational amplifier. Figure 1 as well as Figure 2 , Figure 1 A schematic diagram of a signal processing circuit in the related art is shown. Figure 2 A signal schematic diagram of a signal processing circuit in the related art is shown, wherein the signal processing circuit includes a chopping modulation switch, an amplifying circuit, a chopping demodulation switch and an analog-to-digital converter ADC.

[0035] Specifically, the chopper modulation switch includes four switches, two of which are controlled by the clock signal CLK1, and the other two switches are controlled by the clock signal CLK2. The clock signal CLK1 and the clock signal CLK2 do not overlap each other, so the two differential signals VIP and VIN can be alternately input into the negative input terminal and the positive input terminal of the amplifier circuit, and the differential signals VIP and VIN can be modulated into high-frequency signals and input into the amplifier circuit.

[0036] The amplifier circuit includes an operational amplifier OP, two input capacitors C1 and two feedback capacitors C2. The operational amplifier OP, the two input capacitors C1 and the two feedback capacitors C2 form a capacitive amplifier circuit. The amplification factor of the amplifier circuit is the capacitance ratio of the capacitor C2 to the capacitor C1, and finally the differential amplified signals VOP and VON can be outputted at the inverting output terminal and the non-inverting output terminal of the operational amplifier OP respectively.

[0037] The chopping demodulation switch includes four switches, two of which are controlled by the clock signal CLK1, and the other two switches are controlled by the clock signal CLK2. Since the clock signal CLK1 and the clock signal CLK2 do not overlap each other, the high-frequency differential amplification signals VOP and VON output by the operational amplifier OP can be converted into low-frequency differential output signals VOUTP and VOUTN.

[0038] The analog-to-digital converter ADC includes two sampling capacitors CS, two sampling switches and a reset switch. The two sampling switches are controlled by a sampling clock signal CLKS, and the reset switch is controlled by a reset clock signal CLKI. When the sampling switches are closed and the reset switch is opened, the two sampling capacitors CS can be charged based on the differential output signals VOUTP and VOUTN, respectively, so as to collect voltage information and perform analog-to-digital conversion.

[0039] It can be seen that the chopper modulation switch changes the polarity of the input end of the amplifier circuit, and the chopper demodulation switch restores the polarity of the differential output signals VOUTP and VOUTN, so that the sampling capacitor CS can be charged based on the differential output signals VOUTP and VOUTN and complete the signal measurement. At the same time, since the chopper modulation switch modulates the differential signals VOP and VON to high frequency, and the chopper demodulation switch is used to convert the high-frequency differential amplification signals VOP and VON into low-frequency differential output signals VOUTP and VOUTN, then for the offset voltage and flicker noise of the operational amplifier, the offset voltage and flicker noise of the operational amplifier are modulated to high frequency by the chopper demodulation switch, so the offset voltage and flicker noise of the operational amplifier can be eliminated through the post-stage filtering circuit.

[0040] However, in Figure 1 In the embodiment, a chopper demodulation switch and a sampling switch are arranged between the sampling capacitor CS and the output end of the operational amplifier OP. Therefore, the settling error of the sampling capacitor CS in the analog-to-digital converter will be affected by the on-resistance of both the chopper demodulation switch and the sampling switch. If the on-resistance is not reduced, the accuracy of the analog-to-digital converter will be reduced. If a transistor with a larger area is used as the sampling switch to reduce the on-resistance, the parasitic capacitance of the sampling switch will be increased, thereby affecting the sampling settling speed.

[0041] To this end, the present application provides a signal processing circuit, a chip and an electronic device, which are described in detail below.

[0042] First, see Figure 3 , Figure 3 A schematic diagram of a signal processing circuit in an embodiment of the present application is shown, wherein the signal processing circuit includes an analog-to-digital conversion module 10, a signal amplification module 20, a first chopping switch module 30 and a second chopping switch module 40.

[0043] Specifically, the analog-to-digital conversion module 10 has a first sampling input terminal 101 and a second sampling input terminal 102. The analog-to-digital conversion module 10 can perform analog-to-digital conversion on the differential signal input by the first sampling input terminal 101 and the second sampling input terminal 102, and finally output a digital signal corresponding to the voltage difference between the first sampling input terminal 101 and the second sampling input terminal 102, thereby realizing the voltage measurement process.

[0044] For example, the analog-to-digital conversion module 10 may include, but is not limited to, a successive approximation analog-to-digital converter.

[0045] (Successive Approximation Register ADC, SAR ADC), ∑-Δ analog-to-digital converter (Sigma-Delta ADC) or a hybrid analog-to-digital converter composed of SAR ADC and Sigma-Delta ADC, etc.

[0046] It should be noted that the analog-to-digital conversion module 10 includes sampling capacitors CS1, CS2 and a reset switch SI, one end of the reset switch SI is connected to the first sampling input terminal 101, and the other end is connected to the second sampling input terminal 102. The sampling capacitors CS1 and CS2 can be charged by the voltage signals input by the first sampling input terminal 101 and the second sampling input terminal 102, thereby storing charge signals related to the input voltage; when the reset switch SI is closed, the charges stored in the sampling capacitors CS1 and CS2 can be cleared, so that the sampling capacitors CS1 and CS2 can be sampled during the sampling stage.

[0047] It can be understood that the analog-to-digital conversion module 10 may include other circuit structures in addition to the sampling capacitors CS1, CS2 and the reset switch SI. For example, when the analog-to-digital conversion module 10 includes a SAR ADC, the analog-to-digital conversion module 10 may also include a comparator and a successive approximation logic module; for example, when the analog-to-digital conversion module 10 includes a Sigma-Delta ADC, the analog-to-digital conversion module 10 may also include a digital-to-analog converter, an integrator and a quantizer.

[0048] The signal amplifying module 20 has a first input terminal 201, a second input terminal 202, a first output terminal 203 and a second output terminal 204. The signal amplifying module 20 can amplify the signals inputted from the first input terminal 201 and the second input terminal 202, and output the amplified signals at the first output terminal 203 and the second output terminal 204 to improve the signal-to-noise ratio of the signal processing circuit.

[0049] In some embodiments of the present application, the signal amplification module 20 may include a PGA amplifier, in which case the first input terminal 201 and the second input terminal 202 input a voltage signal, and the first output terminal 203 and the second output terminal 204 output an amplified voltage signal, so that the analog-to-digital conversion module 10 performs analog-to-digital conversion on the amplified voltage signal. In some embodiments of the present application, the signal amplification module 20 may include a TIA amplifier, in which case the first input terminal 201 and the second input terminal 202 input a current signal, and the first output terminal 203 and the second output terminal 204 may output an amplified voltage signal, so that the analog-to-digital conversion module 10 performs analog-to-digital conversion on the amplified voltage signal.

[0050] In some embodiments of the present application, the signal amplification module 20 includes an operational amplifier OP, a first impedance element, a second impedance element, a third impedance element and a fourth impedance element; the first end of the first impedance element is connected to the first chopping switch module 30, and the second end of the first impedance element is connected to the non-inverting input terminal of the operational amplifier OP; the first end of the second impedance element is connected to the first chopping switch module 30, and the second end of the second impedance element is connected to the inverting input terminal of the operational amplifier OP; the first end of the third impedance element is connected to the non-inverting input terminal of the operational amplifier OP, and the second end of the third impedance element is connected to the inverting output terminal of the operational amplifier OP; the first end of the fourth impedance element is connected to the inverting input terminal of the operational amplifier OP, and the second end of the fourth impedance element is connected to the non-inverting output terminal of the operational amplifier OP.

[0051] It should be noted that the first impedance element, the second impedance element, the third impedance element and the fourth impedance element may include resistors and / or capacitors. For example, see Figure 4 , Figure 4 Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown, wherein the first impedance element includes a first capacitor C1, the second impedance element includes a second capacitor C2, the third impedance element includes a third capacitor C3, and the fourth impedance element includes a fourth capacitor C4. At this time, the operational amplifier OP, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 form a PGA amplifier circuit with a capacitor structure, so that the voltage signals input to the first input terminal 201 and the second input terminal 202 can be amplified, so as to output the first differential amplification signal VOP and the second differential amplification signal VON at the first output terminal 203 and the second output terminal 204 respectively.

[0052] For example, see Figure 5 , Figure 5 Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown, wherein the first impedance element includes a first resistor R1, the second impedance element includes a second resistor R2, the third impedance element includes a third resistor R3, and the fourth impedance element includes a fourth resistor R4. At this time, the operational amplifier OP, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 constitute a PGA amplifier circuit with a resistor structure, so that the voltage signals input to the first input terminal 201 and the second input terminal 202 can be amplified, so as to output a differential amplification signal VOP and a differential amplification signal VON at the first output terminal 203 and the second output terminal 204 respectively.

[0053] It can be understood that in some possible embodiments, the first impedance element, the second impedance element, the third impedance element and the fourth impedance element may include both resistance and capacitance. For example, the first impedance element includes the first resistor R1 and the first capacitor C1, the second impedance element includes the second resistor R2 and the second capacitor C2, the third impedance element includes the third resistor R3 and the third capacitor C3, the fourth impedance element includes the fourth resistor R4 and the fourth capacitor C4, the first capacitor C1 and the first resistor R1 are connected in parallel as the first impedance element, and the second impedance element, the third impedance element and the fourth impedance element are similar, and they are not repeated here.

[0054] The first chopping switch module 30 can modulate the differential input signal to a high frequency under the control of a preset clock signal and input it into the signal amplification module 20. For example, during the high level period of the preset clock signal, the first chopping switch module 30 controls the first input terminal 201 of the signal amplification module 20 to input the first differential signal VIP of the differential input signal, and the second input terminal 202 of the signal amplification module 20 to input the second differential signal VIN of the differential input signal; and during the low level period of the preset clock signal, the first chopping switch module 30 controls the first input terminal 201 of the signal amplification module 20 to input the second differential signal VIN of the differential input signal, and the second input terminal 202 of the signal amplification module 20 to input the first differential signal VIP of the differential input signal. The above process is performed alternately, so that the differential input signal is modulated to a high frequency and input into the signal amplification module 20.

[0055] In some embodiments of the present application, see Figure 6 , Figure 6 Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown, wherein the first chopping switch module 30 includes a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4; the first end of the first switch S1 is used to access the first differential signal VIP, and the second end of the first switch S1 is connected to the first input terminal 201; the first end of the second switch S2 is used to access the first differential signal VIP, and the second end of the second switch S2 is connected to the second input terminal 202; the first end of the third switch S3 is used to access the second differential signal VIN, and the second end of the third switch S3 is connected to the first input terminal 201; the first end of the fourth switch S4 is used to access the second differential signal VIN, and the second end of the fourth switch S4 is connected to the second input terminal 202.

[0056] Specifically, when the first switch S1 and the fourth switch S4 are closed, and the second switch S2 and the third switch S3 are opened, the first differential signal VIP can be continuously input into the first input terminal 201 of the signal amplifying circuit, and the second differential signal VIN can be continuously input into the second input terminal 202 of the signal amplifying circuit; conversely, when the first switch S1 and the fourth switch S4 are opened, and the second switch S2 and the third switch S3 are closed, the first differential signal VIP can be continuously input into the second input terminal 202 of the signal amplifying circuit, and the second differential signal VIN can be continuously input into the first input terminal 201 of the signal amplifying circuit. The above process can be alternately performed to modulate the differential input signal to a high frequency and input it into the signal amplifying module 20.

[0057] The second chopping switch module 40 can be used to modulate the differential output signal output by the signal amplification module 20 to a low frequency under the control of a preset control signal and input the signal to the analog-to-digital conversion module 10. For example, in a time period, the second chopping switch module 40 can control the first output terminal 203 of the signal amplification module 20 to be connected to the first sampling input terminal 101 of the analog-to-digital converter, and control the second output terminal 204 of the signal amplification module 20 to be connected to the second sampling input terminal 102 of the analog-to-digital converter; in another time period, the second chopping switch module 40 can control the second output terminal 204 of the signal amplification module 20 to be connected to the first sampling input terminal 101 of the analog-to-digital converter, and control the first output terminal 203 of the signal amplification module 20 to be connected to the second sampling input terminal 102 of the analog-to-digital converter.

[0058] In some embodiments of the present application, see Figure 6 The second chopping switch module 40 includes a fifth switch S5, a sixth switch S6, a seventh switch S7 and an eighth switch S8; a first end of the fifth switch S5 is connected to the first output terminal 203, and a second end of the fifth switch S5 is connected to the first sampling input terminal 101; a first end of the sixth switch S6 is connected to the first output terminal 203, and a second end of the sixth switch S6 is connected to the second sampling input terminal 102; a first end of the seventh switch S7 is connected to the second output terminal 204, and a second end of the seventh switch S7 is connected to the first sampling input terminal 101; a first end of the eighth switch S8 is connected to the second output terminal 204, and a second end of the eighth switch S8 is connected to the second sampling input terminal 102.

[0059] Specifically, when the fifth switch S5 and the eighth switch S8 are closed, and the sixth switch S6 and the seventh switch S7 are opened, the first sampling input terminal 101 of the analog-to-digital conversion module 10 is connected to the first differential amplified signal VOP of the differential output signal, and the second sampling input terminal 102 of the analog-to-digital conversion module 10 is connected to the second differential amplified signal VON of the differential output signal; conversely, when the fifth switch S5 and the eighth switch S8 are opened, and the sixth switch S6 and the seventh switch S7 are closed, the first sampling input terminal 101 of the analog-to-digital conversion module 10 is connected to the second differential amplified signal VON of the differential output signal, and the second sampling input terminal 102 of the analog-to-digital conversion module 10 is connected to the first differential amplified signal VOP of the differential output signal.

[0060] It should be noted that, when the first chopping switch module 30 controls the first input terminal 201 of the signal amplifying module 20 to input the first differential signal VIP, and the second input terminal 202 of the signal amplifying module 20 to input the second differential signal VIN, the second chopping switch module 40 can control the first output terminal 203 of the signal amplifying module 20 to be connected to the first sampling input terminal 101 of the analog-to-digital converter, and control the second output terminal 204 of the signal amplifying module 20 to be connected to the second sampling input terminal 102 of the analog-to-digital converter; and when the first chopping switch module 30 controls the first input terminal 201 of the signal amplifying module 20 to input the second differential signal VIN, and the second input terminal 202 of the signal amplifying module 20 to input the first differential signal VIP, the second chopping switch module 40 can control the first output terminal 203 of the signal amplifying module 20 to be connected to the second sampling input terminal 102 of the analog-to-digital converter, and control the second output terminal 204 of the signal amplifying module 20 to be connected to the first sampling input terminal 101 of the analog-to-digital converter.

[0061] In the above two processes, although the first chopping switch module 30 changes the polarity of the input signal of the first input terminal 201 and the second input terminal 202, since the second chopping switch module 40 will also change the polarity of the output signal of the first output terminal 203 and the second output terminal 204, the polarity of the input signal of the first sampling input terminal 101 and the second conversion input terminal will not change, so that the measurement of the signal by the analog-to-digital conversion module 10 can be guaranteed while realizing signal chopping.

[0062] In an embodiment of the present application, the second chopping switch module 40 also enables the analog-to-digital conversion module 10 to establish sampling under the control of the preset control signal. For example, when the second chopping switch module 40 controls the first output terminal 203 of the signal amplification module 20 to be connected to the first sampling input terminal 101 of the analog-to-digital converter, and controls the second output terminal 204 of the signal amplification module 20 to be connected to the second sampling input terminal 102 of the analog-to-digital converter, the sampling capacitors CS1 and CS2 can be charged and sampled; when the second chopping switch module 40 controls the second output terminal 204 of the signal amplification module 20 to be connected to the first sampling input terminal 101 of the analog-to-digital converter, and controls the first output terminal 203 of the signal amplification module 20 to be connected to the second sampling input terminal 102 of the analog-to-digital converter, the sampling capacitors CS1 and CS2 can also be charged and sampled.

[0063] It can be seen that the present application reuses the second chopping switch module 40 as the sampling switch of the analog-to-digital conversion module 10. The second chopping switch module 40 can not only realize the chopping demodulation function, but also realize the sampling switch function of the sampling capacitors CS1 and CS2. Ultimately, there is no need to set a sampling switch between the sampling capacitors CS1 and CS2 and the second chopping switch module 40, thereby avoiding the problem of increased on-resistance caused by setting the chopping demodulation switch and the sampling switch at the same time.

[0064] In some embodiments of the present application, see Figure 6 as well as Figure 7 The preset clock signal includes a first clock signal CLK1 and a second clock signal CLK2, and the preset control signal includes a first control signal CLKS1 and a second control signal CLKS2; the first clock signal CLK1 and the second clock signal CLK2 do not overlap with each other, the first control signal CLKS1 has multiple high levels only during a first level (e.g., a high level) of the first clock signal CLK1, and the second control signal CLKS2 has multiple high levels only during a second level (e.g., a low level) of the first clock signal CLK1.

[0065] For example, the first switch S1 and the fourth switch S4 of the first chopping switch module 30 change their switch states based on the first clock signal CLK1, the second switch S2 and the third switch S3 change their switch states based on the second clock signal CLK2, the fifth switch S5 and the eighth switch S8 of the second chopping switch module 40 change their switch states based on the first control signal CLKS1, the sixth switch S6 and the seventh switch S7 change their switch states based on the second control signal CLKS2, and the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 are NMOS tubes for example.

[0066] During the high level period of the first clock signal CLK1, the first switch S1 and the fourth switch S4 are closed, and the second switch S2 and the third switch S3 are opened, so the first chopping switch module 30 can control the first differential signal VIP to be continuously input into the first input terminal 201 of the signal amplifier circuit, and the second differential signal VIN to be continuously input into the second input terminal 202 of the signal amplifier circuit; at the same time, since the first control signal CLKS1 has multiple high levels only during the first level (e.g., high level) of the first clock signal CLK1, the second control signal CLKS2 has multiple high levels only during the second level of the first clock signal CLK1. There are multiple high levels during the period (for example, low level), so the fifth switch S5 and the eighth switch S8 switch back and forth between the closed state and the open state, while the sixth switch S6 and the seventh switch S7 remain in the open state, so the second chopping switch module 40 can control the first output terminal 203 of the signal amplifying module 20 to be intermittently connected to the first sampling input terminal 101, and control the second output terminal 204 of the signal amplifying module 20 to be intermittently connected to the second sampling input terminal 102. At this time, the fifth switch S5 and the eighth switch S8 serve as sampling switches of the analog-to-digital conversion module 10, so that the analog-to-digital conversion module 10 establishes sampling.

[0067] During the low level period of the first clock signal CLK1, the first switch S1 and the fourth switch S4 are opened, and the second switch S2 and the third switch S3 are closed, so the first chopping switch module 30 can control the first differential signal VIP to be continuously input into the second input terminal 202 of the signal amplifier circuit, and the second differential signal VIN to be continuously input into the first input terminal 201 of the signal amplifier circuit; at the same time, since the first control signal CLKS1 has multiple high levels only during the first level (e.g., high level) of the first clock signal CLK1, the second control signal CLKS2 has multiple high levels only during the second level of the first clock signal CLK1. There are multiple high levels during the period (for example, low level), so the sixth switch S6 and the seventh switch S7 switch back and forth between the closed state and the open state, while the fifth switch S5 and the eighth switch S8 remain in the open state, so the second chopping switch module 40 can control the second output terminal 204 of the signal amplifying module 20 to be intermittently connected to the first sampling input terminal 101, and control the first output terminal 203 of the signal amplifying module 20 to be intermittently connected to the second sampling input terminal 102. At this time, the sixth switch S6 and the seventh switch S7 serve as sampling switches of the analog-to-digital conversion module 10, so that the analog-to-digital conversion module 10 establishes sampling.

[0068] It can be seen that during the high level period of the first clock signal CLK1, the fifth switch S5 and the eighth switch S8 are multiplexed as sampling switches of the analog-to-digital conversion module 10; during the low level period of the first clock signal CLK1, the sixth switch S6 and the seventh switch S7 are multiplexed as sampling switches of the analog-to-digital conversion module 10. Therefore, under the control of the first control signal CLKS1 and the second control signal CLKS2, the second chopping switch module 40 can not only modulate the differential output signal output by the signal amplification module 20 to a low frequency and input it into the analog-to-digital conversion module 10, but also enable the analog-to-digital conversion module 10 to establish sampling.

[0069] In some embodiments of the present application, the first control signal CLKS1 is generated based on the first clock signal CLK1 and the reset clock signal CLKI of the analog-to-digital conversion module 10, the second control signal CLKS2 is generated based on the second clock signal CLK2 and the reset clock signal CLKI of the analog-to-digital conversion module 10, and the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are less than the frequency of the reset clock signal CLKI.

[0070] It should be noted that the reset clock signal CLKI refers to the clock signal for controlling the reset switch SI in the analog-to-digital conversion module 10. The first clock signal CLK1 and the reset clock signal CLKI can generate the first control signal CLKS1 through a logic gate circuit. The second clock signal CLK2 and the reset clock signal CLKI can generate the first control signal CLKS1 through a logic gate circuit.

[0071] For example, see Figure 6 , the first clock signal CLK1 and the reset clock signal CLKI can generate the first control signal CLKS1 through a logic gate circuit composed of a NOT gate and an AND gate, the reset clock signal CLKI outputs the inverted reset clock signal CLKI through the NOT gate, and then the first clock signal CLK1 and the inverted reset clock signal CLKI pass through the AND gate, and then the first control signal CLKS1 can be output. Similarly, the second clock signal CLK2 and the reset clock signal CLKI can generate the second control signal CLKS2 through a logic gate circuit composed of a NOT gate and an AND gate, the reset clock signal CLKI outputs the inverted reset clock signal CLKI through the NOT gate, and then the second clock signal CLK2 and the inverted reset clock signal CLKI pass through the AND gate, and then the second control signal CLKS2 can be output.

[0072] Since the first clock signal CLK1 and the second clock signal CLK2 do not overlap, and the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are lower than the frequency of the reset clock signal CLKI, during the high level of the first clock signal CLK1 and the low level of the second clock signal CLK2, Figure 7The first control signal CLKS1 shown has multiple high levels and multiple levels, while the second control signal CLKS2 is maintained at a low level; conversely, during the low level of the first clock signal CLK1 and the high level of the second clock signal CLK2, the second control signal CLKS2 has multiple high levels and multiple levels, while the first control signal CLKS1 is maintained at a low level.

[0073] For example, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 are NMOS tubes. During the high level of the first clock signal CLK1 and the low level of the second clock signal CLK2, the first switch S1 and the fourth switch S4 are kept in a closed state, and the second switch S2 and the third switch S3 are kept in an open state. At the same time, because the first control signal CLKS1 has multiple high levels and multiple low levels, and the second control signal CLKS2 is kept at a low level, the fifth switch S5 and the eighth switch S8 switch back and forth between the closed state and the open state, and the sixth switch S6 and the seventh switch S7 are kept in an open state.

[0074] On the contrary, during the low level of the first clock signal CLK1 and the high level of the second clock signal CLK2, the first switch S1 and the fourth switch S4 remain in the open state, the second switch S2 and the third switch S3 remain in the closed state, and since the second control signal CLKS2 has a plurality of high levels and a plurality of low levels, and the first control signal CLKS1 remains at a low level, the sixth switch S6 and the seventh switch S7 switch back and forth between the closed state and the open state, and the fifth switch S5 and the eighth switch S8 remain in the open state.

[0075] It can be seen that, by controlling the first switch S1 and the fourth switch S4 through the first clock signal CLK1, controlling the second switch S2 and the third switch S3 through the second clock signal CLK2, controlling the fifth switch S5 and the eighth switch S8 through the first control signal CLKS1, and controlling the sixth switch S6 and the seventh switch S7 through the second control signal CLKS2, not only signal chopping modulation and signal chopping demodulation can be achieved, but also the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 can be multiplexed as sampling switches of the analog-to-digital conversion module 10.

[0076] It should be pointed out that the above content about the signal processing circuit is intended to clearly illustrate the implementation verification process of the present application. Those skilled in the art can make equivalent modified designs under the guidance of the present application. For example, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 can also use transistors with switching functions such as PMOS tubes, triodes or JEFT tubes.

[0077] The embodiment of the present application also provides a chip, which includes the above-mentioned signal processing circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. Since the chip of the present application has the signal processing circuit described in the above embodiment, it has all the beneficial effects of the signal processing circuit in the above embodiment, which will not be repeated here.

[0078] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0079] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A signal processing circuit, characterized in that: include: Analog-to-digital conversion module and signal amplification module; A first chopping switch module, the first chopping switch module is used to modulate the differential input signal to a high frequency under the control of a preset clock signal and input the high frequency into the signal amplification module; a second chopping switch module, the second chopping switch module being used for modulating the differential output signal output by the signal amplification module to a low frequency under the control of a preset control signal and inputting the low frequency signal into the analog-to-digital conversion module; Wherein, the second chopping switch module also enables the analog-to-digital conversion module to establish sampling under the control of the preset control signal.

2. The signal processing circuit according to claim 1, characterized in that The preset clock signal includes a first clock signal and a second clock signal, and the preset control signal includes a first control signal and a second control signal; The first clock signal and the second clock signal do not overlap each other, the first control signal has a plurality of high levels only during a first level period of the first clock signal, and the second control signal has a plurality of high levels only during a second level period of the first clock signal.

3. The signal processing circuit according to claim 2, characterized in that: The first control signal is generated based on the first clock signal and a reset clock signal of the analog-to-digital conversion module, and the second control signal is generated based on the second clock signal and a reset clock signal of the analog-to-digital conversion module; The frequencies of the first clock signal and the second clock signal are lower than the frequency of the reset clock signal.

4. The signal processing circuit according to claim 2, characterized in that: The analog-to-digital conversion module has a first sampling input terminal and a second sampling input terminal, and the signal amplification module has a first input terminal, a second input terminal, a first output terminal and a second output terminal; During the first level period of the first clock signal, the first chopping switch module controls the first input terminal to continuously access the first differential signal, and controls the second input terminal to continuously access the second differential signal; the second chopping switch module controls the first output terminal to be intermittently connected to the first sampling input terminal, and controls the second output terminal to be intermittently connected to the second sampling input terminal; During the second level period of the first clock signal, the first chopping switch module controls the first input terminal to continuously access the second differential signal, and controls the second input terminal to continuously access the first differential signal; The second chopping switch module controls the second output terminal to be intermittently connected to the first sampling input terminal, and controls the first output terminal to be intermittently connected to the second sampling input terminal.

5. The signal processing circuit according to claim 4, characterized in that: The first chopping switch module includes a first switch, a second switch, a third switch and a fourth switch; The first end of the first switch is used to access the first differential signal, and the second end of the first switch is connected to the first input end; The first end of the second switch is used to access the first differential signal, and the second end of the second switch is connected to the second input end; The first end of the third switch is used to access the second differential signal, and the second end of the third switch is connected to the first input end; The first end of the fourth switch is used to access the second differential signal, and the second end of the fourth switch is connected to the second input end; The first switch and the fourth switch change their switch states based on the first clock signal, and the second switch and the third switch change their switch states based on the second clock signal.

6. The signal processing circuit according to claim 4, characterized in that: The second chopping switch module includes a fifth switch, a sixth switch, a seventh switch and an eighth switch; A first end of the fifth switch is connected to the first output end, and a second end of the fifth switch is connected to the first sampling input end; A first end of the sixth switch is connected to the first output end, and a second end of the sixth switch is connected to the second sampling input end; A first end of the seventh switch is connected to the second output end, and a second end of the seventh switch is connected to the first sampling input end; A first end of the eighth switch is connected to the second output end, and a second end of the eighth switch is connected to the second sampling input end; The fifth switch and the eighth switch change their switch states based on a first control signal, and the sixth switch and the seventh switch change their switch states based on a second control signal.

7. The signal processing circuit according to claim 1, characterized in that: The signal amplification module includes an operational amplifier, a first impedance element, a second impedance element, a third impedance element and a fourth impedance element; The first end of the first impedance element is connected to the first chopper switch module, and the second end of the first impedance element is connected to the non-inverting input end of the operational amplifier; A first end of the second impedance element is connected to the first chopper switch module, and a second end of the second impedance element is connected to the inverting input end of the operational amplifier; The first end of the third impedance element is connected to the non-inverting input end of the operational amplifier, and the second end of the third impedance element is connected to the inverting output end of the operational amplifier; A first end of the fourth impedance element is connected to the inverting input end of the operational amplifier, and a second end of the fourth impedance element is connected to the non-inverting output end of the operational amplifier.

8. The signal processing circuit according to claim 7, characterized in that: The first impedance element includes a first resistor and / or a first capacitor, and the second impedance element includes a second resistor and / or a second capacitor; The third impedance element includes a third resistor and / or a third capacitor, and the fourth impedance element includes a fourth resistor and / or a fourth capacitor.

9. A chip, characterized in that: The method comprises the signal processing circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 9 arranged in the device body.

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