A test circuit, an electronic device, and a test method for configuring channel logic

Abstract

The present application discloses a test circuit for configuring channel logic, an electronic device, and a test method. The interface corresponding to the configuration channel is located at the Type-C interface. The test circuit includes a processor, an output selection module, an output excitation module, an output device, an input device, and an input selection module. The processor includes a test control module and a test pattern output module. The test control module controls the output selection module to select the test pattern output by the test pattern output module, and obtains parsed data via the output device, the input device, and the input selection module according to the output excitation module. The test control module also controls the input selection module to select a test comparison module to determine the test result. This test circuit uses hardware testing, reducing the complexity of signal transmission. On the one hand, it realizes automatic, efficient, and comprehensive testing according to test cases; on the other hand, it comprehensively covers the test scope in the protocol according to the output excitation module, ensuring the comprehensiveness of the test.

Description

Technical Field

[0001] The present application relates to the field of testing technologies, and in particular, to a test circuit for configuring channel logic, an electronic device, and a test method. Background Art

[0002] Many communication and charging interfaces of electronic devices adopt the Type-C interface. The Type-C interface uses a symmetric top and bottom design, and the socket is flat and rectangular. With the application of the Type-C interface, Power Delivery (PD) communication in fast charging technology has become increasingly important. When the transmitter and receiver perform PD communication, a large number of signals are transmitted through the Configuration Channel (CC). Whether the CC module is normal or not is crucial for the realization of the entire Type-C function.

[0003] Therefore, before the electronic device (such as a chip) leaves the factory, it is very necessary to perform logical tests on the configuration channel. However, the traditional test method cannot balance high test efficiency and comprehensive test coverage. Summary of the Invention

[0004] In view of this, the present application provides a test circuit for configuring channel logic, an electronic device, and a test method to balance high test efficiency and comprehensive test coverage.

[0005] In a first aspect, the present application provides a test circuit for configuring channel logic. The test circuit is integrated inside the electronic device. The test circuit includes a processor, an output selection module, an output excitation module, an output unit, an input unit, and an input selection module.

[0006] Specifically, the processor includes a test control module and a test pattern output module. The test pattern output module includes test cases that cover the specification requirements. The test cases include test patterns of configuration channel signals and theoretical results. The test control module is used to control the output selection module to select the test patterns output by the test pattern output module;

[0007] The output unit is used to output the test patterns to the input unit according to the output excitation module controlled by the test control module;

[0008] The input unit is used to input the parsed data obtained according to the test patterns to the input selection module;

[0009] The processor further includes a test comparison module;

[0010] The test control module is further configured to control the input selection module to select the test comparison module, so as to determine the test result of the configured channel logic according to the parsed data and the theoretical result.

[0011] In some possible implementation manners, the output excitation module includes at least one of a clock adjustment module, an amplitude adjustment module, or a common mode adjustment module;

[0012] The clock adjustment module is configured to control the rate of outputting the test pattern within a preset frequency range according to a first preset step size;

[0013] The amplitude adjustment module is configured to control the signal amplitude when outputting the test pattern within a second preset frequency range according to a second preset step size;

[0014] The common mode adjustment module is configured to control the low-level voltage when outputting the test pattern.

[0015] In some possible implementation manners, the lower limit of the preset frequency range is 270 kHz, and the upper limit of the preset frequency range is 330 kHz;

[0016] The lower limit of the preset amplitude range is 1.0 V, and the upper limit of the preset amplitude range is 1.2 V;

[0017] The low-level voltage includes -250 mV, 0, and 250 mV.

[0018] In some possible implementation manners, the test circuit further includes a transmission buffer module, and the output selection module outputs the test pattern to the output device through the transmission buffer module.

[0019] In some possible implementation manners, the test circuit further includes a reception buffer module, and the input device inputs the parsed data to the input selection module through the reception buffer module.

[0020] In some possible implementation manners, the processor further includes a conventional parsing module and a conventional output module. The conventional parsing module is configured to parse the configured channel signal input by the external control through the input device, and the conventional output module is configured to output the configured channel signal to the outside of the electronic device through the output device.

[0021] In some possible implementation manners, the test pattern is a pattern that conforms to the two-way symbol coding rule.

[0022] In a second aspect, the present application provides an electronic device, characterized in that the electronic device includes the test circuit as described in the first aspect or any one of the possible implementation manners of the first aspect.

[0023] In a third aspect, the present application provides a method for testing configured channel logic. The method is implemented based on the test circuit described in the first aspect or any possible implementation manner of the first aspect, and the method includes:

[0024] According to the test control module, control the output selection module to select the test pattern output by the test pattern output module. The test control module and the test pattern output module are included in the processor. The test pattern output module includes test cases that cover the specification requirements. The test cases include the test patterns for configuring the channel signals and the theoretical results.

[0025] Based on the outputter, the output excitation module controlled by the test control module outputs the test pattern to the inputter.

[0026] Based on the inputter, input the parsed data obtained according to the test pattern to the input selection module.

[0027] According to the test control module, control the input selection module to select the test comparison module, so as to determine the test result of the configured channel logic according to the parsed data and the theoretical result. The test comparison module is included in the processor.

[0028] In some possible implementation manners, determining the test result of the configured channel logic according to the parsed data and the theoretical result includes:

[0029] When the parsed data and the theoretical result match successfully, determine that the test of the configured channel logic passes.

[0030] Otherwise, determine that the test of the configured channel logic fails.

[0031] Based on the implementation manners provided in the above aspects, the present application can be further combined to provide more implementation manners.

[0032] From the above technical solutions, it can be seen that the present application has at least the following advantages:

[0033] The present application provides a test circuit for configured channel logic. The test circuit is integrated inside the electronic device and directly performs tests using hardware, reducing the complexity of signal transmission. On the one hand, it can automatically, efficiently, and comprehensively test the configured channel logic according to the preset test cases. On the other hand, the test circuit includes an output excitation module, which can cover all test ranges in the protocol, ensuring the comprehensiveness of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic structural diagram of a test circuit for configured channel logic disclosed in an embodiment of the present application.

[0035] Figure 2 Schematic diagram of another test circuit for configuring channel logic disclosed in an embodiment of the present application;

[0036] Figure 3 Schematic diagram of yet another test circuit for configuring channel logic disclosed in an embodiment of the present application;

[0037] Figure 4 Schematic diagram of an electronic device disclosed in an embodiment of the present application;

[0038] Figure 5 Flowchart of a test method for configuring channel logic disclosed in an embodiment of the present application. Detailed implementation manners

[0039] To make the above objects, features, and advantages of the present application more obvious and understandable, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0040] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. The terms "first" and "second" in the embodiments of the present application are only used for descriptive purposes and cannot be construed as indicating or implying relative importance, chronological order of operations, or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0041] First, the background technology related to the embodiments of the present application will be introduced in detail.

[0042] With the application of the Type-C interface, Power Delivery (PD) communication in fast charging technology has become increasingly important. When the transmitter and receiver perform PD communication, a large number of signals are transmitted through the Configuration Channel (CC). Whether the CC module is normal is crucial for the realization of the entire Type-C function. For example, the CC module can determine whether the device is a power source (Source) or a power sink by detecting resistors, and can also coordinate charging parameters such as voltage, current, power, etc. Therefore, before the electronic device (such as a chip) leaves the factory, it is very necessary to test the configuration channel.

[0043] The logic test of the circuit is a process to verify whether the circuit design meets the expected functions and timing requirements. By inputting specific signals and checking the output results of the circuit, the normal operation of the circuit can be ensured to prevent the electronic control products (especially chips) from having abnormal functions due to design defects after leaving the factory, resulting in economic losses.

[0044] Traditional configuration channel logic tests usually rely on external control to send a large amount of test data to the circuit, resulting in long test times and high test costs. Furthermore, traditional test methods require, on the one hand, strict alignment of external signals with the internal clock of the electronic device circuit, which places high requirements on the test data; on the other hand, precisely because external signals need to be strictly aligned with the internal clock of the electronic device circuit, and the internal clock is usually a fixed value, traditional test methods are difficult to cover all rate situations within the transmission rate range required by the protocol, resulting in a small test coverage rate.

[0045] In view of this, an embodiment of the present application provides a test circuit for configuration channel logic. This test circuit is integrated inside the electronic device and includes a processor, an output selection module, an output excitation module, an outputter, an inputter, and an input selection module.

[0046] Specifically, the processor includes a test control module and a test pattern output module. The test pattern output module includes test cases that cover the specification requirements, where the test cases include the test patterns of the configuration channel signals and the theoretical results. The test control module is used to control the output selection module to select the test patterns output by the test pattern output module. The outputter is used to output the test patterns to the inputter according to the output excitation module controlled by the test control module. The inputter is used to input the parsed data obtained from the test patterns to the input selection module. The test control module is also used to control the input selection module to select the test comparison module in the processor to determine the test results of the configuration channel logic based on the parsed data and the theoretical results.

[0047] This test circuit is integrated inside the electronic device and directly performs tests using hardware, reducing the complexity of signal transmission. On the one hand, it can achieve automatic, efficient, and comprehensive testing of the configuration channel logic according to the preset test cases; on the other hand, this test circuit includes an output excitation module, which can cover all test ranges in the protocol, ensuring the comprehensiveness of the test.

[0048] To make the technical solution of the present application clearer and easier to understand, the following introduces a test circuit for configuration channel logic provided by the present application in combination with specific embodiments.

[0049] See Figure 1 It is a schematic structural diagram of a test circuit for configuration channel logic disclosed in an embodiment of the present application.

[0050] The test circuit 1000 provided in an embodiment of the present application is integrated inside the electronic device and includes a processor 100, an output selection module 200, an output excitation module 300, an outputter 400, an inputter 500, and an input selection module 600. The arrows in the figure indicate the transmission directions of signals / data.

[0051] The processor 100 in this application refers to a processing module used to control the input test pattern and perform test comparison. This application does not specifically limit the form of the processor 100. For example, the processor 100 can be a single-chip microcomputer, a microprocessor, etc.

[0052] Specifically, the processor 100 may include a test control module 10, a test pattern output module 11, and a test comparison module 12. Among them, the test control module 10 is used to output control signals during the test process and can be controlled by an external device through a control port (commonly an IIC slave) to start the test at the beginning of the test. The test pattern output module 11 includes test cases that meet the coverage specifications (such as the PD specification). The test cases include test patterns and theoretical results for configuring channel signals, and the test cases can be stored in a pattern library. The test pattern for configuring channel logic tests should conform to the Biphase Mark Code (BMC) rule. BMC is a coding method based on phase modulation and is used to achieve the combined transmission of clock signals and data signals. Specifically, in BMC, the clock frequency is twice the data transmission rate. When the data is "1", a waveform jump occurs at the midpoint of the symbol period, and when the data is "0", no jump occurs. At the same time, a unified jump occurs between two adjacent data, thus achieving signal synchronization and having the characteristic of anti-interference. The test comparison module 12 is used to compare the test results obtained from the test with the theoretical results in the test cases. If the test results are the same as the theoretical results, it can be determined that the logic test passes; otherwise, it can be determined that the test fails.

[0053] In the initial stage of the test, the test control module 10 can output a control signal to control the output selection module 200 to select the test pattern output by the test pattern output module 11. For example, the test control module 10 can output a control signal to the output selection module 200, instructing the output selection module 200 to send a data request to the test pattern output module 11, or the test control module 10 can control the test pattern output module 11 to send a test pattern to the output selection module 200 and instruct the output selection module 200 to receive the test pattern.

[0054] Then, the output device 400 can output the test pattern to the input device 500 according to the test pattern received by the output selection module 200 and the output excitation module 300 controlled by the test control module 10. Among them, the output device 400 can include an analog output unit, which is controlled by the test control module 10 to turn on and output data.

[0055] In some possible implementations, to test the performance of the electronic device at different data transfer rates (bit rates), the output excitation module 300 may include a clock adjustment module 30 for simulating multiple data transfer rates (bit rates). Since the bit rate is positively correlated with the symbol rate (baud rate), and the symbol rate is directly determined by the clock frequency, it can be understood that the data transfer rate will be faster at a higher clock frequency.

[0056] In some possible implementations, the clock adjustment module 30 may control the rate of outputting the test pattern within a preset frequency range according to a preset step size. According to relevant specification requirements, in the configuration channel signal communication of the electronic device, the clock frequency needs to cover the range from 270 kilohertz (kHz) to 330 kHz, that is, the lower limit of the preset frequency range can be 270 kHz, and the upper limit of the preset frequency range can be 330 kHz. In some possible implementations, the clock adjustment module 30 may cover the preset frequency range with a step size of 10 kHz for testing. For example, after transmitting all test patterns at a clock frequency of 270 kHz, the test patterns are transmitted at a clock frequency of 280 kHz until all test patterns are transmitted at a clock frequency of 330 kHz.

[0057] In some possible implementations, the output excitation module 300 may include an amplitude adjustment module 31 for controlling the signal amplitude when outputting the test pattern, so as to verify the accuracy of the signal transmission of the electronic device configuration channel within the signal amplitude range specified by the protocol, from 1.0 volt (abbreviated as V) to 1.2 volts (abbreviated as V). For example, the amplitude adjustment module 31 may cover the aforementioned signal amplitude range with a step size of 100 millivolts (mV) to adjust the output test pattern.

[0058] In some possible implementations, the output excitation module 300 may include a common-mode adjustment module 32 for controlling the low-level output when outputting the test pattern. Among them, the common-mode level refers to the common average voltage of the differential signal relative to the input terminal, and its low level is the voltage that ensures the logic circuit correctly recognizes the logic "0", so it is necessary to test the low-level characteristics of the common-mode level of the output signal. For example, the common-mode adjustment module 32 may test three gears with low levels of -250 mV, 0, and 250 mV respectively.

[0059] Next, the inputter 500 may input the parsed data to the input selection module 600 according to the parsed data obtained by parsing the test pattern. Among them, the inputter 500 may include an analog input unit, which is controlled by the test control module 10 to be turned on and input data.

[0060] Finally, the test control module 10 can also control the input selection module 600 to select the test comparison module 12 to determine the test result of the configured channel logic according to the parsed data and the theoretical result. Among them, the test comparison module 12 includes the test cases output by the test pattern output module 11, that is, the test comparison module 12 includes the test pattern and the corresponding theoretical result. Thus, the test comparison module 12 can compare the parsed data obtained by parsing by the input device 500 with the theoretical result. When the parsed data matches the theoretical result successfully, it is determined that the logic test of the configured channel passes. When the parsed data fails to match the theoretical result, it is determined that the logic test fails.

[0061] Based on the above description, the present application provides a test circuit for configuring channel logic. This test circuit is integrated inside the electronic device and uses hardware for direct testing, reducing the complexity of signal transmission. On the one hand, it can achieve automatic, efficient, and comprehensive testing of the configured channel logic according to the preset test cases. On the other hand, this test circuit includes an output excitation module, which can cover all test ranges in the protocol to ensure the comprehensiveness of the test.

[0062] See Figure 2 FIG. is a schematic structural diagram of another test circuit for configuring channel logic disclosed in an embodiment of the present application.

[0063] Compared with Figure 1 the disclosed test circuit, Figure 2 the disclosed test circuit further includes a transmit buffer module 700 and a receive buffer module 800. After receiving the test pattern, the output selection module 200 will first output the test pattern to the transmit buffer module 700, and output the test pattern to the output device 400 through the transmit buffer module 700. After the input device 500 parses the parsed data, it will first input the parsed data to the receive buffer module 800, and input the parsed data to the input selection module 600 through the receive buffer module 800. Among them, the functions of the transmit buffer module 700 and the receive buffer module 800 are to temporarily store data and coordinate data transmission between different rates or different interfaces, so as to ensure stable and reliable data transmission. For example, a First-In-First-Out (FIFO) buffer memory can be selected.

[0064] See Figure 3 FIG. is a schematic structural diagram of yet another test circuit for configuring channel logic disclosed in an embodiment of the present application.

[0065] Compared with Figure 1 or Figure 2 the disclosed test circuit, Figure 3In the disclosed test circuit, the processor further includes a conventional parsing module 14 and a conventional output module 15. The dotted lines indicate that the transmit buffer module and the receive buffer module are optional structures. The conventional parsing module is used to parse the configuration channel signal input by the external control through the input device, and the conventional output module is used to output the configuration channel signal to the external through the output device. That is, in a non-test scenario, when the electronic device communicates with the external for the configuration channel, data reception and transmission will be performed separately.

[0066] Specifically, in the scenario of communicating with the external, the input device 500, the input selection module 600, the conventional parsing module 14, and the possibly existing receive buffer module 800 can form a receive module. The input device 500 receives the configuration channel signal from the external and sends it to the conventional parsing module 14 via (the receive buffer module 800) and the input selection module 600; the output device 400, the output selection module 200, the conventional output module 15, and the possibly existing transmit buffer module 700 can form a transmit module. The conventional output module 15 outputs the configuration channel signal to the external via the output selection module 200, (the transmit buffer module 700), and the output device 400. Among them, the two processes of the device receiving external signals and sending signals to the external are independent.

[0067] Based on the above test circuit for the configuration channel logic, the present application provides an electronic device, which will be introduced in detail below with reference to the accompanying drawings.

[0068] See Figure 4 , which is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application.

[0069] The electronic device 10000 provided in the embodiment of the present application includes the test circuit 100 introduced in the above embodiment. This electronic device can support fast charging technology using a Type-C interface. For example, it can be a mobile phone, wireless earphones, a tablet computer, etc. The embodiment of the present application does not make any limitations in this regard.

[0070] Based on the above content, the present application also provides a test method for the configuration channel logic. See Figure 5 The schematic diagram of a test method for the configuration channel logic shown, this method is implemented based on the above test circuit, and specifically includes:

[0071] S502: According to the test control module, control the output selection module to select the test pattern output by the test pattern output module. The test control module and the test pattern output module are included in the processor. The test pattern output module includes test cases covering the specification requirements. The test cases include the test patterns of the configuration channel signal and the theoretical results.

[0072] S504: Based on the output device, the output excitation module controlled by the test control module outputs the test pattern to the input device.

[0073] S506: Input the parsed data obtained according to the test pattern into the input selection module based on the input device.

[0074] S508: Control the input selection module to select the test comparison module according to the test control module, so as to determine the test result of the configured channel logic based on the parsed data and the theoretical result. The test comparison module is included in the processor.

[0075] Among them, when the parsed data and the theoretical result match successfully, it is determined that the test of the configured channel logic passes; otherwise, it is determined that the test of the configured channel logic fails.

[0076] The specific details of the above steps are similar to those in the previous text and will not be elaborated here.

[0077] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the systems or devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, refer to the description in the method section.

[0078] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally means that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or its similar expression means any combination of these items, including any combination of single item (one) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0079] It should also be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0080] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination thereof. The software modules may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the art.

[0081] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A test circuit for configuring channel logic, characterized in that, The interface corresponding to the configuration channel is located at the Type-C interface. The test circuit is integrated inside the electronic device. The test circuit includes a processor, an output selection module, an output excitation module, an output device, an input device, and an input selection module; The processor includes a test control module and a test pattern output module. The test pattern output module includes test cases covering the specification requirements. The test cases include the test pattern and the theoretical result of the configuration channel signal. The test control module is used to control the output selection module to select the test pattern output by the test pattern output module; The output device is used to output the test pattern to the input device according to the output excitation module controlled by the test control module; The input device is used to input the parsed data obtained according to the test pattern to the input selection module; The processor further includes a test comparison module; The test control module is further used to control the input selection module to select the test comparison module, so as to determine the test result of the configuration channel logic according to the parsed data and the theoretical result.

2. The test circuit according to claim 1, characterized in that The output excitation module includes at least one of a clock adjustment module, an amplitude adjustment module, or a common mode adjustment module; The clock adjustment module is used to control the output rate of the test pattern within a preset frequency range according to a first preset step size; The amplitude adjustment module is used to control the signal amplitude when outputting the test pattern within a preset amplitude range according to a second preset step size; The common mode adjustment module is used to control the low-level voltage when outputting the test pattern.

3. The test circuit according to claim 2, characterized in that, The lower limit of the preset frequency range is 270 kHz, and the upper limit of the preset frequency range is 330 kHz; The lower limit of the preset amplitude range is 1.0 V, and the upper limit of the preset amplitude range is 1.2 V; The low-level voltage includes -250 mV, 0, and 250 mV.

4. The test circuit according to claim 1, characterized in that, The test circuit further includes a transmit buffer module. The output selection module outputs the test pattern to the output device through the transmit buffer module.

5. The test circuit according to claim 1, characterized in that The test circuit further includes a receive buffer module. The input device inputs the parsed data to the input selection module through the receive buffer module.

6. The test circuit according to claim 1, wherein The processor further includes a conventional parsing module and a conventional output module. The conventional parsing module is used to parse the configuration channel signal input by the external control through the input device. The conventional output module is used to output the configuration channel signal to the outside of the electronic device through the output device.

7. The test circuit according to any one of claims 1 to 6, characterized in that, The test pattern is a pattern that conforms to the two-way symbol coding rule.

8. An electronic device, characterized in that, The electronic device includes the test circuit according to any one of claims 1 to 7.

9. A test method for configuring channel logic, characterized in that, Implemented based on the test circuit according to any one of claims 1 to 7, the method includes: According to the test control module, controlling the output selection module to select the test pattern output by the test pattern output module. The test control module and the test pattern output module are included in the processor. The test pattern output module includes test cases covering the specification requirements. The test cases include the test pattern and the theoretical result of the configuration channel signal; Based on the output excitation module controlled by the test control module by the outputter, output the test pattern to the inputter; Based on the inputter inputting the parsed data obtained according to the test pattern to the input selection module; According to the test control module controlling the input selection module to select the test comparison module, so as to determine the test result of the configured channel logic according to the parsed data and the theoretical result, and the test comparison module is included in the processor.

10. The method according to claim 9, characterized in that, The determining the test result of the configured channel logic according to the parsed data and the theoretical result includes: When the parsed data and the theoretical result match successfully, it is determined that the test of the configured channel logic passes; Otherwise, it is determined that the test of the configured channel logic fails.

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