Test circuit, chip and test method for auxiliary channel logic of display interface

Abstract

The invention discloses a test circuit, a chip and a test method for auxiliary channel logic of a display interface. The test circuit comprises a processor, an output selection module, a clock adjustment module, an output device, an input device and an input selection module. The processor comprises a test control module and a test code pattern output module. The test control module is used for controlling the output selection module to select the test code pattern output by the test code pattern output module. The output device is used for outputting the test code pattern to the input device according to the clock adjusting module. The input device is used for inputting analysis data obtained according to the test code pattern to the input selection module. And the test control module is also used for controlling the input selection module to select the test comparison module so as to determine a test result. The test circuit is integrated in a chip, the complexity of signal transmission is reduced, and on one hand, automatic, efficient and comprehensive testing can be achieved according to a test case; on the other hand, the data transmission rate in the module coverage protocol can be adjusted according to the clock, and the test comprehensiveness is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a testing circuit, chip and testing method for display interface auxiliary channel logic. Background Art

[0002] Auxiliary Channel (AUX) is an independent communication path used for auxiliary data transmission, link management, device control and protocol management, and is a key functional module in Display Port (DP). For example, during the DP link initialization phase, AUX can negotiate the best transmission parameters (such as number of channels, rate, etc.) through two-way communication to complete link training and ensure data transmission stability.

[0003] Therefore, before electronic devices (such as chips) leave the factory, it is necessary to perform logic testing on auxiliary channels. However, traditional testing methods cannot balance the high test efficiency and comprehensive test coverage. Summary of the invention

[0004] In view of this, the present application provides a test circuit, chip and test method for display interface auxiliary channel logic, so as to take into account both high test efficiency and comprehensive test coverage.

[0005] In a first aspect, the present application provides a test circuit for display interface auxiliary channel logic, the test circuit is integrated inside a chip, and the test circuit includes a processor, an output selection module, a clock adjustment module, an output device, an input device, and an input selection module.

[0006] Specifically, the processor includes a test control module and a test pattern output module, the test pattern output module includes test cases covering specification requirements, the test cases include test patterns and theoretical results of auxiliary channel signals, and the test control module is used to control the output selection module to select the test pattern output by the test pattern output module; The output device is used to output the test pattern to the input device according to the clock adjustment module controlled by the test control module; The input device is used to input the parsed data obtained according to the test pattern into the input selection module; The processor also includes a test comparison module; The test control module is further used to control the input selection module to select the test comparison module to determine the test result of the display interface auxiliary channel logic according to the analysis data and the theoretical result.

[0007] In some possible implementations, the clock adjustment module is used to control the rate of outputting the test pattern within a preset frequency range according to a preset step size.

[0008] In some possible implementations, the preset step size is 10 kHz, the lower limit of the preset frequency interval is 830 kHz, and the upper limit of the preset frequency interval is 1.25 MHz.

[0009] In some possible implementations, the test circuit further includes a sending buffer module, and the output selection module outputs the test code pattern to the outputter through the sending buffer module.

[0010] In some possible implementations, the test circuit further includes a receiving buffer module, and the inputter inputs the parsed data to the input selection module through the receiving buffer module.

[0011] In some possible implementations, the processor further includes a conventional analysis module and a conventional output module, wherein the conventional analysis module is used to analyze the auxiliary channel signal input by the external control through the input device, and the conventional output module is used to output the auxiliary channel signal to the outside of the chip through the output device.

[0012] In some possible implementations, the test code pattern is a code pattern that complies with Manchester encoding rules.

[0013] In a second aspect, the present application provides a chip, characterized in that the chip includes a test circuit as described in the first aspect or any possible implementation of the first aspect.

[0014] In a third aspect, the present application provides a method for testing auxiliary channel logic of a display interface, the method being implemented based on the test circuit as described in the first aspect or any possible implementation of the first aspect, the method comprising: According to the test control module, the output selection module is controlled to select the test pattern output by the test pattern output module, the test control module and the test pattern output module are included in the processor, the test pattern output module includes test cases covering the specification requirements, and the test cases include the test pattern and theoretical results of the auxiliary channel signal; Based on the output device outputting the test pattern to the input device according to the clock adjustment module controlled by the test control module; Inputting parsed data obtained according to the test pattern into an input selection module based on the input device; The test control module controls the input selection module to select a test comparison module to determine the test result of the display interface auxiliary channel logic according to the analysis data and the theoretical result, and the test comparison module is included in the processor.

[0015] In some possible implementations, determining the test result of the display interface auxiliary channel logic according to the parsed data and the theoretical result includes: When the parsed data and the theoretical result match successfully, it is determined that the test of the display interface auxiliary channel logic passes; Otherwise, it is determined that the test of the display interface auxiliary channel logic fails.

[0016] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations.

[0017] It can be seen from the above technical solutions that the present application has at least the following advantages: The present application provides a test circuit for the auxiliary channel logic of a display interface. The test circuit is integrated inside a chip and uses hardware to perform direct testing, thereby reducing the complexity of signal transmission. On the one hand, it is possible to implement automatic, efficient, and comprehensive testing of the auxiliary channel logic based on preset test cases; on the other hand, the test circuit includes a clock adjustment module, which can cover the testing of all data transmission rates in the protocol, thereby ensuring the comprehensiveness of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the structure of a test circuit for display interface auxiliary channel logic disclosed in an embodiment of the present application; Figure 2 A schematic diagram of the structure of another test circuit for display interface auxiliary channel logic disclosed in an embodiment of the present application; Figure 3 A schematic diagram of the structure of another test circuit for display interface auxiliary channel logic disclosed in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a chip disclosed in an embodiment of the present application; Figure 5 The present invention is a flowchart of a method for testing auxiliary channel logic of a display interface disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0020] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. The terms "first" and "second" in the embodiments of the present application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance, operation time sequence, or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0021] First, the background technology involved in the embodiments of the present application is introduced in detail.

[0022] The auxiliary channel (AUX) is an independent communication path used for auxiliary data transmission, link management, device control and protocol management. It is a key functional module in the display port (DP). For example, during the DP link initialization phase, AUX can negotiate the best transmission parameters (such as the number of channels, rate, etc.) through two-way communication to complete link training and ensure data transmission stability. Therefore, it is very necessary to test the auxiliary channel before electronic equipment (such as chips) leaves the factory.

[0023] The logic test of the circuit is the process of verifying whether the circuit design meets the expected functional and timing requirements. It can ensure the normal operation of the circuit by inputting specific signals and checking the output results of the circuit to prevent electronic control products (especially chips) from malfunctioning or even causing economic losses due to design defects after leaving the factory.

[0024] Traditional auxiliary channel logic testing usually relies on external control to send a large amount of test data to the circuit, resulting in long test time and high test cost. Furthermore, on the one hand, traditional test methods require strict alignment of external signals with the internal clock of the chip circuit, which places high demands on test data; on the other hand, it is precisely because the external signal needs to be strictly aligned with the internal clock of the chip circuit, and the internal clock is usually a fixed value, that traditional test methods are difficult to cover all rate conditions within the transmission rate range required by the protocol, resulting in low test coverage.

[0025] In view of this, an embodiment of the present application provides a test circuit for display interface auxiliary channel logic, which is integrated inside the chip and includes a processor, an output selection module, a clock adjustment module, an output device, an input device and an input selection module.

[0026] Specifically, the processor includes a test control module and a test pattern output module, wherein the test pattern output module includes test cases covering the specification requirements, wherein the test cases include test patterns and theoretical results of auxiliary channel signals. The test control module is used to control the output selection module to select the test pattern output by the test pattern output module. The output device is used to output the test pattern to the input device according to the clock adjustment module controlled by the test control module. The input device is used to input the parsed data obtained according to the test pattern to the input selection module. The test control module is also used to control the input selection module to select the test comparison module in the processor to determine the test result of the auxiliary channel logic of the display interface according to the parsed data and the theoretical result.

[0027] The test circuit is integrated inside the chip and uses hardware for direct testing, which reduces the complexity of signal transmission. On the one hand, it can realize automatic, efficient and comprehensive testing of auxiliary channel logic according to preset test cases; on the other hand, the test circuit includes a clock adjustment module, which can cover all data transmission rate tests in the protocol to ensure the comprehensiveness of the test.

[0028] In order to make the technical solution of the present application clearer and easier to understand, a test circuit for display interface auxiliary channel logic provided by the present application is introduced below in conjunction with a specific embodiment.

[0029] See also Figure 1 A schematic diagram of the structure of a test circuit for display interface auxiliary channel logic disclosed in an embodiment of the present application.

[0030] The test circuit 1000 provided in the embodiment of the present application is integrated inside the chip, and includes a processor 100, an output selection module 200, a clock adjustment module 300, an output device 400, an input device 500 and an input selection module 600. The arrows in the figure indicate the transmission direction of the signal / data.

[0031] The processor 100 in this application refers to a processing module for controlling the input of test patterns and performing test comparisons. This application does not specifically limit the form of the processor 100, for example, the processor 100 may be a single chip microcomputer, a microprocessor, and the like.

[0032] Specifically, the processor 100 may include a test control module 10, a test pattern output module 11 and a test comparison module 12. Among them, the test control module 10 is used for the output of the control signal during the test process, and the test can be started by the external chip through the chip control port (commonly IIC slave) at the beginning of the test. The test pattern output module 11 includes test cases required by the coverage specification (for example, the DP specification), and the test cases include the test pattern and theoretical results of the auxiliary channel signal. The test cases can be stored in the pattern library. The test pattern used for the display interface auxiliary channel logic test should comply with the Manchester Manchester encoding rule. Manchester encoding divides each data bit (0 or 1) into two equal time periods, and there must be a level jump at the center of the bit, so as to transmit clock and data information through the level jump. For example, according to the IEEE802.3 standard, when the jump from low level to high level indicates that the data is "1", otherwise it is "0". The test comparison module 12 is used to compare the test results obtained by the test with the theoretical results in the test case. If the test results are the same as the theoretical results, it can be judged that the logic test has passed; otherwise, it can be judged that the test has failed.

[0033] At the beginning of the test, the test control module 10 may output a control signal to control the output selection module 200 to select the test pattern output by the test pattern output module 11. For example, the test control module 10 may output a control signal to the output selection module 200 to instruct the output selection module 200 to send a data request to the test pattern output module 11, or the test control module 10 may control the test pattern output module 11 to send a test pattern to the output selection module 200 and instruct the output selection module 200 to receive the test pattern.

[0034] Then, the output device 400 can output the test pattern to the input device 500 according to the test pattern received by the output selection module 200 and the clock adjustment module 300 controlled by the test control module 10. Among them, the output device 400 may include an analog output unit, which is controlled by the test control module 10 to turn on and output data. In order to test the performance of the chip at different data transmission rates (bit rates), the test circuit may include a clock adjustment module 300 for simulating multiple data transmission rates (bit rates). Since the bit rate is positively correlated with the symbol rate (baud rate), and the symbol rate is directly determined by the clock frequency, it can be understood that the data transmission rate will be faster at a higher clock frequency.

[0035] In some possible implementations, the clock adjustment module 300 can control the rate of outputting the test pattern within a preset frequency range according to a preset step size. According to relevant specifications, in the auxiliary channel signal communication of the chip, the clock frequency needs to cover the range of 830 kilohertz (KHz) to 1.25 megahertz (MHz), that is, the lower limit of the preset frequency range can be 830KHz, and the upper limit of the preset frequency range can be 1.25 MHz. In some possible implementations, the clock adjustment module 300 can cover the preset frequency range for testing with a step size of 10 KHz. For example, after all test patterns are transmitted at a clock frequency of 830 KHz, the test patterns are transmitted at a clock frequency of 840 KHz, until all test patterns are finally transmitted at a clock frequency of 1.25 MHz.

[0036] Next, the input device 500 can obtain parsed data according to the test pattern and input the parsed data to the input selection module 600. The input device 500 can include an analog input unit, which is controlled by the test control module 10 to be turned on and input data.

[0037] Finally, the test control module 10 can also control the input selection module 600 to select the test comparison module 12 to determine the test result of the auxiliary channel logic of the display interface according to the parsing data and the theoretical result. Among them, the test comparison module 12 includes the test case output by the test pattern output module 11, that is, the test comparison module 12 includes the test pattern and the corresponding theoretical result. Therefore, the test comparison module 12 can compare the parsing data obtained by the input device 500 with the theoretical result. When the parsing data matches the theoretical result successfully, it is determined that the logic test of the auxiliary channel passes. When the parsing data fails to match the theoretical result, it is determined that the logic test fails.

[0038] Based on the above description, the present application provides a test circuit for the auxiliary channel logic of the display interface. The test circuit is integrated inside the chip and uses hardware to directly test, reducing the complexity of signal transmission. On the one hand, it can realize automatic, efficient and comprehensive testing of the auxiliary channel logic according to preset test cases; on the other hand, the test circuit includes a clock adjustment module, which can cover all data transmission rate tests in the protocol to ensure the comprehensiveness of the test.

[0039] See also Figure 2 It is a structural schematic diagram of another test circuit for display interface auxiliary channel logic disclosed in an embodiment of the present application.

[0040] and Figure 1 Compared with the public test circuit, Figure 2The disclosed test circuit also includes a sending buffer module 700 and a receiving buffer module 800. After the output selection module 200 receives the test pattern, it will first output the test pattern to the sending buffer module 700, and then output the test pattern to the output device 400 through the sending buffer module 700. After the input device 500 parses the parsed data, it will first input the parsed data to the receiving buffer module 800, and then input the parsed data to the input selection module 600 through the receiving buffer module 800. Among them, the sending buffer module 700 and the receiving buffer module 800 play the role of temporarily storing data and coordinating data transmission between different rates or different interfaces, so as to ensure smooth and reliable data transmission. For example, a first-in-first-out (FIFO) buffer memory can be selected.

[0041] See also Figure 3 This is a structural schematic diagram of another test circuit for display interface auxiliary channel logic disclosed in an embodiment of the present application.

[0042] and Figure 1 or Figure 2 Compared with the public test circuit, Figure 3 In the disclosed test circuit, the processor also includes a conventional analysis module 14 and a conventional output module 15. The dotted line indicates that the sending buffer module and the receiving buffer module are optional structures. The AUX signal usually has positive and negative polarities, which are represented by "+" and "-" in the figure. The conventional analysis module is used to analyze the auxiliary channel signal input by the external control through the input device, and the conventional output module is used to output the auxiliary channel signal to the outside of the chip through the output device. That is, in a non-test scenario, when the chip communicates with the outside through the auxiliary channel, data will be received and sent respectively.

[0043] Specifically, in the scenario of communicating with the outside, the input device 500, the input selection module 600, the conventional analysis module 14 and the possible receiving buffer module 800 can constitute a receiving module, and the input device 500 receives the auxiliary channel signal from the outside and sends it to the conventional analysis module 14 via (receiving buffer module 800) and the input selection module 600; the output device 400, the output selection module 200, the conventional output module 15 and the possible sending buffer module 700 can constitute a sending module, and the conventional output module 15 outputs the auxiliary channel signal to the outside via the output selection module 200, (sending buffer module 700) and the output device 400. Among them, the two processes of the chip receiving external signals and sending signals to the outside are independent.

[0044] Based on the test circuit of the auxiliary channel logic of the above-mentioned display interface, the present application provides a chip, which is described in detail below with reference to the accompanying drawings.

[0045] See also Figure 4, which is a schematic diagram of the structure of a chip disclosed in an embodiment of the present application.

[0046] The chip 10000 provided in the embodiment of the present application includes the test circuit 100 described in the above embodiment. The chip can support auxiliary channel communication and has both the signal sending function and the signal receiving function, for example, it is a chip for audio signal transmission, such as a wireless audio chip, etc. The embodiment of the present application does not limit the specific type of the chip.

[0047] Based on the above content, the present application also provides a method for testing the auxiliary channel logic of the display interface. Figure 5 A schematic diagram of a method for testing the auxiliary channel logic of a display interface is shown, and the method is implemented based on the above-mentioned test circuit and specifically includes: S502: The test control module controls the output selection module to select the test pattern output by the test pattern output module, wherein the test control module and the test pattern output module are included in the processor, and the test pattern output module includes test cases covering the specification requirements, and the test cases include test patterns and theoretical results of auxiliary channel signals.

[0048] S504: Outputting the test pattern to the inputter based on the clock adjustment module controlled by the test control module according to the outputter.

[0049] S506: Inputting the parsed data obtained according to the test pattern to the input selection module based on the input device.

[0050] S508: The test control module controls the input selection module to select a test comparison module to determine the test result of the display interface auxiliary channel logic according to the analysis data and the theoretical result, and the test comparison module is included in the processor.

[0051] When the parsed data and the theoretical result match successfully, it is determined that the test of the auxiliary channel logic of the display interface passes; otherwise, it is determined that the test of the auxiliary channel logic of the display interface fails.

[0052] The specific details of the above steps are similar to those in the previous text and will not be repeated here.

[0053] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system or device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0054] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0055] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0056] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0057] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A test circuit for display interface auxiliary channel logic, characterized in that: The test circuit is integrated inside the chip, and the test circuit includes a processor, an output selection module, a clock adjustment module, an output device, an input device and an input selection module; The processor comprises a test control module and a test pattern output module, wherein the test pattern output module comprises test cases covering specification requirements, wherein the test cases comprise test patterns and theoretical results of auxiliary channel signals, and the test control module is used to control the output selection module to select the test pattern output by the test pattern output module; The output device is used to output the test pattern to the input device according to the clock adjustment module controlled by the test control module; The input device is used to input the parsed data obtained according to the test pattern into the input selection module; The processor also includes a test comparison module; The test control module is further used to control the input selection module to select the test comparison module to determine the test result of the display interface auxiliary channel logic according to the analysis data and the theoretical result.

2. The test circuit according to claim 1, characterized in that: The clock adjustment module is used to control the rate of outputting the test pattern within a preset frequency range according to a preset step size.

3. The test circuit according to claim 2, characterized in that: The preset step size is 10 kHz, the lower limit of the preset frequency range is 830 kHz, and the upper limit of the preset frequency range is 1.25 MHz.

4. The test circuit according to claim 1, characterized in that: The test circuit further includes a sending buffer module, and the output selection module outputs the test pattern to the outputter through the sending buffer module.

5. The test circuit according to claim 1, characterized in that: The test circuit further includes a receiving buffer module, and the input device inputs the parsed data to the input selection module through the receiving buffer module.

6. The test circuit according to claim 1, characterized in that: The processor further comprises a conventional analysis module and a conventional output module, wherein the conventional analysis module is used to analyze the auxiliary channel signal inputted by the external control through the input device, and the conventional output module is used to output the auxiliary channel signal to the outside of the chip through the output device.

7. The test circuit according to any one of claims 1 to 6, characterized in that: The test code pattern is a code pattern that complies with the Manchester encoding rule.

8. A chip, characterized in that: The chip comprises the test circuit according to any one of claims 1 to 7.

9. A method for testing the auxiliary channel logic of a display interface, characterized in that: Based on the test circuit implementation described in any one of claims 1 to 7, the method comprises: According to the test control module, the output selection module is controlled to select the test pattern output by the test pattern output module, the test control module and the test pattern output module are included in the processor, the test pattern output module includes test cases covering the specification requirements, and the test cases include the test pattern and theoretical results of the auxiliary channel signal; Based on the output device outputting the test pattern to the input device according to the clock adjustment module controlled by the test control module; Inputting parsed data obtained according to the test pattern into an input selection module based on the input device; The test control module controls the input selection module to select a test comparison module to determine the test result of the display interface auxiliary channel logic according to the analysis data and the theoretical result, and the test comparison module is included in the processor.

10. The method according to claim 9, characterized in that The step of determining the test result of the display interface auxiliary channel logic according to the analytical data and the theoretical result includes: When the parsed data and the theoretical result match successfully, it is determined that the test of the display interface auxiliary channel logic passes; Otherwise, it is determined that the test of the display interface auxiliary channel logic fails.

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