An HDMI digital signal processing method and apparatus

Abstract

The present invention provides an HDMI digital signal processing method and apparatus, which transmit original data and an original reference clock from a video source through a transmitter and a receiver. The method includes the following steps: receiving the original data and the original reference clock by the transmitter; performing encoding processing on the original data to obtain encoded data; performing N-fold frequency multiplication processing on the encoded data and the original reference clock simultaneously and then transmitting them; wherein, the N-fold frequency multiplication processing of the encoded data is: sequentially replicating the encoded data N times bit by bit, and correspondingly splitting and forming N groups of frequency-multiplied data. The present invention solves the requirement for video resolution lower than the minimum reference clock of the PLL by the method of simultaneously increasing the frequency of data and clock; further, by the method of replicating data bit by bit, the recovery of the original data can be simply realized by using the existing serialization and deserialization processes.

Description

Technical Field

[0001] This application relates to the field of video data transmission, and particularly to an HDMI digital signal processing method and apparatus. Background Art

[0002] HDMI (High-Definition Multimedia Interface) is a widely used digital interface for transmitting high-definition video and audio signals. HDMI uses TMDS differential signals for data transmission. A standard HDMI consists of three pairs of differential channels for transmitting data and a pair of TMDS clock channels. Each data transmission channel can transmit a 10-bit data stream within one clock cycle.

[0003] In an HDMI interface, digital signal transmission and reception are achieved through a TX (transmitter) and an RX (receiver). The main function of the transmitter is to encode and serialize / deserialize the original digital audio-visual signal into an HDMI signal for transmission. The main function of the RX is to receive and decode the HDMI signal to restore the original audio-visual data. In the above process, a high-precision clock signal also needs to be generated by a PLL (phase-locked loop) set in the transmitter to ensure synchronous data transmission.

[0004] Normally, the reference clock input to the PLL should be equal to the TMDS clock in the corresponding HDMI video format. When the actual TMDS clock does not meet the minimum reference clock input of the PLL, the external clock needs to be processed to be several times the original clock before being input to the PLL so that the PLL outputs the clock required for the transmission link. And in this process, in order to achieve data and clock matching, the original video data also needs to be oversampled before being transmitted to the link channel.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solutions of this application and facilitating the understanding of those skilled in the art. It cannot be simply considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of this application. Summary of the Invention

[0006] To solve the above problems, the present invention provides an HDMI digital signal processing method and apparatus. In a first aspect, an HDMI digital signal processing method is provided, which transmits the original data and the original reference clock from a video source through a transmitter and a receiver, and includes the following steps:

[0007] Use the transmitter to receive the original data and the original reference clock;

[0008] Perform encoding processing on the original data to obtain encoded data;

[0009] The encoded data and the original reference clock are both subjected to N-fold frequency multiplication and then transmitted.

[0010] Among them, the N-fold frequency multiplication of the encoded data is: the encoded data is sequentially copied N times bit by bit, and correspondingly split into N groups of frequency-multiplied data.

[0011] The present invention solves the requirement for video resolution lower than the minimum reference clock of the PLL by simultaneously increasing the frequency of data and clock, and together with other video formats that meet the requirements of the PLL minimum reference clock, covers all resolution formats for HDMI transmission; further, by the method of bit-by-bit replication of data, the low-frequency data is oversampled onto the high-frequency clock, and the existing serialization and deserialization processes can be utilized to naturally realize the recovery of the original data without additional processing operations.

[0012] The transmitter receives the original data corresponding to one pixel signal in each cycle of the original reference clock, and the original data is parallel data.

[0013] The original data is subjected to data encoding processing using TMDS technology to obtain corresponding encoded data, and the encoded data is 10-bit parallel data.

[0014] The encoded data is sequentially copied N times from the high bit to the low bit bit by bit, and each time 10 bits of data are correspondingly split to form a group of frequency-multiplied data for sending until all the N groups of frequency-multiplied data are sent out.

[0015] The encoded data in the current clock cycle is subjected to temporary storage processing, and the temporarily stored encoded data is subjected to N-fold frequency multiplication processing.

[0016] The N-fold frequency multiplication of the original reference clock is: the original reference clock is frequency-multiplied by N and then input into the phase-locked loop of the physical layer IP core of the serial deserializer as a reference clock to generate a corresponding first transmission clock; the frequency of the reference clock is greater than or equal to the startup frequency of the physical layer IP core of the serial deserializer.

[0017] The process of simultaneously performing N-fold frequency multiplication on the encoded data and the original reference clock and then transmitting them includes: Based on the first parallel transmission clock, sequentially transmitting the N groups of frequency-multiplied data to the serial deserializer physical layer IP core for serialization processing, obtaining N groups of HDMI digital signals and transmitting them together with the correspondingly generated first serial transmission clock; Using a receiver to receive the N groups of HDMI digital signals and the first serial transmission clock, and reducing the frequency of the first serial transmission clock to 1 / N times to generate a second serial transmission clock; Based on the second serial transmission clock, transmitting the N groups of HDMI digital signals to the serial deserializer physical layer IP core, extracting the intermediate value of consecutive N-bit signals in the same clock cycle as one signal and then performing deserialization processing to obtain a group of parallel data and transmitting it together with the correspondingly generated second parallel transmission clock.

[0018] Using a receiver to receive the parallel data and the second parallel transmission clock; Restoring the parallel data to the original data through decoding processing; Using the second parallel transmission clock as the original reference clock and transmitting it together with the original data.

[0019] On the other hand, the present invention provides an HDMI digital signal processing device, the processing device includes a transmitter and a receiver, and the processing device is used to implement an HDMI digital signal processing method as described in any one of the first aspects.

[0020] The transmitter and the receiver are implemented using an FPGA chip.

[0021] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) The method for implementing data upsampling in the present invention can oversample low-frequency data onto a high-frequency clock after bit-by-bit replication, and can be more flexible when upsampling data; 2) The data upsampling method of the present invention solves the requirement for video resolution lower than the minimum reference clock of the PLL, and together with other video formats that meet the PLL minimum reference clock requirement, covers all resolution formats of HDMI transmission; 3) The present invention can conveniently implement the restoration of the original data by using the existing serialization and deserialization processes. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for use in the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a schematic diagram of HDMI transmission.

[0024] Figure 2 Schematic diagram of the digital signal processing flow provided in this embodiment. Detailed implementation manners

[0025] The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0026] Hereinafter, each embodiment of the present application will be described in detail with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided for the readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0027] The steps in the following embodiments do not correspond one by one to the content of the invention.

[0028] Embodiment 1

[0029] As Figure 1 shown is a schematic diagram of HDMI transmission in the prior art. Referring to Figure 1 , a transmitter (TX, HDMI Transmitter) and a receiver (RX, HDMI Receiver) are two key components for realizing HDMI digital signal transmission. A video source is used to provide original data and a corresponding reference clock. The original data is parallel data, and each pixel is usually 8b data (i.e., 8-bit data, generally RGB or YUV data. Taking RGB as an example, each channel is 8 bits and there are three channels in total); the transmitter is connected to the video source. After receiving the original data and the reference clock, it will perform data encoding processing and parallel-to-serial conversion processing on them. Taking the reception of RGB data as an example, there are three transmission channels. For each transmission channel, the transmitter will simultaneously receive data on a corresponding bit through 8 interfaces respectively, convert it into 10-bit encoded data through TMDS encoding technology, and convert it into high-speed serial data (i.e., HDMI digital signal) and then send it through a data channel (there are three data channels, namely data channel 0 / 1 / 2, corresponding to one transmission channel respectively). Correspondingly, the receiver is connected to the transmitter, and its main function is to receive and decode the HDMI digital signal and restore it to the original data, that is, to convert the HDMI digital signal into parallel data and perform decoding to restore it to the original RGB or YUV format. Both the transmitter and the receiver are implemented by FPGA chips.

[0030] In the above process, both the serialization and deserialization processes of data require the SerDes PHY IP (i.e., serializer / deserializer physical layer IP core) for processing. The SerDes PHY IP is a physical layer interface integrating SerDes (serializer / deserializer) functions, which can convert parallel data into serial data for high-speed transmission and restore the serial data to parallel data at the receiving end. That is, the SerDes PHY IP is an essential component for completing HDMI transmission.

[0031] It can be understood that in order to ensure the synchronous transmission of data, a high-precision clock signal is essential. As Figure 1 shown, a dedicated clock signal channel: the TMDS clock channel is provided in the HDMI interface, and this channel is used for the transmission of the clock signal. A phase-locked loop is provided in the SerDes PHY IP, which can lock the phase and frequency using the input reference clock to generate the required transmission clock to ensure the reliable transmission of HDMI digital signals. The frequencies of the transmission clocks required for HDMI digital signals corresponding to videos with different resolutions are different. As the resolution decreases, the corresponding required frequency of the transmission clock also decreases. However, the startup of the SerDes PHY IP has a minimum clock frequency (hereinafter referred to as the startup frequency). When a clock signal with a frequency lower than the startup frequency is input, the SerDes PHY IP cannot be started normally, thus resulting in the failure to achieve the transmission of HDMI digital signals. Therefore, when the frequency of the transmission clock required for a video with a certain resolution is greater than or equal to the startup frequency of the SerDes PHY IP, it is sufficient to make the frequency of the reference clock input to the phase-locked loop equal to the required transmission clock frequency; when the frequency of the transmission clock required for a video with a certain resolution is less than the startup frequency of the SerDes PHY IP, the SerDes PHY IP cannot be started directly using a clock signal with this frequency. Therefore, the original clock signal needs to be frequency-multiplied before being input to the phase-locked loop. At this time, the transmission clock generated by the phase-locked loop can meet the startup requirements of the SerDes PHY IP. However, when the clock signal is frequency-multiplied, it is necessary to process the corresponding data to ensure the error-free transmission of the data.

[0032] For clarity, the following is illustrated by an example: For example, when the startup frequency of the SerDes PHY IP is 50 MHz and the frequency of the transmission clock required for the video with resolution A is 75 MHz, at this time, a reference clock with a frequency of 75 MHz can be used, and there is no need to process the reference clock and the original data of the video source. Specifically, the transmitter receives the reference clock and the original data. The phase-locked loop generates the corresponding transmission clock according to the input reference clock. After the transmitter converts the original data (8 bits, parallel data) into the corresponding HDMI digital signal (10 bits, serial data) through data encoding and serial-to-parallel conversion processing, it is sent out. The receiver receives the transmission clock signal and the HDMI digital signal, and then converts the HDMI digital signal (10 bits, serial data) into the corresponding original data (8 bits, parallel data) through serial-to-parallel conversion and decoding processing and then sends it out.

[0033] In another case, for example, when the startup frequency of the SerDes PHY IP is 50 MHz and the frequency of the transmission clock required for the video with resolution B is 25 MHz, the original reference clock of 25 MHz cannot be directly used. In order to meet the startup of the SerDes PHY IP, the reference clock and the original data of the video source can be frequency-doubled. For example, the original reference clock of 25 MHz is tripled (x3) to 75 MHz as the reference clock input to the phase-locked loop. At this time, the transmission clock output by the phase-locked loop can meet the startup conditions of the SerDes PHY IP and can perform HDMI transmission. It should be understood that because the original reference clock is tripled, the corresponding original data also needs to be oversampled three times correspondingly to meet the data and clock matching. In the prior art, the oversampling of the original data is performed according to the pixel signal. The original data corresponding to each pixel is 8-bit parallel data. The transmitter will first encode it and convert it from parallel to serial to 10-bit serial data (for example, 1010101010), and then triple-frequency it to 101010101010101010101010101010 before sending it out. Because the clock signal and the data are frequency-doubled, the process of restoring it to the original data (8 bits, parallel data) is relatively cumbersome.

[0034] To solve the above problems, the present invention provides an FPGA-based HDMI digital signal processing method, which realizes the purpose of data upsampling by sampling the data by bit multiple times. Specifically, refer to Figure 2As shown, a flowchart of an HDMI digital signal processing method is given. In this embodiment, taking the tripling (x3) of the original reference clock of 25 MHz to 75 MHz as an example. As mentioned above, HDMI transmits data in units of pixels, and the color information of each pixel is divided into three parts and transmitted through three data channels, that is, each color channel corresponds to occupying one TMDS data channel. Hereinafter, the transmission process of one of the data channels is taken as an example.

[0035] Step 1: The video source sends out the original data and the corresponding original reference clock.

[0036] As Figure 2 shown, first of all, the video source sends out the original data and the corresponding original reference clock to the transmitter. In this embodiment, the original data is a parallel data stream, the data bit width corresponding to each pixel is 8 bits, and the frequency of the corresponding original reference clock is 25 MHz. In other embodiments, the original data is also a parallel data stream, but the bit width corresponding to each pixel and the frequency of the corresponding original reference clock are not limited.

[0037] Step 2: The transmitter IP core receives the original data and performs data encoding.

[0038] Refer to Figure 2 shown, in this embodiment, for the sake of easy understanding, the functions such as serialization, deserialization, and generation of related clock signals performed by the SerDes PHY IP in the transmitter and receiver are split and represented in the TX end and RX end of the serial deserializer physical layer IP core. That is, the transmitter mainly includes two major parts: the transmitter IP core and the TX end of the serial deserializer physical layer IP core, while the receiver mainly includes two major parts: the receiver IP core and the RX end of the serial deserializer physical layer IP core.

[0039] First of all, the transmitter IP core receives the original data and the original reference clock, and it receives 8-bit parallel data corresponding to one pixel in each clock cycle; and after data encoding through the TMDS technology (encoded by the data encoding module), the corresponding encoded data is obtained, and this encoded data is 10-bit parallel data (for example, 1010101010).

[0040] Step 3: Perform frequency doubling processing on the original reference clock and the encoded data simultaneously.

[0041] It can be understood that in order to start the SerDes PHY IP, the original reference clock (25 MHz) can be tripled as the reference clock (75 MHz) and input into the phase-locked loop, and the phase-locked loop generates the corresponding transmission clock (75 MHz); at the same time, in order to match the clock and the data, it is necessary to perform corresponding triple upsampling on the data in each clock cycle. As Figure 2As shown in the figure, the original reference clock and the encoded data are frequency - doubled by the clock and data frequency - up - conversion module. On the one hand, the original reference clock is tripled and then input into the phase - locked loop at the TX end of the serial deserializer physical layer IP core as the reference clock, so that the phase - locked loop generates the corresponding first parallel transmission clock (75 MHz). The clock frequency - doubling method here can be implemented by existing technologies and will not be elaborated here. On the other hand, the encoded data is also tripled. The specific data frequency - up - conversion method is as follows:

[0042] 1) Receive the encoded data;

[0043] It can be understood that the encoded data (for example, 1010101010) is parallel data, so the corresponding number of receiving ports is required, that is, there are 10 ports (port 9 to port 0), which are respectively used to receive one digit (that is, port 9 receives 1, port 8 receives 0,..., port 1 receives 1, port 0 receives 0). That is, in one clock cycle of the original reference clock, 10 - bit data can be transmitted.

[0044] 2) Copy each bit three times in sequence and split it into three transmissions;

[0045] After the encoded data 1010101010 is copied three times bit by bit from the high - order bit to the low - order bit, 111000111000111000111000111000 is obtained. Since the HDMI digital signal is 10 - bit data, 111000111000111000111000111000 should be split into three groups of frequency - doubled data (that is, 1110001110, 0011100011, and 1000111000) and then sent to the SerDes PHY IP for serial - to - parallel conversion processing.

[0046] A specific process can be divided into the following steps:

[0047] 1. First, copy the encoded data three times bit by bit from the high - order bit to the low - order bit and then output data_o={data_i[9],data_i[9],data_i[9],data_i[8],data_i[8],data_i[8],data_i[7],data_i[7],data_i[7],data_i[6]}; where data_o represents the output data, that is, the first group of frequency - doubled data, and data_i[9] refers to the 9th bit of the data encoding, and can also be understood as the received data of port 9;

[0048] To prevent the subsequent data from being received before the encoded data of the current group is completely processed, which may cause the current data to become invalid, the received encoded data can be temporarily stored each time. After temporary storage, the encoded data is copied and split bit by bit and then sent. In other embodiments, if it can be processed in a timely manner, temporary storage may not be necessary.

[0049] 2. Then, continue to copy the encoded data at lower bit positions bit by bit and output data_o = {data_temp[6], data_temp[6], data_temp[5], data_temp[5], data_temp[5], data_temp[4], data_temp[4], data_temp[4], data_temp[3], data_temp[3]}; where data_o represents the output data, which here corresponds to the data after the second group of frequency doubling. data_temp[6] refers to the 6th bit of the encoded data after temporary storage.

[0050] 3. Finally, copy the encoded data of the remaining bits three times bit by bit and output data_o = {data_temp[3], data_temp[2], data_temp[2], data_temp[2], data_temp[1], data_temp[1], data_temp[1], data_temp[0], data_temp[0], data_temp[0]}; where data_o represents the output data, which here corresponds to the data after the third group of frequency doubling.

[0051] The above three steps complete the upsampling and splitting of a group of encoded data. For each subsequent group of encoded data, the above processing is performed in sequence.

[0052] At this time, the frequency doubling process of the original reference clock and the encoded data has been completed, and the first parallel transmission clock and three groups of frequency-doubled data are obtained correspondingly. Since the frequency of the first parallel transmission clock (75 MHz) is three times that of the original reference clock (25 MHz) (i.e., one clock cycle of the original reference clock is equal to three clock cycles of the first parallel transmission clock), the number of bits corresponding to the three groups of frequency-doubled data is also three times that of the encoded data. That is, in one clock cycle of the first parallel transmission clock, one group of frequency-doubled data can be transmitted correspondingly, and in three clock cycles of the first parallel transmission clock, three groups of frequency-doubled data are transmitted correspondingly. Therefore, the first parallel transmission clock and the three groups of frequency-doubled data are still corresponding.

[0053] Step 4: Perform serial-to-parallel conversion and then send it to the receiver.

[0054] The three groups of data after frequency doubling (1110001110, 0011100011, and 1000111000) obtained after frequency doubling splitting are parallel data, which need to be first converted into serial data (i.e., HDMI digital signal) and then transmitted to the receiver by the transmitter.

[0055] As described above, in HDMI, the serialization and deserialization processes of data are both processed by the SerDes PHY IP. The SerDes PHY IP includes two parts. One is the serialization processing module for the parallel data stream of the transmitter (i.e., the TX end of the serial deserialization physical layer IP core), and the other is the parallelization processing module for the serial data stream of the receiver (i.e., the RX end of the serial deserialization physical layer IP core).

[0056] Specifically, as described above, in one clock cycle of the first parallel transmission clock, it corresponds to a group of data after frequency doubling. Then the above three groups of data after frequency doubling will be sequentially sent to the parallel-to-serial conversion module at the TX end of the SerDes PHY IP in three consecutive clock cycles of the first parallel transmission clock to ensure that there is no out-of-order situation. The parallel-to-serial conversion module sequentially converts the three groups of data after frequency doubling into three groups of serial data (i.e., three groups of HDMI digital signals) and then sends them out in sequence. Specifically, the TX end of the SerDes PHY IP will sequentially send the three groups of HDMI digital signals, namely HDMI digital signal 1 (1110001110), HDMI digital signal 2 (0011100011), and HDMI digital signal 3 (1000111000), to the RX end of the SerDes PHY IP. It can be understood that the HDMI digital signal is high-speed serial data, and 1 bit of data is transmitted in each clock cycle under the serial clock. Therefore, the frequency of its corresponding first serial transmission clock (750 MHz) should be 10 times that of the first parallel transmission clock, and the three groups of HDMI digital signals are transmitted in 30 clock cycles.

[0057] Step 5: The receiver receives the HDMI digital signal and performs serial-to-parallel conversion and decoding.

[0058] Specifically, the RX end of the serial deserializer physical layer IP core sequentially receives three groups of HDMI digital signals and the corresponding first serial transmission clock (750 MHz). It will convert the 750 MHz first serial transmission clock into a 250 MHz second serial transmission clock by reducing the frequency by 1 / 3 through the clock down-conversion module. At this time, each clock cycle under the second serial transmission clock corresponds to three clock cycles under the first serial transmission clock. That is, three bits of data will be received in each clock cycle under the second serial transmission clock, and the middle value of the three consecutive bits received in the same clock cycle will be extracted and output. Specifically, three sampling clock phases (0°, 120°, 240°) are generated through the clock down-conversion module, corresponding to the middle positions of 3 bits in each group. Then, a 3-bit wide shift register is used to capture 3 consecutive bits in the second serial transmission clock domain, and the middle value is extracted through a selector and output. Then, the three groups of HDMI digital signals (i.e., 111000111000111000111000111000) finally receive 10-bit serial data (1010101010), which is then converted into the corresponding 10-bit parallel data 1010101010 (corresponding to the encoded data) by the serial-to-parallel conversion module.

[0059] After the RX end of the serial deserializer physical layer IP core completes the serial-to-parallel conversion, it will send the obtained parallel data and the corresponding clock signal to the receiver IP core. It can be understood that since the serial data is converted into parallel data, the corresponding clock signal also needs to be changed, that is, from the 250 MHz second serial transmission clock to the 25 MHz second parallel transmission clock. The receiver IP core receives the second parallel transmission clock and the parallel data, decodes the parallel data through the data decoding module therein, and finally obtains the original data corresponding to the video source transmission; and the frequency of the second parallel transmission clock is the same as the original reference clock, which can be sent out together with the original reference clock and the original data.

[0060] Through the data up-conversion method of replicating by bit, the present invention can naturally realize the recovery of the original data by using the existing serialization and deserialization processes, and is more concise than the existing data up-conversion methods without additional processing operations.

[0061] In this embodiment, taking the triple frequency multiplication of the clock and data simultaneously as an example, in other embodiments, the multiple of the frequency multiplication can be confirmed according to the actual situation as long as the startup of the SerDes PHY IP can be ensured. It can be understood that the original reference clock is up-converted by N times (N is a positive integer, N≥2), and at the same time, the corresponding encoded data of each pixel point is replicated by N times by bit and split into N parts and sent sequentially.

[0062] The present invention also provides an HDMI digital signal processing device. The processing device includes a transmitter and a receiver, and is configured to implement an HDMI digital signal processing method as described above. The transmitter and the receiver can be implemented using FPGA chips.

[0063] Some common English nouns or letters used in the present invention for the convenience of clear description are only for exemplary reference rather than limiting interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0064] It should also be noted that, in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. An HDMI digital signal processing method, which transmits original data and original reference clock from a video source through a transmitter and a receiver, is characterized in that It includes the following steps: Use a transmitter to receive the original data and the original reference clock; Perform encoding processing on the original data to obtain encoded data; Perform N-fold frequency multiplication processing on the encoded data and the original reference clock simultaneously and then transmit; Among them, the N-fold frequency multiplication processing of the encoded data is: sequentially replicate the encoded data N times by bit positions, and correspondingly split to form N groups of frequency-multiplied data; The N-fold frequency multiplication processing of the original reference clock is: perform N-fold frequency multiplication on the original reference clock and then input it into the phase-locked loop of the serial deserializer physical layer IP core as a reference clock to generate a corresponding first parallel transmission clock; the frequency of the reference clock is greater than or equal to the startup frequency of the serial deserializer physical layer IP core; The process of the transmission includes: based on the first parallel transmission clock, sequentially transmit the N groups of frequency-multiplied data to the serial deserializer physical layer IP core for serialization processing, obtain N groups of HDMI digital signals and transmit them together with the correspondingly generated first serial transmission clock to the receiver.

2. The HDMI digital signal processing method according to claim 1, wherein, The transmitter receives the original data corresponding to one pixel signal within each cycle of the original reference clock, and the original data is parallel data.

3. A method for processing HDMI digital signals according to claim 2, characterized in that, Use TMDS technology to perform data encoding processing on the original data to obtain corresponding encoded data, and the encoded data is 10-bit parallel data.

4. A method for processing HDMI digital signals according to claim 3, wherein, Replicate the encoded data N times in sequence from the high bit to the low bit by bit position, and split to form a group of frequency-multiplied data for transmission every 10 bits of data until all the N groups of frequency-multiplied data are sent out.

5. A method for processing HDMI digital signals according to claim 3, characterized in that, Perform temporary storage processing on the encoded data in the current clock cycle, and perform N-fold frequency multiplication processing on the encoded data after the temporary storage processing.

6. A method for processing HDMI digital signals according to claim 1, characterized in that, The process of performing N-fold frequency multiplication processing on the encoded data and the original reference clock simultaneously and then transmitting further includes: Use a receiver to receive the N groups of HDMI digital signals and the first serial transmission clock, and reduce the frequency of the first serial transmission clock to 1 / N times to generate a second serial transmission clock; Based on the second serial transmission clock, transmit the N groups of HDMI digital signals to the serial deserializer physical layer IP core, extract the intermediate value of consecutive N-bit signals in the same clock cycle as one signal and then perform deserialization processing, obtain a group of parallel data and transmit it together with the correspondingly generated second parallel transmission clock.

7. An HDMI digital signal processing method according to claim 6, characterized in that, Use a receiver to receive the parallel data and the second parallel transmission clock; Restore the parallel data to the original data through decoding processing; Transmit the second parallel transmission clock as the original reference clock together with the original data.

8. An HDMI digital signal processing device, characterized in that, The processing device includes a transmitter and a receiver, and the processing device is used to implement a method for processing HDMI digital signals as described in any one of claims 1-7.

9. An HDMI digital signal processing device according to claim 8, wherein, The transmitter and the receiver are implemented using an FPGA chip.

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