Variable MIM capacitor and preparation method thereof

Abstract

The invention provides a variable MIM capacitor and a preparation method thereof. According to the preparation method of the variable MIM capacitor, the characteristic that different photoresist layers have different light sensitivities is utilized, and a photoresist structure with a stepped morphology is formed under the same photomask. And taking the mask block as a mask block for etching the capacitor substrate so as to obtain a capacitor structure with a stepped morphology. And based on the stepped capacitor structure, various different capacitance values can be obtained through a capacitor series connection principle, so that the requirements of different capacitance values in the chip can be met by using one stepped capacitor structure without using more single-medium capacitors, thereby effectively reducing the occupancy rate of the MIM capacitor on the chip area, and improving the chip performance. And the miniaturization development trend of the device is met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a variable MIM capacitor and a preparation method thereof. Background Art

[0002] Metal-Insulator-Metal (MIM) capacitors have the advantages of high capacitance density, stable high-frequency performance, low loss, high temperature resistance, and high reliability, and are widely used in integrated circuits and other fields. Figure 1 As shown, the structure of the existing MIM capacitor usually includes two layers of metal plates 100 and a single layer of dielectric layer 101, and the dielectric layer 101 is located between the two layers of metal plates 100. According to the calculation formula of the capacitance value: C = εS / 4πkd, it can be known that ε is the dielectric constant, which is determined by the material of the dielectric layer 101; k is the electrostatic constant, and the electrostatic constant k is a fixed value under certain conditions. Therefore, in the existing process, the capacitance value of the MIM capacitor is adjusted by adjusting the thickness d of the dielectric layer 101 and the area S of the dielectric layer 101. However, if the thickness d of the dielectric layer 101 is reduced in order to increase the capacitance value, there will be a risk of time-dependent dielectric breakdown (TDDB). If the capacitance value is increased by expanding the area S of the dielectric layer 101, it is not conducive to the development trend of digitalization and miniaturization of semiconductor processes. In addition, in order to meet the requirements of different capacitance values ​​in the chip circuit, it is necessary to set a variety of different MIM capacitors, which will occupy a large chip area and is not conducive to the development trend of device miniaturization.

[0003] Therefore, a new MIM capacitor is urgently needed to solve the above technical problems. Summary of the invention

[0004] The object of the present invention is to provide a variable MIM capacitor and a method for preparing the same, so as to solve at least one technical problem of how to obtain a multi-stage variable capacitor and how to reduce the chip area occupancy rate of the MIM capacitor.

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a variable MIM capacitor, comprising:

[0006] A capacitor substrate is provided, the capacitor substrate comprising a plurality of stacked metal layers, and a dielectric layer is disposed between two adjacent metal layers;

[0007] At least two photoresist layers are formed on the top surface of the capacitor substrate; and the light sensitivity of each photoresist layer is different;

[0008] Photolithography the at least two photoresist layers using the same photomask to form a stepped photoresist structure and expose a portion of the top surface of the capacitor substrate;

[0009] Using the stepped photoresist structure as a barrier, the capacitor substrate is etched until the metal layer at the bottom is exposed, and the metal layers and dielectric layers in the capacitor substrate after etching are combined into a stepped capacitor structure.

[0010] Optionally, in the method for preparing the variable MIM capacitor, during the process of etching the capacitor substrate, the exposed portions of the photoresist layers in each layer of the stepped photoresist structure are removed by etching.

[0011] Optionally, in the method for preparing the variable MIM capacitor, each metal layer in the capacitor substrate and the dielectric layer located below the metal layer form a first-order membrane structure; wherein,

[0012] In the process of etching the capacitor substrate, the membrane structures of each level are etched at least sequentially from top to bottom; and while the exposed parts of the membrane structures of each level are etched, the stepped photoresist structure is consumed synchronously.

[0013] Optionally, in the method for preparing the variable MIM capacitor, the capacitor substrate includes an N-stage film structure; N≥2, and N is an integer; wherein the number of layers of the photoresist layer is equal to the number of layers of the dielectric layer.

[0014] Optionally, in the method for preparing the variable MIM capacitor, during the process of etching the capacitor substrate, each time a portion of the surface of the metal layer of the first-order membrane structure is exposed by etching, at least the photoresist layer on the top layer is simultaneously consumed.

[0015] Optionally, in the method for preparing the variable MIM capacitor, an anti-reflective coating is further formed between the top surface of the capacitor substrate and the at least two photoresist layers; and,

[0016] During the etching of the capacitor substrate, the surface of the anti-reflective coating is gradually exposed as the stepped photoresist structure is consumed; and each time a portion of the surface of the metal layer of the membrane structure is exposed by etching, the exposed portion of the surface of the anti-reflective coating is removed by an etching process.

[0017] Optionally, in the method for preparing the variable MIM capacitor, during the process of etching the capacitor substrate, the process time of the over-etching process used when etching to expose the bottom metal layer is less than the process time of the over-etching process used when etching to expose the metal layers of each level of the membrane structure.

[0018] Optionally, in the method for preparing the variable MIM capacitor, the at least two photoresist layers are positive photoresist layers, and the photosensitivity of the at least two photoresist layers decreases from top to bottom; or, the at least two photoresist layers are negative photoresist layers, and the photosensitivity of the at least two photoresist layers increases from top to bottom; so that the planar size of each photoresist layer in the stepped photoresist structure formed by photolithography increases layer by layer from top to bottom; and,

[0019] With the stepped photoresist structure as a barrier, the plane size of each step of the membrane structure in the stepped capacitor structure formed by etching increases step by step from top to bottom, and the plane sizes of the metal layer and the dielectric layer in the membrane structure of the same step are the same.

[0020] Optionally, in the method for preparing the variable MIM capacitor, in the process of etching the capacitor substrate, etching gases used include: chlorine, boron trichloride, trifluoromethane and sulfur hexafluoride.

[0021] Optionally, in the method for preparing the variable MIM capacitor, after etching the capacitor substrate, the method for preparing the variable MIM capacitor further includes:

[0022] forming an intermetallic dielectric layer; the intermetallic dielectric layer covers the surface of the capacitor substrate after etching;

[0023] A plurality of metal plugs are formed; the plurality of metal plugs are arranged at intervals and all penetrate the intermetallic dielectric layer to connect with the corresponding metal layer; wherein each metal layer is connected with at least one metal plug.

[0024] Based on the same concept, the present invention also provides a variable MIM capacitor, which is prepared by the variable MIM capacitor preparation method, and the variable MIM capacitor includes:

[0025] Multiple metal layers, with a dielectric layer disposed between two adjacent metal layers; and each metal layer and each dielectric layer are combined into a stepped capacitor structure.

[0026] In summary, the present invention provides a variable MIM capacitor and a method for preparing the same. Compared with the prior art, the method for preparing the variable MIM capacitor utilizes the different light sensitivities of different photoresist layers to form a photoresist structure with a stepped morphology under the same photomask. And based on this, it is used as a mask to block the etching of the capacitor substrate, and then a capacitor structure with a stepped morphology is obtained. And based on the stepped capacitor structure, a variety of different capacitance values ​​can be obtained through the principle of capacitor series connection, then the use of one stepped capacitor structure can meet the needs of different capacitance values ​​in the chip, without the need to use more single dielectric capacitors, thereby effectively reducing the occupancy rate of the MIM capacitor to the chip area, which is in line with the miniaturization development trend of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0028] Figure 1 It is a structural schematic diagram of a single-medium variable MIM capacitor in the prior art.

[0029] Figure 2 4 is a flow chart of a method for preparing a variable MIM capacitor in an embodiment of the present invention.

[0030] Figure 3 Schematic diagram of a capacitor substrate in an embodiment of the present invention.

[0031] Figure 4 Schematic diagram of the positions of the first photoresist layer and the second photoresist layer in an embodiment of the present invention.

[0032] Figure 5 Schematic diagram of a stepped photoresist structure in an embodiment of the present invention.

[0033] Figure 6 Schematic diagram of removing the exposed portion of the anti-reflection coating in an embodiment of the present invention.

[0034] Figure 7 Schematic diagram of the process of etching the first-order film structure in an embodiment of the present invention.

[0035] Figure 8 It is a schematic diagram of a portion of the second dielectric layer and a portion of the second photoresist layer remaining during the etching of the first-stage film structure in an embodiment of the present invention.

[0036] Fig. 9 It is a schematic diagram of over-etching and removing the remaining second dielectric layer and second photoresist layer in an embodiment of the present invention.

[0037] Fig.10 Schematic diagram of the process of etching the second-stage film structure in an embodiment of the present invention.

[0038] Fig.11 It is a schematic diagram of the structure after the second-stage film structure etching is completed in an embodiment of the present invention.

[0039] Fig.12 Schematic diagram of the positions of the metal interlayer dielectric layer and the metal plug in an embodiment of the present invention.

[0040] Fig.13 Schematic diagram of a fourth-order variable MIM capacitor in an embodiment of the present invention.

[0041] And, in the attached drawings:

[0042] 100-metal plate; 101-dielectric layer;

[0043] 201-first metal layer; 202-first dielectric layer; 203-second metal layer; 204-second dielectric layer; 205-third metal layer; 206-anti-reflective coating; 207-first photoresist layer; 208-second photoresist layer; 209-intermetallic dielectric layer; 210-metal plug; 301-fourth-order variable MIM capacitor;

[0044] M-mask. DETAILED DESCRIPTION

[0045] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0046] In addition, the X-axis direction, Y-axis direction and Z-axis direction referred to in the present application specification are three directions perpendicular to each other in three-dimensional space; the plane size refers to the size on the plane where the X-axis direction - Y-axis direction is located.

[0047] See also Figure 2 , this embodiment provides a method for preparing a variable MIM capacitor, comprising:

[0048] Step 1 S10: providing a capacitor substrate, wherein the capacitor substrate comprises a plurality of stacked metal layers, and a dielectric layer is disposed between two adjacent metal layers;

[0049] Step 2 S20: forming at least two photoresist layers on the top surface of the capacitor substrate; and the light sensitivity of each photoresist layer is different;

[0050] Step three S30: photolithography the at least two photoresist layers using the same photomask to form a stepped photoresist structure and expose a portion of the top surface of the capacitor substrate;

[0051] Step 4 S40: using the stepped photoresist structure as a barrier, etching the capacitor substrate until the metal layer at the bottom is exposed, and after etching, each metal layer and each dielectric layer in the capacitor substrate are combined into a stepped capacitor structure.

[0052] Based on this, the preparation method of the variable MIM capacitor provided in the present embodiment utilizes the different light sensitivities of different photoresist layers to form a photoresist structure with a stepped morphology under the same photomask. And accordingly, it is used as a mask to block the etching of the capacitor substrate, thereby obtaining a capacitor structure with a stepped morphology. And based on the stepped capacitor structure, a variety of different capacitance values ​​can be obtained through the principle of capacitor series connection, then using one of the stepped capacitor structures can meet the needs of different capacitance values ​​in the chip, without using more single dielectric capacitors, thereby effectively reducing the occupancy rate of the MIM capacitor to the chip area, which is in line with the miniaturization development trend of the device.

[0053] The following is combined with Figure 2 to Figure 13 The preparation method of the variable MIM capacitor provided in this embodiment is specifically described.

[0054] Step 1 S10: Please refer to Figure 3 , providing a capacitor substrate, the capacitor substrate comprising a plurality of stacked metal layers, and a dielectric layer is arranged between two adjacent metal layers.

[0055] In other words, the capacitor substrate is a structure in which metal layers and dielectric layers are alternately stacked, and a metal layer is further arranged on the dielectric layer located on the top layer, so that the upper and lower surfaces of each dielectric layer are respectively covered by a metal layer. Exemplarily, the capacitor substrate includes three metal layers and two dielectric layers, and from bottom to top they are: a first metal layer 201, a first dielectric layer 202, a second metal layer 203, a second dielectric layer 204 and a third metal layer 205. In other examples, more layers of the metal layers and the dielectric layers may be provided, but to ensure the integrity of the capacitor structure, the number of the metal layers is one more than the number of the dielectric layers. Among them, each metal layer in the capacitor substrate and the dielectric layer located under the metal layer constitute a first-order membrane structure. And in the present embodiment, the capacitor substrate includes an N-order membrane structure; N ≥ 2, and N is an integer. For example Figure 3 The capacitor substrate shown includes a second-order film structure; that is, N=2.

[0056] It should be noted that the metal layer, dielectric layer and metal layer stacked in sequence can constitute a single dielectric capacitor, and the capacitor substrate with multiple metal layers and dielectric layers is provided in this embodiment, the purpose is to utilize the principle of capacitors connected in series, that is, 1 / C 0 =1 / C 1 +1 / C 2 +……+1 / C n (n is a positive integer), to achieve the total capacitance C 0 Therefore, in the subsequent process, an etching process is required to adjust the size of each single dielectric capacitor, thereby adjusting its capacitance value.

[0057] Furthermore, this embodiment does not limit the specific deposition process of the metal layer and the dielectric layer, nor does it limit the specific material of the metal layer and the dielectric layer. Exemplarily, the material of the metal layer includes aluminum-copper alloy (AlCu), and the metal layer is formed by an evaporation process; the material of the dielectric layer includes silicon nitride (SIN), and the dielectric layer is formed by a chemical vapor deposition process.

[0058] Step 2 S20: Please refer to Figure 4 , forming at least two photoresist layers on the top surface of the capacitor substrate; and the light sensitivity of each photoresist layer is different.

[0059] It should be noted that the number of the photoresist layers is consistent with the number of the dielectric layers to ensure that a multi-stage capacitor structure is formed in subsequent etching. For example, the capacitor substrate is provided with a first dielectric layer 202 and a second dielectric layer 204, then a first photoresist layer 207 and a second photoresist layer 208 can be formed in sequence on the top surface of the third metal layer 205 to form a second-order capacitor structure (see the subsequent etching process for details). And, the light sensitivity of the photoresist layers of each layer is different, which means that under the same exposure conditions, the dissolution degree of the photoresist layers of each layer is different, so that the planar dimensions of the photoresist layers of each layer are different.

[0060] Preferably, before forming the at least two photoresist layers, an anti-reflection coating 206 is formed on the surface of the top metal layer of the capacitor substrate. The anti-reflection coating 206 is used to reduce reflection during the photolithography process, thereby improving the accuracy and efficiency of the photolithography.

[0061] Step 3 S30: Please refer to Figure 5 , using the same photomask M to photolithographically process the at least two photoresist layers to form a stepped photoresist structure and expose a portion of the top surface of the capacitor substrate.

[0062] Exemplarily, the at least two photoresist layers are both negative photoresist layers, and the photosensitivity of the at least two photoresist layers increases from top to bottom, so that the planar dimensions of each of the photoresist layers after photolithography increase from top to bottom, and serve as the stepped photoresist structure. Figure 5 As shown, the first photoresist layer 207 and the second photoresist layer 208 are both negative photoresists. Under the same photomask M, the first photoresist 207 after photolithography has a stronger light sensitivity, so its plane size is larger than the plane size of the second photoresist layer 208 after photolithography, so as to form Figure 5 In other examples, the photoresist layers of more than two layers also present a stepped morphology with the plane size increasing layer by layer from top to bottom, and the morphology of the stepped photoresist structure can be transferred to the morphology of the capacitor substrate in the subsequent etching process.

[0063] In another example, the at least two photoresist layers are both positive photoresist layers, and the light sensitivity of the at least two photoresist layers decreases from top to bottom, and the photomask for photolithography of the at least two photoresist layers is Figure 5 The light-transmitting area and the light-shielding area in the mask M shown in the figure are arranged in opposite directions, so that the plane size of each photoresist layer after photolithography increases from top to bottom, forming Figure 5 The stepped photoresist structure shown.

[0064] And, the stepped photoresist structure after photolithography exposes part of the top surface of the capacitor substrate. For example, the first photoresist 207 exposes part of the surface of the third metal layer 205 located at the top layer. When an anti-reflective coating 206 is formed on the top surface of the capacitor substrate, the stepped photoresist structure exposes part of the surface of the anti-reflective coating 206.

[0065] Step 4 S40: Please refer to Figures 6 to 13 , using the stepped photoresist structure as a barrier, etching the capacitor substrate until the metal layer at the bottom is exposed, and after etching, each metal layer and each dielectric layer in the capacitor substrate are combined into a stepped capacitor structure.

[0066] It is understandable that the etching purpose of step 4 S40 is to replicate the morphology of the stepped photoresist structure to the capacitor substrate, so that the capacitor substrate forms a structure with the same stepped morphology. Based on this, the formed stepped capacitor structure can be considered to be composed of a plurality of single dielectric capacitors of different planar sizes. That is, a plurality of capacitors with different capacitance values ​​are connected in series.

[0067] Further, in the process of etching the capacitor substrate, at least the membrane structure of each step is etched from top to bottom in sequence. And the partial structure exposed by each layer of the photoresist layer in the stepped photoresist structure will be gradually consumed and removed through etching, then with the consumption of the stepped photoresist structure, the partial structure exposed in each step of the membrane structure will also be synchronously etched. Specifically, in the etching process from top to bottom, when each etching exposes a partial surface of the metal layer of the membrane structure of one step, the photoresist layer located at the top layer will be consumed and removed. And because each of the photoresist layers is distributed in a stepped manner, in the etching process, in addition to the photoresist layer of the top layer being consumed, the partial structure exposed by the remaining photoresist layers of each layer will also be consumed. And when etching exposes a partial surface of the metal layer of the membrane structure of one step, the photoresist layer of the top layer is completely consumed and removed, and the plane size of the remaining photoresist layers of each layer is reduced to the plane size of the adjacent upper layer of the photoresist layer before the current etching. That is, the horizontal dimension equivalent to the stepped photoresist structure is reduced as a whole. Based on this, in the process of etching the film structure of each step, not only will the new first-order film structure be exposed by etching downwards, but also as the horizontal dimension of the stepped photoresist structure is reduced as a whole, each film structure of the upper step that has been etched will expose a partial structure therewith, and these exposed partial structures will also be etched away synchronously. In addition, when the top surface of the capacitor substrate is formed with an anti-reflection coating 206, as the photoresist layers of each layer are consumed during the etching process, the anti-reflection coating 206 will be gradually exposed therewith, and then in each step etching process, the exposed part of the anti-reflection coating 206 will be etched away synchronously.

[0068] For example, Figure 6 As shown, the first photoresist layer 207 and the second photoresist layer 208 are used as etching stops, and the exposed portion of the anti-reflection coating 206 is first etched away, and the planar size of the anti-reflection coating 206 after etching is consistent with the planar size of the first photoresist layer 207. Since the film thickness of the anti-reflection coating 206 is relatively thin, the first photoresist layer 207 and the second photoresist layer 208 are substantially not consumed during the etching process of the anti-reflection coating 206. Then, as shown in FIG. Figure 7 As shown, the first photoresist layer 207 and the second photoresist layer 208 are used as etching barriers to etch away the exposed portion of the third metal layer 205. In the process of etching the third metal layer 205, the second dielectric layer 204 located below the third metal layer 205 will be exposed, and the second dielectric layer 204 will be etched synchronously. At the same time, the exposed portions of the first photoresist layer 207 and the second photoresist layer 208 are consumed to a certain extent. Figure 8As shown, when the etching of the exposed portion of the third metal layer 205 is completed and only some residues remain on the exposed portion of the second dielectric layer 204, the surface of the metal layer of the next-order membrane structure is exposed by etching, that is, part of the surface of the second metal layer 203 is exposed. At this time, only some residues remain on the second photoresist layer 208, which has been basically consumed; and only some residues remain on the exposed portion of the first photoresist layer 207. Further, by adopting an over-etching process, the residues of the exposed portion of the second photoresist layer 208 and the first photoresist layer 207 can be completely removed; and the residues of the exposed portion of the second dielectric layer 204 can be removed. Based on the consumption of the first photoresist layer 207, part of the surface of the anti-reflective coating 206 will be exposed, and the over-etching process will also simultaneously remove the exposed portion of the anti-reflective coating 206, thereby forming Fig. 9 The structure shown.

[0069] according to Fig. 9 It can be seen that in this etching, the second photoresist layer 208 located at the top layer is removed, and the planar size of the first photoresist layer 207 and the planar size of the anti-reflection layer 206 are both reduced to the planar size of the second photoresist layer 208 before etching. At the same time, the planar size of the third metal layer 205 and the second dielectric layer 204 are simultaneously reduced to the planar size of the first photoresist layer 207 before etching. Similarly, when the capacitor substrate is continuously etched, Fig.10 As shown, the exposed metal layer in the next-level film structure, that is, the second metal layer 203, will be etched away. And the part of the first dielectric layer 202 exposed by the etching of the second metal layer 203 will also be etched synchronously. At the same time, the first photoresist 207 layer will be consumed, and the third metal layer 205 exposed by the first photoresist layer 207 will also be consumed by etching; and, as the etching of the third metal layer 205 is consumed, part of the second dielectric layer 204 located at the next layer will be exposed, and part of the second dielectric layer 204 will also be etched synchronously. The final etching forms Fig.11 The stepped capacitor structure shown.

[0070] like Fig.11 As shown, the first photoresist layer 207 located at the top layer is completely consumed, and the plane size of the first-order film structure formed by the third metal layer 205 and the second dielectric layer 204 is equal to the initial plane size of the second photoresist layer 208 before etching, and the plane size of the other-order film structure formed by the second metal layer 203 and the second dielectric layer 204 is equal to the initial plane size of the first photoresist layer 207 before etching. Thus, a second-order variable MIM capacitor is formed.

[0071] Furthermore, since the material of the third metal layer 205 includes an aluminum-copper alloy and the material of the second dielectric layer 204 includes silicon nitride, preferably, the third metal layer 205 and the second dielectric layer 204 are etched by a dry etching process, and chlorine (Cl 2 ), boron trichloride (BCl 3 ), trifluoromethane (CHF 3 ), sulfur hexafluoride (SF 6 ) are mixed into an etching gas to etch the third metal layer 205 and the second dielectric layer 204 respectively. The mixed etching gas can etch the metal layer and the dielectric layer synchronously, and by adjusting the ratio of different gases in the etching gas, different selective etching ratios can be formed for the metal layer and the dielectric layer. Preferably, nitrogen (N 2 ) and helium (He) are used as protective gases during the etching process.

[0072] Furthermore, during the etching process, by changing the ratio of the etching gas in the process, the etching rate of the photoresist can be effectively controlled, and when the photoresist layer located on the top layer is removed, the exposed metal layer and the dielectric layer can be removed simultaneously. 3 and / or BCL 3 Gas ratio.

[0073] Furthermore, the present embodiment does not limit the mixing ratio and flow rate of various gases in the etching gas, which can be determined according to factors such as the specific etching film thickness. For example, in the process of etching the third metal layer 205 and the second dielectric layer 204, 70 sccm of Cl 2 , 10sccm CHF 3 and 10 Torr of He for pre-etching (Break through, BT) to adjust and protect the topography of the stepped photoresist structure and the capacitor substrate. Figure 6 As shown, 40 sccm of Cl 2 , 30sccm BCl 3 , 4sccm CHF 3 , 10 sccm N 2 and 10 Torr of He to etch the natural oxide layer, part of the anti-reflection coating 206 and part of the third metal layer 205. Figure 7 and Figure 8 As shown, using 50 sccm Cl 2 , 50sccm BCl 3 , 10sccm CHF 3and 10 Torr of He to perform main etching on the third metal layer 205. During the main etching process, as the exposed portion of the third metal layer 205 is gradually etched away, a portion of the second dielectric layer 204 is exposed to the etching gas, and a portion of the second dielectric layer 204 is etched away simultaneously. Figure 8 and Fig. 9 As shown, using 30 sccm Cl 2 , 80 sccm BCl 3 And 10 Torr of He is used to perform over etching to etch away the remaining portion of the second dielectric layer 204 .

[0074] It should be noted that an over-etching process will also be performed in the subsequent process of etching the first dielectric layer 202 to expose a portion of the first metal layer 201, and this process is used to ensure that the etching residue is completely removed. Figure 8 , Fig. 9 and Fig.11 It can be seen that the over-etching process performed in etching the second dielectric layer 204 not only needs to remove dielectric residues and photolithography residues, but also needs to etch and remove the portion of the anti-reflective coating 206 exposed due to the consumption of the first photoresist layer 207, so that the remaining planar size of the anti-reflective coating 206 is equal to the planar size of the first photoresist layer 207 after the etching consumption (e.g. Fig. 9 As shown). The over-etching process performed in etching the first dielectric layer 202 to expose a portion of the first metal layer 201 does not require etching the remaining anti-reflective coating 206. Therefore, the process time of the over-etching process used when etching the first dielectric layer 202 to expose the first metal layer 201 located at the top layer is less than the process time of the over-etching process used when etching the second dielectric layer 204 to expose the second metal layer 203. Similarly, when the capacitor substrate includes a three-level or higher film structure, the process time of the over-etching process used when etching to expose the bottom metal layer is less than the process time of the over-etching process used when etching to expose the metal layer of each level of the film structure. Exemplarily, the process time of the over-etching process used when etching the bottom dielectric layer to expose the bottom metal layer is 7 seconds, while the process time of the remaining over-etching processes is 7.5 seconds.

[0075] Based on this, since the material of the second metal layer 203 is the same as that of the third metal layer 205, and the material of the second dielectric layer 204 is also the same as that of the first dielectric layer 202. Therefore, the second metal layer 203 and the first dielectric layer 202 can be etched with reference to the above-mentioned process parameters for etching the third metal layer 205 and the second dielectric layer 204 until a Fig.11 The structure shown.

[0076] Further, compare Figure 5 and Fig.11 It can be known that after multiple steps of layer-by-layer etching, the initial plane size of the first photoresist layer 207 is replicated on the first dielectric layer 202 and the second metal layer 203, and the initial plane size of the second photoresist layer 208 is replicated on the second dielectric layer 204 and the third metal layer 205. And the first metal layer 201, the first dielectric layer 202 and the second metal layer 203 constitute a first capacitor structure whose relative electrode coverage size is the initial plane size of the first photoresist layer 207, and the second metal layer 203, the second dielectric layer 204 and the third metal layer 205 constitute a second capacitor structure whose relative electrode coverage size is the initial plane size of the second photoresist layer 208. Thus, a second-order capacitor structure is formed. Exemplarily, the capacitance value of the first capacitor structure is 200μF, and the capacitance value of the second capacitor structure is 100μF. When the first metal layer 201 and the second metal layer 203 are directly introduced into the circuit, a first capacitor structure of 200μF can be provided to the circuit; when the third metal layer 205 and the second metal layer 203 are directly introduced into the circuit, a first capacitor structure of 100μF can be provided to the circuit; and when the first metal layer 201 and the third metal layer 205 are directly introduced into the circuit, a third capacitor structure in which the first capacitor structure and the second capacitor structure are connected in series can be provided to the circuit, and its capacitance value is about 66.67μF. It can be seen that the variable MIM capacitor can obtain different capacitance values ​​through different lead wires, realize the adjustable effect of the capacitance value, and expand its application range.

[0077] Preferably, in other examples, more-order capacitor structures may be provided, and the process of etching to form the more-order capacitor structures may refer to the process of forming the two-order capacitor structure, which will not be described in detail in this embodiment.

[0078] Furthermore, after executing step 4 S40, a cleaning process is required to remove the remaining anti-reflective coating 206 and other etching residues. Fig.12The MIM capacitor shown. Therefore, the method for preparing the variable MIM capacitor also includes: forming a metal interlayer dielectric layer 209 on the surface of the stepped capacitor structure. The metal interlayer dielectric layer 209 completely covers the surface of the capacitor substrate after etching to achieve electrical isolation. Preferably, the material of the metal interlayer dielectric layer 209 is silicon dioxide or fluorosilicate glass. And, after forming the metal interlayer dielectric layer 209, an etching process is used to form a plurality of contact holes in the metal interlayer dielectric layer 209 to expose a portion of the surface of each metal layer. Then, as Fig.12 As shown, metal material is used to fill each of the contact holes to form a plurality of metal plugs 210. The plurality of metal plugs 210 are arranged at intervals and all penetrate the intermetallic dielectric layer 209 to connect with the corresponding metal layer, and each metal layer is connected with at least one metal plug 210. Preferably, the material of the metal plug 210 includes but is not limited to tungsten, aluminum, copper or silver. In other examples, it is also possible to form Fig.13 The fourth-order variable MIM capacitor 301 shown, or a fifth-order, sixth-order capacitor structure, etc., can meet the requirements of different capacitance values.

[0079] Based on the same concept, this embodiment also provides a variable MIM capacitor. Fig.12 and Fig.13 The variable MIM capacitor is prepared by the above-mentioned variable MIM capacitor preparation method. Specifically, the variable MIM capacitor includes multiple metal layers, and a dielectric layer is arranged between two adjacent metal layers; and each metal layer and each dielectric layer are combined into a stepped capacitor structure.

[0080] Specifically, each metal layer and the dielectric layer located below the metal layer in the stepped capacitor structure form a first-order membrane structure, and the dielectric layer and the metal layer in the membrane structure of the same order have the same planar size; and the stepped capacitor structure includes at least two-order membrane structures, and the planar size of the membrane structures of each order increases from top to bottom. Fig.12 As shown, the first dielectric layer 202 and the second metal layer 203 constitute a first-order film structure; the second dielectric layer 204 and the third metal layer 205 constitute a second-order film structure. Fig.12 The stepped capacitor structure shown is a two-stage MIM capacitor. The first dielectric layer 202 and the second metal layer 203 in the first-stage film structure have the same planar size, the second dielectric layer 204 and the third metal layer 205 in the second-stage film structure have the same planar size, and the planar size of the first-stage film structure is larger than the planar size of the second-stage film structure, so as to form a stepped morphology. In other examples, a multi-stage MIM capacitor can be formed. Fig.13As shown, the plane size of each level of the membrane structure increases from top to bottom. Based on the different plane sizes, the capacitance of the capacitor formed by each level of the membrane structure and the adjacent next metal layer is different. According to the principle of capacitor series connection, a variety of different capacitance values ​​can be obtained. Then, using one stepped capacitor structure can meet the requirements of different capacitance values ​​in the chip.

[0081] Optionally, the variable MIM capacitor provided in this embodiment is not only suitable for various power devices prepared by the BCD (Bipolar-CMOS-DMOS) process to play a role in filtering and voltage stabilization, and is beneficial to improving the accuracy and sensitivity of power and voltage regulation; it can also be applied to other logic devices, etc., and this embodiment does not make specific limitations on this.

[0082] In summary, the present embodiment provides a variable MIM capacitor and a method for preparing the same. Among them, the method for preparing the variable MIM capacitor utilizes the different light sensitivities of different layers of photoresist layers to form a photoresist structure with a stepped morphology under the same mask M. And based on this, it is used as a mask barrier for etching the capacitor substrate, thereby obtaining a capacitor structure with a stepped morphology. And based on the stepped capacitor structure, a variety of different capacitance values ​​can be obtained through the principle of capacitor series connection, then using one of the stepped capacitor structures can meet the needs of different capacitance values ​​in the chip, without using more single dielectric capacitors, thereby effectively reducing the occupancy rate of the MIM capacitor to the chip area, which is in line with the miniaturization development trend of the device.

[0083] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a variable MIM capacitor, characterized in that: include: A capacitor substrate is provided, the capacitor substrate comprising a plurality of stacked metal layers, and a dielectric layer is disposed between two adjacent metal layers; forming at least two photoresist layers on the top surface of the capacitor substrate; The photoresist layers of each layer have different light sensitivities; Photolithography the at least two photoresist layers using the same photomask to form a stepped photoresist structure and expose a portion of the top surface of the capacitor substrate; Using the stepped photoresist structure as a barrier, the capacitor substrate is etched until the metal layer at the bottom is exposed, and the metal layers and dielectric layers in the capacitor substrate after etching are combined into a stepped capacitor structure.

2. The method for preparing a variable MIM capacitor according to claim 1, characterized in that: During the process of etching the capacitor substrate, the exposed parts of the photoresist layers in the stepped photoresist structure are removed by etching.

3. The method for preparing a variable MIM capacitor according to claim 2, characterized in that: Each metal layer in the capacitor substrate and the dielectric layer located below the metal layer form a first-order membrane structure; wherein, In the process of etching the capacitor substrate, the membrane structures of each level are etched at least sequentially from top to bottom; and while the exposed parts of the membrane structures of each level are etched, the stepped photoresist structure is consumed synchronously.

4. The method for preparing a variable MIM capacitor according to claim 3, characterized in that: The capacitor substrate includes an N-order film structure; N≥2, and N is an integer; wherein the number of the photoresist layers is equal to the number of the dielectric layers.

5. The method for preparing a variable MIM capacitor according to claim 3, characterized in that: In the process of etching the capacitor substrate, each time a portion of the surface of the metal layer of the first-order membrane structure is exposed by etching, at least the photoresist layer located at the top layer is consumed synchronously.

6. The method for preparing a variable MIM capacitor according to claim 3, characterized in that: An anti-reflection coating is also formed between the top surface of the capacitor substrate and the at least two photoresist layers; and, During the etching of the capacitor substrate, the surface of the anti-reflective coating is gradually exposed as the stepped photoresist structure is consumed; and each time a portion of the surface of the metal layer of the membrane structure is exposed by etching, the exposed portion of the surface of the anti-reflective coating is removed by an etching process.

7. The method for preparing a variable MIM capacitor according to claim 6, characterized in that: During the process of etching the capacitor substrate, the process time of the over-etching process used when etching to expose the bottom metal layer is shorter than the process time of the over-etching process used when etching to expose the metal layers of the film structures at each level.

8. The method for preparing a variable MIM capacitor according to claim 3, characterized in that: The at least two photoresist layers are both positive photoresist layers, and the photosensitivity of the at least two photoresist layers decreases from top to bottom; or, the at least two photoresist layers are both negative photoresist layers, and the photosensitivity of the at least two photoresist layers increases from top to bottom; so that the planar size of each of the photoresist layers in the stepped photoresist structure formed by photolithography increases layer by layer from top to bottom; as well as, With the stepped photoresist structure as a barrier, the plane size of each step of the membrane structure in the stepped capacitor structure formed by etching increases step by step from top to bottom, and the plane sizes of the metal layer and the dielectric layer in the membrane structure of the same step are the same.

9. The method for preparing a variable MIM capacitor according to claim 1, characterized in that: In the process of etching the capacitor substrate, the etching gases used include: chlorine, boron trichloride, trifluoromethane and sulfur hexafluoride.

10. The method for preparing a variable MIM capacitor according to claim 1, characterized in that: After etching the capacitor substrate, the method for preparing the variable MIM capacitor further includes: forming an intermetallic dielectric layer; the intermetallic dielectric layer covers the surface of the capacitor substrate after etching; A plurality of metal plugs are formed; the plurality of metal plugs are arranged at intervals and all penetrate the intermetallic dielectric layer to connect with the corresponding metal layer; wherein each metal layer is connected with at least one metal plug.

11. A variable MIM capacitor, characterized in that: The variable MIM capacitor is prepared by the method for preparing the variable MIM capacitor according to any one of claims 1 to 10, and the variable MIM capacitor comprises: Multiple metal layers, with a dielectric layer disposed between two adjacent metal layers; and each metal layer and each dielectric layer are combined into a stepped capacitor structure.

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