Quantum well double-heterojunction device and preparation method and application thereof

Abstract

The invention discloses a quantum well double-heterojunction device. The quantum well double-heterojunction device structurally comprises a substrate, a buffer layer, an AlGaN gradient heterojunction layer and an AlGaN / GaN heterojunction epitaxial layer from bottom to top in sequence, wherein the AlGaN gradient heterojunction layer sequentially comprises an Al < x > Ga < 1-x > N layer and an Al < y > Ga < 1-y > N layer from bottom to top; by arranging the AlGaN gradient heterojunction layer of which the Al component is gradually reduced from bottom to top, an electric field in a GaN channel can be relieved, negative charges on the lower side of the GaN channel are reduced, the carrier mobility is improved, meanwhile, due to the fact that the 2DHGa of the structure is farther from 2DEGa, the coulomb interaction of the 2DHGa can effectively restrain reduction of the electron mobility, and the performance of the device is improved. Therefore, the effect of improving the electron mobility of the QWHEMT structure is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a quantum well double heterojunction device and a preparation method and application thereof. Background Art

[0002] GaN materials have the advantages of high electron drift velocity, high thermal conductivity, wide bandgap, and high breakdown electric field. Therefore, GaN materials are widely used in the manufacture of high temperature and high pressure resistant, high power, and radiation resistant semiconductor devices. Gallium nitride-based high electron mobility transistors (GaN HEMTs) have superior electrical properties, unique high electron saturation velocity and high breakdown voltage, which has attracted widespread attention in power, radio frequency devices and other application fields. At the same time, the AlGaN / GaN heterojunction interface has a large conduction band step, strong piezoelectric polarization and spontaneous polarization effects, and can form deep and narrow quantum wells, thereby accumulating high-density two-dimensional electron gas. Therefore, devices with AlGaN / GaN heterojunctions have high electron mobility and saturation velocity, and are widely used in radio frequency, 5Ga communication network construction and other fields.

[0003] At present, the GaN-based RF device material system includes AlGaN / GaN, InAlN / GaN, ScAlN / GaN and AlN / GaN heterostructure materials. At present, AlGaN / GaN HEMTs are the most mature in the industry and have been commercialized. The maximum fmax of RF devices using AlGaN barriers is close to 300GaHz, and its Lsd = 1.1μm. However, due to the large thickness of the AlGaN barrier layer, the aspect ratio of the device also increases (Tbarrier / LGa), which causes the short channel effect (SCE) and leads to device performance degradation. In order to improve the DC transconductance and alleviate the short channel effect, the short channel effect problem can be solved by using the partial groove technology under the gate area and the ultra-thin barrier layer structure on the material of the traditional AlGaN barrier. However, for the ultra-thin barrier layer structure, due to the thinning of the barrier layer, the 2DEGa concentration will be greatly reduced, resulting in a decrease in the saturated output current of the device, affecting the output power of the device. The advantage of recessed gate technology is that the barrier of the gate source and gate drain regions of the device is not thinned, and the current level loss of the device is small. However, the damage caused by gate etching increases the leakage of the device and reduces the breakdown voltage, thus affecting the output power of the device.

[0004] In order to solve the above problems, InAlN / GaN, ScAlN / GaN and AlN / GaN heterostructure materials with high Al components have been proposed by researchers, which can achieve high two-dimensional electron gas (2DEGa) under ultra-thin barrier layer thickness, thereby maintaining a large output current level and suppressing the short channel effect. The above new material technology is mainly applied to Ga-face GaN material system, while N-face GaN after polarity reversal has many advantages, such as improving gate modulation efficiency and reducing the impact of short channel effect, having a natural back barrier to limit 2-DEGa, lower square resistance of GaN channel, and easier preparation of ohmic contact resistance. Although N-face GaN material has great advantages in millimeter wave power devices, its difficulty is that the surface activity of N-face GaN material is high, and the growth process is very difficult, which can only be obtained through MBE growth. At present, only UCSB has solved the material growth problem and prepared millimeter wave devices in the world.

[0005] AlN / GaN / AlN quantum well (QWs) epitaxial material replaces the traditional AlGaN barrier layer and ordinary AlGaN back barrier with non-strained AlN layer, and uses strained GaN quantum wells between the binary AlN buffer layer and the barrier layer to improve carrier confinement, prevent carriers from overflowing the channel, and suppress the short channel effect.

[0006] Although traditional QW GaN HEMTs have a high breakdown voltage, they are limited by the AlN / GaN / AlN structure, with an electron mobility of only 700 cm 2 / Vs, which is lower than the 700cm of conventional AlGaN / GaN HEMT 2 / Vs.

[0007] However, conventional QW GaN HEMTs cannot effectively reduce the internal electric field of the GaN channel even with an AlGaN buffer layer in the absence of stress. In order to reduce the electric field of the GaN channel, it is necessary to control the polarization charge and reduce the negative charge on the lower side of the GaN channel. In addition, since 2DHGa is farther away from 2DEGa, the mobility drop caused by the Coulomb interaction of 2DHGa is suppressed.

[0008] The polarization charge depends on stress, and when the AlGaN lattice is compressed, the buffer charge of AlGaN decreases. Therefore, the negative interface charge in the lower part of the GaN channel decreases. On the contrary, when the piezoelectric charge of the relaxed AlGaN buffer is too high, it cannot effectively reduce the electric field of the GaN channel.

[0009] The Chinese patent publication number CN105845796A discloses a multi-quantum well structure for AlGaN optoelectronic devices. x Ga 1-x N potential well and Al yGa 1-y N barrier layers are formed by overlapping multiple layers (where x < y), and 4-20 layers are grown in a cycle. This structure reduces the energy band tilt caused by the quantum confinement Stark effect, increases the overlap of the electron-hole wave function in the quantum well, increases the wave function overlap integral, increases the recombination probability of the electron-hole pair, and increases the internal quantum efficiency of the device's luminescence. However, this patent focuses more on optimizing the multi-quantum well structure to improve the luminescence efficiency of optoelectronic devices.

[0010] In summary, there is an urgent need to develop a device that can alleviate the electric field in the GaN channel to solve the problems existing in the prior art. Summary of the invention

[0011] Based on the above defects, the present invention discloses a quantum well double heterojunction device, which can alleviate the electric field in the GaN channel, effectively improve the electron mobility of the QW HEMT structure, while maintaining strong electron confinement and optimizing the heat dissipation performance of the device.

[0012] An object of the present invention is to provide a quantum well double heterojunction device, wherein the structure of the quantum well double heterojunction device comprises, from bottom to top, a substrate, a buffer layer, an AlGaN graded heterojunction layer, an AlGaN / GaN heterojunction epitaxial layer, and an electrode layer;

[0013] The AlGaN graded heterojunction layer includes Al x Ga 1-x N layer, Al y Ga 1-y N layers;

[0014] The AlGaN / GaN heterojunction epitaxial layer includes a GaN channel layer, an insertion layer, an Al z Ga 1-z N barrier layer;

[0015] The electrode layer is composed of a source electrode, a drain electrode and a gate electrode, wherein

[0016] The source and drain electrodes are deposited on Al z Ga 1-z On both sides of the N barrier layer, the gate is deposited between the source and drain, and there is a gap between the source and drain and the gate. z Ga 1-z The N barrier layer, the source electrode, the drain electrode and the gate electrode are all covered by a passivation layer formed by SiN;

[0017] The source electrode, the drain electrode and the gate electrode all partially extend upward from the device to form electrode extension portions of the source electrode, the drain electrode and the gate electrode respectively;

[0018] Said x>y.

[0019] Furthermore, the value of x is 0.7-0.9.

[0020] Furthermore, the value of y is 0.2-0.4.

[0021] Furthermore, the value of z is 0.5-0.7.

[0022] Furthermore, the material of the insertion layer is AlN.

[0023] Furthermore, the Al x Ga 1-x The thickness of the N layer is 10-20nm; the Al y Ga 1-y The thickness of the N layer is 40-60nm.

[0024] Furthermore, the thickness of the GaN channel layer is 10-30 nm, the thickness of the insertion layer is 0.5-5 nm, and the thickness of the Al z Ga 1-z The thickness of the N barrier layer is 5-10 nm.

[0025] Another object of the present invention is to provide a method for preparing the quantum well double heterojunction device, comprising the following steps:

[0026] S1, after annealing the substrate, growing a buffer layer on the surface of the substrate;

[0027] S2. Al is grown on the buffer layer x Ga 1-x N layer and Al y Ga 1-y N layer, forming an AlGaN graded heterojunction layer;

[0028] S3, in Al y Ga 1-y The GaN channel layer, insertion layer, and Al z Ga 1-z N barrier layer, forming an AlGaN / GaN heterojunction epitaxial layer;

[0029] S4. In Al z Ga 1-z The gate, source and drain are deposited on the upper surface of the N barrier layer to form an electrode layer;

[0030] S5, in the electrode layer, and part of the Al z Ga 1-zThe upper surface of the N barrier layer is subjected to SiN passivation treatment, and the thickness of the SiN is controlled to form a passivation layer; the passivation layer is etched with interconnection through holes with the source, drain and gate to complete the preparation of the electrode extension parts of the source, drain and gate.

[0031] Furthermore, the passivation layer is prepared by a CVD process.

[0032] Furthermore, in step S1, the annealing treatment conditions are: 2 In the atmosphere, the temperature is 950-1000°C and the time is 8-12 minutes.

[0033] Another object of the present invention is to provide an application of the quantum well double heterojunction device in a semiconductor device.

[0034] The present invention has at least the following beneficial effects:

[0035] The device of the present invention is provided with an AlGaN graded heterojunction layer and an AlGaN / GaN heterojunction epitaxial layer. Firstly, by providing a quantum well double heterojunction of the AlGaN graded heterojunction layer and the AlGaN / GaN heterojunction epitaxial layer, the device can have a wide band gap, and the device can be kept with a low gate tunneling leakage current, thereby reducing the leakage of the device; secondly, by providing an AlGaN graded heterojunction layer in which the Al component gradually decreases from bottom to top, the electric field in the GaN channel can be relieved, the negative charge on the lower side of the GaN channel can be reduced, and the carrier mobility can be improved. At the same time, because the 2DHGa (two-dimensional hole gas) of the structure is farther away from the 2DEGa (two-dimensional electron gas), the Coulomb interaction of the 2DHGa can effectively suppress the decrease of the electron mobility, thereby improving the electron mobility of the QW HEMT (quantum well high mobility transistor) structure; in addition, the GaN channel layer, the insertion layer, and the Al z Ga 1-z The AlGaN / GaN heterojunction epitaxial layer composed of the N barrier layer can make the interface of the device have a large polarization charge density and a high electron concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic structural diagram of the quantum well double heterojunction device prepared in Example 1-2;

[0037] Figure 2 This is a schematic diagram of the structure of the device prepared in Comparative Example 1;

[0038] Figure 3 The results of square resistance, mobility and carrier concentration in the Hall test of Example 1;

[0039] Figure 4 These are the results of square resistance, mobility and carrier concentration in the Hall test of comparative example 1.

[0040] 1. Substrate; 2. Buffer layer; 3. Al x Ga 1-x N layer; 4. Al y Ga 1-y N layer; 5. GaN channel layer; 6. Insertion layer; 7. Al z Ga 1-z N barrier layer; 8. source; 9. drain; 10. gate; 11. passivation layer. DETAILED DESCRIPTION

[0041] In order to more clearly illustrate the technical solution of the present invention, the following examples are listed. Unless otherwise stated, the raw materials, reactions and post-treatment methods shown in the examples are common raw materials on the market and technical methods well known to those skilled in the art.

[0042] Example 1

[0043] A quantum well double heterojunction device, such as Figure 1 As shown, the structure of the quantum well double heterojunction device is, from bottom to top, a sapphire substrate 1 (1 mm), an AlN buffer layer 2 (2 μm), an AlGaN graded heterojunction layer, an AlGaN / GaN heterojunction epitaxial layer, and an electrode layer;

[0044] The AlGaN graded heterojunction layer includes Al 0.85 Ga 0.15 N layer 3 (10nm), Al 0.3 Ga 0.7 N layer 4 (50nm);

[0045] The AlGaN / GaN heterojunction epitaxial layer includes, from bottom to top, a GaN channel layer 5 (20 nm), an AlN insertion layer 6 (2 nm), an Al 0.6 Ga 0.4 N barrier layer 7 (6 nm);

[0046] The electrode layer is composed of a source electrode 8 (Ti / Al / Ni / Au, 20nm / 110nm / 40nm / 50nm), a drain electrode 9 (Ti / Al / Ni / Au, 20nm / 110nm / 40nm / 50nm) and a gate electrode 10 (Ni / Au, 30nm / 50nm), wherein

[0047] The source electrode 8 and the drain electrode 9 are deposited on Al 0.6 Ga 0.4 On both sides of the N barrier layer 7, the gate 10 is deposited between the source 8 and the drain 9, and there are gaps between the source 8 and the drain 9 and the gate 10. 0.6 Ga0.4 The N barrier layer 7, the source electrode 8, the drain electrode 9 and the gate electrode 10 are all covered by a passivation layer 11 formed of SiN;

[0048] The source electrode 8, the drain electrode 9 and the gate electrode 10 are partially extended upwards of the device to form electrode extension portions of the source electrode 8, the drain electrode 9 and the gate electrode 10 respectively;

[0049] The method for preparing the quantum well double heterojunction device is as follows:

[0050] S1, at 1000℃, H 2 The sapphire substrate is annealed in an atmosphere for 10 minutes to grow an AlN buffer layer on the surface of the sapphire substrate;

[0051] S2. Al is grown on the AlN buffer layer 0.85 Ga 0.15 N layer and Al 0.3 Ga 0.7 N layer, forming an AlGaN graded heterojunction layer;

[0052] S3, in Al 0.3 Ga 0.7 The GaN channel layer, AlN insertion layer, Al 0.6 Ga 0.4 N barrier layer, forming an AlGaN / GaN heterojunction epitaxial layer;

[0053] S4. In Al 0.6 Ga 0.4 Ti / Al / Ni / Au (20nm / 110nm / 40nm / 50nm) were deposited on the N barrier layer as the source material, and Ti / Al / Ni / Au (20nm / 110nm / 40nm / 50nm) were deposited as the drain material. 2 atmosphere, annealed at 830℃ for 45s to form AlN insertion layer and Al 0.6 Ga 0.4 N barrier layer forms ohmic contact; 0.6 Ga 0.4 A gate region is defined on the N barrier layer, and Ni / Au (30nm / 50nm) is deposited as the gate to form a Schottky contact;

[0054] S5, in the Al 0.6 Ga 0.4 SiN is deposited on the N barrier layer 7, the source 8, the drain 9 and the gate 10 as a passivation layer (20 nm). 0.6 Ga 0.4The N barrier layer is used to cover and protect the device, and holes are opened in the passivation layer on the source, drain and gate by dry etching (SF6, ICP 50W), and Ti / Au (20nm / 100nm) metal is deposited in the holes for device interconnection to obtain the quantum well double heterojunction device.

[0055] Example 2

[0056] A quantum well double heterojunction device, such as Figure 1 As shown, the structure of the quantum well double heterojunction device is, from bottom to top, a sapphire substrate 1 (1 mm), an AlN buffer layer 2 (2 μm), an AlGaN graded heterojunction layer, an AlGaN / GaN heterojunction epitaxial layer, and an electrode layer;

[0057] The AlGaN graded heterojunction layer includes Al 0.86 Ga 0.14 N layer 3 (10nm), Al 0.3 Ga 0.7 N layer 4 (50nm);

[0058] The AlGaN / GaN heterojunction epitaxial layer includes, from bottom to top, a GaN channel layer 5 (20 nm), an AlN insertion layer 6 (2 nm), an Al 0.6 Ga 0.4 N barrier layer 7 (6 nm);

[0059] The electrode layer is composed of a source electrode 8 (Ti / Al / Ni / Au, 20nm / 110nm / 40nm / 50nm), a drain electrode 9 (Ti / Al / Ni / Au, 20nm / 110nm / 40nm / 50nm) and a gate electrode 10 (Ni / Au, 30nm / 50nm), wherein

[0060] The source electrode 8 and the drain electrode 9 are deposited on Al 0.6 Ga 0.4 On both sides of the N barrier layer 7, the gate 10 is deposited between the source 8 and the drain 9, and there are gaps between the source 8 and the drain 9 and the gate 10. 0.6 Ga 0.4 The N barrier layer 7, the source electrode 8, the drain electrode 9 and the gate electrode 10 are all covered by a passivation layer 11 formed of SiN;

[0061] The source electrode 8, the drain electrode 9 and the gate electrode 10 are partially extended upwards of the device to form electrode extension portions of the source electrode 8, the drain electrode 9 and the gate electrode 10 respectively;

[0062] The method for preparing the quantum well double heterojunction device is as follows:

[0063] S1, at 1000℃, H2 The sapphire substrate is annealed in an atmosphere for 10 minutes to grow an AlN buffer layer on the surface of the sapphire substrate;

[0064] S2, Al is grown on the AlN buffer layer 0.86 Ga 0.14 N layer and Al 0.3 Ga 0.7 N layer, forming an AlGaN graded heterojunction layer;

[0065] S3, in Al 0.3 Ga 0.7 The GaN channel layer, AlN insertion layer, Al 0.6 Ga 0.4 N barrier layer, forming an AlGaN / GaN heterojunction epitaxial layer;

[0066] S4-1, in Al 0.6 Ga 0.4 Ti / Al / Ni / Au (20nm / 110nm / 40nm / 50nm) were deposited on the N barrier layer as the source material, and Ti / Al / Ni / Au (20nm / 110nm / 40nm / 50nm) were deposited as the drain material. 2 The AlN insertion layer and Al 0.6 Ga 0.4 The N barrier layer forms an ohmic contact;

[0067] S4-2, in Al 0.6 Ga 0.4 The gate region is defined on the N barrier layer, and Ni / Au (30nm / 50nm) is deposited as the gate to form a Schottky contact, and SiN is deposited as a passivation layer (20nm) for the source, drain, gate and Al 0.6 Ga 0.4 The N barrier layer is used to cover and protect the device, and holes are opened in the passivation layer on the source, drain and gate by dry etching (SF6, ICP 50W), and Ti / Au (20nm / 100nm) metal is deposited in the holes for device interconnection to obtain the quantum well double heterojunction device.

[0068] Comparative Example 1

[0069] A device having a structure as follows Figure 2 As shown, the difference between the device and Example 1 is that the AlN layer in this comparative example is not provided with Al 0.85 Ga 0.15 N layer and Al 0.3 Ga 0.7Instead, the GaN channel layer, AlN insertion layer, AlN layer, and AlN layer are grown directly on the AlN layer. 0.6 Ga 0.4 The N barrier layer, other structures and materials are the same as those in Example 1.

[0070] Test Case

[0071] The devices of Example 1 and Comparative Example 1 were subjected to Hall tests.

[0072] Test results such as Figure 3-4 As shown in Table 1, Figure 3 The results of square resistance, mobility and carrier concentration in the Hall test of Example 1 are shown. Figure 4 The results of square resistance, mobility and carrier concentration in the Hall test of Comparative Example 1 are shown.

[0073] Table 1 Performance test results of devices of Example 1 and Comparative Example 1

[0074]

[0075] According to Table 1 and Figure 3 , Figure 4 It can be seen that the devices of Example 1 and Comparative Example 1 have similar carrier concentrations, but the device of Example 1 has higher electron mobility and lower sheet resistance. The above results confirm that the quantum well double heterojunction structure can effectively suppress the decrease in device electron mobility, thereby achieving the effect of improving the electron mobility of the QW HEMT structure.

[0076] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive in all respects, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention.

[0077] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A quantum well double heterojunction device, characterized in that: The structure of the quantum well double heterojunction device includes, from bottom to top, a substrate, a buffer layer, an AlGaN graded heterojunction layer, an AlGaN / GaN heterojunction epitaxial layer, and an electrode layer; The AlGaN graded heterojunction layer includes Al x Ga 1-x N layer, Al y Ga 1-y N layers; The AlGaN / GaN heterojunction epitaxial layer includes a GaN channel layer, an insertion layer, an Al z Ga 1-z N barrier layer; The electrode layer is composed of a source electrode, a drain electrode and a gate electrode, wherein The source and drain electrodes are deposited on Al z Ga 1-z On both sides of the N barrier layer, the gate is deposited between the source and drain, and there is a gap between the source and drain and the gate. z Ga 1-z The N barrier layer, the source electrode, the drain electrode and the gate electrode are all covered by a passivation layer formed by SiN; The source electrode, the drain electrode and the gate electrode all partially extend upward from the device to form electrode extension portions of the source electrode, the drain electrode and the gate electrode respectively; Said x>y.

2. The quantum well double heterojunction device according to claim 1, characterized in that: The value of x is 0.7-0.

9.

3. The quantum well double heterojunction device according to claim 1, characterized in that: The value of y is 0.2-0.

4.

4. The quantum well double heterojunction device according to claim 1, characterized in that: The value of z is 0.5-0.

7.

5. The quantum well double heterojunction device according to claim 1, characterized in that: The material of the insertion layer is AlN.

6. The quantum well double heterojunction device according to claim 1, characterized in that: The Al x Ga 1-x The thickness of the N layer is 10-20nm; the Al y Ga 1-y The thickness of the N layer is 40-60nm.

7. The quantum well double heterojunction device according to claim 1, characterized in that: The thickness of the GaN channel layer is 10-30 nm, the thickness of the insertion layer is 0.5-5 nm, and the thickness of the Al z Ga 1-z The thickness of the N barrier layer is 5-10 nm.

8. The method for preparing the quantum well double heterojunction device according to any one of claims 1 to 7, characterized in that: The method for preparing the quantum well double heterojunction device comprises the following steps: S1, after annealing the substrate, growing a buffer layer on the surface of the substrate; S2. Al is grown on the buffer layer x Ga 1-x N layer and Al y Ga 1-y N layer, forming an AlGaN graded heterojunction layer; S3, in Al y Ga 1-y The GaN channel layer, insertion layer, and Al z Ga 1-z N barrier layer, forming an AlGaN / GaN heterojunction epitaxial layer; S4. In Al z Ga 1-z The gate, source and drain are deposited on the upper surface of the N barrier layer to form an electrode layer; S5, in the electrode layer, and part of the Al z Ga 1-z The upper surface of the N barrier layer is subjected to SiN passivation treatment, and the thickness of the SiN is controlled to form a passivation layer; The passivation layer is etched to form interconnected through holes with the source electrode, the drain electrode and the gate electrode, thereby completing the preparation of the electrode extension parts of the source electrode, the drain electrode and the gate electrode.

9. The method for preparing a quantum well double heterojunction device according to claim 8, characterized in that: The passivation layer is prepared by CVD process.

10. Application of the quantum well double heterojunction device according to any one of claims 1 to 8 in a semiconductor device.

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