High-voltage-resistant groove type MOSFET structure and manufacturing method thereof
By epitaxially forming a thick P-type base region and forming an N-type connecting trench gate structure in the trench type MOSFET, the on-resistance and reliability problems of traditional Trench MOSFETs are solved, and higher frequency characteristics and reliability are achieved.
Patent Information
- Application Number
- CN202510344565.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2025-06-06
AI Technical Summary
When traditional Trench MOSFETs ensure breakdown voltage, their characteristic on-resistance and gate leakage charge are large, resulting in reliability problems and large on-resistance, making it difficult to meet the high requirements of modern circuits for frequency characteristics.
By epitaxially forming a thicker P-type base region in the trench type MOSFET, the trench gate structure is completely wrapped, and an N-type region is formed at the bottom of the trench to connect the trench gate structure and the N-drift region, increasing the depth of the N+ source region to shorten the conductive channel length.
It reduces gate leakage charge, improves switching speed, reduces the electric field at the bottom of the trench, effectively protects the gate oxygen layer, improves the reliability of the device, and reduces the on-resistance.
Smart Images
Figure CN120111940A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of power devices, and in particular relates to a high-voltage trench MOSFET structure and a manufacturing method thereof. Background Art
[0002] Trench MOSFET, or trench metal oxide semiconductor field effect transistor, is an important power device; it is widely used in DC-DC conversion, voltage regulators, power management modules, electromechanical control, display control, and automotive electronics. Compared with planar MOSFET, Trench MOSFET has significant advantages. First, it eliminates the JFET effect, reduces the internal impedance, and makes the on-resistance closer to the ideal value. Secondly, Trench MOSFET can reduce the cell size and increase the cell density, thereby increasing the current density and effectively saving chip area. These advantages make Trench MOSFET excel in power density, efficiency, and heat dissipation performance.
[0003] With the development of modern circuits, the frequency characteristics of power devices are increasingly required. Under the premise of ensuring a certain breakdown voltage, reducing the characteristic on-resistance and gate-drain charge of Trench MOSFET as much as possible has become the main design goal. Figure 1 In the traditional Trench MOSFET structure, the thickness of the P-type base region 120 is relatively small, and the trench 210 generally penetrates the P-type base region 120 and extends into the N-drift region 120. At this time, the introduction of the trench 210 will lead to electric field concentration at the corner of the gate oxide layer 220, which can easily cause the breakdown of the gate oxide layer 220, causing serious reliability problems. In addition, the conduction channel length of the traditional Trench MOSFET is relatively long, and the on-resistance is relatively large, and there is still a large room for improvement from the ideal on-resistance. Summary of the invention
[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a high-voltage trench MOSFET structure and a manufacturing method thereof.
[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:
[0006] A high-voltage trench MOSFET structure comprises an N+ substrate, an N-drift region and a P-type base region which are arranged in sequence from bottom to top, wherein the N+ substrate is heavily N-doped, the N-drift region is lightly N-doped, and the P-type base region is P-doped; an N+ source region is formed on the upper part of the P-type base region, and P+ regions are formed on both sides of the N+ source region, wherein the N+ source region is heavily N-doped, and the P+ region is heavily P-doped; a trench gate structure is formed in the middle of the N+ source region, wherein the trench gate structure penetrates the N+ source region downward and extends into the P-type base region; the bottom of the trench gate structure is connected to the N-drift region through an N-type region, wherein the N-type region is N-doped; the upper end of the trench gate structure is covered with an interlayer dielectric layer, wherein the width of the interlayer dielectric layer is greater than the width of the trench; a source metal is arranged on the upper ends of the interlayer dielectric layer, the N+ source region and the P+ region, and a drain metal is arranged on the lower end of the N+ substrate.
[0007] Furthermore, the trench gate structure includes a trench opened in the P-type body region, a gate oxide layer formed on the trench wall, and a gate filled in the trench. The gate oxide layer includes a bottom gate oxide layer formed at the bottom of the trench and a sidewall gate oxide layer formed on the sidewall of the trench, and the thickness of the bottom gate oxide layer is greater than the thickness of the sidewall gate oxide layer.
[0008] Furthermore, the thickness of the sidewall gate oxide layer is 400A to 600A, and the thickness of the bottom gate oxide layer is 2000A to 5000A thicker than the thickness of the sidewall gate oxide layer.
[0009] Furthermore, the depth of the groove is 0.9 μm to 1.5 μm.
[0010] Furthermore, the width of the N-type region is smaller than the width of the interlayer dielectric layer, and is greater than or equal to the width of the trench.
[0011] Furthermore, the depth of the N+ source region is greater than the depth of the P+ region; and / or
[0012] The thickness of the interlayer dielectric layer is 0.8 μm to 1.3 μm.
[0013] Furthermore, the P-type base region is formed on the N-drift region by epitaxy; the thickness of the P-type base region is 2 μm to 3 μm.
[0014] A method for manufacturing a high-voltage trench MOSFET structure comprises the following steps:
[0015] S100, taking an N+ substrate, and epitaxially growing an N-drift region and a P-type base region on the N+ substrate in sequence; the N+ substrate is heavily N-doped, the N-drift region is lightly N-doped, and the P-type base region is P-doped;
[0016] S200, forming an N+ source region by implantation on the upper portion of the P-type base region, wherein the N+ source region is heavily N-type doped;
[0017] S300, manufacturing a trench gate structure and an N-type region; the trench gate structure penetrates the N+ source region from the middle of the N+ source region downward and extends into the P-type base region; the bottom of the trench gate structure is connected to the N-drift region through the N-type region, and the N-type region is N-doped;
[0018] S400, forming a P+ region by implantation on both sides of the N+ source region, and performing a high temperature annealing treatment, wherein the P+ region is heavily doped with P type;
[0019] S500, forming an interlayer dielectric layer at the upper end of the trench gate structure, wherein the P-type base regions on both sides of the trench form a platform region, and both ends of the interlayer dielectric layer extend horizontally outward to above the platform region;
[0020] S600 , forming a source metal at the upper ends of the interlayer dielectric layer and the P-type base region, and forming a drain metal at the lower end of the N+ substrate.
[0021] Furthermore, in the step S200, the N+ source region is formed by tilted implantation, and the tilted implantation angle is 20° to 40°.
[0022] Furthermore, the step S300 includes the following sub-steps:
[0023] S310, depositing a hard mask, and forming a groove in the middle of the N+ source region by photolithography and etching processes, wherein the groove penetrates downward through the N+ source region and extends into the P-type base region;
[0024] S320, implanting N-type ions at the bottom of the trench to form an N-type region connecting the bottom of the trench and the N-drift region;
[0025] S330, depositing an oxide layer with a thickness of 2000 Å to 5000 Å in the trench, then depositing a hard mask, removing the oxide layer on the sidewall of the trench by photolithography and etching, and retaining the oxide layer at the bottom of the trench;
[0026] S340, growing an oxide layer with a thickness of 400 Å to 600 Å in the trench again to form a gate oxide layer;
[0027] S350, depositing polysilicon in the trench, and etching back to form a gate.
[0028] In the present invention, a P-type base region is formed by epitaxy, the thickness of the P-type base region is increased, and the P-type base region can completely wrap the trench gate structure; at the same time, an N-type region is formed at the bottom of the trench to realize the connection between the trench gate structure and the N-drift region. In this way, not only the gate leakage charge can be reduced to increase the switching speed, but also the electric field at the bottom of the trench can be reduced, so that the gate oxide layer can be effectively protected and the reliability can be improved. By thickening the gate oxide layer at the bottom of the trench, the reliability of the gate oxide layer here can be further improved, so that the reliability of the device is higher. In addition, by increasing the depth of the N+ source region by adopting the tilted injection method, the length of the formed conductive channel can be shortened, and the resistance of the conductive channel can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0030] Figure 1 This is a schematic diagram of the structure of a trench MOSFET in current technology.
[0031] Figure 2 It is a schematic structural diagram of an embodiment of a high withstand voltage trench MOSFET structure of the present invention.
[0032] Figure 3 The flowchart is a method for manufacturing a high withstand voltage trench MOSFET structure according to an embodiment of the present invention.
[0033] Figure 4 Schematic diagram of the structure after epitaxial growth of the N-drift region.
[0034] Figure 5 Schematic diagram of the structure after epitaxial growth of the P-type base region.
[0035] Figure 6 This is a schematic diagram of the structure after the N+ source region is formed by implantation.
[0036] Figure 7 This is a schematic diagram of the structure after the groove is opened.
[0037] Figure 8 It is a schematic diagram of the structure after the N-type region is formed.
[0038] Fig. 9 Schematic diagram of the structure after the gate oxide layer is formed.
[0039] Fig.10 Schematic diagram of the structure after the gate is formed.
[0040] Fig.11 This is a schematic diagram of the structure after implantation to form the P+ region.
[0041] Fig.12 Schematic diagram of the structure after the interlayer dielectric layer is made.
[0042] The accompanying drawings in the specification are as follows:
[0043] N+ substrate-100; N-drift region-110; P-type base region-120; N+ source region-130; P+ region-140; N-type region-150; trench-210; gate oxide layer-220; bottom gate oxide layer-221; sidewall gate oxide layer-222; gate-230; interlayer dielectric layer-300; source metal-400; drain metal-500. DETAILED DESCRIPTION
[0044] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.
[0045] See also Figure 2 , Figure 2 The schematic diagram of the structure of an embodiment of a high-voltage trench MOSFET structure of the present invention. The high-voltage trench MOSFET structure of this embodiment includes an N+ substrate 100, an N-drift region 110 and a P-type base region 120 arranged in sequence from bottom to top, wherein the N+ substrate 100 is heavily N-doped, the N-drift region 110 is lightly N-doped, and the P-type base region 120 is P-doped. In this embodiment, the P-type base region 120 is formed by epitaxy on the N-drift region 110, thereby greatly increasing the thickness of the P-type base region 120, and the thickness of the P-type base region 120 is 2μm to 3μm.
[0046] An N+ source region 130 is formed on the upper portion of the P-type base region 120, and P+ regions 140 are formed on both sides of the N+ source region 130. The N+ source region 130 is heavily doped with N type, and the P+ region 140 is heavily doped with P type. In this embodiment, the depth of the N+ source region 130 is greater than the depth of the P+ region 140, so that the length of the conductive channel formed when conducting can be shortened, thereby reducing the resistance of the conductive channel.
[0047] A trench gate structure is formed in the middle of the N+ source region 130, and the trench gate structure penetrates downwardly through the N+ source region 130 and extends into the P-type base region 120. The trench gate structure generally includes a trench 210 opened in the P-type body region, a gate oxide layer 220 formed on the trench wall of the trench 210, and a gate 230 filled in the trench 210; the depth of the trench 210 is generally 0.9μm to 1.5μm. In this embodiment, the gate oxide layer 220 includes a bottom gate oxide layer 221 formed at the bottom of the trench 210 and a sidewall gate oxide layer 222 formed on the sidewall of the trench 210, and the thickness of the bottom gate oxide layer 221 is greater than the thickness of the sidewall gate oxide layer 222. The thickness of the sidewall gate oxide layer 222 is generally 400A to 600A, and the thickness of the bottom gate oxide layer 221 is generally 2000A to 5000A thicker than the thickness of the sidewall gate oxide layer 222. In this embodiment, a thicker P-type base region 120 is formed by epitaxy to wrap around the trench gate structure, which can not only reduce the gate leakage charge and improve the switching speed, but also reduce the electric field at the bottom of the trench 210, thereby effectively protecting the gate oxide layer 220 and improving reliability. In addition, the thickening of the bottom gate oxide layer 221 can further improve the reliability of the gate oxide layer 220 here.
[0048] The bottom of the trench gate structure is connected to the N-drift region 110 through an N-type region 150, and the N-type region 150 is N-doped; the upper end of the trench gate structure is covered with an interlayer dielectric layer 300, and the thickness of the interlayer dielectric layer 300 is 0.8μm to 1.3μm; the width of the interlayer dielectric layer 300 is greater than the width of the trench 210. The width of the N-type region 150 is less than the width of the interlayer dielectric layer 300, and is greater than or equal to the width of the trench 210, so that the voltage resistance performance of the device can be guaranteed. The upper ends of the interlayer dielectric layer 300, the N+ source region 130 and the P+ region 140 are provided with a source metal 400. Of course, a passivation layer is generally provided on the source metal 400. The lower end of the N+ substrate 100 is provided with a drain metal 500.
[0049] In this embodiment, by increasing the thickness of the P-type base region 120, the P-type base region 120 can completely wrap the trench gate structure; at the same time, an N-type region 150 is formed at the bottom of the trench 210 to realize the connection between the trench gate structure and the N-drift region 110. This can not only reduce the gate leakage charge and improve the switching speed, but also reduce the electric field at the bottom of the trench 210, so that the gate oxide layer 220 can be effectively protected and the reliability can be improved. By thickening the gate oxide layer 220 at the bottom of the trench 210, the reliability of the gate oxide layer 220 here can be further improved, so that the reliability of the device is higher. In addition, by increasing the depth of the N+ source region 130, the length of the formed conductive channel can be shortened, which can reduce the resistance of the conductive channel.
[0050] See also Figure 3 , Figure 3 The flowchart of one embodiment of the method for manufacturing a high-voltage trench MOSFET structure of the present invention. The method for manufacturing a high-voltage trench MOSFET structure of this embodiment includes the following steps:
[0051] S100, take an N+ substrate 100, wherein the N+ substrate 100 is heavily N-type doped. Figure 4 First, an N-drift region 110 is epitaxially grown on an N+ substrate 100. The N-drift region 110 is lightly N-type doped. Figure 5 , a P-type base region 120 is epitaxially grown on the N-drift region 110; the P-type base region 120 is P-type doped. In this embodiment, an additional epitaxial process is used to form the P-type base region 120 alone, thereby greatly increasing the thickness of the P-type base region 120. The thickness of the P-type base region 120 is 2μm to 3μm, so as to completely wrap the trench gate structure in the subsequent process.
[0052] S200, please refer to Figure 6 After a hard mask is deposited on the upper part of the P-type base region 120, an N+ source region 130 is formed by injecting N-type ions of a predetermined concentration, and the N+ source region 130 is heavily doped with N-type. In this embodiment, the N+ source region 130 is formed by tilted injection, and the tilted injection angle is 20° to 40°, so that the depth of the N+ source region 130 can be increased.
[0053] S300, fabricating a trench gate structure and an N-type region 150; the trench gate structure penetrates the N+ source region 130 downward from the middle of the N+ source region 130 and extends into the P-type base region 120; the bottom of the trench gate structure is connected to the N-drift region 110 via the N-type region 150, and the N-type region 150 is N-doped. This step may include the following sub-steps:
[0054] S310, please refer to Figure 7 , deposit a hard mask, and form a groove in the middle of the N+ source region 130 through photolithography and etching processes, the groove penetrates downward through the N+ source region 130 and extends into the P-type base region 120; the depth of the groove 210 is generally 0.9μm to 1.5μm. Since the thickness of the P-type base region 120 is increased by epitaxially growing the P-type base region 120 alone in this embodiment, the P-type base region 120 can completely wrap the groove 210, and the groove 210 will not extend into the N-drift region 110.
[0055] S320, please refer to Figure 8, N-type ions are implanted at the bottom of the trench 210 to form an N-type region 150 connecting the bottom of the trench 210 and the N-drift region 110. The N-type region 150 is N-doped, and the width of the N-type region 150 is generally not less than the width of the trench 210. In order to ensure the withstand voltage performance of the device, the width of the N-type region 150 is generally less than the width of the interlayer dielectric layer 300 formed subsequently.
[0056] S330, depositing an oxide layer with a thickness of 2000A to 5000A in the trench 210, then depositing a hard mask, removing the oxide layer on the sidewall of the trench 210 by photolithography and etching, and retaining the oxide layer at the bottom of the trench 210 to increase the thickness of the gate oxide layer 220 at the bottom of the trench 210.
[0057] S340, please refer to Fig. 9 , an oxide layer with a thickness of 400A to 600A is grown in the trench 210 again to form a gate oxide layer 220. That is, the gate oxide layer 220 includes a bottom gate oxide layer 221 formed at the bottom of the trench 210 and a sidewall gate oxide layer 222 formed on the sidewall of the trench 210, the thickness of the sidewall gate oxide layer 222 is generally 400A to 600A, and the thickness of the bottom gate oxide layer 221 is 2000A to 5000A thicker than that of the sidewall gate oxide layer 222.
[0058] S350, see Fig.10 , polysilicon is deposited in the trench 210 , and is etched back to form the gate 230 , thereby completing the fabrication of the trench gate structure and the N-type region 150 .
[0059] S400, see Fig.11 First, a hard mask is deposited, and then the required P+ region 140 pattern is formed on both sides of the N+ source region 130 by photolithography and etching, and then the P+ region 140 is formed by implantation. The P+ region 140 is heavily doped with P type and can be formed by implanting Al ions. After that, a high temperature annealing treatment is performed for a period of time under a predetermined temperature environment.
[0060] S500, please refer to Fig.12 , an interlayer dielectric layer 300 is formed at the upper end of the trench gate structure, the P-type base region 120 on both sides of the trench 210 forms a platform region, and the two ends of the interlayer dielectric layer 300 extend horizontally outward to the top of the platform region. Of course, a Ni layer is generally deposited on the front side, and etched by a photolithography process, and a contact region (Contact) is formed at the upper end of the P+ region after annealing. Since this part of the structure is a conventional structure and has nothing to do with the improvement of this embodiment, it is not shown in the figure.
[0061] S600, please continue to read Figure 2, a source metal 400 is formed on the upper end of the interlayer dielectric layer 300 and the P-type base region 120, and a drain metal 500 is formed on the lower end of the N+ substrate 100. This step may include the following sub-steps:
[0062] S610, deposit a metal layer on the front side, and etch it through a photolithography process to form a source metal 400. Of course, a passivation material is generally deposited and etched through a photolithography process to form a passivation layer; since this part of the structure is a conventional structure and has nothing to do with the improvement of this embodiment, it is not shown in the figure.
[0063] S620, after completing the front process, grind the back side to the required thickness, and perform polishing, cleaning, evaporation, alloying and other processes in sequence to form a back side metal as the drain metal 500.
[0064] In this embodiment, the P-type base region 120 is formed by epitaxy, and the thickness of the P-type base region 120 is increased, so that it can completely wrap the trench 210, thereby reducing the gate-drain charge and improving the switching speed, and can reduce the electric field at the bottom of the trench 210, thereby effectively protecting the gate oxide layer 220 and improving reliability. In addition, by increasing the depth of the N+ source region 130 by using an inclined implantation method, the length of the formed conductive channel can be shortened, and the resistance of the conductive channel can be reduced.
[0065] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A high withstand voltage trench MOSFET structure, characterized in that: The invention comprises an N+ substrate, an N-drift region and a P-type base region which are arranged in sequence from bottom to top, wherein the N+ substrate is heavily N-doped, the N-drift region is lightly N-doped, and the P-type base region is P-doped; an N+ source region is formed on the upper part of the P-type base region, and P+ regions are formed on both sides of the N+ source region, wherein the N+ source region is heavily N-doped, and the P+ region is heavily P-doped; a trench gate structure is formed in the middle part of the N+ source region, wherein the trench gate structure penetrates the N+ source region downward and extends into the P-type base region; the bottom of the trench gate structure is connected to the N-drift region through an N-type region, wherein the N-type region is N-doped; the upper end of the trench gate structure is covered with an interlayer dielectric layer, wherein the width of the interlayer dielectric layer is greater than the width of the trench; a source metal is arranged on the upper ends of the interlayer dielectric layer, the N+ source region and the P+ region, and a drain metal is arranged on the lower end of the N+ substrate.
2. A high withstand voltage trench MOSFET structure as claimed in claim 1, characterized in that: The trench gate structure comprises a trench opened in a P-type body region, a gate oxide layer formed on the trench wall and a gate filled in the trench. The gate oxide layer comprises a bottom gate oxide layer formed at the bottom of the trench and a sidewall gate oxide layer formed on the sidewall of the trench, and the thickness of the bottom gate oxide layer is greater than the thickness of the sidewall gate oxide layer.
3. The high withstand voltage trench MOSFET structure according to claim 1, characterized in that: The thickness of the sidewall gate oxide layer is 400A-600A, and the thickness of the bottom gate oxide layer is 2000A-5000A thicker than that of the sidewall gate oxide layer.
4. The high withstand voltage trench MOSFET structure according to claim 2, wherein: The depth of the groove is 0.9 μm to 1.5 μm.
5. The high withstand voltage trench MOSFET structure according to claim 2, wherein: The width of the N-type region is smaller than the width of the interlayer dielectric layer, and is greater than or equal to the width of the trench.
6. The high withstand voltage trench MOSFET structure according to any one of claims 1 to 5, characterized in that: The depth of the N+ source region is greater than the depth of the P+ region; and / or The thickness of the interlayer dielectric layer is 0.8 μm to 1.3 μm.
7. The high withstand voltage trench MOSFET structure according to any one of claims 1 to 5, characterized in that: The P-type base region is formed on the N-drift region by epitaxy; the thickness of the P-type base region is 2 μm to 3 μm.
8. A method for manufacturing a high-voltage trench MOSFET structure, characterized in that: The following steps are involved: S100, taking an N+ substrate, and epitaxially growing an N-drift region and a P-type base region on the N+ substrate in sequence; the N+ substrate is heavily N-doped, the N-drift region is lightly N-doped, and the P-type base region is P-doped; S200, forming an N+ source region by implantation on the upper portion of the P-type base region, wherein the N+ source region is heavily N-type doped; S300, manufacturing a trench gate structure and an N-type region; the trench gate structure penetrates the N+ source region from the middle of the N+ source region downward and extends into the P-type base region; the bottom of the trench gate structure is connected to the N-drift region through the N-type region, and the N-type region is N-doped; S400, forming a P+ region by implantation on both sides of the N+ source region, and performing a high temperature annealing treatment, wherein the P+ region is heavily doped with P type; S500, forming an interlayer dielectric layer at the upper end of the trench gate structure, wherein the P-type base regions on both sides of the trench form a platform region, and both ends of the interlayer dielectric layer extend horizontally outward to above the platform region; S600 , forming a source metal at the upper ends of the interlayer dielectric layer and the P-type base region, and forming a drain metal at the lower end of the N+ substrate.
9. The method for manufacturing a high withstand voltage trench MOSFET structure according to claim 8, characterized in that: In the step S200, the N+ source region is formed by tilted implantation, and the tilted implantation angle is 20° to 40°.
10. The method for manufacturing a high withstand voltage trench MOSFET structure according to claim 8, characterized in that: The step S300 includes the following sub-steps: S310, depositing a hard mask, and forming a groove in the middle of the N+ source region by photolithography and etching processes, wherein the groove penetrates downward through the N+ source region and extends into the P-type base region; S320, implanting N-type ions at the bottom of the trench to form an N-type region connecting the bottom of the trench and the N-drift region; S330, depositing an oxide layer with a thickness of 2000 Å to 5000 Å in the trench, then depositing a hard mask, removing the oxide layer on the sidewall of the trench by photolithography and etching, and retaining the oxide layer at the bottom of the trench; S340, growing an oxide layer with a thickness of 400 Å to 600 Å in the trench again to form a gate oxide layer; S350, depositing polysilicon in the trench, and etching back to form a gate.