Cell structure of shielded gate trench MOSFET and manufacturing method thereof

Abstract

The application discloses a kind of shielded gate trench MOSFET cell structure and its manufacturing method, shielded gate trench MOSFET cell structure includes substrate, drift region and interlayer dielectric layer, the drift region is provided with deep groove, the deep groove is provided with shielded gate, intermediate oxide layer and control gate;The upper portion of the drift region is formed with body region and source region by injection, the interlayer dielectric is provided with source contact hole that is through source region and extends into body region, the sidewall and bottom of the source contact hole are formed with high-doped contact region by injection;The lower of the source contact hole is formed with charge balance region by high-energy ion injection.In the application, by setting charge balance region, the lateral depletion of adjacent drift region by shielded gate can be enhanced when shielded gate trench MOSFET device is in reverse bias state, the specific on-resistance of the device is reduced, the epitaxial layer drift region is accelerated, and the reliability and radiation resistance of the device are improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit applications, and in particular relates to a cell structure of a shielded gate trench MOSFET and its fabrication method. Background Technology

[0002] Trench MOSFETs improve performance by constructing the gate within a deep trench within the structure, building upon traditional DMOS. In a trench MOSFET, the trench gate extends through the P-type body region to its bottom, forming a channel between the source and drain regions, effectively reducing the JFET region found in traditional DMOS. Therefore, the total on-resistance of the trench MOSFET is significantly reduced. Furthermore, this reduction in on-resistance is not only due to the elimination of the series resistance in the JFET region, but also because the vertical gate structure allows for a higher cell density, thus reducing channel resistance, accumulation region resistance, and drift region resistance. Building upon trench MOSFETs, previous researchers proposed shielded-gate trench MOSFETs. The shielded-gate trench MOSFET structure significantly improves upon the high input capacitance and switching losses of previous trench MOSFETs. Moreover, due to the presence of the shielded gate, the influence of the gate voltage on the drain is greatly reduced, and a stronger electric field can be generated when a reverse voltage is applied to the drain, further reducing the on-resistance. Although shielded-gate trench MOSFETs can effectively reduce the on-resistance of DMOS and also possess a certain lateral electric field, their breakdown voltage layer remains a conventional "resistive" layer due to the presence of oxide layers on the trench sidewalls. As the reverse breakdown voltage increases, its on-resistance also gradually increases, failing to escape the "silicon limit" relationship between on-resistance and breakdown voltage inherent in traditional power devices. While optimization can be achieved by adjusting the structure and injection conditions, this inherent contradiction persists. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a cell structure of a shielded gate trench MOSFET and a method for fabricating the same.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0005] A cell structure of a shielded gate trench MOSFET includes a substrate, a drift region disposed on the substrate, and an interlayer dielectric layer disposed on the drift region. A drain metal is disposed at the lower end of the substrate. A deep trench is disposed on the drift region, and a sidewall oxide layer is disposed on the trench wall. A shielding gate is disposed at the lower part of the deep trench, and a control gate is disposed at the upper part of the deep trench. The shielding gate and the control gate are isolated by an intermediate oxide layer. An active region is formed above the drift region by implantation, and a body region is formed below the active region by implantation. A source metal is disposed on the interlayer dielectric layer at a position corresponding to the source region above it. A source contact hole is disposed below the source metal, penetrating the interlayer dielectric and the source region and extending into the body region. The source contact hole is filled with a metal plug. The sidewalls and bottom of the source contact hole are formed with highly doped contact regions by implantation. A charge balance region is formed below the source contact hole by high-energy ion implantation. The charge balance region is used to enhance the lateral depletion of the shielding gate on the adjacent drift region when the shielded gate trench MOSFET device is in reverse bias.

[0006] Furthermore, the drift region includes a first epitaxial layer grown on the substrate and a second epitaxial layer grown on the first epitaxial layer, wherein the deep trench penetrates the second epitaxial layer and extends into the first epitaxial layer.

[0007] Furthermore, the substrate is a heavily doped substrate of the first doping type, and both the first epitaxial layer and the second epitaxial layer are heavily doped of the first doping type; the shielding gate and the control gate are of the second doping type; the body region is lightly doped of the second doping type; the source region includes a first heavily doped region and a second heavily doped region, the first heavily doped region is located on the side of the source region adjacent to the deep trench, and the second heavily doped region is located on the side of the first heavily doped region away from the deep trench; the first heavily doped region is heavily doped of the first doping type, and the second heavily doped region is heavily doped of the second doping type; the charge balance region is of the second doping type, and the highly doped contact region is heavily doped of the second doping type.

[0008] Furthermore, the resistivity of the substrate is 0.001 Ω·cm to 0.003 Ω·cm, the material of the metal plug is tungsten, and the material of the source metal is aluminum-copper.

[0009] Furthermore, the first doping type is N-type doping, and the second doping type is P-type doping; or

[0010] The first doping type is P-type doping, and the second doping type is N-type doping.

[0011] Furthermore, the width of the charge balance region is 0.13 μm to 0.17 μm, the depth is 2.2 μm to 2.8 μm, and the carrier concentration is 3.7 e⁻¹. 16 cm-3 ~4.3e 16 cm -3 .

[0012] A method for fabricating a cell structure of a shielded gate trench MOSFET includes the following steps:

[0013] S100: A drift region is formed on a substrate, and a deep trench is formed on the drift region;

[0014] S200, A shielding gate, an intermediate oxide layer and a control gate are sequentially formed in the deep trench;

[0015] S300, A body region and a source region are sequentially formed in the upper part of the drift region by injection;

[0016] S400: An interlayer dielectric layer is formed by chemical vapor deposition, and through-hole etching is performed above the source region to form a source contact hole that penetrates the interlayer dielectric and the source region and extends into the bulk region.

[0017] S500: High-energy ion implantation is performed below the source contact hole to form a charge balance region, and highly doped contact regions are formed on the sidewalls and bottom of the source contact hole through implantation.

[0018] S600: Fill the source contact hole with a metal plug and form a source metal connected to the metal plug on the interlayer dielectric layer; form a drain metal on the back side of the substrate.

[0019] Furthermore, the substrate is a heavily doped substrate of the first doping type, the drift region is heavily doped of the first doping type; the shielding gate and the control gate are of the second doping type; the body region is lightly doped of the second doping type; the source region includes a first heavily doped region and a second heavily doped region, the first heavily doped region is located on the side of the source region adjacent to the deep trench, and the second heavily doped region is located on the side of the first heavily doped region away from the deep trench; the first heavily doped region is heavily doped of the first doping type, and the second heavily doped region is heavily doped of the second doping type; the charge balance region is of the second doping type, and the highly doped contact region is heavily doped of the second doping type.

[0020] Furthermore, step S100 includes the following sub-steps:

[0021] S101. Take a substrate with a first epitaxial layer;

[0022] S102. After thinning the first epitaxial layer, a second epitaxial layer is grown, and the first epitaxial layer and the second epitaxial layer form a drift region;

[0023] S103. A first oxide layer, a nitride layer, and a second oxide layer are sequentially grown on the second epitaxial layer.

[0024] S104. Define the formation region of the deep trench; and remove the first oxide layer, nitride layer and second oxide layer of the deep trench formation region by photolithography to expose the surface of the second epitaxial layer in the deep trench region.

[0025] S105. Etch downwards the exposed portion of the second epitaxial layer and extend it into the first epitaxial layer to form a deep trench.

[0026] Furthermore, step S200 includes the following sub-steps:

[0027] S201. Etch away the second oxide layer, retaining the first oxide layer and nitride layer; perform linear oxidation on the trench walls of the deep trench and deposit the third oxide layer;

[0028] S202. Polysilicon is grown once using an epitaxial growth process until the deep trench is filled and the outer surface of the deep trench is covered.

[0029] S203. Remove the primary polysilicon outside the deep trench by chemical mechanical polishing, and etch back the primary polysilicon in the deep trench. The remaining primary polysilicon after etching is located at the bottom of the deep trench, forming a shielding gate.

[0030] S204, deposit silicon dioxide to form the fourth oxide layer until the deep trench is filled;

[0031] S205. The fourth oxide layer in the deep trench is etched back to form a shallow trench; the remaining fourth oxide layer below the shallow trench forms an intermediate oxide layer.

[0032] S206. Etch to remove the third oxide layer on the shallow trench sidewall and remove the nitride layer and the first oxide layer on the drift area.

[0033] S207. A thin oxide layer is formed on the sidewalls of the shallow trench and the surface of the drift area by thermal oxidation;

[0034] S208. Secondary polysilicon is grown using an epitaxial growth process until the shallow trench is filled and the outer surface of the shallow trench is covered.

[0035] S209. Secondary polysilicon outside the shallow trench is removed by chemical mechanical polishing, and the secondary polysilicon in the shallow trench is etched back to make it lower than the silicon surface to form a control gate.

[0036] S210. The control gate is thermally annealed to form a surface oxide layer.

[0037] In this invention, based on the existing manufacturing principles of shielded gate trench MOSFET devices, a second type of doping impurity is injected into the drift region of the first type of doping through high-energy implantation to form a superjunction VDMOS structure, thereby improving the performance of VDMOS. In this structure, by utilizing the charge balance effect, the lateral depletion of the drift region in the shielded gate trench MOSFET device under reverse bias is increased. This allows the existing structure to use a higher concentration of doping while maintaining the same breakdown voltage, thus reducing the on-resistance. It also achieves a higher breakdown voltage without changing the concentration and thickness of the drift region in the existing shielded gate trench MOSFET device, and improves the reliability and radiation resistance of the shielded gate trench MOSFET device. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 This is a schematic diagram of a cell structure of an embodiment of the shielded gate trench MOSFET of the present invention.

[0040] Figure 2 This is a flowchart of an embodiment of the method for fabricating the cell structure of the shielded gate trench MOSFET of the present invention.

[0041] Figure 3 This is a schematic diagram of the structure after the deep trenches have been formed.

[0042] Figure 4 This is a schematic diagram of the structure after the deposition of the third oxide layer.

[0043] Figure 5 This is a schematic diagram of the structure after one polycrystalline silicon growth.

[0044] Figure 6 This is a schematic diagram of the structure after a single etch-back of polysilicon.

[0045] Figure 7 This is a schematic diagram of the structure after the fourth oxide layer has been etched back and the third oxide layer, nitride layer, and first oxide layer have been removed.

[0046] Figure 8 This is a schematic diagram of the structure after the formation of a thin oxide layer.

[0047] Figure 9 This is a schematic diagram of the structure after secondary polycrystalline silicon growth.

[0048] Figure 10 This is a schematic diagram of the structure after the formation of the solid region.

[0049] Figure 11 This is a schematic diagram of the structure after the source contact hole is formed.

[0050] Figure 12 This is a schematic diagram of the structure after the formation of the charge balance region and the highly doped contact region.

[0051] The diagrams in the instruction manual are labeled as follows:

[0052] Substrate - 100; Drift region - 200; First epitaxial layer - 210; Second epitaxial layer - 220; Deep trench - 230; Sidewall oxide layer - 231; Shielding gate - 232; Intermediate oxide layer - 233; Control gate - 234; Surface oxide layer - 235; Shallow trench - 236; Body region - 240; Source region - 250; First heavily doped region - 251; Second heavily doped region - 252;

[0053] First oxide layer - 310; Nitride layer - 320; Second oxide layer - 330; Third oxide layer - 340; Primary polysilicon - 350; Thin oxide layer - 360; Secondary polysilicon - 370; Interlayer dielectric layer - 400; Source contact hole - 500; Highly doped contact region - 501; Metal plug - 510; Charge balance region - 520; Drain metal - 600; Source metal - 700. Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0055] Please see Figure 1 , Figure 1 This is a schematic diagram of a cell structure of an embodiment of the shielded gate 232 trench MOSFET of the present invention. The cell structure of the shielded gate 232 trench MOSFET of this embodiment includes a substrate 100, a drift region 200 disposed on the substrate 100, and an interlayer dielectric layer 400 disposed on the drift region 200. The substrate 100 is a heavily doped substrate of the first doping type, and the resistivity of the substrate 100 is 0.001 Ω·cm to 0.003 Ω·cm. A drain metal 600 is disposed at the lower end of the substrate 100, thereby forming the drain of the shielded gate 232 trench MOSFET device.

[0056] A deep trench 230 is provided on the drift region 200, and a sidewall oxide layer 231 is provided on the trench wall of the deep trench 230. A shielding gate 232 is provided at the lower part of the deep trench 230, and a control gate 234 is provided at the upper part of the deep trench 230. The shielding gate 232 and the control gate 234 are isolated by an intermediate oxide layer 233. In this embodiment, the drift region 200 includes a first epitaxial layer 210 grown on the substrate 100 and a second epitaxial layer 220 grown on the first epitaxial layer 210. The deep trench 230 penetrates the second epitaxial layer 220 and extends into the first epitaxial layer 210. The shielding gate 232 is formed by etching back polysilicon filling the deep trench 230, and the shielding gate 232 structure is located at the bottom of the deep trench 230. After the shielding gate 232 is formed, an oxide layer is formed on its top and an intermediate isolation oxide layer is formed by etching back. The thickness of the intermediate isolation oxide layer is approximately 200 nm. The control gate 234 is formed by refilling polysilicon on top of the deep trench 230 and then etching it back. The width of the control gate 234 is greater than the width of the shielding gate 232, which ensures that the impurity concentration in the subsequent channel region (i.e., the area where the deep trench 230 is located) is not affected by the shielding gate 232. The depth of the control gate 234 can be varied and is usually adjusted according to the depth of the deep trench 230.

[0057] Both the first epitaxial layer 210 and the second epitaxial layer 220 are heavily doped with the first doping type. The thickness and resistivity of the first epitaxial layer 210 and the second epitaxial layer 220 are selected based on the breakdown voltage of the shielded gate 232 trench MOSFET device design. For example, for an SGTMOS device with a breakdown voltage of around 100V, the thickness of the first epitaxial layer 210 can be 5.5μm, and the resistivity can be 0.18Ω·cm; the thickness of the second epitaxial layer 220 can be 3.0μm, and the resistivity can be 0.36Ω·cm. For shielded gate 232 trench MOSFET devices with higher breakdown voltage designs, the thickness of the epitaxial layer is typically thicker.

[0058] The depth of the deep trench 230 is typically determined by the breakdown voltage of the designed device; the higher the breakdown voltage requirement, the deeper the deep trench 230. For a shielded gate 232 trench MOSFET with a breakdown voltage of approximately 100V, the depth of the deep trench 230 can be 6.1μm, its width can be selected as 1μm, and the pitch width can be selected as 2.5μm. The thickness of the oxide layer 231 at the bottom and sidewalls of the deep trench 230 can be selected as 550nm.

[0059] The upper part of the drift region 200 is injected to form an active region 250, and the carrier concentration of the source region 250 is generally in the range of 1e. 19 cm -3The source region 250 may include a first heavily doped region 251 and a second heavily doped region 252. The first heavily doped region 251 is located on the side of the source region 250 adjacent to the deep trench 230, and the second heavily doped region 252 is located on the side of the first heavily doped region 251 away from the deep trench 230. The first heavily doped region 251 is a first type of heavy doping, and the second heavily doped region 252 is a second type of heavy doping. A body region 240 is formed below the source region 250 by implantation. The body region 240 is a second type of light doping. The impurity concentration of the body region 240 is generally around 1e. 17 cm -3 The main purpose is to meet the device threshold voltage and ensure that the device does not experience source-drain punch-through.

[0060] A source metal 700 is disposed on the interlayer dielectric layer 400 at a position corresponding to the source region 250. The source metal 700 can be made of aluminum or copper. Below the source metal 700, a second heavily doped region 252 is disposed, penetrating the interlayer dielectric and the source region 250, and extending into the source contact hole 500 of the body region 240. The source contact hole 500 is filled with a metal plug 510, thereby connecting the source region 250 to the source metal 700 through the metal plug 510, forming the source of the trench MOSFET device with shielded gate 232. The use of a metal plug 510 to fill the source contact hole 500 can reduce the device area. The material of the metal plug 510 is generally tungsten metal, that is, the metal plug 510 is generally a tungsten plug.

[0061] In addition, after forming the source contact hole 500, a highly doped contact region 501 is formed on the sidewalls and bottom of the source contact hole 500 by implantation. The highly doped contact region 501 is a second-type heavily doped region to form an ohmic contact. Below the source contact hole 500, a charge balance region 520 is formed by high-energy ion implantation. The charge balance region 520 is used to enhance the lateral depletion of the shielding gate 232 on the adjacent drift region 200 when the trench MOSFET device of the shielding gate 232 is in reverse bias. The charge balance region 520 is a second-type doped region, with a width of 0.13 μm to 0.17 μm, preferably 0.15 μm; a depth of 2.2 μm to 2.8 μm, preferably 2.5 μm; and a carrier concentration of 3.7 e-1. 16 cm -3 ~4.3e 16 cm -3 4e is preferred 16 cm -3 To ensure that the carrier concentration is roughly the same as that of the surrounding drift zone, lateral depletion is guaranteed.

[0062] In this embodiment, the trench MOSFET device with shielded gate 232 is an N-type device, meaning the first doping type is N-type doping and the second doping type is P-type doping. In this case, the doping impurity of the substrate 100 can be arsenic, and the doping impurities of the first epitaxial layer 210 and the second epitaxial layer 220 can be phosphorus. Alternatively, the trench MOSFET device with shielded gate 232 can also be a P-type device, in which case the first doping type is P-type doping and the second doping type is N-type doping.

[0063] In this embodiment, by injecting ions below the source contact hole 500, the original "resistive" withstand layer is transformed into a "junctional" withstand layer, which can reduce the resistance of the JFET region; accelerate EPI depletion, ensure a small electric field strength at the trench edge, improve the reliability of the shielded gate 232 trench MOSFET device; and optimize the radiation resistance of the shielded gate 232 trench MOSFET device.

[0064] In this embodiment, based on the existing manufacturing principle of the shielded gate 232 trench MOSFET device, a second type of doped impurity is injected into the first type of doped drift region 200 through high-energy implantation to form a superjunction VDMOS structure, thereby improving the performance of the VDMOS. In this structure, by utilizing the charge balance effect, the lateral depletion of the drift region 200 of the shielded gate 232 trench MOSFET device under reverse bias is increased, allowing the existing structure to use a higher concentration of doping while maintaining the same breakdown voltage, thus reducing the on-resistance. Similarly, without changing the concentration and thickness of the drift region 200 in the existing shielded gate 232 trench MOSFET device, this structure also has a higher breakdown voltage. This embodiment reduces the specific on-resistance of the shielded gate 232 trench MOSFET device, accelerates the depletion of the epitaxial layer drift region 200, ensures a smaller electric field strength at the trench edge, and improves the reliability of the shielded gate 232 trench MOSFET device; in addition, it can also effectively improve the radiation resistance of the shielded gate 232 trench MOSFET device.

[0065] Please see Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the cell structure fabrication method for the shielded gate 232 trench MOSFET of the present invention. This embodiment uses an N-type shielded gate 232 trench MOSFET as an example for explanation. Of course, a P-type shielded gate 232 trench MOSFET can also be fabricated using the method of this embodiment, only requiring changes to the doping type of each part. The cell structure fabrication method for the shielded gate 232 trench MOSFET includes the following steps:

[0066] S100, please refer to Figure 3 A drift region 200 is formed on the substrate 100, and a deep trench 230 is formed on the drift region 200. Figure 3 In the middle, the grooves at both ends are the terminal region grooves, and the three grooves in the middle are the deep grooves 230 of the cell structure, that is... Figure 3 The diagram shows a three-cell structure. This step may include the following sub-steps:

[0067] S101. Take a substrate 100 having a first epitaxial layer 210. The substrate 100 is an N+ substrate 100, and its doping impurity can be arsenic. Its resistivity is usually 0.001 Ω·cm to 0.003 Ω·cm. The first epitaxial layer 210 is N+ doped.

[0068] S102. The first epitaxial layer 210 is thinned. Based on the designed breakdown voltage of the trench MOSFET device with shielded gate 232, the first epitaxial layer 210 is etched to a suitable thickness. Then, a second epitaxial layer 220 is grown. The second epitaxial layer 220 is N+ doped. The first epitaxial layer 210 and the second epitaxial layer 220 form the drift region 200. The thickness and resistivity of the second epitaxial layer 220 are also selected based on the designed breakdown voltage of the trench MOSFET device with shielded gate 232.

[0069] S103. A first oxide layer 310, a nitride layer 320, and a second oxide layer 330 are sequentially grown on the second epitaxial layer 220. The first oxide layer 310, the nitride layer 320, and the second oxide layer 330 constitute a hard mask layer, which is generally about 450 nm in size.

[0070] S104. Photoresist is used to define the formation area of ​​the deep trench 230; and the first oxide layer 310, nitride layer 320 and second oxide layer 330 in the formation area of ​​the deep trench 230 are removed sequentially by photolithography to expose the silicon surface of the second epitaxial layer 220 in the deep trench 230 area.

[0071] S105. The exposed portion of the second epitaxial layer 220 is etched downwards and extends into the first epitaxial layer 210 to form a deep trench 230.

[0072] S200, a shielding gate 232, an intermediate oxide layer 233, and a control gate 234 are sequentially formed in the deep trench 230. This step may include the following sub-steps:

[0073] S201, please refer to Figure 4 The second oxide layer 330 is removed by etching, while the first oxide layer 310 and the nitride layer 320 are retained. Then, the trench walls of the deep trench 230 are linearly oxidized and the third oxide layer 340 is deposited.

[0074] S202, please refer to Figure 5P-type doped primary polycrystalline silicon 350 is grown using an epitaxial growth process until it fills the deep trench 230 and covers the outer surface of the deep trench 230.

[0075] S203, please refer to Figure 6 The epitaxially grown primary polysilicon 350 is chemically and mechanically polished until the primary polysilicon 350 on the surface (i.e., the secondary polysilicon 370 outside the deep trench 230) is completely removed. Then, the primary polysilicon 350 in the deep trench 230 is etched back, and the remaining primary polysilicon 350 after etching is located at the bottom of the deep trench 230, forming a shielding gate 232. Figure 6 It can be seen that the primary polysilicon 350 in the trench of the terminal area is only etched back to be flush with the silicon surface, which is different from the etch-back position of the primary polysilicon 350 in the deep trench 230 of the cell structure.

[0076] S204, deposit silicon oxide to form a fourth oxide layer until the deep trench 230 is filled.

[0077] S205, please refer to Figure 7 The fourth oxide layer in the deep trench 230 is etched back to form a shallow trench 236; the remaining fourth oxide layer below the shallow trench 236 forms an intermediate oxide layer. The thickness of the intermediate isolation oxide layer is approximately 200 nm.

[0078] S206, please continue reading Figure 7 The third oxide layer 340 on the sidewall of the shallow trench 236 is etched away so that the width of the control gate 234 formed subsequently is greater than the width of the shielding gate 232; and the nitride layer 320 and the first oxide layer 310 on the drift region 200 are removed.

[0079] S207, please refer to Figure 8 A thin oxide layer 360 is formed on the sidewalls of the shallow trench 236 and the surface of the drift region 200 by thermal oxidation.

[0080] S208, please refer to Figure 9 P-type doped secondary polycrystalline silicon 370 is grown using an epitaxial growth process until it fills the shallow trench 236 and covers the outer surface of the shallow trench 236.

[0081] S209, please refer to Figure 10 The epitaxially grown secondary polysilicon 370 is chemically and mechanically polished until the secondary polysilicon 370 on the surface (i.e., the secondary polysilicon 370 outside the shallow trench 236) is completely removed. Then, the secondary polysilicon 370 in the shallow trench 236 is etched back to make it about 100nm below the silicon surface to form the control gate 234.

[0082] S210, please continue reading Figure 10The control gate 234 is thermally annealed to form a surface oxide layer 235.

[0083] S300, please continue reading Figure 10 In the upper part of the drift region 200, a body region 240 and a source region 250 are sequentially formed by implantation. Specifically, photoresist is first used to define the area of ​​the body region 240 on the drift region 200, followed by ion implantation of the body region 240, and then push-well formation is performed to form the body region 240. Please refer to [link to relevant documentation]. Figure 11 Subsequently, a source region 250 is formed on the upper part of the body region 240 by implantation. The body region 240 is P-doped, and the source region 250 includes an N+ doped region.

[0084] S400, please continue reading Figure 11 An interlayer dielectric layer 400 is formed by chemical vapor deposition, and a via etching is performed above the source region 250 to form a source contact hole 500 that penetrates the interlayer dielectric and the source region 250 and extends into the body region 240.

[0085] S500, please refer to Figure 12 High-energy ion implantation is performed below the source contact hole 500 to form a charge balance region 520. Highly doped contact regions 501 are formed on the sidewalls and bottom of the source contact hole 500 through implantation. The charge balance region 520 is P-type doped to enhance the lateral depletion of the shielding gate 232 on the adjacent drift region 200 when the trench MOSFET device is in reverse bias. The width of the charge balance region 520 is 0.13 μm to 0.17 μm, preferably 0.15 μm; the depth of the charge balance region 520 is 2.2 μm to 2.8 μm, preferably 2.5 μm; and the carrier concentration is 3.7 e-1. 16 cm -3 ~4.3e 16 cm -3 4e is preferred 16 cm -3 The carrier concentration is designed to be approximately the same as that of the surrounding drift region to ensure lateral depletion. The highly doped contact region 501 is P+ doped to form an ohmic contact.

[0086] S600, please continue reading Figure 1 The process involves filling the source contact hole 500 with a metal plug 510 and forming a source metal 700 connected to the metal plug 510 on the interlayer dielectric layer 400; and after thinning the substrate 100, forming a drain metal 600 on the back side of the substrate 100. These are all conventional processes and will not be described in detail here.

[0087] The cell structure fabrication method of the shielded gate 232 trench MOSFET in this embodiment only adds the process of implanting to form a charge balance region 520 to the original device cell structure fabrication process, thus not increasing the manufacturing difficulty. This embodiment enhances the lateral depletion of charge carriers by adding ion implantation to the original shielded gate 232 trench MOSFET design process to form the charge balance region 520, thereby reducing the specific on-resistance of the shielded gate 232 trench MOSFET device, accelerating the depletion of the epitaxial layer drift region 200, ensuring a low electric field strength at the trench edge, and improving the reliability of the shielded gate 232 trench MOSFET device. Furthermore, it can effectively improve the radiation resistance of the shielded gate 232 trench MOSFET device; thus, it can effectively improve the device performance of the shielded gate 232 trench MOSFET without adding additional photolithography layers or increasing process complexity.

[0088] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A method for fabricating the cell structure of a shielded gate trench MOSFET, characterized in that, Includes the following steps: S100. A drift region is formed on a substrate, and a deep trench is formed on the drift region; the substrate is a heavily doped substrate of the first doping type, and the drift region is heavily doped of the first doping type; S200, A shielding gate, an intermediate oxide layer and a control gate are sequentially formed in the deep trench; S300, A body region and a source region are sequentially formed in the upper part of the drift region by injection; S400: An interlayer dielectric layer is formed by chemical vapor deposition, and through-hole etching is performed above the source region to form a source contact hole that penetrates the interlayer dielectric and the source region and extends into the bulk region. S500: High-energy ion implantation is performed below the source contact hole to form a charge balance region, and highly doped contact regions are formed on the sidewalls and bottom of the source contact hole through implantation; the charge balance region is a second doping type, and the highly doped contact region is a second doping type heavily doped. S600: Fill the source contact hole with a metal plug and form a source metal connected to the metal plug on the interlayer dielectric layer; form a drain metal on the back side of the substrate.

2. The method for fabricating the cell structure of a shielded gate trench MOSFET as described in claim 1, characterized in that, The shielding gate and control gate are of the second doping type; the body region is of the second doping type with light doping; the source region includes a first heavily doped region and a second heavily doped region, the first heavily doped region is located on the side of the source region adjacent to the deep trench, and the second heavily doped region is located on the side of the first heavily doped region away from the deep trench; the first heavily doped region is of the first doping type with heavy doping, and the second heavily doped region is of the second doping type with heavy doping.

3. The method for fabricating the cell structure of a shielded gate trench MOSFET as described in claim 1, characterized in that, Step S100 includes the following sub-steps: S101. Take a substrate with a first epitaxial layer; S102. After thinning the first epitaxial layer, a second epitaxial layer is grown, and the first epitaxial layer and the second epitaxial layer form a drift region; S103. A first oxide layer, a nitride layer, and a second oxide layer are sequentially grown on the second epitaxial layer. S104. Define the formation area of ​​deep trenches; Then, the first oxide layer, nitride layer and second oxide layer in the deep trench formation region are removed sequentially by photolithography to expose the surface of the second epitaxial layer in the deep trench region. S105. Etch downwards the exposed portion of the second epitaxial layer and extend it into the first epitaxial layer to form a deep trench.

4. The method for fabricating the cell structure of a shielded gate trench MOSFET as described in claim 1, characterized in that, Step S200 includes the following sub-steps: S201. Etch away the second oxide layer, retaining the first oxide layer and nitride layer; perform linear oxidation on the trench walls of the deep trench and deposit the third oxide layer; S202. Polysilicon is grown once using an epitaxial growth process until the deep trench is filled and the outer surface of the deep trench is covered. S203. Remove the primary polysilicon outside the deep trench by chemical mechanical polishing, and etch back the primary polysilicon in the deep trench. The remaining primary polysilicon after etching is located at the bottom of the deep trench, forming a shielding gate. S204, deposit silicon dioxide to form the fourth oxide layer until the deep trench is filled; S205. The fourth oxide layer in the deep trench is etched back to form a shallow trench; the remaining fourth oxide layer below the shallow trench forms an intermediate oxide layer. S206. Etch to remove the third oxide layer on the shallow trench sidewall and remove the nitride layer and the first oxide layer on the drift area. S207. A thin oxide layer is formed on the sidewalls of the shallow trench and the surface of the drift area by thermal oxidation; S208. Secondary polysilicon is grown using an epitaxial growth process until the shallow trench is filled and the outer surface of the shallow trench is covered. S209. Secondary polysilicon outside the shallow trench is removed by chemical mechanical polishing, and the secondary polysilicon in the shallow trench is etched back to make it lower than the silicon surface to form a control gate. S210. The control gate is thermally annealed to form a surface oxide layer.

5. A cell structure for a shielded gate trench MOSFET, characterized in that: The cell structure fabrication method for a shielded gate trench MOSFET as described in any one of claims 1 to 4 includes a substrate, a drift region disposed on the substrate, and an interlayer dielectric layer disposed on the drift region. A drain metal is disposed at the lower end of the substrate. A deep trench is disposed on the drift region, and a sidewall oxide layer is disposed on the trench wall. A shielding gate is disposed at the lower part of the deep trench, and a control gate is disposed at the upper part of the deep trench. The shielding gate and the control gate are isolated by an intermediate oxide layer. An active region is formed above the drift region by implantation, and a body region is formed below the active region by implantation. A source metal is disposed on the interlayer dielectric layer at a position corresponding to the position above the active region. The device comprises a source contact hole extending into the body region and penetrating the interlayer dielectric and the source region below the source metal, the source contact hole being filled with a metal plug; the sidewalls and bottom of the source contact hole are formed with highly doped contact regions by implantation; a charge balance region is formed below the source contact hole by high-energy ion implantation, the charge balance region being used to enhance the lateral depletion of the shielding gate on the adjacent drift region when the shielded gate trench MOSFET device is in reverse bias; the substrate is a heavily doped substrate of the first doping type, the drift region is heavily doped of the first doping type; the charge balance region is of the second doping type, and the highly doped contact region is heavily doped of the second doping type.

6. The cell structure of the shielded gate trench MOSFET as described in claim 5, characterized in that: The drift region includes a first epitaxial layer grown on the substrate and a second epitaxial layer grown on the first epitaxial layer, wherein the deep trench penetrates the second epitaxial layer and extends into the first epitaxial layer.

7. The cell structure of the shielded gate trench MOSFET as described in claim 6, characterized in that: Both the first epitaxial layer and the second epitaxial layer are heavily doped with the first doping type; the shielding gate and the control gate are of the second doping type; the body region is lightly doped with the second doping type; the source region includes a first heavily doped region and a second heavily doped region, the first heavily doped region is located on the side of the source region adjacent to the deep trench, and the second heavily doped region is located on the side of the first heavily doped region away from the deep trench; the first heavily doped region is heavily doped with the first doping type, and the second heavily doped region is heavily doped with the second doping type.

8. The cell structure of the shielded gate trench MOSFET as described in claim 7, characterized in that: The resistivity of the substrate is 0.001 Ω·cm to 0.003 Ω·cm, the material of the metal plug is tungsten, and the material of the source metal is aluminum-copper.

9. The cell structure of the shielded gate trench MOSFET as described in claim 5, characterized in that: The first doping type is N-type doping, and the second doping type is P-type doping; or The first doping type is P-type doping, and the second doping type is N-type doping.

10. The cell structure of the shielded gate trench MOSFET as described in claim 5, characterized in that: The charge balance region has a width of 0.13 μm to 0.17 μm, a depth of 2.2 μm to 2.8 μm, and a carrier concentration of 3.7 e. 16 cm -3 ~4.3e 16 cm -3 .

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