Field stop layer preparation method, process monitoring method and semiconductor device preparation method

Abstract

The invention provides a field stop layer preparation method, a process monitoring method and a semiconductor device preparation method, and belongs to the technical field of semiconductor power devices. Comprising a gate oxide layer located on the upper surface of the epitaxial layer, a polycrystalline silicon layer located on the upper surface of the gate oxide layer, a body region located in the epitaxial layer and a first injection region located in the body region; gluing the front surface of the wafer prefabricated member, turning over the wafer prefabricated member with the front surface protection glue, and thinning the back surface of the wafer prefabricated member; performing ion implantation on the back surface of the wafer prefabricated member by adopting a front surface implantation machine to form a field stop layer; and turning over again, and removing the front protection glue. The method has the beneficial effects that the field stop layer is formed by utilizing a front injection machine in the front-section process, so that production line pollution is avoided, and the manufacturing process of the field stop layer is more favorably realized; the problem that the back injection machine table of a wafer factory is limited is solved, no extra machine table needs to be purchased, the utilization rate of the machine table is improved, and cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and in particular to a method for preparing a field cutoff layer and a process monitoring method, as well as a method for preparing semiconductor devices. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs), as the mainstream power switching devices in medium- and high-power power electronics, have become one of the most important power semiconductor devices today. Due to their excellent overall performance, IGBT devices are widely used in transportation, motor control, traction drives, smart grids, home appliances, and many other fields. In practical applications, IGBT devices are usually used in anti-parallel connection with fast recovery diodes (FRDs). The role of the FRD is to provide a freewheeling path for the inductive load when the IGBT is turned off, preventing excessively high voltage spikes from damaging the IGBT. However, this anti-parallel connection increases the system cost and size, hindering the miniaturization and integration of the device. With the continuous development of semiconductor technology, in order to address the aforementioned issues and meet higher power handling requirements, the industry has begun to explore the monolithic integration of IGBTs and FRDs. Reverse-conducting insulated-gate bipolar transistors (RC-IGBTs) have emerged as a result. RC-IGBT devices integrate IGBTs and FRDs on the same chip, eliminating the need for additional anti-parallel diodes and significantly saving silicon area. Especially for high-voltage devices with small single-chip areas, the advantages of RC-IGBTs are even more pronounced because the monolithically integrated IGBT and FRD share a single terminal, resulting in a larger junction area and a relatively smaller proportion of active area. Compared to traditional IGBT devices, RC-IGBT devices offer numerous advantages such as smaller size, lower cost, higher power density, lower parasitic inductance, higher reliability, and simplified manufacturing processes, making them a research hotspot in the field of power electronics.

[0003] In existing technologies, high-voltage RC-IGBT devices typically employ a non-punch-through (NPT) structure. For example... Figure 1As shown, a traditional NPT structure high-voltage RC-IGBT device includes an N-type epitaxial layer 1 (N-EPI), a P-type body region 2 formed on the front side of the N-type epitaxial layer 1, an N+ type first injection region 3 formed in the P-type body region, an N+ type second injection region 4 and a P+ type injection region 5 alternately formed on the back side of the N-type epitaxial layer 1, a gate metal layer G1 and an emitter metal layer E1 on the front side, and a collector metal layer C1 on the back side. The N+ type second injection region 4 serves as the cathode of the fast recovery diode (FRD), and the P+ type injection region 5 serves as the collector of the IGBT. To achieve high withstand voltage, the NPT structure has a relatively thick chip, such as approximately 520 μm for a 3000V device, resulting in a large on-state voltage drop (Vcesat). Therefore, existing NPT structures face significant challenges in balancing withstand voltage and on-state voltage drop, making it difficult to simultaneously meet the requirements of high withstand voltage and low on-state voltage drop.

[0004] To overcome the shortcomings of the NPT structure and meet customers' requirements for high withstand voltage and low on-state voltage drop, the RC-IGBT adopts a field-stop structure. For example... Figure 2 As shown, the field-stop structure, by adding a field-stop layer 6 to the back side of the N-type epitaxial layer 1, can reduce the chip thickness while maintaining high withstand voltage. For example, the chip thickness of a 3000V device can be reduced to approximately 400μm, thereby reducing the on-state voltage drop (Vcesat). Furthermore, adding the field-stop layer has almost no impact on the performance of the reverse FRD.

[0005] However, in actual production, due to limitations in equipment at some cooperating wafer fabs, such as the lack of back-side implantation equipment or the maximum energy of the back-side implantation equipment being only 80keV, which does not meet the requirement of implantation energy >100keV, it is impossible to form a field stop layer by traditional back-side implantation of phosphorus (P) or hydrogen (H). This poses a huge challenge to the implementation of field stop structure RC-IGBTs in these wafer fabs using traditional methods, and a new solution is urgently needed to overcome the limitations of existing technologies. Summary of the Invention

[0006] To address the above technical problems, this invention provides a method for preparing a field stop layer; furthermore, it provides a process monitoring method for preparing the field stop layer; and still more specifically, it provides a method for preparing a semiconductor device.

[0007] The technical problem solved by this invention can be achieved by the following technical solutions: A method for preparing a field cutoff layer, comprising: Step S1, providing a wafer preform, the wafer preform including a gate oxide layer on the upper surface of the epitaxial layer, a polysilicon layer on the upper surface of the gate oxide layer, a body region in the epitaxial layer, and a first implantation region in the body region; Step S2: Apply adhesive to the front side of the wafer preform, flip the wafer preform with the front protective adhesive, and thin the back side of the wafer preform. Step S3: Ion implantation is performed on the back side of the wafer preform using a front-side implantation machine to form a field stop layer; Step S4: Flip the wafer preform over again and remove the protective adhesive on the front side.

[0008] Preferably, the thickness of the wafer preform after thinning is 390μm~410μm.

[0009] Preferably, the injected element of the field stop layer is phosphorus, the injection concentration is 1.0E+12cm-2~3.0E+12cm-2, the injection energy is 120keV~150keV, and after injection, it is sent to the furnace tube for two-step annealing and bonding treatment. The furnace tube temperature for the first step of annealing is 1200℃~1250℃, and the time is 140min~160min; the furnace tube temperature for the second step of annealing is 1150℃~1250℃, and the time is 640min~650min.

[0010] On the other hand, a process monitoring method for the preparation of a field stop layer is also provided, for monitoring the process of the field stop layer preparation method as described above, including: Step A1: Select several wafer preforms; Step A2: Deposit a polysilicon layer or a metal layer on the front side of the wafer preform provided in step S1, and perform a resistance test on the polysilicon layer or metal layer to obtain an initial resistance value. Step A3: Form the field cutoff layer according to the process of steps S2-S4; Step A4: Perform a resistance test on the polysilicon layer or metal layer on the front side of the flipped wafer preform again to obtain a second resistance value; Step A5: Based on the correlation between the initial and second resistance values ​​of the polysilicon layer or metal layer and the temperature change, determine the temperature reflected on the front side of the wafer preform during the annealing process of the field stop layer. Step A6: Based on the determined temperature, simulate and analyze the effects of field stop layer annealing on the junction depth and surface concentration of the front body region, as well as the changing trends of electrical parameters threshold voltage and on-state voltage drop. Based on the target parameter values, deduce the body region injection and annealing process conditions.

[0011] Furthermore, a method for fabricating a semiconductor device is also provided, including the field stop layer fabrication method described above, comprising: Step B1: Prepare wafer preforms; Step B2: Form the field cutoff layer according to the process of steps S2-S4; Step B3: After removing the front protective adhesive, an interlayer dielectric layer is formed on the front side of the wafer preform, a contact hole is formed in the interlayer dielectric layer, and a front metal layer is formed on the surface of the interlayer dielectric layer and in the contact hole. Step B4: A passivation layer is formed on the upper surface of the front metal layer; Step B5: Flip the wafer preform over to form a second implantation region and a third implantation region on the field cutoff layer; Step B6: Form a back metal layer on the back side of the wafer preform.

[0012] Furthermore, a method for fabricating a semiconductor device is also provided, including the field stop layer fabrication method described above, comprising: Step B1: Prepare wafer preforms; Step B2: Form a field cutoff layer according to the process of steps S2-S4, and form a second injection region on the field cutoff layer after step S3 and before step S4; Step B3: After removing the front protective adhesive, an interlayer dielectric layer is formed on the front side of the wafer preform, a contact hole is formed in the interlayer dielectric layer, and a front metal layer is formed on the surface of the interlayer dielectric layer and in the contact hole. Step B4: A passivation layer is formed on the upper surface of the front metal layer; Step B5: Flip the wafer preform over and form a third implantation region on the field cutoff layer; Step B6: Form a back metal layer on the back side of the wafer preform.

[0013] Preferably, step B1 includes: Step B11, provide the epitaxial layer; Step B12: Ion implantation is performed in the epitaxial layer to form a field confinement ring; Step B13: Local oxidation is performed on the upper surface of the epitaxial layer to form an oxide layer; Step B14: A gate oxide layer is grown on the upper surface of the epitaxial layer, a polysilicon layer is deposited on the upper surface of the gate oxide layer, and the gate region is defined by photolithography. Excess gate oxide layer and polysilicon layer are etched away to form the gate structure of the semiconductor device. Step B15: Using the gate structure of the semiconductor device as a barrier layer, ion implantation is performed in the epitaxial layer to form a body region, and ion implantation is performed in the body region to form a first implantation region.

[0014] Preferably, the resistivity of the epitaxial layer is 200 Ω·m to 250 Ω·m, and the thickness is 700 μm; and / or The field-limiting ring is implanted with boron at a concentration of 3.0E+14cm⁻² to 7.0E+14cm⁻², at an energy of 60keV to 80keV, followed by furnace tube annealing at 1200℃ for 200min; and / or The thickness of the oxide layer is 15,000 angstroms to 18,000 angstroms; and / or The thickness of the gate oxide layer is 1000 angstroms to 1500 angstroms; and / or The thickness of the polycrystalline silicon layer is 7000 angstroms to 10000 angstroms; and / or The implanted element in the body region is boron, with an implantation concentration of 3.0E+13cm-2 to 4.0E+13cm-2 and an implantation energy of 50keV to 80keV.

[0015] Preferably, the injected element in the second injection region is phosphorus, the injection energy is 40keV~60keV, and the injection concentration is 3.0E+14cm-2~8.0E+14cm-2; The third injection region is injected with boron, with an injection energy of 20keV~40keV and an injection concentration of 8.0E+12cm-2~3.0E+13cm-2. After injection, laser annealing is performed to activate the injection, with a laser annealing temperature of 1050℃ and a time of 1min.

[0016] Preferably, the withstand voltage of the semiconductor device is not less than 3kV.

[0017] The advantages or beneficial effects of the technical solution of this invention are as follows: The field stop layer of this invention is formed using a front-side injection machine, solving the problem of limited back-side injection P or H machines in wafer fabs, and can meet the requirements of different on-state voltage drops. By using P or H injection to form the field stop layer in the front-end process, production line contamination and serious losses are avoided. At the same time, since there are more thermal processes in the subsequent processes, the injection energy required by the injection machine is smaller, and more machines can be selected, which is more conducive to realizing the field stop layer process. In addition, by using the front-side injection machine in the front-end process to form the field stop layer, there is no need to purchase a back-side injection machine for the subsequent process, which improves the machine utilization rate and reduces the production cost of purchasing machines. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a traditional NPT-structured high-voltage RC-IGBT device in the prior art; Figure 2 This is a schematic diagram of the structure of a traditional field-stop high-voltage RC-IGBT device in the prior art; Figure 3 This is a schematic diagram of the fabrication method of a traditional field-stop high-voltage RC-IGBT device in the prior art; Figure 4 This is a schematic flowchart of the field stop layer preparation method in a preferred embodiment of the present invention; Figure 5 This is a schematic flowchart of a semiconductor device fabrication method in a preferred embodiment of the present invention; Figure 6 This is a schematic flowchart of a semiconductor device fabrication method in another preferred embodiment of the present invention; Figure 7 This is a schematic diagram of the overall process of semiconductor device fabrication method in application example 1 of the present invention; Figures 8a-8h This is a cross-sectional structural diagram of each step in the preparation method in application example 1 of the present invention; Figure 9 This is a schematic diagram of the overall process of the semiconductor device fabrication method in application example 2 of the present invention; Figures 10a-10h This is a cross-sectional structural diagram of each step in the preparation method in application example 2 of the present invention; Figure 11 This is a flowchart illustrating the process monitoring method for the field stop layer fabrication method in a preferred embodiment of the present invention. Figure 12 The graph shows a comparison of the conduction curves of the traditional NPT structure, the field cutoff structure of this invention, and application examples 1 and 2. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0022] Currently, the number of wafer fabs in China capable of manufacturing high-voltage (≥3kV) devices is limited, and most are concentrated in 6-inch wafer production. High-voltage RC-IGBT devices typically employ a non-punch-through (NPT) structure, which is simple to manufacture but has a relatively large on-state voltage drop (Vcesat). To meet the requirement of a low on-state voltage drop (Vcesat), a field-stop structure is needed. Figure 3 As shown, the fabrication method of a traditional field-stop type high-voltage RC-IGBT device includes the following steps: Step 1: Select an N-type epitaxial layer (N-EPI), perform field-limited ring injection, and anneal in a furnace tube; Step 2: Formation of the active region; Step 3: Deposition and etching of gate oxide and polysilicon; Step 4: P-body injection, furnace tube annealing & N+ type first injection zone injection, furnace tube annealing; Step 5: Inter-layer dielectric (ILD) deposition, reflow & contact via (CT) lithography, etching, ionized metal plasma (IMP) & front gate metal layer and emitter metal layer deposition; Step 6: Passivation layer formation: Polyamide (PA) & Polyimide (PI); Step 7: Wafer flipping & backside thinning & P or H injection to form a field stop layer; Step 8: N+ type second injection region injection & P+ type injection region injection & laser annealing; wherein, N+ type second injection region 4 is the cathode of the reverse fast recovery diode (FRD), and P+ type injection region 5 is the collector of the IGBT; Step 9: Deposit the back collector metal layer and flip the wafer to obtain the desired wafer. Figure 2 The field-stop type high-voltage RC-IGBT device shown is shown.

[0023] In traditional fabrication methods, the field stop layer is formed in the back-end process, using a back-side implantation machine. However, due to the lack of complete equipment in some 6-inch wafer fabs, which lack back-side implantation machines, the field stop layer cannot be formed by the traditional back-side implantation of phosphorus (P) or hydrogen (H).

[0024] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a method for preparing a field stoppage layer is provided, such as... Figure 4 As shown, it includes: Step S1, provide wafer preforms, such as Figure 8c As shown, the wafer preform includes a gate oxide layer 102 located on the upper surface of the epitaxial layer 101, a polysilicon layer 103 located on the upper surface of the gate oxide layer 102, a body region 104 located in the epitaxial layer 101, and a first implantation region 105 located in the body region 104. Step S2, as follows Figure 8d As shown, adhesive is applied to the front side of the wafer preform, the wafer preform with front protective adhesive 106 is flipped over, and the back side of the wafer preform is thinned. As an example and not a limitation, the thickness of the wafer preform after thinning is 390μm~410μm; Step S3, as follows Figure 8e As shown, a front-side implantation machine is used to perform ion implantation on the back side of the wafer preform to form a field stop layer 107. As an example and not a limitation, the injected element in the field stop layer 107 is phosphorus, with an injection concentration of 1.0E+12cm-2 to 3.0E+12cm-2 and an injection energy of 120keV to 150keV. After injection, it is sent to the furnace tube for two-step annealing and bonding treatment. The furnace tube temperature for the first step of annealing is 1200℃ to 1250℃, and the time is 140min to 160min. The furnace tube temperature for the second step of annealing is 1150℃ to 1250℃, and the time is 640min to 650min. Step S4: Flip the wafer preform over again and remove the front protective adhesive 106.

[0025] Specifically, in response to the problem that existing technologies are limited by equipment and cannot form a field stop layer using the traditional back-side injection of phosphorus (P) or hydrogen (H) methods, this invention proposes an feasible method for preparing a field stop layer. This method utilizes an existing front-side injection equipment to achieve the field stop layer 107 in the front-end process, thereby forming a field stop structure.

[0026] Examples 2 and 3 below present a method for fabricating a semiconductor device. The resulting semiconductor device is a reverse-conducting IGBT device with a withstand voltage of not less than 3kV. In other words, to address the issues of thick chip thickness and large on-state voltage drop in high-voltage RC-IGBT NPT structures, this invention proposes a method for fabricating high-voltage (≥3kV) RC-IGBT devices. This high-voltage RC-IGBT device employs a field-stop structure to balance withstand voltage and on-state voltage drop.

[0027] The manufacturing process of RC-IGBT devices is divided into front-end and back-end processes. Traditionally, the field stop layer can only be formed in the back-end process, that is, after all the front-end processes are completed, the wafer is flipped and thinned to form the field stop layer on its back side. The process of forming the field stop layer using P-injection after thinning is a back-end process. At this stage, the front-end injection equipment cannot be used to prevent production line contamination and significant losses. Therefore, to use a front-end injection equipment to form the field stop layer, it needs to be completed in the front-end process, which is equivalent to forming the field stop layer before the front-end process is fully completed. The field stop layer is affected by other front-end annealing processes. However, the field stop layer in this invention is formed after the front-end structure is basically completed (remaining ILD + metal layer), thus reducing the impact of front-end annealing. Therefore, the process conditions of the field stop layer in this embodiment are not significantly different from those of traditional field stop layers. To achieve the same performance, this invention only requires fine-tuning of the injection energy and dosage of the field stop layer, and suitable process conditions are determined experimentally.

[0028] Example 1 This invention provides a method for fabricating a semiconductor device, including the field stop layer fabrication method described above, such as... Figure 5 as well as Figures 8a-8h As shown, it includes: Step B1, fabricating a wafer preform; further, step B1 includes: Step B11, providing an epitaxial layer 101; by way of example and not limitation, the resistivity of the epitaxial layer 101 is 200 Ω·m to 250 Ω·m and the thickness is 700 μm; Step B12: Ion implantation is performed in epitaxial layer 101 to form a field-confining ring; by way of example and not limitation, the implanted element of the field-confining ring is boron, the implantation concentration is 3.0E+14cm-2~7.0E+14cm-2, the implantation energy is 60keV~80keV, and after implantation, furnace tube annealing is performed at a temperature of 1200℃ for 200min. Step B13: Local oxidation is performed on the upper surface of the epitaxial layer 101 to form an oxide layer; by way of example and not limitation, the thickness of the oxide layer is 15,000 angstroms to 18,000 angstroms. Step B14: A gate oxide layer 102 is grown on the upper surface of the epitaxial layer 101, a polysilicon layer 103 is deposited on the upper surface of the gate oxide layer 102, and the gate region is defined by photolithography. Excess gate oxide layer 102 and polysilicon layer 103 are etched away to form the gate structure of the semiconductor device. By way of example and not limitation, the thickness of the gate oxide layer 102 is 1000 angstroms to 1500 angstroms; the thickness of the polysilicon layer 103 is 7000 angstroms to 10000 angstroms. Step B15: Using the gate structure of the semiconductor device as a barrier layer, ion implantation is performed in the epitaxial layer to form a body region 104. The implanted element in the body region 104 is boron, the implantation concentration is 3.0E+13cm-2~4.0E+13cm-2, and the implantation energy is 50keV~80keV. Ion implantation is then performed in the body region 104 to form a first implantation region 105.

[0029] Step B2: Form the field cutoff layer 107 according to the process of steps S2-S4; the injection parameters of the field cutoff layer 107 have been described above and will not be repeated here.

[0030] Step B3: After removing the front protective adhesive 106, an interlayer dielectric layer 108 is formed on the front side of the wafer preform, a contact hole is formed in the interlayer dielectric layer 108, and a front metal layer 109 is formed on the surface of the interlayer dielectric layer 108 and in the contact hole. Step B4: A passivation layer is formed on the upper surface of the front metal layer 109; Step B5: Flip the wafer preform and form a second implantation region 110 and a third implantation region 111 on the field stop layer 107. The implantation element in the second implantation region 110 is phosphorus, the implantation energy is 40keV~60keV, and the implantation concentration is 3.0E+14cm-2~8.0E+14cm-2. The implantation element in the third implantation region 111 is boron, the implantation energy is 20keV~40keV, and the implantation concentration is 8.0E+12cm-2~3.0E+13cm-2. After implantation, laser annealing activation is performed at a temperature of 1050℃ for 1 minute. Step B6: Form a back metal layer 112 on the back side of the wafer preform.

[0031] Example 2 This invention provides a method for fabricating a semiconductor device, including the field stop layer fabrication method described above, such as... Figure 6 as well as Figures 10a-10h As shown, it includes: Step B1: Prepare wafer preforms; Step B2: Form the field cutoff layer 107 according to the process of steps S2-S4, and after step S3 and before step S4, form the second injection region 110 on the field cutoff layer 107. Step B3: After removing the front protective adhesive 106, an interlayer dielectric layer 108 is formed on the front side of the wafer preform, a contact hole is formed in the interlayer dielectric layer 108, and a front metal layer 109 is formed on the surface of the interlayer dielectric layer 108 and in the contact hole. Step B4: A passivation layer is formed on the upper surface of the front metal layer 109; Step B5: Flip the wafer preform over and form a third implantation region 111 on the field stop layer 107; Step B6: Form a back metal layer 112 on the back side of the wafer preform.

[0032] Steps B1, B3-B4, and B6 are the same as steps B1, B3-B4, and B6 in Embodiment 2, and will not be repeated here.

[0033] Application Example 1 of the Invention High-voltage RC-IGBT devices were fabricated using the preparation method described in Example 2 above, such as... Figure 7 As shown, its preparation method includes the following steps: C1, such as Figure 8a As shown, based on the electrical performance requirements of the RC-IGBT device, the crystal orientation is selected as... <100> The epitaxial layer 101 (N-EPI) has a resistivity of 200 Ω·m ~ 250 Ω·m and a thickness of approximately 700 μm. P-type ion boron was used to form a field-confining ring on the epitaxial layer 101. The implantation concentration of the field-confining ring was 3.0E+14cm-2~7.0E+14cm-2, and the implantation energy was 60keV~80keV. After implantation, furnace tube annealing was performed at a temperature of about 1200℃ for about 200min. C2. A local oxidation process is performed on the epitaxial layer 101 to achieve local oxidation isolation of LOCOS. The thickness of the oxide layer is approximately 15,000 angstroms to 18,000 angstroms. C3, such as Figure 8b As shown, a gate oxide layer 102 is grown on the epitaxial layer 101, and a polysilicon layer 103 is deposited on it. The thickness of the gate oxide layer 102 is 1000 angstroms to 1500 angstroms, and the thickness of the polysilicon layer 103 is 7000 angstroms to 10000 angstroms. Using a photomask for the gate, the gate region is defined by photolithography, and then excess gate oxide layer 102 and polysilicon layer 103 are removed by etching to form the planar gate of the RC-IGBT. As an example, not a limitation, such as Figure 8b Only a planar gate structure is shown. In fact, in practical applications, it is not limited to this and a trench gate structure can also be used. The trench structure differs from the planar structure in that a trench is first formed on the epitaxial layer 101. The depth of the trench is generally 4μm~6μm. Then, a gate oxide layer 102 is grown and a polysilicon layer 103 is deposited. After the polysilicon layer 103 is etched back, the trench gate of the RC-IGBT cell region is formed.

[0034] C4, such as Figure 8cAs shown, the gate region forming the RC-IGBT cell region serves as a barrier layer, and a P-body region 104 is formed by P-type boron ions. The implantation concentration of the P-body region 104 is 3.0E+13cm-2~4.0E+13cm-2, and the implantation energy is 50keV~80keV. In the P-body region 104 of the RC-IGBT cell region, an N+ ion implantation region is formed by self-aligned photolithography using an N+ photomask. N-type ion implantation is then performed on it to form an N+ type first implantation region 105, which serves as the emitter of the RC-IGBT cell region. C5, such as Figure 8d As shown, adhesive is applied to the front side of the wafer to form a front protective adhesive 106, which protects the front side; the wafer is then flipped over and thinned to 390μm~410μm. C6, such as Figure 8e As shown, an N-type phosphorus ion is implanted on the back side of the wafer to form a field stop layer 107. The implantation concentration of the field stop layer 107 is 1.0E+12cm-2~3.0E+12cm-2, and the implantation energy is 120keV~150keV. After implantation, a two-step furnace tube annealing process is performed. The furnace tube temperature in the first step is 1200℃~1250℃, and the time is 140min~160min. The furnace tube temperature in the second step is 1150℃~1250℃, and the time is 640min~650min. C7. Flip the wafer and remove the protective adhesive 106 from the front side; C8, such as Figure 8f As shown, an interlayer dielectric layer 108 of ILD is deposited, and an emitter metal contact hole is formed using a photomask of the contact hole. The sputtered metal is AlSiCu or AlCu with a thickness of 2.5μm~6μm to form a front metal layer 109, which serves as the emitter metal layer of the RC-IGBT cell region and the anode metal layer of the FRD cell region. C9. Passivation layer formation: PA & PI are deposited, followed by photolithography and etching; C10, such as Figure 8gAs shown, the wafer is flipped over, and N-type phosphorus ion implantation is performed on its back side using an FRD N+ cathode implantation photomask to form an N+ type second implantation region 110, which serves as the FRD N+ cathode. The implantation energy of the N+ type second implantation region 110 is 40keV~60keV, and the implantation concentration is 3.0E+14cm-2~8.0E+14cm-2. The IGBT P+ collector is subjected to general implantation, and P-type boron ion implantation is performed to form a P+ type third implantation region 111, which serves as the IGBT P+ collector. The implantation energy of the P+ type third implantation region 111 is 20keV~40keV, and the implantation concentration is 8.0E+12cm-2~3.0E+13cm-2. After implantation, it is laser annealed for activation. The laser annealing conditions are: laser annealing temperature of 1050℃ and annealing time of 1min. C11, such as Figure 8h As shown, a back metal layer 112 is formed by back gold plating on the back side of the wafer. The back metal composition of the back metal layer 112 is Al / Ti / Ni / Ag.

[0035] Application Example 2 of the Invention High-voltage RC-IGBT devices were fabricated using the preparation method described in Example 3 above, such as... Figure 9 As shown, its preparation method includes the following steps: D1, such as Figure 10a As shown, based on the electrical performance requirements of the RC-IGBT device, the crystal orientation is selected as... <100> The epitaxial layer 101 (N-EPI) has a resistivity of 200 Ω·m to 250 Ω·m and a thickness of approximately 700 μm. P-type ion boron was used to form a field-confining ring on epitaxial layer 101. The implantation concentration of the field-confining ring was 3.0E+14cm-2 to 7.0E+14cm-2, and the implantation energy was 60keV to 80keV. After implantation, furnace tube annealing was performed at a temperature of approximately 1200℃ for approximately 200min. D2. Perform a local oxidation process on the epitaxial layer 101 to achieve local oxidation isolation of LOCOS, with an oxide layer thickness of approximately 15,000 angstroms to 18,000 angstroms. D3, such as Figure 10b As shown, a gate oxide layer 102 is grown on the epitaxial layer 101, and a polysilicon layer 103 is deposited on it. The thickness of the gate oxide layer 102 is 1000 angstroms to 1500 angstroms, and the thickness of the polysilicon layer 103 is 7000 angstroms to 10000 angstroms. Using a photomask for the gate, the gate region is defined by photolithography, and then excess gate oxide layer 102 and polysilicon layer 103 are removed by etching to form the planar gate of the RC-IGBT. As an example, not a limitation, such as Figure 10bOnly a planar grid structure is shown. In fact, in practical applications, it is not limited to this. A trench grid structure can also be used. The difference between the trench grid structure and the planar structure has been described above and will not be repeated here.

[0036] D4, such as Figure 10c As shown, the gate region forming the RC-IGBT cell region serves as a barrier layer, and a P-body region 104 is formed by P-type boron ions. The implantation concentration of the P-body region 104 is 3.0E+13cm-2~4.0E+13cm-2, and the implantation energy is 50keV~80keV. In the P-body region 104 of the RC-IGBT cell region, an N+ ion implantation region is formed by self-aligned photolithography using an N+ photomask. N-type ion implantation is then performed on it to form an N+ type first implantation region 105, which serves as the emitter of the RC-IGBT cell region. D5, such as Figure 10d As shown, adhesive is applied to the front side of the wafer to form a front protective adhesive 106, which protects the front side; the wafer is then flipped over and thinned to 390μm~410μm. D6, such as Figure 10e As shown, an N-type phosphorus ion is implanted on the back side of the wafer to form a field stop layer 107. The implantation concentration of the field stop layer 107 is 1.0E+12cm-2~3.0E+12cm-2, and the implantation energy is 120keV~150keV. After implantation, a two-step furnace tube annealing process is performed. The furnace tube temperature in the first step is 1200℃~1250℃, and the time is 140min~160min. The furnace tube temperature in the second step is 1150℃~1250℃, and the time is 640min~650min. D7. Using an FRD N+ cathode implantation photomask, N-type phosphorus ions are implanted onto its back side to form an N+ type second implantation region 110, which serves as the FRD N+ cathode. The implantation energy of the N+ type second implantation region 110 is 40keV~60keV, and the implantation concentration is 3.0E+14cm-2~8.0 E+14 cm-2. D8. Flip the wafer over and remove the protective adhesive 106 from the front side; D9, such as Figure 10f As shown, an interlayer dielectric layer 108 of ILD is deposited, and an emitter metal contact hole is formed using a photomask of the contact hole. The sputtered metal is AlSiCu or AlCu with a thickness of 2.5μm~6μm to form a front metal layer 109, which serves as the emitter metal layer of the RC-IGBT cell region and the anode metal layer of the FRD cell region. D10, Passivation layer formation: PA & PI are deposited, followed by photolithography and etching; D11, such as Figure 10gAs shown, the wafer is flipped over, and the IGBT P+ collector is implanted with P-type boron ions to form the P+ type third implantation region 111, which serves as the IGBT P+ collector. The implantation energy of the P+ type third implantation region 111 is 20keV~40keV, and the implantation concentration is 8.0E+12cm-2~3.0E+13cm-2. After implantation, it is laser annealed and activated. The laser annealing conditions are: laser annealing temperature of 1050℃ and annealing time of 1min. D12, such as Figure 10h As shown, a back metal layer 112 is formed by back gold plating on the back side of the wafer. The back metal composition of the back metal layer 112 is Al / Ti / Ni / Ag.

[0037] In both Application Example 1 and Application Example 2, the field cutoff layer 107 implantation process of the RC-IGBT devices is completed in the front-end process. Unlike Application Example 1, the FRD N+ cathode phosphorus implantation process in Application Example 2 is completed in the front-end process, while the FRD N+ cathode phosphorus implantation process in the RC-IGBT device in Application Example 1 is completed in the back-end process.

[0038] Since the field cutoff layer was formed after the P-body region 104 of the front structure of the RC-IGBT device was completed in both Application Example 1 and Application Example 2, the high-temperature annealing of the furnace tube after the field cutoff layer injection will cause changes in the junction depth and surface concentration of the P-body, which will affect the electrical parameters of the RC-IGBT device. The main parameters affected are the threshold voltage Vth and the on-state voltage drop Vcesat.

[0039] To avoid the impact of this process on the electrical parameters of RC-IGBT devices, this invention provides a process monitoring method for the preparation of a field cutoff layer, used in the process of the field cutoff layer preparation method described above, to monitor the impact of the high-temperature furnace tube annealing process of the back field cutoff layer on the front structure.

[0040] like Figure 11 As shown, the process monitoring methods include: Step A1: Select several wafer preforms; Step A2: Deposit a polysilicon layer or a metal layer on the front side of the wafer preform provided in step S1, and perform a resistance test on the polysilicon layer or metal layer to obtain an initial resistance value. Step A3: Form the field cutoff layer according to the process of steps S2-S4; Step A4: Perform a resistance test on the polysilicon layer or metal layer on the front side of the flipped wafer preform again to obtain a second resistance value. Step A5: Based on the correlation between the initial and second resistance values ​​of the polysilicon layer or metal layer and the temperature change, determine the temperature reflected on the front side of the wafer preform during the annealing process of the field stop layer. Step A6: Based on the determined temperature, simulate and analyze the effects of field stop layer annealing on the junction depth and surface concentration of the front body region, as well as the changing trends of electrical parameters threshold voltage and on-state voltage drop. Based on the target parameter values, deduce the body region injection and annealing process conditions.

[0041] Specifically, N experimental wafers with identical processes are selected. After completing the C4 or D4 steps described above, a layer of polysilicon or metal is deposited on the front side of the wafer, and the initial resistance of the polysilicon or metal is tested. The wafer is then flipped over, and the field stop layer is implanted and annealed on its back side. After the field stop layer process is completed, the wafer is flipped over again, and the resistance of the polysilicon or metal on the front side is tested again. Based on the empirical values ​​of the resistance of the polysilicon or metal changing with temperature, the actual temperature reflected on the front side of the wafer by the high-temperature furnace tube annealing of the field stop layer can be determined. The obtained front side temperature is used to simulate the effect of the high-temperature furnace tube annealing of the field stop layer on the junction depth and surface concentration of the front P-body region 104, as well as the changing trends of the electrical parameters threshold voltage Vth and on-state voltage drop Vcesat. Based on the target values ​​of the parameters, combined with empirical values ​​or simulation results, the conditions for P-body region 104 implantation and furnace tube annealing are deduced.

[0042] The difference between Application Example 1 and Application Example 2 lies in the location of the FRD N+ cathode phosphorus implantation process in the RC-IGBT device. In Application Example 1, the FRD N+ cathode phosphorus implantation process in the RC-IGBT device is completed in the later stages of the process. After implantation, only laser annealing is performed. Laser annealing only activates the charge carriers and has little effect on junction pushing. Therefore, the junction of the FRD N+ cathode in the RC-IGBT device is very shallow and has a high surface concentration.

[0043] In Application Example 2, the FRD N+ cathode implantation process in the RC-IGBT device is completed in the front-end process. After implantation, it undergoes furnace tube annealing after P-body implantation, reflow furnace tube after ILD deposition, and alloy after metal deposition. The furnace tube annealing temperature is relatively high, which pushes the junction of the FRD N+ cathode in the RC-IGBT device deeper, resulting in a deeper junction and lower surface concentration. This has a smaller impact on the concentration of boron implantation at the IGBT P+ collector in the RC-IGBT device. Therefore, the on-state voltage drop of the RC-IGBT device in Application Example 2 is smaller than that of the RC-IGBT in Application Example 1.

[0044] The comparison graphs of the conduction curves of the RC-IGBT devices in Application Example 1 and Application Example 2 are shown below. Figure 12As shown, the on-state voltage drop of the field-stop RC-IGBT devices in Application Examples 1 and 2 is smaller than that of the NPT RC-IGBT devices. Furthermore, under low currents ≤30A, the on-state voltage drops of the field-stop RC-IGBT devices in Application Examples 1 and 2 are essentially the same; however, under high currents >30A, the on-state voltage drop of Application Example 2 is smaller than that of Application Example 1. In summary, a suitable fabrication process can be selected based on the required on-state voltage drop (Vcesat).

[0045] The advantages or beneficial effects of adopting the above technical solution are as follows: Compared to NPT structure RC-IGBT devices, the field-stop structure RC-IGBT device proposed in this invention has a relatively small on-state voltage drop Vcesat while ensuring sufficient withstand voltage.

[0046] Compared with the fabrication process of traditional field-stop RC-IGBT devices, this invention solves the problem of limited P or H injection equipment on the back side of the wafer fab, and has multiple implementation methods to meet the requirements of different on-state voltage drops (Vcesat). At the same time, through process monitoring, a suitable process fabrication flow can be selected according to the parameter requirements of the on-state voltage drop (Vcesat), and the injection position of the FRDN+ cathode can be adjusted to adjust the on-state voltage drop (Vcesat) to meet the needs of different applications.

[0047] In the front-end process, the field cutoff layer is formed by injecting P or H. Due to the large number of thermal processes in the subsequent processes, compared with the traditional field cutoff RC-IGBT device fabrication process, the injection energy of the injection equipment is smaller, more equipment can be selected, and it is more conducive to realizing the field cutoff layer fabrication process.

[0048] This invention utilizes a front-side injection machine in the front-end process to form a field stop layer, eliminating the need to purchase a back-side injection machine in the back-end process, thereby increasing machine utilization and reducing the production cost of purchasing machines.

[0049] The method of this invention is mainly applied to high-voltage RC-IGBT devices. The structure of the power RC-IGBT device is not limited to the structure mentioned in this invention; it can also be a superjunction IGBT, etc. The gate structure used in the device of this invention can be a planar gate structure, but is not limited to a planar gate structure; a trench gate structure can also be used.

[0050] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A method for preparing a field stop layer, characterized in that, include: Step S1, providing a wafer preform, the wafer preform including a gate oxide layer on the upper surface of the epitaxial layer, a polysilicon layer on the upper surface of the gate oxide layer, a body region in the epitaxial layer, and a first implantation region in the body region; Step S2: Apply adhesive to the front side of the wafer preform, flip the wafer preform with the front protective adhesive, and thin the back side of the wafer preform. Step S3: Ion implantation is performed on the back side of the wafer preform using a front-side implantation machine to form a field stop layer; Step S4: Flip the wafer preform over again and remove the protective adhesive on the front side.

2. The method for preparing the field stop layer according to claim 1, characterized in that, The thickness of the wafer preform after thinning is 390μm~410μm.

3. The method for preparing the field stoppage layer according to claim 1, characterized in that, The injected element in the field stop layer is phosphorus, with an injection concentration of 1.0E+12cm-2 to 3.0E+12cm-2 and an injection energy of 120keV to 150keV. After injection, it is sent to a furnace tube for two-step annealing and bonding treatment. The furnace tube temperature for the first step of annealing is 1200℃ to 1250℃, and the time is 140min to 160min. The furnace tube temperature for the second step of annealing is 1150℃ to 1250℃, and the time is 640min to 650min.

4. A process monitoring method for preparing a field stop layer, characterized in that, For monitoring the process of the field stop layer preparation method as described in any one of claims 1-3, including: Step A1: Select several wafer preforms; Step A2: Deposit a polysilicon layer or a metal layer on the front side of the wafer preform provided in step S1, and perform a resistance test on the polysilicon layer or metal layer to obtain an initial resistance value. Step A3: Form the field cutoff layer according to the process of steps S2-S4; Step A4: Perform a resistance test on the polysilicon layer or metal layer on the front side of the flipped wafer preform again to obtain a second resistance value; Step A5: Based on the correlation between the initial and second resistance values ​​of the polysilicon layer or metal layer and the temperature change, determine the temperature reflected on the front side of the wafer preform during the annealing process of the field stop layer. Step A6: Based on the determined temperature, simulate and analyze the effects of field stop layer annealing on the junction depth and surface concentration of the front body region, as well as the changing trends of electrical parameters threshold voltage and on-state voltage drop. Based on the target parameter values, deduce the body region injection and annealing process conditions.

5. A method for fabricating a semiconductor device, characterized in that, The method for preparing a field stop layer as described in any one of claims 1-3 includes: Step B1: Prepare wafer preforms; Step B2: Form the field cutoff layer according to the process of steps S2-S4; Step B3: After removing the front protective adhesive, an interlayer dielectric layer is formed on the front side of the wafer preform, a contact hole is formed in the interlayer dielectric layer, and a front metal layer is formed on the surface of the interlayer dielectric layer and in the contact hole. Step B4: A passivation layer is formed on the upper surface of the front metal layer; Step B5: Flip the wafer preform over to form a second implantation region and a third implantation region on the field cutoff layer; Step B6: Form a back metal layer on the back side of the wafer preform.

6. A method for fabricating a semiconductor device, characterized in that, The method for preparing a field stop layer as described in any one of claims 1-3 includes: Step B1: Prepare wafer preforms; Step B2: Form a field cutoff layer according to the process of steps S2-S4, and form a second injection region on the field cutoff layer after step S3 and before step S4; Step B3: After removing the front protective adhesive, an interlayer dielectric layer is formed on the front side of the wafer preform, a contact hole is formed in the interlayer dielectric layer, and a front metal layer is formed on the surface of the interlayer dielectric layer and in the contact hole. Step B4: A passivation layer is formed on the upper surface of the front metal layer; Step B5: Flip the wafer preform over and form a third implantation region on the field cutoff layer; Step B6: Form a back metal layer on the back side of the wafer preform.

7. The method for fabricating a semiconductor device according to claim 5 or 6, characterized in that, Step B1 includes: Step B11, provide the epitaxial layer; Step B12: Ion implantation is performed in the epitaxial layer to form a field confinement ring; Step B13: Local oxidation is performed on the upper surface of the epitaxial layer to form an oxide layer; Step B14: A gate oxide layer is grown on the upper surface of the epitaxial layer, a polysilicon layer is deposited on the upper surface of the gate oxide layer, and the gate region is defined by photolithography. Excess gate oxide layer and polysilicon layer are etched away to form the gate structure of the semiconductor device. Step B15: Using the gate structure of the semiconductor device as a barrier layer, ion implantation is performed in the epitaxial layer to form a body region, and ion implantation is performed in the body region to form a first implantation region.

8. The semiconductor device fabrication method according to claim 7, characterized in that, The resistivity of the epitaxial layer is 200 Ω·m ~ 250 Ω·m, and the thickness is 700 μm; and / or The field-limiting ring is implanted with boron at a concentration of 3.0E+14cm⁻² to 7.0E+14cm⁻², at an energy of 60keV to 80keV, followed by furnace tube annealing at 1200℃ for 200min; and / or The thickness of the oxide layer is 15,000 angstroms to 18,000 angstroms; and / or The thickness of the gate oxide layer is 1000 angstroms to 1500 angstroms; and / or The thickness of the polycrystalline silicon layer is 7000 angstroms to 10000 angstroms; and / or The implanted element in the body region is boron, with an implantation concentration of 3.0E+13cm-2 to 4.0E+13cm-2 and an implantation energy of 50keV to 80keV.

9. The method for fabricating a semiconductor device according to claim 5 or 6, characterized in that, The second injection region is injected with phosphorus, the injection energy is 40keV~60keV, and the injection concentration is 3.0E+14cm-2~8.0E+14cm-2; The third injection region is injected with boron, with an injection energy of 20keV~40keV and an injection concentration of 8.0E+12cm-2~3.0E+13cm-2. After injection, laser annealing is performed to activate the injection, with a laser annealing temperature of 1050℃ and a time of 1min.

10. The method for fabricating a semiconductor device according to claim 5 or 6, characterized in that, The withstand voltage of the semiconductor device is not less than 3kV.

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