Semiconductor device and display device including the same

Abstract

The invention relates to a semiconductor device and a display device including the same. The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. The semiconductor device includes a transistor having an oxide semiconductor film. The transistor includes a region in which the maximum value of the field-effect mobility of the transistor having a gate voltage higher than 0 V and not more than 10 V is 40 or more and less than 150. A region in which the threshold voltage is from-1 V to 1 V (inclusive); and a region in which the S value is less than 0.3 V / decade.

Description

[0001] This divisional application is a divisional application based on the Chinese patent application with application number 201780018390.7, application date March 14, 2017, and invention name “Semiconductor device and display device including the semiconductor device”. More specifically, this divisional application is a further divisional application based on the Chinese patent application with application number 202210902715.0, application date March 14, 2017, and invention name “Semiconductor device and display device including the semiconductor device”. Technical Field

[0002] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device.

[0003] Note that an embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of an embodiment of the invention disclosed in this specification, etc. relates to an object, method or manufacturing method. The present invention relates to a process, machine, product or composition of matter. An embodiment of the present invention particularly relates to an oxide semiconductor or a method for manufacturing the oxide semiconductor. An embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof and a manufacturing method thereof.

[0004] In this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are all embodiments of semiconductor devices. Camera devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells or organic thin-film solar cells, etc.), and electronic devices may include semiconductor devices. Background Art

[0005] The technology of forming a transistor (also called a field effect transistor (FET) or a thin film transistor (TFT)) by using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) or image display devices (display devices). As materials that can be applied to semiconductor thin films of transistors, semiconductor materials represented by silicon are well known. As other materials, oxide semiconductors have attracted attention. For example, a technology for manufacturing transistors using In-Ga-Zn-based oxide semiconductors has been disclosed (see Patent Document 1).

[0006] In addition, a method for achieving high field effect mobility (sometimes referred to as mobility or μ) having the following structure is disclosed.FE ) in which a plurality of oxide semiconductor layers are stacked, an oxide semiconductor layer used as a channel among the plurality of oxide semiconductor layers contains indium and gallium, and the ratio of indium is higher than the ratio of gallium (see Patent Document 1).

[0007] Non-patent document 1 discloses that 1-x Ga 1+x O 3 (ZnO) m (-1≤x≤1, and m is a natural number). In addition, non-patent document 1 discloses the solid solution range of the homologous phase. For example, the solid solution range of the homologous phase in the case of m=1 is in the range of x being -0.33 to 0.08, and the solid solution range of the homologous phase in the case of m=2 is in the range of x being -0.68 to 0.32.

[0008] [References]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2007-96055

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2014-007399

[0012] [Non-patent literature]

[0013] [Non-patent document 1] M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the 2 O 3 -Ga 2 ZnO 4 -ZnO System at 1350℃", J.Solid State Chem., 1991, Vol.93, pp.298-315 Summary of the invention

[0014] The higher the field effect mobility of a transistor using an oxide semiconductor film for the channel region, the better. However, when the field effect mobility of a transistor is increased, the transistor has a problem that its characteristics tend to be normally-on characteristics. Note that "normally-on characteristics" refers to a state in which a channel exists even when no voltage is applied to the gate electrode, and current flows through the transistor.

[0015] In addition, in a transistor using an oxide semiconductor film for a channel region, oxygen vacancies formed in the oxide semiconductor film have a negative impact on transistor characteristics. For example, oxygen vacancies formed in the oxide semiconductor film bond with hydrogen to become a carrier supply source. The carrier supply source formed in the oxide semiconductor film causes a change in the electrical characteristics of the transistor including the oxide semiconductor film, typically causing a drift in the threshold voltage.

[0016] For example, when the amount of oxygen vacancies in the oxide semiconductor film is too much, the threshold voltage of the transistor drifts in the negative direction and the transistor has a normally-on characteristic. Therefore, especially in the channel region of the oxide semiconductor film, the amount of oxygen vacancies is preferably small, or the amount of oxygen vacancies is preferably such that the transistor does not exhibit a normally-on characteristic.

[0017] In addition, Non-Patent Document 1 discloses In x Zn y Ga z O w For example, and in x, y and z to obtain ZnGa 2 O 4 When x, y and z are close to 0, 1 and 2 respectively, a spinel type crystal structure is easily formed or mixed. As compounds having a spinel type crystal structure, there are known compounds with AB 2 O 4 (A and B are metals).

[0018] However, when a spinel crystal structure is formed in or mixed in an In-Ga-Zn-based oxide semiconductor, the electrical characteristics or reliability of a semiconductor device (e.g., a transistor) including the In-Ga-Zn-based oxide semiconductor may be adversely affected by the spinel crystal structure.

[0019] In view of the above problems, one of the purposes of one embodiment of the present invention is to improve the field effect mobility and reliability of a transistor including an oxide semiconductor film. One of the purposes of one embodiment of the present invention is to prevent the electrical characteristics of a transistor including an oxide semiconductor film from changing and to improve the reliability of the transistor. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with low power consumption. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. One of the purposes of one embodiment of the present invention is to provide a novel oxide semiconductor. One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. One of the purposes of one embodiment of the present invention is to provide a novel display device.

[0020] Note that the description of the above-mentioned objects does not prevent the existence of other objects. One embodiment of the present invention does not need to achieve all of the above-mentioned objects. Objects other than the above-mentioned objects are obvious from the description of the specification, etc., and can be extracted from the description of the specification, etc.

[0021] One embodiment of the present invention is a semiconductor device including a transistor, the transistor including an insulating film, a first conductive film, a second conductive film, a third conductive film and an oxide semiconductor film. The first conductive film includes a region in contact with the oxide semiconductor film. The second conductive film includes a region in contact with the oxide semiconductor film. The third conductive film includes a region sandwiching the insulating film and overlapping the oxide semiconductor film. The transistor includes a field effect mobility of the transistor having a maximum value of 40 cm when the gate voltage is greater than 0 V and less than 10 V. 2 / Vs or more and less than 150cm 2 / Vs, the threshold voltage is between -1V and 1V, the S value is less than 0.3V / decade, and the off-state current is less than 1×10 -12 A / cm 2 In the area of ​​μ FE (max) represents the maximum value of the field effect mobility of the transistor and μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is greater than or equal to 1 and less than 1.5.

[0022] One embodiment of the present invention is a semiconductor device including a transistor, the transistor including a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, an oxide semiconductor film, and a third insulating film on the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. The transistor includes a gate voltage greater than 0V and less than 10V. The maximum field effect mobility of the transistor is 40cm 2 / Vs or more and less than 150cm 2 / Vs, the threshold voltage is between -1V and 1V, the S value is less than 0.3V / decade, and the off-state current is less than 1×10 -12 A / cm 2 In the area of ​​μ FE (max) represents the maximum value of the field effect mobility of the transistor and μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μFE (max) / μ FE (Vg=2V) is greater than or equal to 1 and less than 1.5.

[0023] In the above embodiment, it is preferable that the oxide semiconductor film includes a shallow defect state density of less than 1.0×10 - 12 cm -2 area.

[0024] One embodiment of the present invention is a semiconductor device including a transistor, the transistor including an insulating film, a first conductive film, a second conductive film, a third conductive film and an oxide semiconductor film. The first conductive film includes a region in contact with the oxide semiconductor film. The second conductive film includes a region in contact with the oxide semiconductor film. The third conductive film includes a region sandwiching the insulating film and overlapping the oxide semiconductor film. The transistor includes a gate voltage greater than 0V and less than 10V. The maximum field effect mobility of the transistor is 40cm 2 / Vs or more and less than 150cm 2 / Vs, the threshold voltage is between -1V and 1V, the S value is less than 0.3V / decade, and the off-state current is less than 1×10 -12 A / cm 2 In the area of ​​μ FE (max) represents the maximum value of the field effect mobility of the transistor and μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is 1.5 or more and less than 3.

[0025] One embodiment of the present invention is a semiconductor device including a transistor, the transistor including a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, an oxide semiconductor film, and a third insulating film on the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. The transistor includes a gate voltage greater than 0V and less than 10V. The maximum field effect mobility of the transistor is 40cm 2 / Vs or more and less than 150cm 2 / Vs, the threshold voltage is between -1V and 1V, the S value is less than 0.3V / decade, and the off-state current is less than 1×10 -12 A / cm 2 In the area of ​​μ FE(max) represents the maximum value of the field effect mobility of the transistor and μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is 1.5 or more and less than 3.

[0026] In the above embodiment, it is preferred that the oxide semiconductor film includes a shallow defect state density of 1.0×10 - 12 cm -2 Above and below 2.0×10 -12 cm -2 area.

[0027] One embodiment of the present invention is a semiconductor device including a transistor, the transistor including an insulating film, a first conductive film, a second conductive film, a third conductive film and an oxide semiconductor film. The first conductive film includes a region in contact with the oxide semiconductor film. The second conductive film includes a region in contact with the oxide semiconductor film. The third conductive film includes a region sandwiching the insulating film and overlapping the oxide semiconductor film. The transistor includes a field effect mobility of the transistor having a maximum value of 10 cm when the gate voltage is greater than 0 V and less than 10 V. 2 / Vs or more and less than 100cm 2 / Vs, the threshold voltage is between -1V and 1V, the S value is less than 0.3V / decade, and the off-state current is less than 1×10 -12 A / cm 2 In the area of ​​μ FE (max) represents the maximum value of the field effect mobility of the transistor and μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is 3 or more and less than 10.

[0028] One embodiment of the present invention is a semiconductor device including a transistor, the transistor including a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, an oxide semiconductor film, and a third insulating film on the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. The transistor includes a gate voltage greater than 0V and less than 10V. The maximum value of the field effect mobility of the transistor is 10cm 2 / Vs or more and less than 100cm 2 / Vs, the threshold voltage is between -1V and 1V, the S value is less than 0.3V / decade, and the off-state current is less than 1×10 -12 A / cm 2 In the region of μFE(max), μFE(max) represents the maximum value of the field effect mobility of the transistor and μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is 3 or more and less than 10.

[0029] In the above embodiment, it is preferred that the oxide semiconductor film includes a shallow defect state density of 2.0×10 - 12 cm -2 Above and below 3.0×10 -12 cm -2 area.

[0030] In the above embodiment, preferably, the oxide semiconductor film includes a composite oxide semiconductor in which a first region and a second region are mixed together, the first region includes a plurality of first clusters having one or more selected from indium, zinc and oxygen as main components, the second region includes a plurality of second clusters having one or more selected from indium, element M, zinc and oxygen as main components, M is Al, Ga, Y or Sn, the first region includes portions in which the plurality of first clusters are connected to each other, and the second region includes portions in which the plurality of second clusters are connected to each other.

[0031] In the above embodiment, preferably, the atomic number ratio of indium, element M and zinc is In:M:Zn=4:2:3 or about 4:2:3, when In is 4, element M is 1.5 or more and 2.5 or less, and Zn is 2 or more and 4 or less. In the above embodiment, preferably, the atomic number ratio of indium, element M and zinc is In:M:Zn=5:1:6 or about 5:1:6, when In is 5, element M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less.

[0032] In the above embodiment, it is preferred that the first cluster has electrical conductivity and the second cluster has electrical semiconductivity.

[0033] In the above embodiment, preferably, each of the first clusters includes a portion of 0.5 nm or more and 1.5 nm or less.

[0034] One embodiment of the present invention is a display device, which includes a semiconductor device and a display element in any of the above embodiments. One embodiment of the present invention is a display module, which includes a display device and a touch sensor. One embodiment of the present invention is an electronic device, which includes a semiconductor device, a display device or a display module in any of the above embodiments, and an operation key or a battery. One embodiment of the present invention is an electronic device, which includes a semiconductor device, an inverter or a converter in any of the above embodiments.

[0035] An embodiment of the present invention can improve the field effect mobility and reliability of a transistor including an oxide semiconductor film. An embodiment of the present invention can prevent the electrical characteristics of a transistor including an oxide semiconductor film from changing and improve the reliability of the transistor. An embodiment of the present invention can provide a semiconductor device with low power consumption. An embodiment of the present invention can provide a semiconductor device with good electrical characteristics. An embodiment of the present invention can provide a novel oxide semiconductor. An embodiment of the present invention can provide a novel semiconductor device. An embodiment of the present invention can provide a novel display device.

[0036] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not need to achieve all of the above effects. Other effects are obvious from the description of the specification, drawings, claims, etc., and can be extracted from the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The Id-Vg characteristics of the transistor are shown.

[0038] Figure 2 The Id-Vg characteristics of the transistor are shown.

[0039] Figure 3 The Id-Vg characteristics of the transistor are shown.

[0040] Figure 4A and Figure 4B 1 and 2 are schematic top plan views and schematic cross-sectional views illustrating a complex oxide semiconductor.

[0041] Figure 5A and Figure 5B 1 and 2 are schematic top plan views and schematic cross-sectional views illustrating a complex oxide semiconductor.

[0042] Fig. 6A and Figure 6B 1 and 2 are schematic top plan views and schematic cross-sectional views illustrating a complex oxide semiconductor.

[0043] Fig. 7A and Figure 7B 1 and 2 are schematic top plan views and schematic cross-sectional views illustrating a complex oxide semiconductor.

[0044] Figure 8 The atomic ratio of the oxide semiconductor is described.

[0045] Fig.9A and Fig. 9B A sputtering apparatus will be described.

[0046] Fig.10 1 is a process flow chart showing a method for manufacturing a complex oxide semiconductor.

[0047] Fig.11A and Fig. 11B A cross section near the target is shown.

[0048] Fig. 12A and Fig. 12B A cross section near the target is shown.

[0049] Fig.13 HAADF-STEM observation results are shown.

[0050] Fig.14A and Fig. 14B The Id-Vg characteristics and Id-Vd characteristics of the transistor are shown.

[0051] Fig.15 The Id-Vg characteristics calculated by GCA and the linear and saturation mobility curves are shown.

[0052] Fig.16 The Id-Vg characteristics and field-effect mobility curve of the FET including the CAAC-OS are shown.

[0053] Fig.17A is a top view of the transistor, and Fig. 17B and Fig. 17C is a cross-sectional view of a transistor.

[0054] Fig.18 A schematic diagram illustrating the concept of the effective channel length of a transistor.

[0055] FIG. 19A to FIG. 19C Each is a schematic diagram illustrating the donor density.

[0056] Fig. 20 Id-Vg characteristics are shown.

[0057] Fig.21 Id-Vg characteristics are shown.

[0058] Fig. 22 The calculation results of the interface state density are shown.

[0059] Fig.23A and Fig. 23B Id-Vg characteristics are shown.

[0060] Fig.24 The shape of the mobility curve is shown.

[0061] Fig.25 It is a schematic diagram showing the contribution of drift current and diffusion current to Id-Vg characteristics.

[0062] Fig.26 The Id-Vg characteristics and mobility curves of BGTC-type dual-gate structure FETs each including CAAC-OS when sDOS is not assumed are shown.

[0063] Fig. 27 is the band diagram in the thickness direction.

[0064] Fig.28 The Id-Vg characteristics and mobility curves of BGTC-type dual-gate FETs each including CAAC-OS when sDOS is assumed are shown.

[0065] Fig.29 The dependence of the field effect mobility (maximum value) on the IGZO film thickness is shown.

[0066] Fig. 30A and Fig. 30B It is a graph explaining the shape of the sDOS distribution and the mobility curve in the IGZO film.

[0067] Fig.31A is a circuit diagram illustrating resistors and FETs, and Fig.31B Graph showing the relationship between field effect mobility and source and drain regions formed by reducing the resistance of the channel region.

[0068] Fig.32 : is a graph illustrating the saturation mobility when the mobility depends on the temperature.

[0069] Fig.33 The saturation mobility curve of the FET is shown.

[0070] Fig.34 This is a graph illustrating the effect of reduction of the effective channel length on the shape of the mobility curve.

[0071] FIG. 35A to FIG. 35C Mobility curves obtained by device simulation under different conditions are shown.

[0072] Fig.36A and Fig.36B It is a cross-sectional view illustrating a semiconductor device.

[0073] Fig.37A and Fig.37BIt is a cross-sectional view illustrating a semiconductor device.

[0074] Fig.38A and Fig.38B It is a cross-sectional view illustrating a semiconductor device.

[0075] Fig.39A and Fig.39B It is a cross-sectional view illustrating a semiconductor device.

[0076] Fig.40A and Fig.40B It is a cross-sectional view illustrating a semiconductor device.

[0077] Fig.41A and Fig.41B It is a cross-sectional view illustrating a semiconductor device.

[0078] Fig.42A and Fig.42B It is a cross-sectional view illustrating a semiconductor device.

[0079] Fig.43A and Fig.43B It is a cross-sectional view illustrating a semiconductor device.

[0080] FIG. 44A to FIG. 44C The band structure is shown.

[0081] FIG. 45A to FIG. 45C 1 and 2 are a plan view and a cross-sectional view for explaining a semiconductor device.

[0082] FIG. 46A to FIG. 46C 1 and 2 are a plan view and a cross-sectional view for explaining a semiconductor device.

[0083] FIG. 47A to FIG. 47C 1 and 2 are a plan view and a cross-sectional view for explaining a semiconductor device.

[0084] FIG. 48A to FIG. 48C 1 and 2 are a plan view and a cross-sectional view for explaining a semiconductor device.

[0085] Fig.49A and Fig.49B It is a cross-sectional view illustrating a semiconductor device.

[0086] Fig.50A and Fig.50B It is a cross-sectional view illustrating a semiconductor device.

[0087] FIG. 51A to FIG. 51C 1 and 2 are a plan view and a cross-sectional view for explaining a semiconductor device.

[0088] Fig.52 It is a top view illustrating one embodiment of a display device.

[0089] Fig.53 It is a cross-sectional view illustrating one embodiment of a display device.

[0090] Fig.54 It is a cross-sectional view illustrating one embodiment of a display device.

[0091] Fig.55 It is a cross-sectional view illustrating one embodiment of a display device.

[0092] Fig.56 It is a cross-sectional view illustrating one embodiment of a display device.

[0093] Fig.57 It is a cross-sectional view illustrating one embodiment of a display device.

[0094] FIG. 58A to FIG. 58D It is a cross-sectional view for explaining the method of forming the EL layer.

[0095] Fig.59 Schematic diagram for explaining a liquid droplet ejecting device.

[0096] FIG. 60A to FIG. 60C It is a block diagram and a circuit diagram explaining a display device.

[0097] Fig.61 Description Display module.

[0098] Figures 62A to 62E Description of electronic device.

[0099] Figures 63A to 63G Description of electronic device.

[0100] Figures 64A to 64E Description of electronic device.

[0101] Fig.65A and Fig.65B It is a perspective view for explaining the display device.

[0102] Fig.66A and Fig.66B It is a perspective view for explaining the display device.

[0103] Fig.67A and Fig.67B Each is a circuit diagram of a semiconductor device according to an embodiment.

[0104] Fig.68 It is a diagram illustrating a cross-sectional structure of a semiconductor device according to an embodiment.

[0105] Fig.69 It is a diagram illustrating a cross-sectional structure of a semiconductor device according to an embodiment.

[0106] Fig.70 This is a circuit diagram illustrating a storage device according to one embodiment of the present invention.

[0107] Fig.71This is a circuit diagram illustrating a storage device according to one embodiment of the present invention.

[0108] FIG. 72A to FIG. 72C 1 is a circuit diagram and a timing diagram illustrating one embodiment of the present invention.

[0109] FIG. 73A to FIG. 73C It is a chart and a circuit diagram which illustrate one embodiment of the present invention.

[0110] Fig.74A and Fig.74B 1 is a circuit diagram and a timing diagram illustrating one embodiment of the present invention.

[0111] Fig.75A and Fig.75B 1 is a circuit diagram and a timing diagram illustrating one embodiment of the present invention.

[0112] Figures 76A to 76E It is a block diagram, a circuit diagram, and a waveform diagram for explaining one embodiment of the present invention.

[0113] Fig.77A and Fig.77B 1 is a circuit diagram and a timing diagram illustrating one embodiment of the present invention.

[0114] Fig.78A and Fig.78B Each is a circuit diagram for explaining one embodiment of the present invention.

[0115] Figures 79A to 79C Each is a circuit diagram for explaining one embodiment of the present invention.

[0116] Fig.80A and Fig.80B Each is a circuit diagram for explaining one embodiment of the present invention.

[0117] Figures 81A to 81C Each is a circuit diagram for explaining one embodiment of the present invention.

[0118] Fig.82A and Fig.82B Each is a circuit diagram for explaining one embodiment of the present invention.

[0119] Fig.83 This is a block diagram illustrating a semiconductor device according to one embodiment of the present invention.

[0120] Fig.84 This is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention.

[0121] Fig.85A and Fig.85B It is a top view illustrating a semiconductor device according to one embodiment of the present invention.

[0122] Fig.86A and Fig.86B It is a flowchart and a perspective view of a semiconductor device for explaining one embodiment of the present invention.

[0123] Figures 87A to 87C It is a perspective view illustrating an electronic device according to an embodiment of the present invention.

[0124] Figures 88A to 88E A planar HAADF-STEM image and an EDX surface analysis image are shown.

[0125] Figures 89A to 89E A HAADF-STEM image and an EDX surface analysis image of a cross section are shown.

[0126] Fig.90 The Id-Vg characteristics of the transistor are shown. DETAILED DESCRIPTION

[0127] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a variety of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments.

[0128] In the drawings, the size, thickness of a layer or region is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not necessarily limited to the above-mentioned dimensions. Note that in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or values ​​shown in the drawings.

[0129] Note that the ordinal numbers such as “first”, “second”, and “third” used in this specification are added to avoid confusion among constituent elements, and are not intended to limit the number.

[0130] Note that in this specification, when describing the positional relationship of components with reference to the drawings, for the sake of convenience, words and phrases such as "upper", "above", "lower", and "below" are used to indicate the configuration. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the above-mentioned positional relationship is not limited to the words and phrases described in this specification, and other words and phrases may be appropriately used to describe it according to the situation.

[0131] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain terminal, a drain region, or a drain electrode) and a source (source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel region. Note that in this specification, etc., a channel region refers to a region where current mainly flows.

[0132] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and the drain may be interchanged. Therefore, in this specification, etc., the source and the drain may be interchanged.

[0133] Note that in this specification, etc., "electrical connection" includes a case where components are connected to each other through an "object having an electrical function". There is no particular limitation on the "object having any electrical function" as long as electrical signals can be transmitted and received between components connected through the object. Examples of "object having any electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0134] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. "Vertical" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0135] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be sometimes referred to as "conductive film". Also, for example, "insulating film" may be sometimes referred to as "insulating layer".

[0136] In this specification, etc., unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to the state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth, and in a p-channel transistor, the off state refers to the state in which the voltage Vgs between the gate and the source is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

[0137] The off-state current of a transistor sometimes depends on Vgs. Therefore, "the off-state current of the transistor is less than 1" sometimes means that there is a value of Vgs that makes the off-state current of the transistor less than 1. The off-state current of a transistor sometimes refers to: an off-state when Vgs is a predetermined value; an off-state when Vgs is a value within a predetermined range; or an off-state when Vgs is a value that can obtain a sufficiently low off-state current, etc.

[0138] As an example, consider an n-channel transistor with a threshold voltage Vth of 0.5 V and a drain current of 1×10 -9 A, the drain current when Vgs is 0.1V is 1×10 -13 A, the drain current when Vgs is -0.5V is 1×10 -19 A, the drain current when Vgs is -0.8V is 1×10 -22 A. At Vgs of -0.5V or in the range of -0.5V to -0.8V, the drain current of this transistor is 1×10 -19 A or less, so the off-state current of the transistor is sometimes called 1×10 -19 A or less. Due to the existence of the drain current of the transistor being 1×10 -22 A below Vgs, so the off-state current of the transistor is sometimes called 1×10 -22 A or below.

[0139] In this specification and the like, the off-state current of a transistor having a channel width W is sometimes expressed as a current value per channel width W. In addition, the off-state current of a transistor having a channel width W is sometimes expressed as a current value per a predetermined channel width (e.g., 1 μm). In the latter case, the unit of the off-state current is sometimes expressed as a unit having the dimension of current / length (e.g., A / μm).

[0140] The off-state current of a transistor sometimes depends on the temperature. In this specification, unless otherwise specified, the off-state current sometimes refers to the off-state current at room temperature, 60°C, 85°C, 95°C or 125°C. Alternatively, it sometimes refers to the off-state current at a temperature that ensures the reliability of a semiconductor device including the transistor or at a temperature at which a semiconductor device including the transistor is used (for example, any temperature between 5°C and 35°C). "The off-state current of the transistor is less than I" sometimes means that there is a value of Vgs that makes the off-state current of the transistor less than I at room temperature, 60°C, 85°C, 95°C, 125°C, a temperature that ensures the reliability of a semiconductor device including the transistor or at a temperature at which a semiconductor device including the transistor is used (for example, any temperature between 5°C and 35°C).

[0141] The off-state current of a transistor sometimes depends on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-state current sometimes refers to the off-state current when Vds is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, sometimes the off-state current is referred to as the Vds that ensures the reliability of a semiconductor device including the transistor or the Vds used by a semiconductor device including the transistor. “The off-state current of the transistor is less than I” sometimes means: when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, a Vds that ensures the reliability of a semiconductor device including the transistor, or a Vds that is used in a semiconductor device including the transistor, there is a Vgs value that makes the off-state current of the transistor less than I.

[0142] In the above description of off-state current, the drain can be referred to as the source. That is, the off-state current sometimes refers to the current flowing through the source when the transistor is in the off state.

[0143] In this specification, the off-state current may be referred to as leakage current. In this specification, the off-state current may refer to, for example, current flowing between a source and a drain when a transistor is in an off state.

[0144] In this specification, etc., the threshold voltage of a transistor refers to the gate voltage (Vg) when a channel is formed in the transistor. Specifically, the threshold voltage of a transistor sometimes refers to the gate voltage (Vg) at the intersection of the straight line with the maximum slope and the drain current (Id) at the point where the square root is 0 (Id is 0A) in a curve (Vg-√Id characteristic) plotted with the gate voltage (Vg) on ​​the horizontal axis and the drain current (Id) on the vertical axis. Alternatively, the threshold voltage of a transistor sometimes refers to the value of Id [A] × L [μm] / W [μm] when L is the channel length and W is the channel width is 1 × 10 -9 Gate voltage (Vg) at [A].

[0145] In this specification, for example, when the conductivity is sufficiently low, sometimes even when it is expressed as a "semiconductor", it has the characteristics of an "insulator". In addition, the boundary between "semiconductor" and "insulator" is unclear, so it is sometimes impossible to accurately distinguish them. Therefore, the "semiconductor" recorded in this specification can sometimes be replaced by "insulator". Similarly, the "insulator" recorded in this specification can sometimes be replaced by "semiconductor". Or, the "insulator" recorded in this specification can sometimes be replaced by "semi-insulator".

[0146] In this specification, for example, when the conductivity is sufficiently high, it may have the characteristics of a "conductor" even when it is expressed as a "semiconductor". In addition, the boundary between "semiconductor" and "conductor" is unclear, so it is sometimes impossible to accurately distinguish them. Therefore, the "semiconductor" recorded in this specification may sometimes be replaced by "conductor". Similarly, the "conductor" recorded in this specification may sometimes be replaced by "semiconductor".

[0147] In this specification, etc., impurities of a semiconductor refer to elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, DOS (Density of States) may be formed in the semiconductor, the carrier mobility may be reduced, or the crystallinity may be reduced. When the semiconductor includes an oxide semiconductor, as impurities that change the semiconductor characteristics, there are, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements or transition metals other than the main components, and in particular, there are hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, oxygen vacancies are sometimes generated, for example, due to the mixing of impurities such as hydrogen. In addition, when the semiconductor is silicon, as impurities that change the semiconductor characteristics, there are, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0148] (Implementation Method 1)

[0149] In this embodiment, refer to Figures 1 to 35C A semiconductor device according to one embodiment of the present invention will be described.

[0150] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, an oxide semiconductor film, and a third insulating film on the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode is electrically connected to the second gate electrode.

[0151] The maximum field effect mobility of the above transistors including transistors with a gate voltage higher than 0V and less than 10V is 40cm 2 / Vs or more and less than 150cm 2 / Vs, a first region with a threshold voltage of -1V or more and 1V or less, a third region with an S value of less than 0.3V / decade, and an off-state current of less than 1×10 -12 A / cm 2 The fourth region, in μFE (max) represents the maximum value of the field effect mobility of the transistor and μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is greater than or equal to 1 and less than 1.5.

[0152] Sometimes in the above transistor μ FE (max) / μ FE (Vg=2V) is 1.5 or more and less than 3.

[0153] The above structure can also be said to be as follows: A semiconductor device according to one embodiment of the present invention is a transistor including an oxide semiconductor film in a channel region, and the field effect mobility, threshold voltage, off-state current and S value of the transistor are good. Such a semiconductor device can be suitably used for a transistor of a pixel of an organic EL display or a transistor of a driving circuit of an organic EL display.

[0154] Sometimes, the maximum field effect mobility of the transistor including the transistor having a gate voltage higher than 0 V and less than 10 V is 10 cm 2 / Vs or more and less than 100cm 2 / Vs, a first region with a threshold voltage of -1V or more and 1V or less, a third region with an S value of less than 0.3V / decade, and an off-state current of less than 1×10 -12 A / cm 2 The fourth region, in μ FE (max) represents the maximum value of the field effect mobility of the transistor and μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is 3 or more and less than 10.

[0155] The above structure can also be said to be as follows: A semiconductor device according to one embodiment of the present invention is a transistor including an oxide semiconductor film in a channel region, and the transistor has high reliability due to its high heat resistance and stable physical properties. Such a semiconductor device can be suitable for use as a power device. For example, such a semiconductor device can be suitable for use as a semiconductor device in a power converter such as an inverter or a converter. As another example, such a semiconductor device can be used for inverter control of electric vehicles, hybrid vehicles, air conditioners, etc., various general-purpose motors, etc. In this embodiment, an oxide semiconductor according to one embodiment of the present invention is described.

[0156] <1-1. Oxide semiconductor film>

[0157] First, refer to FIG. 4A to FIG. 13 An oxide semiconductor film that can be used for the transistor according to one embodiment of the present invention is described.

[0158] The oxide semiconductor film preferably contains indium. In particular, it preferably contains indium and zinc. In addition, it is preferred to contain aluminum, gallium, yttrium or tin. Alternatively, it may contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten or magnesium.

[0159] Here, the case where the oxide semiconductor film contains indium, element M and zinc is considered. Element M is aluminum, gallium, yttrium or tin, etc. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. Note that as element M, two or more of the above elements can also be combined. The respective terms of the atomic number ratios of indium, element M and zinc contained in the oxide semiconductor film are referred to as [In], [M] and [Zn], respectively.

[0160] <1-2. Structure of Oxide Semiconductor Film>

[0161] Figure 4A and Figure 4B is a schematic diagram of an oxide semiconductor film according to one embodiment of the present invention.

[0162] Figure 4A is a schematic diagram of the top surface of the oxide semiconductor film (here referred to as the ab plane direction), Figure 4B It is a schematic diagram of a cross section (c-axis direction) of an oxide semiconductor film formed on a substrate Sub.

[0163] Although Figure 4A and Figure 4B An example in which an oxide semiconductor film is formed on a substrate is shown, but an embodiment of the present invention is not limited to this, and an insulating film such as a base film or an interlayer film or other semiconductor films such as an oxide semiconductor film may be formed between the substrate and the oxide semiconductor film.

[0164] like Figure 4A and Figure 4B As shown in FIG. 1 , the oxide semiconductor film of one embodiment of the present invention is a composite oxide semiconductor having a structure in which the region A1 and the region B1 are mixed. Therefore, in the following description, the oxide semiconductor film is sometimes referred to as a composite oxide semiconductor.

[0165] Figure 4A and Figure 4BThe region A1 shown is a region with more In, where [In]: [M]: [Zn] = x: y: z (x>0, y≥0, z≥0). The region B1 is a region with less In, where [In]: [M]: [Zn] = a: b: c (a>0, b>0, c>0).

[0166] Note that in this specification, for example, when the ratio of the number of atoms of In to the element M in region A1 is greater than the ratio of the number of atoms of In to the element M in region B1, region A1 has a higher In concentration than region B1. Therefore, in this specification, region A1 is also referred to as an In-rich region, and region B1 is also referred to as an In-poor region.

[0167] For example, the In concentration of region A1 is 1.1 times or more, and preferably 2 times or more and 10 times or less than the In concentration of region B1. Region A1 is an oxide containing at least In, and does not necessarily contain the elements M and Zn.

[0168] Here, the atomic number ratio of elements in the complex oxide semiconductor according to one embodiment of the present invention is described.

[0169] When the region A1 in the composite oxide semiconductor contains In, the element M, and Zn, the atomic number ratio of each element can be Figure 8 The phase diagram shows that the atomic ratio of In, element M and Zn is represented by x:y:z. Figure 8 The atomic number ratio can be expressed as a coordinate (x:y:z) in Figure 8 The proportion of oxygen atoms is not shown.

[0170] exist Figure 8 In the figure, the dotted lines correspond to the line representing the atomic number ratio (-1≤α≤1) of [In]:[M]:[Zn]=(1+α):(1-α):1, the line representing the atomic number ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, the line representing the atomic number ratio of [In]:[M]:[Zn]=(1+α):(1-α):3, the line representing the atomic number ratio of [In]:[M]:[Zn]=(1+α):(1-α):4, and the line representing the atomic number ratio of [In]:[M]:[Zn]=(1+α):(1-α):5.

[0171] The dotted lines are equivalent to the line representing the atomic number ratio of [In]:[M]:[Zn]=1:1:β (β≥0), the line representing the atomic number ratio of [In]:[M]:[Zn]=1:2:β, the line representing the atomic number ratio of [In]:[M]:[Zn]=1:3:β, the line representing the atomic number ratio of [In]:[M]:[Zn]=1:4:β, the line representing the atomic number ratio of [In]:[M]:[Zn]=1:7:β, the line representing the atomic number ratio of [In]:[M]:[Zn]=2:1:β and the line representing the atomic number ratio of [In]:[M]:[Zn]=5:1:β.

[0172] Figure 8 The oxide semiconductor shown having an atomic number ratio of [In]:[M]:[Zn]=0:2:1 or a value in the vicinity thereof tends to have a spinel crystal structure.

[0173] Figure 8 Region A2 in FIG. 1 shows an example of a preferred range of the atomic ratio of indium, element M, and zinc contained in region A1. Note that region A2 includes the atomic ratio on the line representing [In]:[M]:[Zn]=(1+γ):0:(1-γ)(-1≤γ≤1).

[0174] Figure 8 Region B2 in FIG. 1 shows an example of a preferred range of the atomic ratio of indium, element M, and zinc contained in region B1. Note that region B2 includes values ​​of [In]:[M]:[Zn]=4:2:3 to [In]:[M]:[Zn]=4:2:4.1 and their vicinity. The vicinity includes, for example, an atomic ratio of [In]:[M]:[Zn]=5:3:4. Region B2 includes values ​​of [In]:[M]:[Zn]=5:1:6 and their vicinity.

[0175] Since the In concentration of region A2 is high, the conductivity is higher than that of region B2, and thus the carrier mobility (field effect mobility) is improved. Therefore, the on-state current and carrier mobility of the transistor using the oxide semiconductor film having region A1 can be improved.

[0176] In contrast, since the In concentration of region B2 is low, the conductivity is lower than that of region A2, and thus has a function of reducing leakage current. Therefore, the off-state current of the transistor using the oxide semiconductor film having region B1 can be reduced.

[0177] In the oxide semiconductor film of one embodiment of the present invention, region A1 and region B1 form a composite body. That is, carrier movement is easy to occur in region A1, and carrier movement is not easy to occur in region B1. Therefore, the oxide semiconductor of one embodiment of the present invention can be used as a material having high carrier mobility, high switching characteristics, and good semiconductor characteristics.

[0178] For example, Figure 4A As shown, multiple regions A1 exist in a granular state (in a clustered state) in the ab plane direction and the c-axis direction. Note that the clusters may also be unevenly and irregularly distributed. Multiple clusters sometimes overlap or connect to each other. For example, sometimes a cluster overlaps with other clusters and is connected to each other, thereby observing a region A1 in a cloud-like state.

[0179] Note that when all regions A1 are connected in the ab plane direction, the switching characteristics of the transistor decrease (for example, the off-state current of the transistor increases), so Figure 4A and Figure 4B As shown, the region A1 is preferably dispersed in the region B1. Therefore, the region A1 may exist in a state of being surrounded by the region B1 in a three-dimensional manner. That is, the region A1 is sealed by the region B1.

[0180] Region B1 can also be considered to have a structure of a cluster (also called a second cluster) different from the cluster (also called a first cluster) included in region A1. In the above structure, region B1 includes a plurality of second clusters and includes a portion where the plurality of second clusters are connected to each other. In other words, the first cluster included in region A1 includes a portion where the first cluster is connected to other first clusters in a cloud-like manner, and the second cluster included in region B1 includes a portion where the second cluster is connected to other second clusters in a cloud-like manner.

[0181] Note that the ratio of the region A1 spread can be adjusted according to the formation conditions or composition of the composite oxide semiconductor. For example, a composite oxide semiconductor with a low ratio of the region A1 or a composite oxide semiconductor with a high ratio of the region A1 can be formed. Figure 5A and Figure 5B Shown with Figure 4A and Figure 4B The composite oxide semiconductor shown has a lower ratio of composite oxide semiconductor than that of region A1. Figure 5A is equivalent to Figure 4A Schematic diagram of Figure 5B is equivalent to Figure 4BSchematic diagram of the present invention. The ratio of region A1 to region B1 in the composite oxide semiconductor of one embodiment of the present invention is not limited to being low. In a composite oxide semiconductor in which the ratio of region A1 is very large, region B1 is sometimes formed in region A1 depending on the observation range. For example, the size of the granular region of region A1 can be appropriately adjusted according to the formation conditions or composition of the composite oxide semiconductor.

[0182] Sometimes, a clear boundary between region A1 and region B1 cannot be observed. The size of region A1 and region B1 can be evaluated using an EDX surface analysis image using energy dispersive X-ray spectroscopy (EDX). For example, in the EDX surface analysis of a cross-sectional photograph or a planar photograph, the diameter of the cluster in region A1 is sometimes greater than 0.1 nm and less than 2.5 nm. Note that the diameter of the cluster is preferably greater than 0.5 nm and less than 1.5 nm.

[0183] Thus, the oxide semiconductor of one embodiment of the present invention is a composite oxide semiconductor in which region A1 and region B1 are mixed together and have different functions that complement each other. For example, when the oxide semiconductor of one embodiment of the present invention is an In-Ga-Zn oxide (hereinafter referred to as IGZO) in which the element M is Ga, the oxide semiconductor of one embodiment of the present invention can be referred to as Complementary IGZO (abbreviated as: C / IGZO).

[0184] On the other hand, for example, when region A1 and region B1 are stacked in layers, there is no interaction between region A1 and region B1, or interaction is not easy to occur, so the function of region A1 and the function of region B1 sometimes work independently. At this time, even if the carrier mobility can be improved due to region A1, the off-state current of the transistor sometimes increases. Therefore, by using the above-mentioned composite oxide semiconductor or C / IGZO, the function of high carrier mobility and the function of good switching characteristics can be achieved at the same time. This is an excellent effect obtained in the composite oxide semiconductor of one embodiment of the present invention.

[0185] Note that when an oxide semiconductor is deposited using a sputtering device, a film having an atomic ratio different from that of the target is formed. In particular, depending on the substrate temperature during deposition, the atomic ratio of the deposited film may have a smaller content of [Zn] than that of the target.

[0186] Note that the properties of the composite oxide semiconductor of one embodiment of the present invention are not determined only by the atomic number ratio. Therefore, the illustrated regions show the atomic number ratios that the composite oxide semiconductor region A1 and region B1 preferably have, and the boundary between them is not clear.

[0187] The oxide semiconductor according to the present invention is not limited to the above. Fig. 6A and Figure 6B as well as Fig. 7A and Figure 7B is a schematic diagram of an oxide semiconductor film having a structure different from the above-mentioned oxide semiconductor film. Fig. 6A and Fig. 7A It is a schematic diagram of the top surface (ab plane direction) of the complex oxide semiconductor. Figure 6B and Figure 7B Schematic diagram of a cross section (c-axis direction) of a composite oxide semiconductor formed on each substrate Sub. Note that Fig. 6A and Figure 6B as well as Fig. 7A and Figure 7B The structure of the oxide semiconductor film shown in FIG. 1 can be referred to except for the following points: Figure 4A and Figure 4B Illustration of the structure of an oxide semiconductor film shown.

[0188] Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0189] CAAC-OS has c-axis orientation, and multiple nanocrystals are connected in the ab plane direction, and the crystal structure has distortion. Note that the distortion in CAAC-OS refers to the part where the direction of the lattice arrangement changes between the region where the lattice arrangement is consistent and other regions where the lattice arrangement is consistent.

[0190] Fig. 6A and Fig. 7A The dotted lines schematically show a plurality of nanocrystals. The nanocrystals are basically hexagonal. However, the shape is not limited to regular hexagons, and sometimes non-regular hexagons. In the distortion, there are sometimes polygonal nanocrystals such as pentagons and heptagons.

[0191] Note that no clear grain boundaries are observed near the distortion of CAAC-OS. That is, it is known that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This may be because CAAC-OS can tolerate distortion caused by the following reasons: low density of oxygen atoms in the ab plane direction or changes in the bonding distance between atoms due to substitution of metal elements.

[0192] also, Figure 6B and Figure 7B The schematic diagram shows that the nanocrystal has a c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface on which the CAAC-OS film is formed (also referred to as the formed surface) or the top surface of the CAAC-OS film. CAAC-OS has a layered crystal structure (also referred to as a layered structure) exhibiting c-axis orientation, and has a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter referred to as a (M, Zn) layer).

[0193] Note that indium and element M may sometimes replace each other. Therefore, when element M of the (M, Zn) layer is replaced by indium, the layer may also be expressed as an (In, M, Zn) layer. In this case, an In layer and an (In, M, Zn) layer are stacked in the layered structure.

[0194] In nc-OS, the atomic arrangement in a tiny region (e.g., a region between 1 nm and 10 nm, especially a region between 1 nm and 3 nm) is periodic. In nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0195] a-like OS has a structure between nc-OS and amorphous oxide semiconductor. a-like OS contains voids or low-density regions. In other words, a-like OS has an unstable structure compared to nc-OS and CAAC-OS.

[0196] Oxide semiconductors have various structures and various properties. The oxide semiconductor of the present invention may be a composite oxide semiconductor including two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS. Region A1 and region B1 may also have different crystallinity.

[0197] For example, region A1 is preferably non-single crystal. Note that in the case where region A1 has crystallinity, when region A1 is formed of indium, region A1 tends to have a tetragonal structure. In addition, when region A1 is formed of indium oxide ([In]:[M]:[Zn]=x:0:0(x>0)), region A1 tends to have a pyrophyllite-type crystal structure. In addition, when region A1 is formed of In-Zn oxide ([In]:[M]:[Zn]=x:0:z(x>0, z>0)), region A1 tends to have a layered crystal structure.

[0198] The region B1 includes the CAAC-OS. However, the region B1 does not necessarily have to include only the CAAC-OS, and may include a region of a polycrystalline oxide semiconductor or nc-OS.

[0199] CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since clear grain boundaries cannot be confirmed in CAAC-OS, it can be said that the reduction in electron mobility caused by grain boundaries is not likely to occur. The crystallinity of oxide semiconductors is sometimes reduced due to the mixing of impurities or the generation of defects. This means that CAAC-OS has very few impurities or defects (oxygen vacancies, etc.). Therefore, by having CAAC-OS, the physical properties of the composite oxide semiconductor are stable, so a composite oxide semiconductor with heat resistance and high reliability can be provided.

[0200] Note that the dispersion ratio of the region A1 can be adjusted by, for example, changing the formation conditions or composition of the composite oxide semiconductor. Fig. 7A and Figure 7B As shown, a composite oxide semiconductor having a low ratio in the region A1 or a composite oxide semiconductor having a high ratio in the region A1 can be formed.

[0201] <1-3. Transistor Having Oxide Semiconductor Film>

[0202] Next, a case where the above-described oxide semiconductor film is used for a transistor is described.

[0203] By using the above-mentioned complex oxide semiconductor in a transistor, the transistor can have high carrier mobility and high switching characteristics. In addition, the transistor can have high reliability.

[0204] In addition, it is preferable to use an oxide semiconductor film with a low carrier density for the transistor. For example, an oxide semiconductor film with a carrier density of less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 and 1×10 -9 / cm3 The above oxide semiconductor film is used as the above oxide semiconductor film.

[0205] In order to reduce the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as a high-purity intrinsic or substantially high-purity intrinsic state. A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has fewer carrier generation sources, so the carrier density can be reduced. A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, and therefore sometimes has a lower trap state density.

[0206] Charges trapped in trap levels of an oxide semiconductor film take a long time to disappear, and behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel region formed in an oxide semiconductor having a high trap state density may be unstable.

[0207] In order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor film. In order to reduce the impurity concentration in the oxide semiconductor film, it is preferable to also reduce the impurity concentration near the oxide semiconductor film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0208] Here, the influence of each impurity in the oxide semiconductor film is described.

[0209] When the oxide semiconductor film contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor or near the interface of the oxide semiconductor (measured by secondary ion mass spectrometry (SIMS)) is 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0210] When the oxide semiconductor film contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor including an oxide semiconductor film containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferred to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor film. Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor film measured by SIMS analysis is 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0211] When the oxide semiconductor film contains nitrogen, electrons as carriers are generated, the carrier density increases, and the oxide semiconductor is easily converted to n-type. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to have a normally-on characteristic. Therefore, it is preferable to reduce nitrogen in the oxide semiconductor as much as possible, for example, the nitrogen concentration in the oxide semiconductor measured by SIMS analysis is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0212] Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to the metal atom to generate water, thereby sometimes forming an oxygen vacancy (V o When hydrogen enters the oxygen vacancy (V o ), sometimes electrons are generated as carriers. In addition, sometimes electrons are generated as carriers because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS analysis is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0213] By introducing oxygen into the oxide semiconductor film, oxygen vacancies (V o In other words, when the oxygen vacancies (V o ) is filled with oxygen, the oxygen vacancy (V o ) disappears. Therefore, by diffusing oxygen into the oxide semiconductor film, the oxygen vacancies (V o ), thereby improving the reliability of the transistor.

[0214] As a method of introducing oxygen into an oxide semiconductor film, for example, an oxide containing oxygen exceeding the stoichiometric composition can be provided in contact with the oxide semiconductor film. That is, it is preferred to form a region containing oxygen exceeding the stoichiometric composition (hereinafter, also referred to as an oxygen excess region) in the above-mentioned oxide. In particular, when the oxide semiconductor film is used for a transistor, by providing an oxide having an oxygen excess region in a base film or an interlayer film near the transistor, the oxygen vacancies in the transistor can be reduced, thereby improving the reliability of the transistor.

[0215] When an oxide semiconductor film whose impurity concentration is sufficiently reduced is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.

[0216] <1-4. Method for producing composite oxide semiconductor>

[0217] Here, refer to Fig.9A and Fig. 9B , Fig.10 , Fig.11A and Fig. 11B , Fig. 12A and Fig. 12B as well as Fig.13 right Figure 4A and Figure 4B An example of a method for producing a composite oxide semiconductor shown in FIG. 1 is described below. The composite oxide semiconductor according to one embodiment of the present invention can be formed using a sputtering apparatus.

[0218] <1-5. Sputtering device>

[0219] Fig.9A 25 is a cross-sectional view illustrating a deposition chamber 2501 of a sputtering device. Fig. 9B It is a plan view of the magnet unit 2530a and the magnet unit 2530b of the sputtering device.

[0220] Fig.9A The deposition chamber 2501 shown includes a target rack 2520a, a target rack 2520b, a backing plate 2510a, a backing plate 2510b, a target 2500a, a target 2500b, a member 2542, and a substrate rack 2570. Note that the target 2500a is arranged on the backing plate 2510a. The backing plate 2510a is arranged on the target rack 2520a. The magnet unit 2530a is arranged under the target 2500a via the backing plate 2510a. The target 2500b is arranged on the backing plate 2510b. The backing plate 2510b is arranged on the target rack 2520b. The magnet unit 2530b is arranged under the target 2500b via the backing plate 2510b.

[0221] like Fig.9A and Fig. 9BAs shown, the magnet unit 2530a includes a magnet 2530N1, a magnet 2530N2, a magnet 2530S, and a magnet frame 2532. In the magnet unit 2530a, the magnet 2530N1, the magnet 2530N2, and the magnet 2530S are arranged on the magnet frame 2532. The magnet 2530N1, the magnet 2530N2, and the magnet 2530S are arranged in a spaced manner. Note that the magnet unit 2530b has the same structure as the magnet unit 2530a. When the substrate 2560 is moved into the deposition chamber 2501, the substrate 2560 contacts the substrate frame 2570.

[0222] The target 2500a, the backing plate 2510a and the target holder 2520a are separated from the target 2500b, the backing plate 2510b and the target holder 2520b by a member 2542. Note that the member 2542 is preferably an insulator. The member 2542 may also be a conductor or a semiconductor. The member 2542 may also be a conductor or a semiconductor whose surface is covered by an insulator.

[0223] The target holder 2520a and the backing plate 2510a are fixed by screws (bolts, etc.) and the same potential is applied to them. The target holder 2520a has the function of supporting the target 2500a through the backing plate 2510a. The target holder 2520b and the backing plate 2510b are fixed by screws (bolts, etc.) and the same potential is applied to them. The target holder 2520b has the function of supporting the target 2500b through the backing plate 2510b.

[0224] The backing plate 2510a has a function of fixing the target 2500a. The backing plate 2510b has a function of fixing the target 2500b.

[0225] exist Fig.9A , magnetic lines of force 2580a and magnetic lines of force 2580b formed by magnet unit 2530a are shown.

[0226] like Fig. 9B As shown, the magnet unit 2530a adopts a structure in which a square or substantially square magnet 2530N1, a square or substantially square magnet 2530N2, and a square or substantially square magnet 2530S are fixed to a magnet frame 2532. Fig. 9B As shown by the arrow in FIG. 2 , the magnet unit 2530a can be swung in the horizontal direction. For example, the magnet unit 2530a can be swung at a beat of 0.1 Hz or more and 1 kHz or less.

[0227] The magnetic field on the target 2500a changes as the magnet unit 2530a swings. Since the area with a strong magnetic field becomes a high-density plasma area, sputtering of the target 2500a is likely to occur near this area. The same is true for the magnet unit 2530b.

[0228] <1-6. Manufacturing Process of Composite Oxide Semiconductor>

[0229] Fig.10 This is a process flow chart illustrating a method for manufacturing a complex oxide semiconductor.

[0230] Figure 4A and Figure 4B The composite oxide semiconductor shown is at least Fig.10 The present invention is manufactured by the first to fourth steps shown.

[0231] [First step: step of placing a substrate in a deposition chamber]

[0232] The first step includes placing a substrate in a deposition chamber (see Fig.10 . , step S101 in FIG.

[0233] In the first step, for example, the substrate 2560 is disposed on Fig.9A and Fig. 9B The deposition chamber 2501 is shown to include a substrate holder 2570 .

[0234] The temperature of the substrate 2560 may be above room temperature (25° C.) and below 200° C., preferably above room temperature and below 130° C. The substrate temperature within the above range is suitable for the case of using a large-area glass substrate. In particular, when the substrate temperature during deposition of the composite oxide semiconductor is set to room temperature, in other words, when the substrate is not intentionally heated, deformation or bending of the substrate can be suppressed, which is preferred.

[0235] The substrate 2560 can be cooled by a cooling mechanism provided on the substrate holder 2570 or the like.

[0236] When the temperature of the substrate 2560 is set to 100° C. or higher and 130° C. or lower, water in the composite oxide semiconductor can be removed. By removing water as an impurity in this way, it is possible to easily form Figure 5A and Figure 5B The composite oxide semiconductor shown in FIG.

[0237] In addition, when the temperature of the substrate 2560 is set to be greater than 100° C. and less than 130° C., the strain of the sputtering device caused by excessive heat can be prevented. Thus, a semiconductor device with high productivity can be manufactured. Therefore, productivity becomes stable and it is easy to introduce a large-scale production device. Therefore, a large display device using a large-area substrate can be easily manufactured.

[0238] [Second step: step of introducing gas into deposition chamber]

[0239] The second step includes a step of introducing gas into the deposition chamber (see Fig.10 . , step S201 in FIG.

[0240] In the second step, for example, Fig.9A and Fig. 9B A gas is introduced into the deposition chamber 2501 shown. As the gas, one or both of argon gas and oxygen gas can be introduced. Note that an inert gas such as helium, krypton, or xenon can be used instead of argon gas.

[0241] The ratio of oxygen in the total deposition gas when forming a composite oxide semiconductor using an oxygen gas is sometimes referred to as the oxygen flow rate. The oxygen flow rate when forming a composite oxide semiconductor is set to be 0% to 30%, preferably 5% to 30%, and more preferably 7% to 15%.

[0242] In the deposition Figure 5A and Figure 5B When the composite oxide semiconductor is deposited at room temperature, the oxygen flow rate ratio is set to be higher than 30% and lower than 70%, preferably higher than 30% and lower than 50%. In addition, the oxygen flow rate ratio in heated deposition (for example, a temperature of 70°C or higher and 150°C or lower) is set to be higher than 10% and lower than 50%, preferably higher than 30% and lower than 50%.

[0243] In the formation Fig. 6A and Figure 6B The composite oxide semiconductor or Fig. 7A and Figure 7B In the case of the composite oxide semiconductor shown, a mixed gas of a rare gas and oxygen is used, and the ratio of oxygen to the rare gas is set to 70% or more and 100% or less.

[0244] In addition, the gas needs to be highly purified. For example, as the oxygen gas or argon gas used as the gas, a high-purity gas with a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less, and further preferably -120°C or less is used, thereby preventing moisture and the like from mixing into the composite oxide semiconductor as much as possible.

[0245] It is preferred to use an adsorption vacuum pump such as a cryopump to evacuate the deposition chamber 2501 to a high vacuum (5×10 -7 Pa to 1×10 -4 Pa) to remove water and the like, which are impurities to the composite oxide semiconductor, as much as possible. In particular, when the sputtering device is on standby, the deposition chamber 2501 has a H 2 The partial pressure of O gas molecules (equivalent to gas molecules with m / z = 18) is preferably 1×10 -4 Pa or less, more preferably 5×10 -5 Below Pa.

[0246] [Third step: step of applying voltage to target]

[0247] The third step includes a step of applying a voltage to the target (see Fig.10 , step S301 in the process.

[0248] In the third step, for example, Fig.9A and Fig. 9B Voltage is applied to the target holder 2520a and the target holder 2520b shown. For example, the potential applied to the terminal V1 connected to the target holder 2520a is lower than the potential applied to the terminal V2 connected to the substrate holder 2570. The potential applied to the terminal V4 connected to the target holder 2520b is lower than the potential applied to the terminal V2 connected to the substrate holder 2570. The potential applied to the terminal V2 connected to the substrate holder 2570 is the ground potential. The potential applied to the terminal V3 connected to the magnet holder 2532 is the ground potential.

[0249] Note that the potentials applied to the terminals V1, V2, V3, and V4 are not limited to the above potentials. It is not necessary to apply potentials to all of the target holder 2520, the substrate holder 2570, and the magnet holder 2532. For example, the substrate holder 2570 may also be in an electrically floating state. Note that it is assumed that a power source capable of controlling the potential applied to the terminal V1 is electrically connected to the terminal V1. As the power source, a DC power source, an AC power source, or an RF power source may be used.

[0250] As the target 2500a and the target 2500b, it is preferred to use a target containing indium, an element M (M is Al, Ga, Y or Sn), zinc and oxygen. For example, as the target 2500a and the target 2500b, an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) or an In-Ga-Zn metal oxide target (In:Ga:Zn=5:1:7 [atomic ratio]) can be used. The following describes the case of using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]).

[0251] Note that by using a sputtering target including a polycrystalline oxide having a plurality of crystal grains as the target 2500a and the target 2500b, it is easy to obtain Figure 4A and Figure 4B or Figure 8 The composite oxide semiconductor shown has crystallinity.

[0252] [Fourth step: step of depositing a complex oxide semiconductor on a substrate]

[0253] The fourth step includes a step of ejecting sputtered particles from the target and depositing a composite oxide semiconductor on a substrate (see Fig.10 , or step S401 in the above procedure.

[0254] In the fourth step, for example, Fig.9A and Fig. 9B In the deposition chamber 2501 shown, argon gas or oxygen gas is ionized and separated into cations and electrons to generate plasma. Then, the cations in the plasma are accelerated toward the targets 2500a and 2500b due to the potential applied to the target holders 2520a and 2520b. When the cations collide with the In-Ga-Zn metal oxide target, sputtered particles are generated and the sputtered particles are deposited on the substrate 2560.

[0255] Note that when an In-Ga-Zn metal oxide target having an atomic ratio of In:Ga:Zn=4:2:4.1 or 5:1:7 is used as the target 2500a, 2500b, the target may contain a plurality of crystal grains having different compositions. For example, in many cases, the diameter of the plurality of crystal grains is 10 μm or less. For example, when the In-Ga-Zn metal oxide target contains crystal grains having a high In ratio, the ratio of the region A1 may increase.

[0256] <1-7. Deposition model>

[0257] In the fourth step, it can be assumed that Fig.11A and Fig. 11B The deposition model shown.

[0258] Fig.11A and Fig. 11B yes Fig.9A and Fig. 9B The cross-sectional view of the target 2500a shown in FIG. Fig.11A and Fig. 11B , a pad 2510a, a target material 2500a, a plasma 2190, cations 2192, sputtered particles 2194, etc. are shown.

[0259] [First step]

[0260] exist Fig.11A In the process, the argon gas or oxygen gas is ionized and separated into cations 2192 and electrons (not shown) to form a plasma 2190. Then, the cations 2192 in the plasma 2190 are accelerated toward the target 2500a (here, the In-Ga-Zn metal oxide target). Since the cations 2192 collide with the In-Ga-Zn metal oxide target, sputtered particles 2194 are generated, and the sputtered particles 2194 are ejected from the In-Ga-Zn metal oxide target. Note that Ga and Zn are first sputtered preferentially as the sputtered particles 2194 from the In-Ga-Zn metal oxide target.

[0261] Specifically, the cation 2192 collides with the In-Ga-Zn metal oxide target to preferentially eject Ga and Zn, whose relative atomic mass is lower than In, from the In-Ga-Zn metal oxide target. The ejected In, Ga, and Zn are bonded with oxygen and then deposited on the substrate, thereby forming Figure 4A and Figure 4B Area B1 is shown.

[0262] Note that Fig.11A As shown in FIG. 1 , Ga and Zn are preferentially sputtered as sputtered particles 2194, which sometimes results in In segregation on the surface of the target 2500a (here, the surface of the In-Ga-Zn metal oxide target). Fig.11A , the segregated In is shown as cluster 2196.

[0263] [Step 2]

[0264] Then, if Fig. 11B As shown, after In segregation, that is, after cluster 2196 is formed, cluster 2196 (here, a cluster containing In) is sputtered from an In-Ga-Zn metal oxide target.

[0265] In detail, In segregated on the surface of the In-Ga-Zn metal oxide target is ejected from the In-Ga-Zn metal oxide target in a structure like a plurality of clusters. The segregated In having a structure like a plurality of clusters is bonded with oxygen and collides with the previously deposited region B1, and deposits in a clustered (granular) region A1. Note that since the segregated In is ejected, the In, Ga, and Zn on the target surface exist in a state close to the original atomic number ratio.

[0266] Note that Fig. 11B As shown, In is segregated in one area of ​​the surface of the target 2500a, and the segregated In is ejected in other areas of the surface of the target 2500a. That is, since the segregation mechanism of In and the ejection mechanism of the segregated In occur simultaneously, an uneven and irregular structure is formed in which the area A1 is surrounded by the area B1.

[0267] By repeating the above deposition model including the first step and the second step, it is possible to obtain Figure 4A and Figure 4B A composite oxide semiconductor according to one embodiment of the present invention is shown.

[0268] Note that the formation method is not limited to the sputtering method, and pulse laser deposition (PLD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (CVD), atomic layer deposition (ALD), vacuum evaporation, etc. can also be used. As an example of the thermal CVD method, an organic metal chemical vapor deposition (MOCVD) method can be cited.

[0269] <1-8. Verification of deposition model>

[0270] In order to verify the above-mentioned deposition model, a sample Z1 shown below was formed.

[0271] [Sample Z1]

[0272] In the sample Z1, an insulating film 82, an insulating film 84, an oxide semiconductor film 88, and an insulating film 86 are formed in this order on a glass substrate.

[0273] The insulating film 82 and the insulating film 84 are used as base films. As the insulating film 82, a silicon nitride film with a thickness of 400 nm is formed by a PECVD device. As the insulating film 84, a silicon oxynitride film with a thickness of 50 nm is formed by a PECVD device.

[0274] As the oxide semiconductor film 88, an In-Ga-Zn oxide film with a thickness of 40 nm was formed by a sputtering device. Note that the oxide semiconductor film 88 was formed under the following conditions: the substrate temperature was 170° C., argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was 0.2 Pa, and 1500 W of AC power was applied to the metal oxide target (In:Ga:Zn=4:2:4.1 [atomic number ratio]) set in the sputtering device.

[0275] Note that in this embodiment, it is assumed that the oxide semiconductor film 88 is a sputtering target for forming a complex oxide semiconductor.

[0276] After the oxide semiconductor film 88 is formed, the surface of the oxide semiconductor film 88 is subjected to plasma treatment using argon gas. It is assumed that this is sputtering performed in a sputtering device. The plasma treatment is performed under the following conditions: argon gas with a flow rate of 100 sccm is introduced into the chamber; the pressure in the chamber is set to 40 Pa; and a power of 1000 W is applied to the RF power supply (27.12 MHz).

[0277] After the plasma treatment, an insulating film 86 is formed on the oxide semiconductor film 88. The insulating film 86 is used as a protective insulating film. As the insulating film 86, a silicon oxynitride film is formed with a thickness of 100 nm using a PECVD apparatus.

[0278] Through the above-mentioned process, a sample Z1 for verifying the deposition model is formed.

[0279] Next, a high-angle annular dark field STEM (HAADF-STEM) image of the cross section of the sample Z1 was observed. Note that in the HAADF-STEM observation, JEM-ARM200F manufactured by JEOL was used under the condition of an acceleration voltage of 200 kV.

[0280] Fig.13 The HAADF-STEM observation results of sample Z1 are shown.

[0281] like Fig.13 As shown, a structure 90 is formed on the oxide semiconductor film 88. In addition, from the results of HAADF-STEM observation, the thickness of the oxide semiconductor film 88 is about 36 nm, and the thickness of the structure 90 is about 11 nm.

[0282] In order to evaluate the composition of the structure 90, elemental analysis was performed at point 1 shown in the oxide semiconductor film 88 and at point 2 shown in the structure 90. Note that this elemental analysis was performed using an EDX apparatus JED-2300T. The beam diameter of the elemental analysis was set to 0.1 nmφ.

[0283] Table 1 shows the EDX analysis results.

[0284] [Table 1]

[0285]

[0286] When the value of point 1 shown in Table 1 is normalized by the value of In of the metal oxide target, the atomic number ratio is In:Ga:Zn:O=4:2:2.4:7.2. Although the ratio of Zn atoms slightly deviates from the ratio of Zn atoms in the composition of the metal oxide target, the composition of the oxide semiconductor film 88 roughly corresponds to the composition of the metal oxide target. On the other hand, the structure 90 has a higher ratio of In as shown in Table 1. Therefore, the structure 90 can also be said to be a precipitate of In or a precipitate of indium oxide.

[0287] The above-mentioned In precipitates or indium oxide precipitates can be assumed to be In segregated on the surface of the In-Ga-Zn metal oxide target in the above-mentioned deposition model (for example, cluster 2196 ), which means that the above-mentioned deposition model is sufficiently appropriate.

[0288] Note that in the deposition Fig. 6A and Figure 6B In the case of the composite oxide semiconductor of one embodiment of the present invention shown in FIG. 1 , in the fourth step, it can be assumed that Fig. 12A and Fig. 12B The deposition model shown.

[0289] Fig. 12A and Fig. 12B yes Fig.9A and Fig. 9B The cross-sectional view of the target 2500a shown in FIG. Fig. 12A and Fig. 12B, a pad 2510a, a target material 2500a, a plasma 2190, cations 2192, sputtered particles 2194, etc. are shown.

[0290] exist Fig. 12A In the deposition chamber 2501 shown, argon gas or oxygen gas is ionized and separated into cations 2192 and electrons (not shown) to form plasma 2190. Then, the cations 2192 in the plasma 2190 are accelerated toward the target 2500a (here, the In-Ga-Zn metal oxide target). Since the cations 2192 collide with the In-Ga-Zn metal oxide target, sputtered particles 2194 are generated and ejected from the In-Ga-Zn metal oxide target.

[0291] Here, the target 2500a and the target 2500b have a polycrystalline structure including a plurality of crystal grains. In many cases, the diameter of each of the plurality of crystal grains is less than 10 μm. In addition, sometimes, for example, in an In-Ga-Zn metal oxide target having an atomic ratio of In:Ga:Zn=4:2:4.1 or 5:1:7, the plurality of crystal grains have different compositions.

[0292] For example, in Fig. 12A In the embodiment, the target 2500a includes at least a region 2502a where the ratio of In atoms is lower than the ratio of In atoms in the target and a region 2504a where the ratio of In atoms is higher than the ratio of In atoms in the target.

[0293] First, the region 2502a where the In ratio in the target 2500a is low will be described.

[0294] like Fig. 12A As shown, the positive ions 2192 generated in the high-density plasma region are accelerated by the electric field toward the target 2500a side, and then collide with the region 2502a included in the target 2500a. At this time, a cluster 2198 of flat nanocrystals is peeled off from the region 2502a. In many cases, the cluster includes two M-Zn-O layers and an In-O layer therebetween. Note that sputtered particles 2194 are also ejected from the target 2500a as the cluster 2198 is peeled off.

[0295] Sometimes, cluster 2198 includes a triangular plane, such as an equilateral triangle plane. Sometimes, cluster 2198 includes a hexagonal plane, such as an equilateral hexagonal plane. However, the shape of the plane of cluster 2198 is not limited to a triangle or a hexagon. For example, the plane may have a shape formed by combining more than two triangles. For example, a quadrangle (e.g., a rhombus) is formed by combining two triangles (e.g., equilateral triangles).

[0296] The thickness of cluster 2198 is determined by the type of deposition gas, etc. For example, the thickness of cluster 2198 is greater than or equal to 0.4 nm and less than or equal to 1 nm, preferably greater than or equal to 0.6 nm and less than or equal to 0.8 nm. In addition, for example, the width of cluster 2198 is greater than or equal to 1 nm and less than or equal to 3 nm, preferably greater than or equal to 1.2 nm and less than or equal to 2.5 nm.

[0297] When the sputtered particles 2194 pass through the plasma 2190, the surface of the sputtered particles 2194 may be negatively or positively charged. For example, the sputtered particles 2194 sometimes pass through the plasma 2190. 2 - As a result, the oxygen atoms on the surface of the sputtered particle 2194 may be negatively charged. In addition, when passing through the plasma 2190, the sputtered particle 2194 sometimes grows by bonding with In, element M, Zn, or oxygen in the plasma 2190. Therefore, the sputtered particle 2194 has an atom or a collection of multiple atoms.

[0298] The clusters 2198 and sputtered particles 2194 passing through the plasma 2190 reach the surface of the substrate. Since the clusters 2198 have a flat plate shape, they are deposited with one side of the plane facing the surface of the substrate. Note that part of the sputtered particles 2194 are discharged to the outside by a vacuum pump or the like because of their small mass.

[0299] Sputtered particles 2194 reach the surface of the substrate. Sputtered particles 2194 tend to bond to the side of clusters 2198 compared to the top surface of clusters 2198. Sputtered particles 2194 are preferentially deposited on the side of clusters 2198 in a manner that fills in areas where clusters 2198 are not formed. Since the bonds of available sputtered particles 2194 are in an active state, sputtered particles 2194 chemically bond to clusters 2198 to form lateral growth portions. In other words, sputtered particles 2194 enter the area between one cluster and another cluster.

[0300] The lateral growth portion grows in the lateral direction so as to fill a region between one cluster and another cluster (which may also be referred to as a lateral growth buffer region (LGBR)). The lateral direction refers to, for example, a direction perpendicular to the c-axis in the cluster.

[0301] The following reaction is likely to occur, in which sputtered particles adhere to the lateral growth portion of the cluster, oxygen diffused through the LGBR adheres to the sputtered particles, and other sputtered particles are similarly attached. It can be considered that the repetition of this reaction causes solid phase growth in the lateral direction. This lateral growth of the cluster can be called self-assembly.

[0302] The lateral growth parts further grow laterally and collide with each other. The adjacent clusters are connected with the part where the lateral growth parts collide with each other as the connecting part. In other words, the sputtered particles form lateral growth parts on the side of the cluster and cause lateral growth, thereby filling the area between one cluster and another cluster. In this way, the lateral growth parts are formed until the area where no cluster is formed is filled. This mechanism is similar to the deposition mechanism of the atomic layer deposition (ALD) method.

[0303] Therefore, when a plurality of clusters are formed so as to face different directions from each other, since the sputtered particles fill the gaps between clusters while growing laterally, a clear grain boundary is not formed, and a region B1 including CAAC-OS is formed.

[0304] Note that in CAAC-OS, the layered crystal structure is very stable within a wide range of composition, and the bond strength and equilibrium distance between metal atoms and oxygen atoms depend on the metal atoms. Therefore, it can be inferred that the crystal structure of CAAC-OS is tolerant to distortion. That is, the sputtered particles smoothly connect (fix) the clusters, thereby forming a crystal structure different from both single crystals and polycrystalline in the junction. In other words, the junction between adjacent clusters forms a distorted crystal structure. Thus, for example, in the junction, a crystal structure having a hexagonal top surface shape is sometimes deformed into a pentagon or a heptagon.

[0305] Next, the region 2504a having a high In ratio in the target 2500a will be described.

[0306] The positive ions 2192 generated in the high-density plasma region are accelerated toward the target 2500a side by the electric field, and then collide with the region 2504a included in the target 2500a. In the case of using an In-Ga-Zn metal oxide target, Ga and Zn are preferentially sputtered as sputtered particles 2194. That is, the positive ions 2192 collide with the In-Ga-Zn metal oxide target to preferentially eject Ga and Zn whose relative atomic mass is lower than In from the In-Ga-Zn metal oxide target. As described above, the ejected sputtered particles 2194 are deposited on the substrate to fill in the region between the clusters 2198 ejected from the region 2502a and deposited on the substrate, thereby forming a region B1.

[0307] In addition, if Fig. 12A As shown in FIG. 1 , after Ga and Zn are preferentially sputtered as sputtered particles 2194, a state of In segregation is obtained on the surface of the region 2504a with a high In ratio. Fig. 12A , segregated In is represented as clusters 2196. The diameter of clusters 2196 is preferably approximately not less than 0.5 nm and not more than 1.5 nm.

[0308] like Fig. 12BAs shown, after In segregation, that is, after cluster 2196 is formed, cluster 2196 is sputtered from region 2504a where the proportion of In is high.

[0309] Specifically, In segregated on the surface of the In-Ga-Zn metal oxide target is ejected from the In-Ga-Zn metal oxide target in the form of a plurality of granular clusters. The segregated In having a plurality of clusters is bonded to oxygen and collides with the previously deposited region B1, and deposits the region A1 having granular clusters. Note that since the segregated In is ejected, the In, Ga, and Zn existing on the surface of the region 2504a have an atomic number ratio close to the original atomic number ratio.

[0310] Note that Fig. 12A and Fig. 12B As shown, In segregates in one region of the surface of the region 2504a having a high In ratio in the target 2500a, and In segregated in other regions of the surface is ejected. That is, the mechanism of In segregation and the mechanism of ejection of segregated In occur simultaneously.

[0311] Therefore, the region 2504a with a high In ratio tends to form the region A1 because the cluster 2196 is easily formed therein. On the other hand, the region 2502a with a low In ratio tends to form the region B1 because the ejected clusters and sputtered particles are bonded with oxygen and deposited on the substrate.

[0312] As a result, the area A1 and the area B1 expand in a cloud-like manner and are unevenly and irregularly distributed. Fig. 6A and Figure 6B A composite oxide semiconductor according to one embodiment of the present invention is shown.

[0313] <1-9. Classification of Oxide Semiconductors>

[0314] Next, classification of oxide semiconductors will be described.

[0315] Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, a-like OS, and amorphous oxide semiconductors.

[0316] From another viewpoint, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, nc-OS, and the like.

[0317] Generally speaking, an amorphous structure has the following characteristics: it is isotropic but not inhomogeneous; it is in a metastable state and the configuration of atoms is not fixed; the bond angle is not fixed; it has short-range order but not long-range order; etc.

[0318] That is, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. In addition, an oxide semiconductor that does not have isotropy (for example, having a periodic structure in a tiny area) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS does not have isotropy but has an unstable structure with voids. In terms of instability, a-like OS is close to amorphous oxide semiconductors in terms of physical properties.

[0319] [CAAC-OS]

[0320] First, CAAC-OS is described.

[0321] CAAC-OS is a type of oxide semiconductor including a plurality of c-axis-aligned crystal parts (also referred to as grains).

[0322] CAAC-OS is an oxide semiconductor with high crystallinity. The crystallinity of an oxide semiconductor may be reduced due to the incorporation of impurities or the generation of defects. Therefore, it can be said that CAAC-OS has fewer impurities or defects (oxygen vacancies, etc.).

[0323] Note that impurities refer to elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element (especially silicon, etc.) that has a stronger bonding force with oxygen than the metal elements included in the oxide semiconductor will take oxygen from the oxide semiconductor, thereby disrupting the atomic arrangement of the oxide semiconductor, resulting in a decrease in crystallinity. Since heavy metals such as iron or nickel, argon, carbon dioxide, etc. have a large atomic radius (or molecular radius), they will disrupt the atomic arrangement of the oxide semiconductor, resulting in a decrease in crystallinity.

[0324] [nc-OS]

[0325] Next, nc-OS is described.

[0326] The following describes the analysis of nc-OS using an XRD device. When the structure of nc-OS is analyzed using the out-of-plane method, no peak indicating orientation appears. In other words, the crystals of nc-OS do not have orientation.

[0327] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductor. Therefore, the defect state density of nc-OS is lower than that of a-like OS or amorphous oxide semiconductor. Note that the regularity of crystal orientation is not observed between different particles in nc-OS. Therefore, the defect state density of nc-OS is sometimes higher than that of CAAC-OS.

[0328] [a-like OS]

[0329] The a-like OS has a structure between that of the nc-OS and that of the amorphous oxide semiconductor.

[0330] The a-like OS contains voids or low-density regions. Since the a-like OS contains voids, its structure is unstable.

[0331] Since a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is greater than 78.6% and less than 92.3% of a single-crystal oxide semiconductor having the same composition. The density of nc-OS and the density of CAAC-OS are greater than 92.3% and less than 100% of a single-crystal oxide semiconductor having the same composition. It is difficult to form an oxide semiconductor whose density is less than 78% of the density of a single-crystal oxide semiconductor.

[0332] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, a single crystal InGaZnO 4 The density is 6.357g / cm 3 Therefore, for example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, the density of a-like OS is 5.0 g / cm 3 Above and below 5.9g / cm 3 In an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, the density of nc-OS and CAAC-OS are both 5.9 g / cm 3 Above and below 6.3g / cm 3 .

[0333] In the case where an oxide semiconductor having a specific composition does not exist in a single crystal state, by combining single crystal oxide semiconductors of different compositions in an arbitrary ratio, the density of a single crystal oxide semiconductor of a desired composition can be estimated. The density of a single crystal oxide semiconductor having a desired composition can be estimated using a weighted average according to the combination ratio of single crystal oxide semiconductors of different compositions. Note that it is preferable to estimate the density by reducing the types of single crystal oxide semiconductors combined as much as possible.

[0334] As described above, oxide semiconductors have various structures and various characteristics. In the oxide semiconductor film according to one embodiment of the present invention, two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS may be mixed.

[0335] Note that the region A1 is preferably non-single crystal. The region B1 is preferably non-single crystal. The region A1 and the region B1 may have different crystallinity.

[0336] <1-10. Characteristics of transistors>

[0337] Next, refer to Fig.14A and Fig. 14B , Fig.15 , Fig.16 as well as FIG. 17A to FIG. 17C The general characteristics of transistors are described.

[0338] [Id-Vg characteristics of transistor]

[0339] First, drain current-gate voltage characteristics (Id-Vg characteristics) of a transistor will be described. Fig.14A This is a diagram illustrating an example of Id-Vg characteristics of a transistor. Fig.14A For the sake of clarity, the active layer of the transistor is shown as using polysilicon. Fig.14A In FIG. 5 , the vertical axis and the horizontal axis represent Id and Vg, respectively.

[0340] like Fig.14A As shown in the figure, the Id-Vg characteristic is roughly divided into three regions. The first region, the second region and the third region are called the cut-off region (OFF region), the subthreshold region (subthreshold region) and the conduction region (ON region) respectively. The gate voltage at the boundary between the subthreshold region and the conduction region is called the threshold voltage (Vth).

[0341] In order to obtain excellent characteristics of the transistor, it is preferred that the drain current (also called off-state current or Ioff) in the cut-off region is low and the drain current (also called on-state current or Ion) in the on-state region is high. In many cases, field effect mobility is used as an indicator of the on-state current of the transistor. The details of field effect mobility are described later.

[0342] In order to drive the transistor at a low voltage, it is preferred that the slope of the Id-Vg characteristic in the subthreshold region is steep. The index of the magnitude of the change in the Id-Vg characteristic of the subthreshold region is called the subthreshold swing value (SS) or S value. In addition, the S value is expressed by the following formula (1).

[0343] [Formula 1]

[0344]

[0345] The S value is the minimum value of the change in the gate voltage required for the drain current to change by one digit in the subthreshold region. The smaller the S value, the more sharply the switching operation can be performed between on and off.

[0346] [Id-Vd Characteristics of Transistor]

[0347] Next, the drain current-drain voltage characteristics (Id-Vd characteristics) of the transistor will be described. Fig. 14B is a diagram showing an example of the Id-Vd characteristics of a transistor. In Fig. 14B the vertical axis and the horizontal axis represent Id and Vd, respectively.

[0348] As Fig. 14B shown, the conduction region is also classified into two regions. The first region and the second region are called the linear region and the saturation region, respectively. In the linear region, the drain current increases parabolically as the drain voltage rises. On the other hand, in the saturation region, even if the drain voltage changes, the drain current hardly changes. Sometimes, according to vacuum tubes, the linear region is called the triode region and the saturation region is called the pentode region.

[0349] Sometimes the linear region refers to the state where Vg is higher than Vd (Vd < Vg). Sometimes the saturation region refers to the state where Vd is higher than Vg (Vg < Vd). Note that in reality, the threshold voltage of the transistor needs to be considered. Therefore, sometimes the value obtained by subtracting the threshold voltage of the transistor from the gate voltage (Vd < Vg - Vth) is called the linear region. Similarly, sometimes the value obtained by subtracting the threshold voltage of the transistor from the gate voltage (Vg - Vth < Vd) is called the saturation region.

[0350] In the Id-Vd characteristics of a transistor, sometimes the characteristic that the current in the saturation region is constant is called "good saturation". Good saturation of the transistor is particularly important when using a transistor in an organic EL display. For example, by using a transistor with good saturation as the transistor of a pixel in an organic EL display, even if the drain voltage changes, the change in the brightness of the pixel can be suppressed.

[0351] [Analysis Model of Drain Current]

[0352] Next, the analysis model of the drain current will be described. As an analysis model of the drain current, an analytical formula of the drain current based on the gradual channel approximation (GCA) is known. According to GCA, the drain current of the transistor is expressed by the following formula (2).

[0353] [Formula 2]

[0354]

[0355] In formula (2), the upper formula is the formula for the drain current in the linear region, and the lower formula is the formula for the drain current in the saturation region. In formula (2), Id represents the drain current, μ represents the mobility of the active layer, L represents the channel length of the transistor, W represents the channel width of the transistor, Cox represents the gate capacitance, Vg represents the gate voltage, Vd represents the drain voltage, and Vth represents the threshold voltage of the transistor.

[0356] [Field effect mobility]

[0357] Next, the field effect mobility is explained. Field effect mobility is used as an indicator of the current driving force of the transistor. As mentioned above, the conduction region of the transistor is classified into a linear region and a saturation region. The field effect mobility of the transistor can be calculated from the characteristics of each region according to the analytical formula of the drain current of GCA. When it is necessary to distinguish, the field effect mobility in the linear region and the field effect mobility in the saturation region are respectively referred to as linear mobility (Linear mobility) and saturation mobility (Saturation mobility). The linear mobility is expressed by the following formula (3), and the saturation mobility is expressed by the following formula (4).

[0358]

[0359] In this specification and the like, the curve calculated from the formula (3) and the formula (4) is referred to as a mobility curve. Fig.15 The mobility curve calculated from the analysis of the drain current of GCA is shown. Fig.15 In FIG. 1 , Id-Vg characteristics at Vd=10 V when GCA is effective are shown superimposed on mobility curves of linear mobility and saturation mobility.

[0360] exist Fig.15 In the example above, the Id-Vg characteristic is calculated from the analytical formula of the drain current of GCA. The shape of the mobility curve helps to understand the internal state of the transistor.

[0361] As an example, Fig.16 The measured Id-Vg characteristics of a FET including CAAC-OS are shown. Fig.16 In FIG. 1 , the Id-Vg characteristics of the FET, the mobility curves of the saturation mobility, and the linear mobility are shown together. Note that an oxide semiconductor (IGZO) film with an atomic ratio of In:Ga:Zn=1:1:1 is used as the semiconductor layer of the FET. The mobility curves of the saturation mobility and the linear mobility are both obtained from the Id-Vg characteristics at Vd=10V.

[0362] like Fig.16 As shown, when the shape of the FET follows the GCA, the curve of the saturation mobility becomes flat in the saturation region and gradually decreases in the linear region.

[0363] <1-11. Fabrication of transistor for evaluating characteristics>

[0364] Next, the structure of a transistor according to one embodiment of the present invention is described, and evaluation results of electrical characteristics of the manufactured transistor are shown.

[0365] [Transistor Structure Example 1]

[0366] Fig.17A is a top view of transistor 100A. Fig. 17B It is along Fig.17A A cross-sectional view along the dotted line X1-X2. Fig. 17C It is along Fig.17A A cross-sectional view of the dotted line Y1-Y2. Fig.17A In the figure, for the sake of simplicity, the insulating film 110 and other components are omitted. Fig.17A In the same manner, some of the components are omitted. In addition, the dashed line X1-X2 direction is sometimes referred to as the channel length (L) direction, and the dashed line Y1-Y2 direction is sometimes referred to as the channel width (W) direction.

[0367] FIG. 17A to FIG. 17C The transistor 100A shown includes a conductive film 106 on a substrate 102, an insulating film 104 on the conductive film 106, an oxide semiconductor film 108 on the insulating film 104, an insulating film 110 on the oxide semiconductor film 108, a conductive film 112 on the insulating film 110, and an insulating film 116 on the insulating film 104, the oxide semiconductor film 108, and the conductive film 112. Note that the oxide semiconductor film 108 includes a channel region 108i overlapping with the conductive film 112, a source region 108s in contact with the insulating film 116, and a drain region 108d in contact with the insulating film 116.

[0368] In addition, the insulating film 116 contains nitrogen or hydrogen. The insulating film 116 is in contact with the source region 108s and the drain region 108d, and the nitrogen or hydrogen in the insulating film 116 is added to the source region 108s and the drain region 108d. When nitrogen or hydrogen is added to the source region 108s and the drain region 108d, the carrier density is improved.

[0369] The transistor 100A may also include an insulating film 118 on the insulating film 116, a conductive film 120a electrically connected to the source region 108s via an opening 141a provided in the insulating films 116 and 118, and a conductive film 120b electrically connected to the drain region 108d via an opening 141b provided in the insulating films 116 and 118. In addition, an insulating film 122 may be provided on the insulating film 118, the conductive film 120a, and the conductive film 120b. Fig. 17B and Fig. 17C 2 shows a structure in which the insulating film 122 is provided, but one embodiment of the present invention is not limited thereto, and the insulating film 122 does not necessarily need to be provided.

[0370] In this specification and the like, the insulating film 104 is referred to as a first insulating film, the insulating film 110 is referred to as a second insulating film, the insulating film 116 is referred to as a third insulating film, the insulating film 118 is referred to as a fourth insulating film, and the insulating film 122 is referred to as a fifth insulating film. The insulating film 104 is used as a first gate insulating film, the insulating film 110 is used as a second gate insulating film, the insulating films 116 and 118 are used as protective insulating films, and the insulating film 122 is used as a planarizing insulating film.

[0371] The insulating film 110 includes an excess oxygen region. Since the insulating film 110 includes the excess oxygen region, excess oxygen can be supplied to the channel region 108i included in the oxide semiconductor film 108. Therefore, since oxygen vacancies that would be formed in the channel region 108i can be filled with excess oxygen, a semiconductor device with high reliability can be provided.

[0372] In order to supply excess oxygen to the oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108. In this case, the excess oxygen contained in the insulating film 104 may be supplied to the source region 108s and the drain region 108d included in the oxide semiconductor film 108. When excess oxygen is supplied to the source region 108s and the drain region 108d, the resistance of the source region 108s and the drain region 108d may increase.

[0373] On the other hand, when the insulating film 110 formed on the oxide semiconductor film 108 contains excess oxygen, the excess oxygen may be selectively supplied only to the channel region 108i. Alternatively, after the excess oxygen is supplied to the channel region 108i, the source region 108s, and the drain region 108d, the carrier density of the source region 108s and the drain region 108d may be selectively increased, thereby preventing the resistance of the source region 108s and the drain region 108d from increasing.

[0374] In addition, each of the source region 108s and the drain region 108d included in the oxide semiconductor film 108 preferably has an element that forms an oxygen vacancy or an element that bonds to the oxygen vacancy. Typical examples of elements that form the oxygen vacancy or elements that bond to the oxygen vacancy include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements are helium, neon, argon, krypton, and xenon. When the insulating film 116 contains one or more of the above elements, the element that forms the oxygen vacancy diffuses from the insulating film 116 to the source region 108s and the drain region 108d. In addition, or alternatively, the above-mentioned element that forms the oxygen vacancy can also be added to the source region 108s and the drain region 108d by impurity addition treatment.

[0375] When an impurity element is added to an oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is cut off to form an oxygen vacancy. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, and oxygen is separated from the metal element to form an oxygen vacancy. As a result, the carrier density in the oxide semiconductor film increases and the conductivity is improved.

[0376] The conductive film 106 serves as a first gate electrode, and the conductive film 112 serves as a second gate electrode. The conductive film 120a serves as a source electrode, and the conductive film 120b serves as a drain electrode.

[0377] like Fig. 17C As shown, the opening 143 is provided in the insulating films 104 and 110. The conductive film 106 is electrically connected to the conductive film 112 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112. Note that the opening 143 may not be provided, and different potentials may be applied to the conductive film 106 and the conductive film 112. Alternatively, the opening 143 may not be provided, and the conductive film 106 may be used as a light shielding film. For example, when the conductive film 106 is formed using a light shielding material, light irradiated from below to the channel region 108i can be reduced.

[0378] like Fig. 17B and Fig. 17C As shown, the oxide semiconductor film 108 faces each of the conductive film 106 serving as a first gate electrode and the conductive film 112 serving as a second gate electrode, and is sandwiched between the two conductive films serving as gate electrodes.

[0379] In addition, the length of the conductive film 112 in the channel width direction is greater than that of the oxide semiconductor film 108 in the channel width direction. In the channel width direction, the entire oxide semiconductor film 108 is covered by the conductive film 112 with the insulating film 110 sandwiched therebetween. Since the conductive film 112 and the conductive film 106 are connected via the opening 143 provided in the insulating film 104 and the insulating film 110, one side of the oxide semiconductor film 108 is opposite to the conductive film 112 with the insulating film 110 sandwiched therebetween in the channel width direction.

[0380] In other words, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive film 112 are connected via the opening 143 provided in the insulating film 104 and the insulating film 110 , and surround the oxide semiconductor film 108 with the insulating film 104 and the insulating film 110 interposed therebetween.

[0381] By adopting the above structure, the oxide semiconductor film 108 included in the transistor 100A can be electrically surrounded by the electric field of the conductive film 106 used as the first gate electrode and the conductive film 112 used as the second gate electrode. As in the transistor 100A, the device structure of the transistor in which the oxide semiconductor film 108 having a channel region is electrically surrounded by the electric field of the first gate electrode and the second gate electrode can be called a surrounded channel (S-channel) structure. Note that the transistor 100A can also be called a dual-gate structure due to the number of its gate electrodes.

[0382] Since the transistor 100A has an S-channel structure, an electric field for causing a channel can be effectively applied to the oxide semiconductor film 108 using the conductive film 106 or the conductive film 112. As a result, the current driving capability of the transistor 100A is improved, so that a high on-state current characteristic can be obtained. Since the on-state current can be increased, the transistor 100A can be miniaturized. In addition, since the transistor 100A has a structure in which the oxide semiconductor film 108 is surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100A can be improved.

[0383] Note that an opening different from the opening 143 may be formed on the side of the oxide semiconductor film 108 where the opening 143 is not formed in the channel width direction of the transistor 100A.

[0384] Note that the transistor 100A may also be referred to as a top gate self-aligned (TGSA) FET depending on the position of the conductive film 112 relative to the oxide semiconductor film 108 and the method of forming the conductive film 112. Note that the semiconductor device according to one embodiment of the present invention is not limited to this, and may be a bottom gate top contact (BGTC) FET.

[0385] [Formation of transistor]

[0386] Next, a transistor equivalent to the transistor 100A is formed, and the electrical characteristics of the transistor are evaluated. In this embodiment, samples S1A to S1C shown below are manufactured. Note that each of the samples S1A to S1C is a sample in which a transistor having a channel length L of 2 μm and a channel width W of 3 μm is formed. The sample S1A is an oxide semiconductor film 108 including Figure 4A and Figure 4B The composite oxide semiconductor shown in the sample S1B as the oxide semiconductor film 108 includes Figure 5A and Figure 5B The composite oxide semiconductor shown in the sample S1C as the oxide semiconductor film 108 includes Fig. 6A and Figure 6B The composite oxide semiconductor shown.

[0387] [Formation Method of Samples S1A to S1C]

[0388] First, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed on a glass substrate using a sputtering device, and then the conductive film was processed using a photolithography method.

[0389] A stack of four insulating films is formed on the substrate and the conductive film. Insulating films are continuously formed in a vacuum using a plasma enhanced chemical vapor deposition (PECVD) device. As insulating films, a 50nm thick silicon nitride film, a 300nm thick silicon nitride film, a 50nm thick silicon nitride film, and a 50nm thick silicon oxynitride film are sequentially stacked.

[0390] Next, an oxide semiconductor film is formed over the insulating film and processed into an island shape, thereby forming a semiconductor layer. A 40 nm thick oxide semiconductor film is formed as the oxide semiconductor film 108. Note that the oxide semiconductor film is the above-mentioned composite oxide semiconductor or C / IGZO.

[0391] The oxide semiconductor film of sample S1A was formed under the following conditions: the substrate temperature was room temperature (25°C); argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm were introduced into the chamber of the sputtering device; the pressure was set to 0.6 Pa; and 2.5 kw of AC power was applied to a metal oxide target containing indium, gallium and zinc (In:Ga:Zn=4:2:4.1 [atomic number ratio]). The oxygen flow ratio in the deposition of the oxide semiconductor film of sample S1A was 10%.

[0392] Next, an insulating film is formed on the insulating film and the oxide semiconductor layer. As the insulating film, a silicon oxynitride film is formed to a thickness of 150 nm using a PECVD apparatus.

[0393] Next, a heat treatment is performed at 350° C. for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.

[0394] An opening is formed in a desired region of the insulating film by dry etching.

[0395] Next, an oxide semiconductor film with a thickness of 100 nm is formed on the insulating film and in the opening, and the oxide semiconductor film is processed into an island shape to form a conductive film. In addition, after the conductive film is formed, the insulating film in contact with the lower side of the conductive film is continuously processed to form an insulating film.

[0396] As a conductive film, an oxide semiconductor film with a thickness of 10nm, a titanium nitride film with a thickness of 50nm, and a copper film with a thickness of 100nm are formed in sequence. The oxide semiconductor film is formed under the following conditions: the substrate temperature is 170°C; an oxygen gas with a flow rate of 200sccm is introduced into the chamber of the sputtering device; the pressure is set to 0.6Pa; and 2.5kw of AC power is applied to a metal oxide target containing indium, gallium and zinc (In:Ga:Zn=4:2:4.1 [atomic number ratio]). The titanium nitride film and the copper film are formed using a sputtering device.

[0397] Next, plasma treatment is performed on the oxide semiconductor film, the insulating film, and the conductive film using a PECVD apparatus at a substrate temperature of 220° C. in a mixed gas atmosphere containing argon gas and nitrogen gas.

[0398] Next, an insulating film is formed on the oxide semiconductor film, the insulating film, and the conductive film. The insulating film is formed by stacking a 100 nm thick silicon nitride film and a 300 nm thick silicon oxynitride film using a PECVD device.

[0399] Next, a mask is formed on the formed insulating film, and an opening is formed in the insulating film using the mask.

[0400] A conductive film was formed to fill the openings and processed into islands to form conductive films used as source and drain electrodes. As the conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed using a sputtering device.

[0401] Then, an insulating film was formed on the insulating film and the conductive film. As the insulating film, an acrylic photosensitive resin having a thickness of 1.5 μm was used.

[0402] Through the above steps, sample S1A is formed.

[0403] Sample S1B was formed in the same manner as sample S1A except for the formation conditions of the oxide semiconductor film. The oxide semiconductor film of sample S1B was formed under the following conditions: the substrate temperature was room temperature (25°C); argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber of the sputtering device; the pressure was set to 0.6 Pa; and 2.5 kw of AC power was applied to a metal oxide target containing indium, gallium and zinc (In:Ga:Zn=4:2:4.1 [atomic number ratio]). The oxygen flow ratio in the deposition of the oxide semiconductor film of sample S1B was 50%.

[0404] Sample S1C was formed in the same manner as sample S1A except for the formation conditions of the oxide semiconductor film. The oxide semiconductor film of sample S1C was formed under the following conditions: the substrate temperature was room temperature (25°C); an oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering device; the pressure was set to 0.6 Pa; and 2.5 kw of AC power was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic number ratio]). The oxygen flow ratio in the deposition of the oxide semiconductor film of sample S1C was 100%.

[0405] [Id-Vg characteristics of transistor]

[0406] Next, the Id-Vg characteristics of the transistors of samples S1A to S1C were measured. As the measurement conditions of the Id-Vg characteristics of the transistors, the voltage applied to the conductive film used as the first gate electrode (hereinafter, also referred to as the gate voltage (Vg)) and the voltage applied to the conductive film used as the second gate electrode (hereinafter, also referred to as the back gate voltage (Vbg)) were changed from -10V to +10V at intervals of 0.25V. The voltage applied to the conductive film used as the source electrode (hereinafter, also referred to as the source voltage (Vs)) was set to 0V (comm), and the voltage applied to the conductive film used as the drain electrode (hereinafter, also referred to as the drain voltage (Vd)) was set to 0.1V and 20V.

[0407] Figure 1 The Id-Vg characteristic results of sample S1A are shown. Figure 2 The Id-Vg characteristic results of sample S1B are shown. Figure 3 The Id-Vg characteristic results of sample S1C are shown. Figures 1 to 3 In the figure, the first vertical axis represents Id (A), and the second vertical axis represents field effect mobility (μ FE (cm 2 / Vs)), and the horizontal axis represents Vg (V). Note that the field effect mobility was measured at Vd=20V.

[0408] like Figure 1As shown in Table 2, the transistor of the semiconductor device according to one embodiment of the present invention has good electrical characteristics. Figure 1 The characteristics of the transistor are shown.

[0409] [Table 2]

[0410]

[0411] As shown in Table 2, the maximum field effect mobility of the transistors in the sample S1A with a gate voltage higher than 0 V and lower than 10 V is 40 cm 2 / Vs or more and less than 150cm 2 / Vs, a first region with a threshold voltage of -1V or more and 1V or less, a third region with an S value of less than 0.3V / decade, and an off-state current of less than 1×10 -12 A / cm 2 The fourth region, in μ FE (max) represents the maximum value of the field effect mobility of the transistor, μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is greater than or equal to 1 and less than 1.5.

[0412] like Figure 2 As shown in Table 3, the transistor of the semiconductor device according to one embodiment of the present invention has good electrical characteristics. Figure 2 The characteristics of the transistor are shown.

[0413] [Table 3]

[0414]

[0415] As shown in Table 3, the maximum field effect mobility of the transistors in the sample S1B with a gate voltage higher than 0 V and lower than 10 V is 40 cm 2 / Vs or more and less than 150cm 2 / Vs, a first region with a threshold voltage of -1V or more and 1V or less, a third region with an S value of less than 0.3V / decade, and an off-state current of less than 1×10 -12 A / cm 2 The fourth region, in μ FE (max) represents the maximum value of the field effect mobility of the transistor, μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is 1.5 or more and less than 3.

[0416] like Figure 3 As shown in Table 4, the transistor of the semiconductor device according to one embodiment of the present invention has good electrical characteristics. Figure 3 The characteristics of the transistor are shown.

[0417] [Table 4]

[0418]

[0419] As shown in Table 4, the maximum field effect mobility of the transistors of sample S1C including the gate voltage higher than 0 V and lower than 10 V is 10 cm 2 / Vs or more and less than 100cm 2 / Vs, a first region with a threshold voltage of -1V or more and 1V or less, a third region with an S value of less than 0.3V / decade, and an off-state current of less than 1×10 -12 A / cm 2 The fourth region, in μ FE (max) represents the maximum value of the field effect mobility of the transistor, μ FE (Vg = 2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, μ FE (max) / μ FE (Vg=2V) is 3 or more and less than 10.

[0420] The above transistor characteristics can be obtained by using the above composite oxide semiconductor or C / IGZO. In a transistor including the composite oxide semiconductor C / IGZO as a semiconductor layer, a function of high carrier mobility and a function of good switching characteristics can be obtained at the same time.

[0421] <1-12. Evaluation of the shape of the mobility curve by device simulation>

[0422] Next, device simulations were performed to investigate the Figure 1 The shape of the mobility curve of the field effect mobility of the transistor shown is evaluated.

[0423] In device simulation, three factors are assumed as factors determining the shape of the mobility curve: 1. temperature dependence of mobility; 2. donor density distribution in the channel region; and 3. shallow defect state density (also called sDOS) in the oxide semiconductor film.

[0424] [1. Temperature dependence of mobility]

[0425] In a transistor including an oxide semiconductor film, field effect mobility increases sharply due to self-heating. The electron mobility (μ n ) is expressed by the following formula (5).

[0426] [Formula 5]

[0427]

[0428] In formula (5), μ n 300 represents the electron mobility of the oxide semiconductor film at room temperature, T L represents the lattice temperature. As shown in formula (5), the field effect mobility of a transistor including an oxide semiconductor film increases in proportion to the temperature T raised to the power of about 1.5.

[0429] [2. Donor density distribution in the channel region]

[0430] Here, refer to Fig.18 The effective channel lengths of the transistors of Samples S1A to S1C are described.

[0431] Fig.18 A schematic diagram illustrating the concept of the effective channel length of a transistor.

[0432] exist Fig.18 In FIG. 1 , GE, GI, and OS represent a gate electrode, a gate insulating film, and an oxide semiconductor film, respectively. In the oxide semiconductor film, an n-type region is formed. The effective channel length (L eff ) is expressed by the formula (6) shown below.

[0433] [Formula 6]

[0434] L eff =L g -2ΔL (6)

[0435] In formula (6), L g represents the gate length, and ΔL represents the reduction width of the channel length.

[0436] The effective channel length of the transistor can be obtained, for example, through transmission line model (TLM) analysis.

[0437] In the following description, a model is assumed in which the donor density gradually decreases from the n-type region to the channel region based on the above-mentioned effective channel length. In other words, the donor density decreases toward the channel region according to a Gaussian distribution. FIG. 19A to FIG. 19C A schematic diagram illustrating the donor density in the channel region is shown.

[0438] Fig.19A , Fig.19B and Fig.19C The donor density of sample S1A, the donor density of sample S1B, and the donor density of sample S1C are respectively shown.

[0439] exist FIG. 19A to FIG. 19CIn FIG, GE, GI, and OS represent a gate electrode, a gate insulating film, and an oxide semiconductor film, respectively. FIG. 19A to FIG. 19C In the oxide semiconductor film shown, the donor density is 5×10 18 cm -3 The area above is shown in gray, with a donor density of 1×10 16 cm -3 The following areas are shown in black.

[0440] from Fig.19A , Fig.19B and Fig.19C The results shown, Fig.19A , Fig.19B and Fig.19C The effective channel lengths of the transistors shown are estimated to be 2.0 μm, 1.2 μm, and 0.8 μm, respectively. Fig.19A The ΔL of the transistor, Fig.19B The ΔL of the transistor and Fig.19C The ΔL of the transistors are estimated to be 0μm, 0.4μm and 0.6μm respectively.

[0441] [3. Shallow defect state density in oxide semiconductor film]

[0442] Next, the shallow defect state density (also referred to as sDOS) in the oxide semiconductor film is described. The sDOS of the oxide semiconductor film can be estimated from the electrical characteristics of the transistor including the oxide semiconductor film. In the following description, the interface state density of the transistor is measured. In addition, the interface state density and the number of electrons trapped by the interface state N are considered. trap A method to predict the subthreshold leakage current under the condition of

[0443] By comparing the measured value of the drain current-gate voltage (Id-Vg) of the transistor with the calculated drain current-gate voltage (Id-Vg) characteristics, the number of electrons N trapped in the interface state can be evaluated. trap .

[0444] Fig. 20 The ideal Id-Vg characteristics calculated when the source voltage Vs = 0 V and the drain voltage Vd = 0.1 V and the measured Id-Vg characteristics of the transistor are shown. Note that in the measurement results of the transistor, only the 1×10 -13 A or above.

[0445] Compared to the ideal Id-Vg characteristic obtained by calculation, the change of drain current Id with respect to gate voltage Vg in the actually measured Id-Vg characteristic is slow. This is because electrons are trapped in shallow defect states located near the energy (recorded as Ec) at the bottom of the conduction band. In this measurement, the number of electrons (per unit area and per unit energy) trapped in shallow interface states, N, is considered by using the Fermi distribution function. trap , the interface state density N can be estimated more rigorously it .

[0446] First, use Fig.21 The schematic Id-Vg characteristics shown evaluate the number of electrons N trapped in the interface trap state. trap The dotted line shows the ideal Id-Vg characteristic without trap states obtained by calculation. The change in gate voltage Vg when the drain current changes from Id1 to Id2 on the dotted line is called ΔV id The solid line shows the measured Id-Vg characteristic. The change in gate voltage Vg when the drain current changes from Id1 to Id2 on the solid line is called ΔV ex The potential of the interface to be observed when the drain current is Id1, the potential of the interface to be observed when the drain current is Id2, and the amount of change are respectively referred to as φ it1 ,φ it2 and Δφ it .

[0447] exist Fig.21 The measured value has a smaller slope than the calculated value, so we know that ΔV ex Constant ratio ΔV id At this time, ΔV ex With ΔV id The difference between is equivalent to the potential difference required to capture electrons in the shallow interface state. Therefore, the charge change ΔQ caused by the captured electrons can be expressed by the following formula (7): trap .

[0448] [Formula 7]

[0449] ΔQ trap =-C tg (ΔV ex -ΔV id ) (7)

[0450] C tg is the combined capacitance of the insulator and semiconductor per area. Alternatively, the number of electrons trapped (per unit area and per unit energy) N can be used trap ΔQ is expressed by formula (8): trap . Note that q represents the elementary charge.

[0451] [Formula 8]

[0452] ΔQ trap =-qN trap Δφ it (8)

[0453] By combining formula (7) and formula (8), we can get formula (9).

[0454] [Formula 9]

[0455] -C tg (ΔV ex -ΔV id )=-qN trap Δφ it (9)

[0456] Next, by taking Δφ in formula (9) it The limit of is zero, and we can get formula (10).

[0457] [Formula 10]

[0458]

[0459] That is, by using the ideal Id-Vg characteristics, the measured Id-Vg characteristics and formula (10), the number of electrons trapped at the interface N can be estimated. trap Note that the relationship between the drain current and the potential at the interface can be obtained by calculation using the above-mentioned device simulator.

[0460] The number of electrons per unit area and unit energy N can be expressed by formula (11): trap and interface state density N it The relationship between.

[0461] [Formula 11]

[0462]

[0463] Here, f(E) is the Fermi distribution function. By fitting N obtained from formula (10) with formula (11), trap , determine N it By using the N it The device simulator calculates the transfer characteristics including Id<0.1pA.

[0464] exist Fig. 20 In the figure, the white circle shows the application of formula (10) to Fig. 22 The measured Id-Vg characteristics shown in the figure are extracted from N trap result. Fig. 22The vertical axis in represents the Fermi level Ef from the bottom of the semiconductor conduction band Ec. The maximum value is just below Ec on the dotted line. When used as N in formula (11) it Assuming the tail distribution in formula (12), Fig. 22 As shown in the dashed line, N can be fitted with very high accuracy. trap As a result, the peak value N is obtained as the fitting reference value. ta =1.67×10 13 cm -2 eV, and characteristic width W ta =0.105eV.

[0465] [Formula 12]

[0466]

[0467] Fig.23A and Fig. 23B The result of back-calculating the Id-Vg characteristics by feeding back the obtained fitting curve of the interface state to the calculation using the device simulator is shown. Fig.23A The Id-Vg characteristics obtained by calculation when the drain voltage Vd is 0.1 V and 1.8 V, and the measured Id-Vg characteristics of the transistor when the drain voltage Vd is 0.1 V and 1.8 V are shown. Fig. 23B So Fig.23A A graph of the drain current Id as a logarithm.

[0468] The curve obtained by calculation is roughly consistent with the graph of the measured value, which shows that the calculated value and the measured value have a high reproducibility. Therefore, it can be seen that the above method is sufficiently appropriate as a method for calculating the shallow defect state density.

[0469] [4. Calculation results of mobility curve]

[0470] The sDOS in the oxide semiconductor film affects the mobility curve of the field effect mobility. In particular, near the threshold voltage, the shape of the mobility curve changes because electrons are trapped by the sDOS. The sDOS in the oxide semiconductor film is given by N in formula (12): ta With W ta With thickness t OS Then, the mobility curve is calculated according to the above formula (12). Table 5 shows the parameters used for calculation.

[0471] [Table 5]

[0472]

[0473] In this embodiment, the change W is calculated ta Mobility curve for the case of . Fig.24Show W ta The shape of the mobility curve for different values ​​of Fig.24 In, N ta =2.5×10 19 cm -3 eV -1 And ΔL = 0. In addition, there are seven conditions, namely W ta It is 0.015eV, 0.02eV, 0.025eV, 0.03eV, 0.035eV, 0.04eV and 0.045eV.

[0474] like Fig.24 As shown, W ta The smaller the value of , that is, the narrower the energy width of sDOS, the more sharply the mobility curve rises. In addition, it can be seen that the narrower the energy width of sDOS, the peak of the mobility curve drifts from the high Vg side to the low Vg side and decreases.

[0475] [5. Impact of diffusion current on mobility curve]

[0476] Next, the influence of diffusion current on the mobility curve is described. The drain current of FET is expressed by the following formula (13).

[0477] [Formula 13]

[0478]

[0479] As shown in formula (13), the drain current is the sum of the drift current component and the diffusion current component. Note that in formula (13), the first term and the second term represent the drift current and the diffusion current, respectively. Fig.25 It is a schematic diagram for explaining the contribution of the diffusion current and drift current components to the Id-Vg characteristics.

[0480] The influence of the diffusion current component on the mobility curve (saturation) is estimated through device simulation. Assuming that the active layer of FET is an oxide semiconductor, the source region and the drain region are n + The calculation conditions are shown in Table 6. Note that the interface between the GI and the active layer and the trap states (eg, sDOS) in the active layer are not assumed.

[0481] [Table 6]

[0482] Channel length 6μm Channel width 50μm OS film thickness 35nm GI film thickness 256nm Purification membrane thickness 480nm OS mobility <![CDATA[10(cm 2 / V sec)]]> Donor density in the channel <![CDATA[6.6E-9(1 / cm 3 )]]> Donor density under positive S / D <![CDATA[1.0E+19(1 / cm 3 )]]> Leakage voltage 0.1V,10V

[0483] Fig.26 The Id-Vg characteristics and saturation mobility curves obtained by simulation are shown in FIG. Fig.26 In the graph, the Id-Vg characteristic and the saturation mobility curve overlap each other. Fig.26As shown, the mobility curve has a peak near Vth of the Id-Vg characteristic.

[0484] Fig. 27 Schematic diagram showing the band diagram in the thickness direction of a dual-gate FET.

[0485] like Fig. 27 As shown, the band is relatively flat in the thickness direction of the semiconductor due to the gate electric field and current flows through the entire semiconductor film. In a dual-gate FET having such a band, the drain current in the subthreshold region is expressed by the following formula (14).

[0486] [Formula 14]

[0487]

[0488] In formula (14), k represents the Boltzmann constant, T represents the temperature, and n i represents the intrinsic carrier density, t s represents the thickness of the active layer, and Δφ represents the difference between the intrinsic Fermi level and the work function of the gate. Formula (14) means that the diffusion current is proportional to the difference between the diffusion current density at the end of the source region and the diffusion current density at the end of the drain region.

[0489] By substituting equation (14) into the equation defining the saturation mobility, equation (15) can be obtained.

[0490] [Formula 15]

[0491]

[0492] According to formula (15), the saturation mobility curve has a peak near Vth. That is, the peak near Vth of the saturation mobility curve is caused by the diffusion current flowing through the entire active layer, and this peak is observed in an ideal simulation without assuming trap states such as sDOS.

[0493] However, in the actual mobility curve of IGZO-FET, such a sharp peak near Vth is not observed. If it is assumed that there is a shallow electron trap state (i.e., sDOS) in the OS film or at the interface between the OS film and the gate insulating film, the mobility curve can be made close to the shape of the measured mobility curve. Fig.28 The device simulation results when sDOS is assumed in the OS film are shown.

[0494] Fig.28 This indicates that the sDOS in the OS film affects the mobility curve. The thicker the OS film, the more sDOS there is in the OS film. Therefore, the thicker the OS film, the lower the field effect mobility. Fig.29The relationship between the field effect mobility (maximum value) of FET and the OS film thickness is shown.

[0495] exist Fig.29 In FIG. 1 , the vertical axis represents the field effect mobility (maximum value), and the horizontal axis represents the OS film thickness. Fig.29 In the figure, the results of transistors with four different channel lengths (L) (L = 2 μm, 3 μm, 6 μm and 10 μm) overlap with each other. Fig.29 As shown in FIG. 1 , the thicker the OS film, the lower the field effect mobility.

[0496] Fig. 30A and Fig. 30B The saturation mobility curves calculated under different conditions of sDOS distribution are shown. Fig. 30A The distribution of sDOS in the OS film is shown. Fig. 30B The shape of the mobility curve is shown in Fig. 30A and Fig. 30B As shown by the arrow in FIG. 1 , the shape of the saturation mobility curve changes depending on the amount of energy levels of sDOS or the distribution of sDOS.

[0497] [6. Influence of parasitic resistance of source and drain regions]

[0498] Next, the influence of parasitic resistance of the source region and drain region (also called SD region) of TGSA OS-FET is described. TGSA OS-FET includes a source region and a drain region formed by reducing the resistance of the active layer on both sides of the channel region. Sometimes the source region and the drain region play the role of parasitic resistance in FET characteristics. In this case, Fig.31A As shown, the TGSA OS-FET is represented by a circuit diagram.

[0499] In is Fig.31A In the case of the circuit diagram shown, Vd is divided into the voltage applied to the two parasitic resistors and the voltage applied to the FET as shown in formula (16).

[0500] [Formula 16]

[0501] V d =RI d +V FET +RI d (16)

[0502] In formula (16), R represents the parasitic resistance, V FET Represents the potential difference applied to the two ends of the FET channel. In the GCA formula, V FET = Vg-Vth The region above Vg is considered to be the linear region. Fig.31AAs shown in the figure, in the case of parasitic resistance, the Vg in the linear region is formed compared with the case without parasitic resistance, that is, V FET =Vg-Vth has a lower Vg.

[0503] like Fig.15 As shown in FIG. 1 , the saturation mobility decreases after entering the linear region. In view of this, it can be considered that the greater the resistance value of the parasitic resistor, the lower the Vg of the lower limit of the linear region. Therefore, by simulating the device with the size of the source region and the drain region changed, the relationship between the field effect mobility and Vg is obtained. Fig.31B The device simulation results are shown in Figure 2. Fig.31B As shown, the size of the source region and the drain region formed to reduce the resistance of the active layer is increased to increase the parasitic resistance, thereby lowering the Vg of the lower limit of the linear region, that is, the Vg at which the saturation mobility curve starts to decrease.

[0504] [7. Effect of self-heating]

[0505] Next, the effect of FET's self-heating is explained. When current flows through FET, FET generates heat. The greater the current, the greater the heat generated. This is obvious from Joule's law. In addition, the greater the Vg, the greater the current in the FET. According to Joule's law, the greater the Vg, the greater the self-heating of the FET.

[0506] According to the above GCA, as shown in formula (2), the drain current in the saturation region is related to (Vg-Vth) 2 Therefore, when the square root of the drain current is plotted, a straight line is obtained in the saturation region. The slope of the straight line portion is calculated by differentiation, and the calculation result is normalized using the channel length, channel width, and gate capacitance to convert them into mobility, thereby obtaining the saturation mobility.

[0507] The explicit variable of temperature is not included in the GCA formula, so it seems that the saturation mobility does not depend on temperature. However, in OS-FET, part of the parameters included in GCA has temperature dependence. Therefore, the shape of the saturation mobility curve is changed by the influence of the self-heating of the FET.

[0508] The first parameter that changes with temperature is the electron mobility of IGZO. The higher the temperature, the higher the electron mobility of IGZO. That is, if the amount of current flowing through the FET increases and the temperature of the FET rises, the electron mobility of IGZO increases. Therefore, under the condition of high Vg or Vd, the temperature of the FET increases due to self-heating, so the electron mobility increases and the drain current increases. Therefore, the slope of the √Id-Vg characteristic in the saturation region increases, and the saturation mobility increases. The influence of self-heating of the FET is measured using an analog device. Fig.32 The device simulation results are shown in Fig.32, the calculation results of the Id-Vg characteristics and saturation mobility curve of the TGSA CAAC-OS-FET are shown.

[0509] The effect of FET self-heating is particularly significant in TGSA. This is because TGSA FET is less likely to heat up than BGTC FET.

[0510] BGTC FET has excellent heat dissipation performance because the source electrode and drain electrode are located near the channel region where heat is generated in BGTC FET. On the other hand, TGSA FET has low heat dissipation performance because the electrode used as a heat dissipation path in TGSA FET is far from the channel region. Therefore, the temperature of TGSA FET is easy to rise due to self-heating, and the mobility curve is easily affected by self-heating.

[0511] The second parameter that varies according to temperature is the number of carrier electrons. The number of electrons accumulated per unit area in the gate capacitor is represented by Cox (Vg-Vth). In the presence of electron traps, part of the accumulated electrons are captured, and the number of carrier electrons decreases. As described above, the OS includes electron traps, i.e., sDOS, so part of the electrons accumulated in the gate capacitance are not used as carriers.

[0512] The sDOS energy level is lower than the lower end of the conduction band, so when the Boltzmann distribution is taken into account, the higher the temperature, the higher the ratio of carrier electrons to trapped electrons. As mentioned above, the higher the Vg, the higher the temperature of the FET, and the higher the ratio of carrier electrons. Therefore, the higher the Vg, the higher the saturation mobility.

[0513] Assuming that sDOS is taken into account and the electron mobility of CAAC-OS is independent of temperature, the temperature dependence of the saturation mobility of the FET is calculated through device simulation. Fig.33 The calculation results are shown in Figure 2. Fig.33 As shown, compared with the case where the electron mobility is independent of the temperature, in the case where the electron mobility is dependent on the temperature, the mobility is significantly increased as the Vg increases.

[0514] [8. Effect of reduction of effective channel length]

[0515] The channel length of CAAC-OS FET is equivalent to the distance between the source electrode and the drain electrode in the BGTC structure and the length of the gate electrode in the TGSA structure. However, in actual FET characteristics, the effective channel length is n / 2 of the source region and the drain region. + The distance between regions. According to supply and demand conditions, n + The boundary between the region and the channel region is not aligned with the gate electrode terminal, and sometimes n +The region extends beyond the gate electrode end in the channel length direction. In this case, the field effect mobility is apparently improved. Fig.34 The relationship between field effect mobility and Vg is shown. Fig.34 In FIG. 1 , the vertical axis represents field effect mobility, and the horizontal axis represents Vg.

[0516] Assuming the description so far, the shapes of the saturation mobility curves for the three TGSA OS-FETs are obtained. FIG. 35A to FIG. 35C The calculation results of the saturation mobility of the TGSA OS-FET are shown. Fig.35A Equivalent to sample S1A, Fig.35B Equivalent to sample S1B, Fig.35C Equivalent to sample S1C.

[0517] like FIG. 35A to FIG. 35C As shown in FIG. 1 , in particular, by setting the parameters of sDOS to appropriate values, the shape of the saturation mobility curve exhibits different changes. In the semiconductor device corresponding to sample S1A, the saturation mobility curve has Fig.35A This indicates that the sDOS value is small. Similarly, in the semiconductor device corresponding to sample S1B, the saturation mobility curve has Fig.35B The shape shown in Figure 1 indicates that the value of sDOS is small. In the semiconductor device equivalent to sample S1C, the saturation mobility curve has Fig.35C Shape shown.

[0518] use Figure 1 The sDOS value of the oxide semiconductor film of sample S1A was measured by measuring the Id-Vg characteristics of the transistor shown in FIG. In the measurement result, the sDOS value of the oxide semiconductor film of sample S1A was 6.4×10 -12 cm -2 Therefore, the oxide semiconductor film of one embodiment of the present invention includes a region with a small sDOS value, that is, a shallow defect state density of less than 1.0×10 -12 cm -2 area.

[0519] use Figure 2 The sDOS value of the oxide semiconductor film of sample S1B was measured by measuring the Id-Vg characteristics of the transistor shown in FIG. In the measurement result, the sDOS value of the oxide semiconductor film of sample S1B was 1.7×10 -12 cm -2 Therefore, the oxide semiconductor film of one embodiment of the present invention includes a region with a small sDOS value, that is, a shallow defect state density of 1.0×10 -12 cm -2 Above and below 2.0×10 -12 cm -2 area.

[0520] use Figure 3 The sDOS value of the oxide semiconductor film of the sample S1C was measured for the Id-Vg characteristics of the transistor shown in FIG. In the measurement result, the sDOS value of the oxide semiconductor film of the sample S1C was 2.4×10 -12 cm -2 Therefore, the oxide semiconductor film of one embodiment of the present invention includes a small value of sDOS, that is, a shallow defect state density of 2.0×10 -12 cm -2 Above and below 3.0×10 -12 cm -2 area.

[0521] <1-13. Constituent elements of transistors>

[0522] Next, FIG. 17A to FIG. 17C The constituent elements of the transistor shown are described in detail.

[0523] [Substrate]

[0524] The substrate 102 can be made of a material having heat resistance enough to withstand heat treatment in a manufacturing process.

[0525] Specifically, alkali-free glass, soda-lime glass, alkali glass, crystal glass, quartz, sapphire, or the like can be used for the substrate. In addition, an inorganic insulating film can also be used. Examples of the inorganic insulating film include silicon oxide film, silicon nitride film, silicon oxynitride film, and aluminum oxide film.

[0526] The alkali-free glass preferably has a thickness of, for example, 0.2 mm or more and 0.7 mm or less. The above thickness can be obtained by polishing the alkali-free glass.

[0527] As the alkali-free glass, a large-area glass substrate having any of the following sizes can be used: the sixth generation (1500 mm×1850 mm), the seventh generation (1870 mm×2200 mm), the eighth generation (2200 mm×2400 mm), the ninth generation (2400 mm×2800 mm), and the tenth generation (2950 mm×3400 mm). Thus, a large display device can be manufactured.

[0528] Alternatively, as the substrate 102 , a single crystal semiconductor substrate or a polycrystalline semiconductor substrate using silicon or silicon carbide, a compound semiconductor substrate using silicon germanium or the like, an SOI substrate, or the like can be used.

[0529] Alternatively, an inorganic material such as a metal may be used as the substrate 102. Examples of the inorganic material such as a metal include stainless steel and aluminum.

[0530] Alternatively, an organic material such as a resin, a resin film, or a plastic may be used as the substrate 102. Examples of the resin film include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), or a resin having a siloxane bond.

[0531] In addition, a composite material combining an inorganic material and an organic material may be used as the substrate 102. Examples of the composite material include a material in which a metal plate or a thin glass plate is bonded to a resin film, a material in which fibrous metal, particulate metal, fibrous glass or particulate glass is dispersed in a resin film, or a material in which fibrous resin or particulate resin is dispersed in an inorganic material.

[0532] Note that the substrate 102 can be formed using one or more of an insulating film, a semiconductor film, and a conductive film as long as it can support a film or layer to be formed thereon or therebelow.

[0533] [First Insulating Film]

[0534] The insulating film 104 can be formed by appropriately utilizing a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like. The insulating film 104 can be formed, for example, with a single-layer structure or a stacked-layer structure including an oxide insulating film and / or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film 108, at least a region in the insulating film 104 that contacts the oxide semiconductor film 108 is preferably formed using an oxide insulating film. When the insulating film 104 is formed using an oxide insulating film that releases oxygen by heating, the oxygen contained in the insulating film 104 can be moved to the oxide semiconductor film 108 by heat treatment.

[0535] The thickness of the insulating film 104 may be greater than 50 nm, greater than 100 nm and less than 3000 nm, or greater than 200 nm and less than 1000 nm. By increasing the thickness of the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, thereby reducing the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and reducing oxygen vacancies in the channel region 108i of the oxide semiconductor film 108.

[0536] The insulating film 104 can be formed, for example, with a single-layer structure or a stacked-layer structure including silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide. In this embodiment, the insulating film 104 has a stacked-layer structure including a silicon nitride film and a silicon oxynitride film. When the insulating film 104 has such a stacked-layer structure including a silicon nitride film as a lower layer and an oxynitride silicon film as an upper layer, oxygen can be efficiently supplied to the oxide semiconductor film 108.

[0537] [Oxide semiconductor film]

[0538] As the oxide semiconductor film 108 , the above-mentioned complex oxide semiconductor or C / IGZO is suitable.

[0539] [Second Insulating Film]

[0540] The insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, and in particular, a function of supplying oxygen to the channel region 108i. For example, the insulating film 110 may be formed in a single-layer structure or a stacked-layer structure having an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film 108, at least the region in contact with the oxide semiconductor film 108 in the insulating film 110 is preferably formed using an oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like may be used.

[0541] The thickness of the insulating film 110 may be greater than or equal to 5 nm and less than or equal to 400 nm, greater than or equal to 5 nm and less than or equal to 300 nm, or greater than or equal to 10 nm and less than or equal to 250 nm.

[0542] The insulating film 110 preferably has fewer defects, typically the signal observed by the electron spin resonance method (ESR) is preferably smaller. Examples of the above signal include the signal of the E' center observed when the g value is 2.001. Note that the E' center is caused by the dangling bond of silicon. The spin density of 3×10 17 spins / cm 3 Below, preferably 5×10 16 spins / cm 3 The following silicon oxide film or silicon oxynitride film may be used.

[0543] In addition to the above signals, nitrogen dioxide (NO 2). The signal is split into three signals due to the nuclear spin of N: a first signal; a second signal; and a third signal. The first signal is observed at a g value of 2.037 or more and 2.039 or less. The second signal is observed at a g value of 2.001 or more and 2.003 or less. The third signal is observed at a g value of 1.964 or more and 1.966 or less.

[0544] For example, it is preferable to use nitrogen dioxide (NO 2 ) has a spin density of 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 of insulating film.

[0545] Note that nitrogen dioxide (NO 2 ) and other nitrogen oxides (NO x ) forms an energy level in the insulating film 110. This energy level is located in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide (NOx) diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108, this energy level sometimes captures electrons on the side of the insulating film 110. As a result, the captured electrons remain near the interface between the insulating film 110 and the oxide semiconductor film 108, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, when a film with a low content of nitrogen oxide is used as the insulating film 110, the drift of the threshold voltage of the transistor can be reduced.

[0546] As nitrogen oxides (NO x For example, an insulating film with a low release amount of ammonia can be used, such as a silicon oxynitride film. The silicon oxynitride film has a lower release amount of ammonia than nitrogen oxides (NO x ) release is large, typically ammonia release is 1×10 18 Pieces / cm 3 Above and 5×10 19 Pieces / cm 3 Note that the above-mentioned ammonia release amount is the total amount when the heat treatment temperature in the TDS is within the range of 50°C to 650°C or within the range of 50°C to 550°C.

[0547] Since nitrogen oxides (NO x ) reacts with ammonia and oxygen, so by using an insulating film that releases a lot of ammonia, it is possible to reduce nitrogen oxides (NO x ).

[0548] Note that when the insulating film 110 is analyzed using SIMS, the nitrogen concentration in the film is preferably 6×1020 atoms / cm 3 the following.

[0549] The insulating film 110 may also be made of hafnium silicate (HfSiO x ), nitrogen-doped hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), hafnium oxide and other high-k materials. By using this high-k material, the gate leakage current of the transistor can be reduced.

[0550] [Third Insulating Film]

[0551] The insulating film 116 contains nitrogen or hydrogen. The insulating film 116 may also contain fluorine. The insulating film 116 is, for example, a nitride insulating film. The nitride insulating film may be formed using silicon nitride, silicon nitride oxide, silicon oxynitride, silicon nitride fluoride, silicon fluoride nitride, or the like. The hydrogen concentration in the insulating film 116 is preferably 1×10 22 atoms / cm 3 In addition, the insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Therefore, the impurity (nitrogen or hydrogen) concentration in the source region 108s and the drain region 108d in contact with the insulating film 116 becomes high, thereby increasing the carrier density of the source region 108s and the drain region 108d.

[0552] [Fourth Insulating Film]

[0553] An oxide insulating film may be used as the insulating film 118. Alternatively, a stacked film of an oxide insulating film and a nitride insulating film may be used as the insulating film 118. The insulating film 118 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide.

[0554] Note that the insulating film 118 is preferably used as a barrier film for hydrogen, water, or the like from the outside.

[0555] The thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

[0556] [Fifth Insulating Film]

[0557] The insulating film 122 has insulating properties and is formed using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film. Examples of the organic material include a photosensitive resin material such as an acrylic resin or a polyimide resin.

[0558] [Conductive film]

[0559] The conductive films 106, 112, 120a, and 120b can be formed by sputtering, vacuum evaporation, pulsed laser deposition (PLD), thermal CVD, or the like. Alternatively, the conductive films 106, 112, 120a, and 120b can be made of a conductive metal film, a conductive film that reflects visible light, or a conductive film that transmits visible light.

[0560] The conductive metal film may be made of a material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium or manganese. Alternatively, an alloy containing the above metal elements may be used.

[0561] As the above-mentioned conductive metal film, specifically, a two-layer structure of a copper film stacked on a titanium film, a two-layer structure of a copper film stacked on a titanium nitride film, a two-layer structure of a copper film stacked on a tantalum nitride film, a three-layer structure of a copper film stacked on a titanium film and a titanium film formed thereon, etc. can be used. In particular, by using a conductive film containing copper elements, the resistance can be reduced, so it is preferred. As a conductive film containing copper elements, an alloy film containing copper and manganese can be cited. The alloy film can be processed by using a wet etching method, so it is preferred.

[0562] As the conductive films 106, 112, 120a, and 120b, a tantalum nitride film is preferably used. The tantalum nitride film has conductivity and has a high barrier property against copper or hydrogen. Since the amount of hydrogen released from the tantalum nitride film itself is small, the tantalum nitride film can be most suitably used as a metal film in contact with the oxide semiconductor film 108 or a metal film near the oxide semiconductor film 108.

[0563] As the conductive film having conductivity, a conductive high molecule or a conductive polymer may be used.

[0564] The conductive film having the function of reflecting visible light may be made of a material containing a metal element selected from gold, silver, copper and palladium. In particular, a conductive film containing silver is preferred because the reflectivity of visible light can be increased.

[0565] The conductive film having the function of transmitting visible light can be made of a material containing an element selected from indium, tin, zinc, gallium and silicon. Specifically, In oxide, Zn oxide, In-Sn oxide (also called ITO), In-Sn-Si oxide (also called ITSO), In-Zn oxide, In-Ga-Zn oxide, etc. can be used.

[0566] The conductive film having the function of transmitting visible light may also be a film containing graphene or graphite. The film containing graphene oxide may be formed by the following method: forming a film containing graphene oxide and reducing it. As the reduction method, a method using heating and a method using a reducing agent may be used.

[0567] The conductive films 112, 120a, and 120b can be formed by an electroless plating method. As a material that can be formed by the electroless plating method, for example, one or more selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used. In particular, when Cu or Ag is used, the resistance of the conductive film can be reduced, so it is preferable.

[0568] When a conductive film is formed by an electroless plating method, a diffusion prevention film may also be formed under the conductive film to prevent the constituent elements of the conductive film from diffusing to the outside. In addition, a seed layer that enables the conductive film to grow may also be formed between the diffusion prevention film and the conductive film. The diffusion prevention film may be formed, for example, by sputtering. As the diffusion prevention film, for example, a tantalum nitride film or a titanium nitride film may be used. The seed layer may be formed by an electroless plating method. In addition, the seed layer may be formed by using the same material as the conductive film formed by the electroless plating method.

[0569] Note that an oxide semiconductor represented by In-Ga-Zn oxide can be used as the conductive film 112. The oxide semiconductor can have a carrier density when nitrogen or hydrogen is supplied from the insulating film 116. In other words, the oxide semiconductor functions as an oxide conductor (OC). Therefore, the oxide semiconductor can function as a gate electrode.

[0570] For example, the conductive film 112 may have a single-layer structure of an oxide conductor (OC), a single-layer structure of a metal film, or a stacked-layer structure of an oxide conductor (OC) and a metal film.

[0571] Note that when the conductive film 112 has a single-layer structure of a light-shielding metal film or a stacked-layer structure of an oxide conductor (OC) and a light-shielding metal film, it is preferable because light can be blocked from reaching the channel region 108i formed below the conductive film 112. When the conductive film 112 has a stacked-layer structure of an oxide semiconductor or an oxide conductor (OC) and a metal film having a light-shielding property, when a metal film (for example, a titanium film, a tungsten film, or the like) is formed on the oxide semiconductor or the oxide conductor (OC), any of the following effects is exerted: the resistance of the oxide semiconductor or the oxide conductor (OC) is reduced by diffusion of constituent elements in the metal film to the oxide semiconductor or the oxide conductor (OC) side, the resistance is reduced by damage during deposition of the metal film (for example, sputtering damage, etc.), and the resistance is reduced when oxygen vacancies are formed by diffusion of oxygen in the oxide semiconductor or the oxide conductor (OC) into the metal film.

[0572] The thickness of the conductive films 106 , 112 , 120 a , and 120 b can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

[0573] This embodiment mode may be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0574] (Implementation Method 2)

[0575] In this embodiment, refer to FIG. 36A to FIG. 51C A transistor of a different type from the transistor described in Embodiment 1 will be described.

[0576] <2-1. Transistor Structure Example 2>

[0577] Fig.36A and Fig.36B is a cross-sectional view of transistor 100B. Fig.37A and Fig.37B is a cross-sectional view of the transistor 100C. Fig.38A and Fig.38B is a cross-sectional view of transistor 100D. Top views of transistors 100B, 100C, and 100D are similar to Fig.17A The top view of the transistor 100A shown is the same and therefore not shown.

[0578] Fig.36A and Fig.36B The transistor 100B shown is different from the transistor 100A in the stacked structure of the conductive film 112 , the shape of the conductive film 112 , and the shape of the insulating film 110 .

[0579] The conductive film 112 in the transistor 100B includes a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. For example, by using an oxide conductive film as the conductive film 112_1, excess oxygen can be added to the insulating film 110. The above-mentioned oxide conductive film can be formed by sputtering in an atmosphere containing oxygen. As the above-mentioned oxide conductive film, for example, an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, and an oxide containing indium, gallium and zinc can be used.

[0580] like Fig.36B As shown in FIG. 1 , the conductive film 112_2 is connected to the conductive film 106 through the opening 143. By forming the opening 143 after forming the conductive film to be the conductive film 112_1, it is possible to obtain Fig.36B When an oxide conductive film is used for the conductive film 112_1, by adopting a structure in which the conductive film 112_2 is connected to the conductive film 106, contact resistance between the conductive film 112 and the conductive film 106 can be reduced.

[0581] The conductive film 112 and the insulating film 110 in the transistor 100B have a tapered shape. More specifically, the lower end of the conductive film 112 is located outside the upper end of the conductive film 112. The lower end of the insulating film 110 is located outside the upper end of the insulating film 110. In addition, the lower end of the conductive film 112 is formed at substantially the same position as the upper end of the insulating film 110.

[0582] The conductive film 112 and the insulating film 110 of the transistor 100B are preferably formed in a tapered shape because coverage of the insulating film 116 can be improved compared to the case where the conductive film 112 and the insulating film 110 of the transistor 100A are formed in a rectangular shape.

[0583] The other components of the transistor 100B are the same as those of the transistor 100A described above, and exhibit the same effects.

[0584] Fig.37A and Fig.37B The transistor 100C shown is different from the transistor 100A in the stacked structure of the conductive film 112 , the shape of the conductive film 112 , and the shape of the insulating film 110 .

[0585] The conductive film 112 in the transistor 100C includes a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. The lower end of the conductive film 112_1 is located outside the upper end of the conductive film 112_2. For example, the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed using one mask, the conductive film 112_2 is processed using a wet etching method, and the conductive film 112_1 and the insulating film 110 are processed using a dry etching method, thereby obtaining the above structure.

[0586] By adopting the structure of the transistor 100C, a region 108f may be formed in the oxide semiconductor film 108. The region 108f is formed between the channel region 108i and the source region 108s and between the channel region 108i and the drain region 108d.

[0587] The region 108f is used as a high resistance region or a low resistance region. The high resistance region has a resistance equal to that of the channel region 108i and is a region that does not overlap with the conductive film 112 used as a gate electrode. When the region 108f is a high resistance region, the region 108f is used as a bias region. In order to suppress the reduction of the on-state current of the transistor 100C, the regions 108f used as bias regions can each have a length of 1 μm or less in the channel length (L) direction.

[0588] The low resistance region has a resistance lower than that of the channel region 108i and higher than that of the source region 108s and the drain region 108d. When the region 108f is a low resistance region, the region 108f is used as an LDD (Lightly Doped Drain) region. The region 108f used as an LDD region can achieve electric field relaxation in the drain region, thereby reducing the change in the threshold voltage of the transistor caused by the electric field in the drain region.

[0589] Note that when region 108f is used as an LDD region, for example, one or more of nitrogen, hydrogen and fluorine is supplied to region 108f from the insulating film 116, or impurity elements are added from above the conductive film 112_1 using the insulating film 110 and the conductive film 112_1 as a mask, and the impurity elements are added to the oxide semiconductor film 108 through the conductive film 112_1 and the insulating film 110, thereby forming region 108f.

[0590] like Fig.37B As shown, the conductive film 112_2 is connected to the conductive film 106 through the opening 143 .

[0591] The other components of the transistor 100C are the same as those of the transistor 100A described above, and exhibit the same effects.

[0592] Fig.38A and Fig.38BThe transistor 100D shown is different from the transistor 100A in the stacked structure of the conductive film 112 , the shape of the conductive film 112 , and the shape of the insulating film 110 .

[0593] The conductive film 112 in the transistor 100D includes a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. The lower end of the conductive film 112_1 is located outside the lower end of the conductive film 112_2. In addition, the lower end of the insulating film 110 is located outside the lower end of the conductive film 112_1. For example, the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed using one mask, the conductive film 112_2 and the conductive film 112_1 are processed using a wet etching method, and the insulating film 110 is processed using a dry etching method, thereby obtaining the above structure.

[0594] Similar to the transistor 100C, in the transistor 100D, a region 108f may be formed in the oxide semiconductor film 108. The region 108f is formed between the channel region 108i and the source region 108s and between the channel region 108i and the drain region 108d.

[0595] like Fig.38B As shown, in the opening 143 , the conductive film 112_2 is connected to the conductive film 106 .

[0596] The other components of the transistor 100D are the same as those of the transistor 100A described above, and exhibit the same effects.

[0597] <2-2. Transistor Structure Example 3>

[0598] Fig.39A and Fig.39B is a cross-sectional view of transistor 100E. Fig.40A and Fig.40B is a cross-sectional view of transistor 100F. Fig.41A and Fig.41B is a cross-sectional view of transistor 100G. Fig.42A and Fig.42B is a cross-sectional view of the transistor 100H. Fig.43A and Fig.43B is a cross-sectional view of transistor 100J. The top views of transistors 100E, 100F, 100G, 100H, and 100J are different due to the Fig.17A The top view of the transistor 100A shown is the same and therefore not shown.

[0599] The transistors 100E, 100F, 100G, 100H, and 100J are different from the transistor 100A in the structure of the oxide semiconductor film 108. The other components are the same as those of the transistor 100A, and the same effects are achieved.

[0600] Fig.39A and Fig.39B The oxide semiconductor film 108 of the transistor 100E shown includes an oxide semiconductor film 108_1 on the insulating film 104, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d have a three-layer stacked structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3, respectively.

[0601] Fig.40A and Fig.40B The oxide semiconductor film 108 of the transistor 100F shown includes an oxide semiconductor film 108_2 on the insulating film 104 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer stacked structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3.

[0602] Fig.41A and Fig.41B The oxide semiconductor film 108 of the transistor 100G shown includes an oxide semiconductor film 108_1 on the insulating film 104 and an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer stacked structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.

[0603] Fig.42A and Fig.42B The oxide semiconductor film 108 of the transistor 100H shown includes an oxide semiconductor film 108_1 on the insulating film 104, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i has a three-layer stacked structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3. The source region 108s and the drain region 108d have a two-layer stacked structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, respectively. Note that in the cross section of the transistor 100H in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side surfaces of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.

[0604] Fig.43A and Fig.43BThe oxide semiconductor film 108 of the transistor 100J shown includes an oxide semiconductor film 108_2 on the insulating film 104 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i has a two-layer stacked structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. The source region 108s and the drain region 108d each have a single-layer structure of the oxide semiconductor film 108_2. Note that in the cross section of the transistor 100J in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side of the oxide semiconductor film 108_2.

[0605] The side surfaces or the vicinity of the side surfaces in the channel width (W) direction of the channel region 108i are prone to forming defects (e.g., oxygen vacancies) due to damage during processing, or are prone to being contaminated due to the attachment of impurities, etc. Therefore, even if the channel region 108i is substantially intrinsic, the side surfaces or the vicinity of the side surfaces in the channel width (W) direction of the channel region 108i are activated by applying pressure such as an electric field, and are prone to becoming low-resistance (n-type) regions. In addition, if the side surfaces or the vicinity of the side surfaces in the channel width (W) direction of the channel region 108i are n-type regions, since the n-type regions become paths for carriers, parasitic channels may be formed.

[0606] Therefore, in the transistor 100H and the transistor 100J, the channel region 108i has a stacked structure, and the side surface of the channel region 108i in the channel width (W) direction is covered by one layer in the stacked structure. By adopting this structure, defects on the side surface of the channel region 108i or its vicinity can be suppressed or impurities can be reduced from being attached to the side surface of the channel region 108i or its vicinity.

[0607] [Belt structure]

[0608] Here, refer to FIG. 44A to FIG. 44C The band structures of the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110, the band structures of the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110, and the band structures of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and the insulating film 110 are described. Note that FIG. 44A to FIG. 44C This is the band structure of the channel region 108i.

[0609] Fig.44A An example of a band structure in the film thickness direction of a stacked-layer structure including the insulating film 104 , the oxide semiconductor films 108_1 , 108_2 , and 108_3 , and the insulating film 110 is shown. Fig.44B An example of a band structure in the film thickness direction of a stacked-layer structure including the insulating film 104 , the oxide semiconductor films 108_2 and 108_3 , and the insulating film 110 is shown. Fig.44C An example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, oxide semiconductor films 108_1, 108_2, and the insulating film 110 is shown. For easy understanding, the band structure shows the conduction band bottom energy level (Ec) of the insulating film 104, oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110.

[0610] exist Fig.44A In the band structure, a silicon oxide film is used as the insulating films 104 and 110, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film 108_1, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 is used as the oxide semiconductor film 108_2, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film 108_3.

[0611] exist Fig.44B In the band structure, silicon oxide films are used as insulating films 104 and 110, an oxide semiconductor film formed by using a metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 is used as the oxide semiconductor film 108_2, and an oxide semiconductor film formed by using a metal oxide target with an atomic ratio of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film 108_3.

[0612] exist Fig.44C In the band structure, silicon oxide films are used as insulating films 104 and 110, an oxide semiconductor film formed by using a metal oxide target with an atomic ratio of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film 108_1, and an oxide semiconductor film formed by using a metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 is used as the oxide semiconductor film 108_2.

[0613] like Fig.44A As shown in FIG. 1 , in the oxide semiconductor films 108_1, 108_2, and 108_3, the conduction band bottom energy level changes smoothly. Fig.44B As shown in FIG. 1 , in the oxide semiconductor films 108_2 and 108_3, the conduction band bottom energy level changes smoothly. Fig.44CAs shown, in the oxide semiconductor films 108_1 and 108_2, the conduction band bottom energy level changes smoothly. In other words, the conduction band bottom energy level changes continuously or is continuously connected. In order to obtain such a band structure, impurities that form defect energy states such as trap centers or recombination centers are not present at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3.

[0614] In order to form a continuous junction among the oxide semiconductor films 108_1, 108_2, and 108_3, it is necessary to form each film continuously without exposing it to the atmosphere using a multi-chamber deposition apparatus (sputtering apparatus) having a load-lock chamber.

[0615] By adopting Fig.44A , Fig.44B or Fig.44C In the band structure shown, the oxide semiconductor film 108_2 serves as a well, and in a transistor using the above-described stacked-layer structure, a channel region is formed in the oxide semiconductor film 108_2.

[0616] By providing the oxide semiconductor films 108_1 and 108_3 , defect states can be kept away from the oxide semiconductor film 108_2 .

[0617] In addition, sometimes the defect state is farther from the vacuum energy level than the bottom energy level (Ec) of the conduction band of the oxide semiconductor film 108_2 used as the channel region, and electrons are easily accumulated in the defect state. When electrons accumulate in the defect state, the electrons become negative fixed charges, whereby the threshold voltage of the transistor drifts in the positive direction. Therefore, it is preferred to adopt a structure in which the defect state is closer to the vacuum energy level than the bottom energy level (Ec) of the conduction band of the oxide semiconductor film 108_2. By adopting the above structure, electrons are not easily accumulated in the defect state. As a result, the on-state current and field effect mobility of the transistor can be increased.

[0618] The energy level of the bottom of the conduction band of the oxide semiconductor films 108_1 and 108_3 is closer to the vacuum level than that of the oxide semiconductor film 108_2. Typically, the difference between the bottom energy level of the conduction band of the oxide semiconductor film 108_2 and the bottom energy level of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or 0.5 eV, and 2 eV or 1 eV. In other words, the electron affinity of the oxide semiconductor film 108_2 is higher than that of the oxide semiconductor films 108_1 and 108_3. The difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or 0.5 eV, and 2 eV or 1 eV.

[0619] In the above structure, the oxide semiconductor film 108_2 becomes the main current path. That is, the oxide semiconductor film 108_2 is used as a channel region, and the oxide semiconductor films 108_1 and 108_3 are used as oxide insulating films. The oxide semiconductor films 108_1 and 108_3 preferably both contain one or more of the metal elements constituting the oxide semiconductor film 108_2 that form the channel region. By adopting the above structure, interface scattering is not easily generated at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. As a result, the movement of carriers at the interface is not hindered, so the field effect mobility of the transistor is improved.

[0620] In order to prevent the oxide semiconductor films 108_1 and 108_3 from being used as part of the channel region, the oxide semiconductor films 108_1 and 108_3 use a material with sufficiently low conductivity. Therefore, the oxide semiconductor films 108_1 and 108_3 can be called oxide insulating films according to their physical properties and / or functions. The material used for the oxide semiconductor films 108_1 and 108_3 has an electron affinity (difference between the vacuum level and the conduction band bottom level) less than that of the oxide semiconductor film 108_2 and is selected in a manner that there is a difference (band offset) between the conduction band bottom level of each of the oxide semiconductor films 108_1 and 108_3 and the conduction band bottom level of the oxide semiconductor film 108_2. In addition, in order to suppress the difference between the threshold voltages caused by the drain voltage value, the oxide semiconductor films 108_1 and 108_3 preferably use a material whose conduction band bottom level is closer to the vacuum level than the conduction band bottom level of the oxide semiconductor film 108_2. For example, the difference between the conduction band bottom energy level of the oxide semiconductor film 108_2 and the conduction band bottom energy levels of the oxide semiconductor films 108_1 and 108_3 is preferably 0.2 eV or more, and more preferably 0.5 eV or more.

[0621] The oxide semiconductor films 108_1 and 108_3 preferably do not have a spinel crystal structure. This is because if the oxide semiconductor films 108_1 and 108_3 have a spinel crystal structure, the constituent elements of the conductive films 120a and 120b may diffuse into the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and other regions. Note that in the case where the oxide semiconductor films 108_1 and 108_3 are CAAC-OS described later, the properties of the constituent elements of the blocking conductive films 120a and 120b, such as copper, are improved, so it is preferred.

[0622] Although an example of using an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:3:2 as the oxide semiconductor films 108_1 and 108_3 is shown in this embodiment, an embodiment of the present invention is not limited thereto. For example, as the oxide semiconductor films 108_1 and 108_3, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1, 1:1:1.2, 1:3:4, 1:3:6, 1:4:5, 1:5:6, or 1:10:1 may be used. Alternatively, as the oxide semiconductor films 108_1 and 108_3, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of Ga:Zn=10:1 may be used. In this case, when an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1 is used as the oxide semiconductor film 108_2, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of Ga:Zn=10:1 is used as the oxide semiconductor films 108_1 and 108_3, the difference between the conduction band bottom energy level of the oxide semiconductor film 108_2 and the conduction band bottom energy level of the oxide semiconductor films 108_1 and 108_3 can be made greater than 0.6 eV, so it is preferred.

[0623] When an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1 is used as the oxide semiconductor films 108_1 and 108_3, In:Ga:Zn=1:β1:β2 (0<β1≤2, 0<β2≤2) may be present in the oxide semiconductor films 108_1 and 108_3. When an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:3:4 is used as the oxide semiconductor films 108_1 and 108_3, In:Ga:Zn=1:β3:β4 (1≤β3≤5, 2≤β4≤6) may be present in the oxide semiconductor films 108_1 and 108_3. When an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:3:6 is used as the oxide semiconductor films 108_1 and 108_3, In:Ga:Zn=1:β5:β6 (1≤β5≤5, 4≤β6≤8) in the oxide semiconductor films 108_1 and 108_3.

[0624] <2-3. Transistor Structure Example 4>

[0625] Fig.45A is a top view of transistor 300A. Fig.45B It is along Fig.45A Cross-sectional view along the dotted line X1-X2 in FIG. Fig.45C It is along Fig.45A The cross-sectional view of the dotted line Y1-Y2 in FIG. Fig.45A For the sake of convenience, a portion of the components of transistor 300A (such as the insulating film used as the gate insulating film) is omitted for illustration. The dot-dash line X1-X2 direction is sometimes referred to as the channel length direction, and the dot-dash line Y1-Y2 direction is sometimes referred to as the channel width direction. Fig.45A Similarly, some of the components are omitted.

[0626] FIG. 45A to FIG. 45C The transistor 300A shown includes a conductive film 304 on a substrate 302, an insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, an oxide semiconductor film 308 on the insulating film 307, a conductive film 312a on the oxide semiconductor film 308, and a conductive film 312b on the oxide semiconductor film 308. Insulating films 314, 316, and an insulating film 318 are provided on the transistor 300A, specifically, on the conductive films 312a, 312b, and the oxide semiconductor film 308.

[0627] In the transistor 300A, the insulating films 306 and 307 are used as gate insulating films of the transistor 300A, and the insulating films 314, 316, and 318 are used as protective insulating films of the transistor 300A. In addition, in the transistor 300A, the conductive film 304 is used as a gate electrode, the conductive film 312a is used as a source electrode, and the conductive film 312b is used as a drain electrode.

[0628] In this specification and the like, the insulating films 306 and 307 may be referred to as first insulating films, the insulating films 314 and 316 may be referred to as second insulating films, and the insulating film 318 may be referred to as a third insulating film.

[0629] FIG. 45A to FIG. 45C The transistor 300A shown is a channel-etched transistor. The oxide semiconductor film according to one embodiment of the present invention can be applied to a channel-etched transistor.

[0630] <2-4. Transistor Structure Example 5>

[0631] Fig.46A is a top view of transistor 300B. Fig.46B yes Fig.46A Cross-sectional view along the dotted line X1-X2 in FIG. Fig.46C yes Fig.46A sectional view along the dotted line Y1-Y2 in FIG.

[0632] FIG. 46A to FIG. 46CThe transistor 300B shown includes a conductive film 304 on a substrate 302, an insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, an oxide semiconductor film 308 on the insulating film 307, an insulating film 314 on the oxide semiconductor film 308, an insulating film 316 on the insulating film 314, a conductive film 312a electrically connected to the oxide semiconductor film 308 via an opening 341a provided in the insulating film 314 and the insulating film 316, and a conductive film 312b electrically connected to the oxide semiconductor film 308 via an opening 341b provided in the insulating film 314 and the insulating film 316. In the transistor 300B, in more detail, an insulating film 318 is provided on the conductive films 312a, 312b, and the insulating film 316.

[0633] In the transistor 300B, both insulating films 306 and 307 are used as gate insulating films of the transistor 300B, both insulating films 314 and 316 are used as protective insulating films of the oxide semiconductor film 308, and the insulating film 318 is used as a protective insulating film of the transistor 300B. In addition, in the transistor 300B, the conductive film 304 is used as a gate electrode, the conductive film 312a is used as a source electrode, and the conductive film 312b is used as a drain electrode.

[0634] FIG. 45A to FIG. 45C The transistor 300A shown has a channel-etched structure, and FIG. 46A to FIG. 46C The transistor 300B shown has a channel protection structure. The oxide semiconductor film according to one embodiment of the present invention can also be applied to a channel protection transistor.

[0635] <2-5. Transistor Structure Example 6>

[0636] Fig.47A is a top view of transistor 300C, Fig.47B Equivalent to Fig.47A The cross-sectional view along the dot-dash line X1-X2 shown in FIG. Fig.47C Equivalent to Fig.47A A cross-sectional view along the dashed line Y1-Y2 is shown.

[0637] FIG. 47A to FIG. 47C The transistor 300C is shown with FIG. 46A to FIG. 46C The transistor 300B shown is different in the shapes of the insulating films 314 and 316. Specifically, the insulating films 314 and 316 of the transistor 300C are provided in an island shape on the channel region of the oxide semiconductor film 308. The other components are the same as those of the transistor 300B.

[0638] <2-6. Transistor Structure Example 7>

[0639] Fig.48A is a top view of transistor 300D. Fig.48B yes Fig.48A Cross-sectional view along the dotted line X1-X2 in FIG. Fig.48C yes Fig.48A sectional view along the dotted line Y1-Y2 in FIG.

[0640] FIG. 48A to FIG. 48C The transistor 300D shown includes a conductive film 304 on a substrate 302, an insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, an oxide semiconductor film 308 on the insulating film 307, a conductive film 312a on the oxide semiconductor film 308, a conductive film 312b on the oxide semiconductor film 308, an insulating film 314 on the oxide semiconductor film 308 and the conductive films 312a and 312b, an insulating film 316 on the insulating film 314, an insulating film 318 on the insulating film 316, and conductive films 320a and 320b on the insulating film 318.

[0641] In the transistor 300D, the insulating films 306 and 307 are used as the first gate insulating film of the transistor 300D, and the insulating films 314, 316, and 318 are used as the second gate insulating film of the transistor 300D. In addition, in the transistor 300D, the conductive film 304 is used as the first gate electrode, the conductive film 320a is used as the second gate electrode, and the conductive film 320b is used as the pixel electrode for the display device. The conductive film 312a is used as the source electrode, and the conductive film 312b is used as the drain electrode.

[0642] like Fig.48C As shown, the conductive film 320a is connected to the conductive film 304 through the openings 342b and 342c provided in the insulating films 306, 307, 314, 316, and 318. Therefore, the same potential is applied to the conductive film 320a and the conductive film 304.

[0643] The structure of the transistor 300D is not limited to that in which the openings 342b and 342c are provided to connect the conductive film 320a to the conductive film 304. For example, a structure in which only one of the opening 342b and the opening 342c is formed to connect the conductive film 320a to the conductive film 304, or a structure in which the opening 342b and the opening 342c are not provided and the conductive film 320a to the conductive film 304 are not connected may be adopted. Note that when the conductive film 320a and the conductive film 304 are not connected, different potentials may be applied to the conductive film 320a and the conductive film 304.

[0644] The conductive film 320 b is connected to the conductive film 312 b via the opening 342 a provided in the insulating films 314 , 316 , and 318 .

[0645] Note that the transistor 300D has the above-described S-channel structure.

[0646] <2-7. Transistor Structure Example 8>

[0647] FIG. 45A to FIG. 45C The oxide semiconductor film 308 included in the transistor 300A in FIG. 1 may also have a stacked-layer structure. Fig.49A and Fig.49B as well as Fig.50A and Fig.50B An example of this case is shown.

[0648] Fig.49A and Fig.49B is a cross-sectional view of transistor 300E, Fig.50A and Fig.50B is a cross-sectional view of transistor 300F. The top view of transistors 300E and 300F is similar to Fig.45A The top view of transistor 300A shown is the same.

[0649] Fig.49A and Fig.49B The oxide semiconductor film 308 of the transistor 300E shown includes an oxide semiconductor film 308_1 , an oxide semiconductor film 308_2 , and an oxide semiconductor film 308_3 . Fig.50A and Fig.50B The oxide semiconductor film 308 of the transistor 300F shown includes an oxide semiconductor film 308_2 and an oxide semiconductor film 308_3 .

[0650] Note that the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, the oxide semiconductor film 308_1, the oxide semiconductor film 308_2, the oxide semiconductor film 308_3, the conductive films 312a, 312b, the insulating film 314, the insulating film 316, the insulating film 318 and the conductive films 320a, 320b can be formed using the materials of the above-mentioned conductive film 106, the insulating film 116, the oxide semiconductor film 108, the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, the oxide semiconductor film 108_3, the conductive films 120a, 120b, the insulating film 104, the insulating film 118, the insulating film 116 and the conductive film 112, respectively.

[0651] <2-8. Transistor Structure Example 9>

[0652] Fig.51A is a top view of transistor 300G. Fig.51B It is along Fig.51A A cross-sectional view along the dotted line X1-X2 in FIG. Fig.51C It is along Fig.51A sectional view along the dotted line Y1-Y2 in FIG.

[0653] FIG. 51A to FIG. 51CThe transistor 300G shown includes a conductive film 304 on a substrate 302, an insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, an oxide semiconductor film 308 on the insulating film 307, a conductive film 312a on the oxide semiconductor film 308, a conductive film 312b on the oxide semiconductor film 308, an insulating film 314 on the oxide semiconductor film 308, the conductive film 312a and the conductive film 312b, an insulating film 316 on the insulating film 314, a conductive film 320a on the insulating film 316, and a conductive film 320b on the insulating film 316.

[0654] The insulating films 306 and 307 have openings 351. A conductive film 312c electrically connected to the conductive film 304 through the openings 351 is formed over the insulating films 306 and 307. The insulating films 314 and 316 include openings 352a and 352b reaching the conductive film 312b and 312c, respectively.

[0655] The oxide semiconductor film 308 includes an oxide semiconductor film 308_2 on the conductive film 304 side and an oxide semiconductor film 308_3 on the oxide semiconductor film 308_2 .

[0656] An insulating film 318 is provided over the transistor 300G. The insulating film 318 is formed to cover the insulating film 316, the conductive film 320a, and the conductive film 320b.

[0657] In the transistor 300G, the insulating films 306 and 307 are used as the first gate insulating film of the transistor 300G, the insulating films 314 and 316 are used as the second gate insulating film of the transistor 300G, and the insulating film 318 is used as the protective insulating film of the transistor 300G. In addition, in the transistor 300G, the conductive film 304 is used as the first gate electrode, the conductive film 320a is used as the second gate electrode, and the conductive film 320b is used as the pixel electrode for the display device. In addition, in the transistor 300G, the conductive film 312a is used as the source electrode, the conductive film 312b is used as the drain electrode, and the conductive film 312c is used as the connection electrode.

[0658] Note that the transistor 300G has the above-mentioned S-channel structure.

[0659] Furthermore, the structures of the transistors 300A to 300G can also be freely combined.

[0660] This embodiment mode may be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0661] (Implementation method 3)

[0662] In this embodiment, using Figure 52 to Figure 59An example of a display device including the transistor described in the above embodiment mode will be described.

[0663] Fig.52 is a plan view showing an example of a display device. Fig.52 The display device 700 in the embodiment includes: a pixel portion 702 arranged on a first substrate 701; a source driver circuit portion 704 and a gate driver circuit portion 706 arranged on the first substrate 701; a sealant 712 arranged in a manner surrounding the pixel portion 702, the source driver circuit portion 704 and the gate driver circuit portion 706; and a second substrate 705 arranged in a manner opposite to the first substrate 701. The first substrate 701 and the second substrate 705 are sealed by the sealant 712. In other words, the pixel portion 702, the source driver circuit portion 704 and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712 and the second substrate 705. Although in Fig.52 Although not shown in the figure, a display element is provided between the first substrate 701 and the second substrate 705.

[0664] In the display device 700, a flexible printed circuit (FPC) terminal portion 708 electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is provided in a region different from the region on the first substrate 701 and surrounded by the sealant 712. In addition, the FPC terminal portion 708 is connected to the FPC 716, and various signals and the like are supplied from the FPC 716 to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706. In addition, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 are each connected to a signal line 710. Various signals and the like supplied from the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.

[0665] In addition, a plurality of gate driver circuit portions 706 may be provided in the display device 700. The structure of the display device 700 is not limited to the example shown here, and the source driver circuit portion 704 and the gate driver circuit portion 706 are formed on the same first substrate 701 as the pixel portion 702. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate having a source driver circuit or a gate driver circuit formed thereon (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate 701. Note that there is no particular limitation on the connection method of the driver circuit substrate prepared separately, and a chip-on-glass (COG) method, a wire bonding method, or the like may be used.

[0666] The pixel portion 702 , the source driver circuit portion 704 , and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors.

[0667] The display device 700 may include various elements. Examples of the element include electroluminescent (EL) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (transistors that emit light according to current), electron emission elements, liquid crystal elements, electronic ink displays, electrophoretic elements, electrowetting elements, plasma display panels (PDPs), micro-electromechanical systems (MEMS), displays (e.g., grating light valves (GLVs), digital micromirror devices (DMDs), digital microshutter (DMS) elements, interferometric modulation (IMOD) elements, etc.), piezoelectric ceramic displays, etc.

[0668] An example of a display device including an EL element is an EL display. Examples of display devices including electron emission elements include field emission displays (FED) or SED flat-panel displays (SED: Surface-conduction Electron-emitter Display, surface conduction electron emission display). An example of a display device including a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device including an electronic ink display or an electrophoretic element is electronic paper. When a semi-transmissive liquid crystal display or a reflective liquid crystal display is implemented, part or all of the pixel electrode can be used as a reflective electrode. For example, part or all of the pixel electrode can be made to contain aluminum, silver, etc. At this time, a storage circuit such as SRAM can also be set under the reflective electrode. In this way, power consumption can be further reduced.

[0669] As a display mode of the display device 700, a progressive scanning mode or an interlaced scanning mode can be adopted. In addition, when performing color display, the color elements controlled in the pixel are not limited to three colors: R, G and B (R, G and B correspond to red, green and blue, respectively). For example, four pixels of R pixel, G pixel, B pixel and W (white) pixel can be used. Alternatively, as in the PenTile arrangement, a color element can also be composed of two colors of R, G and B. The two colors can also be different depending on the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. can be added to RGB. Note that the size of the display area between the points of each color element can be different. One embodiment of the disclosed invention is not limited to a color display device, and the disclosed invention can also be applied to a display device for black and white display.

[0670] In order to use white light (W) for backlight (organic EL elements, inorganic EL elements, LEDs, fluorescent lamps, etc.) to enable the display device to display in full color, a coloring layer (also called a filter) can also be used. For example, a red (R) coloring layer, a green (G) coloring layer, a blue (B) coloring layer, a yellow (Y) coloring layer, etc. can be appropriately combined. By using a coloring layer, the color reproducibility can be further improved compared to the case where a coloring layer is not used. At this time, it is also possible to directly use the white light in the area that does not include the coloring layer for display by setting an area that includes a coloring layer and an area that does not include a coloring layer. By partially setting an area that does not include a coloring layer, when displaying a bright image, the brightness reduction caused by the coloring layer can sometimes be reduced and power consumption can be reduced by about 20% to 30%. When using self-luminous elements such as organic EL elements or inorganic EL elements for full-color display, R, G, B, Y, and W can also be emitted from elements with each luminous color. By using a self-luminous element, power consumption can sometimes be further reduced compared to the case where a coloring layer is used.

[0671] As a colorization method, any one of the following methods can be used: the above-mentioned color filter method of converting part of the white light into red light, green light and blue light through a color filter; a three-color method using red light, green light and blue light; and a color conversion method or quantum dot method of converting part of the blue light into red light or green light.

[0672] In this embodiment, using Figure 53 to Figure 55 A structure including a liquid crystal element and a structure including an EL element as a display element are described. Fig.53 and Fig.54 It is along Fig.52 The cross-sectional view shown is taken along the dashed line QR, and shows a structure including a liquid crystal element as a display element. Fig.55 It is along Fig.52 1 is a cross-sectional view taken along a dashed line QR, and shows a structure including an EL element as a display element.

[0673] Below, first explain Figure 53 to Figure 55 The common parts are shown, and then the different parts are described.

[0674] <3-1. Common parts of display devices>

[0675] Figure 53 to Figure 55 The display device 700 in the embodiment includes: a routing wiring section 711; a pixel section 702; a source driver circuit section 704; and an FPC terminal section 708. The routing wiring section 711 includes a signal line 710. The pixel section 702 includes a transistor 750 and a capacitor 790. The source driver circuit section 704 includes a transistor 752.

[0676] The transistor 750 and the transistor 752 have the same structure as the above-described transistor 100A. Note that the transistor 750 and the transistor 752 may have the structure of any other transistor among the transistors described in the above embodiment.

[0677] The transistor used in this embodiment includes a highly purified oxide semiconductor film in which the formation of oxygen vacancies is suppressed. The transistor can reduce the off-state current. Therefore, the retention time of electrical signals such as image signals can be extended, and the writing interval can also be extended in the state where the power is turned on. Therefore, the frequency of refresh operation can be reduced, thereby suppressing power consumption.

[0678] In addition, the transistor used in this embodiment can have a high field effect mobility and can therefore be driven at high speed. For example, in a liquid crystal display device including such a transistor capable of high-speed driving, a switching transistor for a pixel portion and a driving transistor for a driving circuit portion can be formed on the same substrate. In other words, since a semiconductor device formed of a silicon wafer or the like does not need to be used separately as a driving circuit, the number of components of the semiconductor device can be reduced. In addition, a high-quality image can also be provided in the pixel portion by using a transistor capable of high-speed driving.

[0679] The capacitor 790 includes a lower electrode and an upper electrode. The lower electrode is formed by processing the same conductive film as the conductive film used as the first gate electrode of the transistor 750. The upper electrode is formed by processing the conductive film used as the source electrode and the drain electrode or the conductive film used as the second gate electrode of the transistor 750. Between the lower electrode and the upper electrode, there are provided: an insulating film formed by forming the same insulating film as the insulating film used as the first gate insulating film of the transistor 750; and an insulating film formed by forming the same insulating film as the insulating film used as the protective insulating film on the transistor 750. That is, the capacitor 790 has a stacked structure in which the insulating film used as a dielectric film is sandwiched between a pair of electrodes.

[0680] exist Figure 53 to Figure 55 In the embodiment, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

[0681] Although Figure 53 to Figure 55The examples in which the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 have the same structure are shown, but an embodiment of the present invention is not limited to this. For example, the pixel portion 702 and the source driver circuit portion 704 may also include different transistors. Specifically, a structure in which the pixel portion 702 uses a top-gate transistor and the source driver circuit portion 704 uses a bottom-gate transistor, or a structure in which the pixel portion 702 uses a bottom-gate transistor and the source driver circuit portion 704 uses a top-gate transistor, etc. can be cited. Note that the above-mentioned "source driver circuit portion 704" can also be referred to as a gate driver circuit portion.

[0682] The signal line 710 is formed in the same process as a conductive film serving as a source electrode and a drain electrode of the transistors 750 and 752. When the signal line 710 is formed using a material containing a copper element, signal delay due to wiring resistance is reduced, and a large-screen display can be achieved.

[0683] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed in the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. The connection electrode 760 and the terminal included in the FPC 716 are electrically connected through the anisotropic conductive film 780.

[0684] For example, a glass substrate can be used as the first substrate 701 and the second substrate 705. A flexible substrate can also be used as the first substrate 701 and the second substrate 705. An example of the flexible substrate is a plastic substrate.

[0685] A structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film and is used to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Alternatively, a spherical spacer may be used as the structure 778.

[0686] On the second substrate 705 side, a light-shielding film 738 serving as a black matrix, a coloring film 736 serving as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the coloring film 736 are provided.

[0687] <3-2. Structural Example of Display Device Including Liquid Crystal Element>

[0688] Fig.53 The display device 700 in the embodiment includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. Fig.53The display device 700 can display an image by changing the alignment state of the liquid crystal layer 776 by applying a voltage between the conductive film 772 and the conductive film 774, thereby controlling the transmission and non-transmission of light.

[0689] The conductive film 772 is electrically connected to a conductive film used as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed over the planarizing insulating film 770 and used as a pixel electrode, that is, one electrode of a display element.

[0690] As the conductive film 772, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. As the conductive film that reflects visible light, for example, a material containing aluminum or silver is preferably used.

[0691] When a conductive film that reflects visible light is used as the conductive film 772, the display device 700 is a reflective liquid crystal display device. When a conductive film that transmits visible light is used as the conductive film 772, the display device 700 is a transmissive liquid crystal display device.

[0692] By changing the structure on the conductive film 772, the driving method of the liquid crystal element can be changed. Fig.54 An example of this is shown below. Fig.54 The display device 700 shown is an example of a liquid crystal element driving method using a horizontal electric field method (for example, FFS mode). Fig.54 In the case of the structure shown, an insulating film 773 is provided on the conductive film 772, and a conductive film 774 is provided on the insulating film 773. In this case, the conductive film 774 has a function as a common electrode, and the orientation state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive film 772 and the conductive film 774 via the insulating film 773.

[0693] Although in Fig.53 and Fig.54 Although not shown in the figure, an alignment film may be provided on the side where the conductive film 772 and / or the conductive film 774 contacts the liquid crystal layer 776. Fig.53 and Fig.54 Although not shown in the figure, optical components (optical substrates) such as polarization components, phase difference components, and anti-reflection components may be appropriately provided. For example, circular polarization using a polarization substrate and a phase difference substrate may also be used. In addition, backlight, side light, etc. may also be used as a light source.

[0694] When a liquid crystal element is used as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, homogeneous phase, etc. depending on the conditions.

[0695] In the case of adopting the lateral electric field method, liquid crystals exhibiting a blue phase without an orientation film can also be used. The blue phase is a type of liquid crystal phase, and refers to the phase that appears just before the transition from the cholesteric phase to the homogeneous phase when the temperature of the cholesteric liquid crystal is raised. Because the blue phase only appears within a narrow temperature range, a liquid crystal composition in which a chiral agent is mixed is used in the liquid crystal layer to expand the temperature range. Since the liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a fast response speed and is optically isotropic, an orientation treatment is not required. Since there is no need to set an orientation film and no friction treatment is required, electrostatic damage caused by the friction treatment can be prevented, thereby reducing defects and damage to the liquid crystal display device in the manufacturing process. In addition, the viewing angle dependence of the liquid crystal material exhibiting a blue phase is small.

[0696] When a liquid crystal element is used as a display element, the following modes can be used: twisted nematic (TN) mode, in-plane switching (IPS) mode, fringe field switching (FFS) mode, axisymmetrically aligned microcell (ASM) mode, optically compensated bend (OCB) mode, ferroelectric liquid crystal (FLC) mode, and antiferroelectric liquid crystal (AFLC) mode, etc.

[0697] In addition, a normally black liquid crystal display device such as a vertical alignment (VA) mode transmissive liquid crystal display device may also be used. There are several examples of vertical alignment modes, such as a multi-domain vertical alignment (MVA) mode, a vertically aligned configuration (PVA) mode, an ASV mode, etc.

[0698] <3-3. Display device using light-emitting element>

[0699] Fig.55 The display device 700 shown includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788. Fig.55 The display device 700 shown can display an image by emitting light from an EL layer 786 of a light-emitting element 782. Note that the EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0700] Examples of materials that can be used for organic compounds include fluorescent materials or phosphorescent materials. Examples of materials that can be used for quantum dots include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core-type quantum dots. In addition, materials containing element groups of Groups 12 and 16, Groups 13 and 15, or Groups 14 and 16 can also be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used.

[0701] The organic compound and the inorganic compound can be deposited by evaporation (including vacuum evaporation), droplet jetting (also known as inkjet), coating, gravure printing, etc. The EL layer 786 may contain a low molecular weight material, a medium molecular weight material (including an oligomer and a dendrimer), or a high molecular weight material.

[0702] Here, refer to FIG. 58A to FIG. 58D A method of forming the EL layer 786 by a droplet discharge method is described. FIG. 58A to FIG. 58D This is a cross-sectional view illustrating a method of forming the EL layer 786.

[0703] First, a conductive film 772 is formed on the planarization insulating film 770, and an insulating film 730 is formed so as to cover a portion of the conductive film 772 (see Fig.58A ).

[0704] Next, droplets 784 are ejected from a droplet ejecting device 783 onto the exposed portion of the conductive film 772, which is the opening of the insulating film 730, to form a layer 785 containing a composition. The droplets 784 are a composition containing a solvent, and adhere to the conductive film 772 (see Fig.58B ).

[0705] Note that the step of ejecting the droplets 784 may be performed under reduced pressure.

[0706] Next, the solvent in the layer 785 containing the composition is removed and the composition is cured to form an EL layer 786 (see Fig.58C ).

[0707] The solvent can be removed by a drying process or a heating process.

[0708] Next, a conductive film 788 is formed over the EL layer 786, thereby forming a light-emitting element 782 (see Fig.58D ).

[0709] As described above, when the EL layer 786 is formed by a droplet discharge method, the composition can be selectively discharged, so that material loss can be reduced. In addition, since a photolithography step for processing a shape is not required, the process can be simplified, thereby achieving cost reduction.

[0710] The above-mentioned droplet ejecting method is a general term including a unit such as a nozzle having an ejection port for a composition or a head having one or more nozzles.

[0711] Next, refer to Fig.59 A liquid droplet ejecting device used in the liquid droplet ejecting method will be described. Fig.59 14 is a schematic diagram for explaining the droplet ejecting device 1400 .

[0712] The droplet ejecting device 1400 includes a droplet ejecting unit 1403. The droplet ejecting unit 1403 is provided with a head 1405 and a head 1412.

[0713] By controlling the control unit 1407 connected to the head 1405 and the head 1412 by the computer 1410, a pre-programmed pattern can be drawn.

[0714] As the timing of drawing, for example, drawing can be performed with reference to a mark 1411 formed on the substrate 1402. Alternatively, the reference point can be determined with reference to the edge of the substrate 1402. Here, the mark 1411 is detected by the imaging unit 1404 and converted into a digital signal by the image processing unit 1409. Then, the digital signal is recognized by the computer 1410 to generate a control signal, and the control signal is transmitted to the control unit 1407.

[0715] As the imaging unit 1404, an image sensor using a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) or the like can be used. Note that information on a pattern to be formed on the substrate 1402 is stored in a storage medium 1408, and a control signal can be transmitted to a control unit 1407 based on the information to control each head 1405, head 1412, etc. of the droplet ejecting unit 1403. The ejected material is supplied to the head 1405, head 1412 through a pipe from a material supply source 1413, a material supply source 1414, respectively.

[0716] The interior of the head 1405 is provided with a space filled with a liquid material and a nozzle for ejecting a liquid material as indicated by a dotted line 1406. Although not shown in the figure, the head 1412 has the same internal structure as the head 1405. When the size of the nozzle of the head 1405 is different from the size of the nozzle of the head 1412, different materials can be used to simultaneously draw patterns with different widths. A single head can be used to eject a variety of light-emitting materials and draw patterns. When drawing patterns over a wide area, in order to increase the throughput, a plurality of nozzles can be used to simultaneously eject the same light-emitting material and draw patterns. When using a large substrate, the head 1405 and the head 1412 are spaced apart in a uniform manner. Fig.59 The substrate can be scanned freely in the directions of the arrows X, Y, and Z, and the area to be drawn can be freely set. Thus, a plurality of identical patterns can be drawn on one substrate.

[0717] In addition, the process of spraying the composition can be carried out under reduced pressure. The substrate can be heated when the composition is sprayed. After spraying the composition, one or both of the drying process and the firing process are carried out. The drying process and the firing process are both a type of heat treatment process, and the purpose, temperature and time of each process are different. The drying process and the firing process are carried out under normal pressure or reduced pressure by laser irradiation, rapid thermal annealing or the use of a heating furnace. Note that there are no particular restrictions on the timing of the heat treatment and the number of times the heat treatment is carried out. In order to carry out a good drying process and firing process, the temperature depends on the material of the substrate and the properties of the composition.

[0718] As described above, the EL layer 786 can be formed using a droplet discharge device.

[0719] Back again Fig.55 An illustration of a display device 700 is shown.

[0720] exist Fig.55 In the display device 700 shown, an insulating film 730 is provided on a planarizing insulating film 770 and a conductive film 772. The insulating film 730 covers a portion of the conductive film 772. Note that the light emitting element 782 has a top emission structure. Therefore, the conductive film 788 has light-transmitting properties and transmits light emitted by the EL layer 786. Although a top emission structure is illustrated in this embodiment mode, the present invention is not limited thereto. For example, a bottom emission structure that emits light to one side of the conductive film 772 or a double-sided emission structure that emits light to both the conductive film 772 side and the conductive film 788 side may also be applied.

[0721] A coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. The coloring film 736 and the light shielding film 738 are covered by the insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with the sealing film 732. Fig.55 The display device 700 shown in the figure has a structure in which the coloring film 736 is provided, but the present invention is not limited to this. For example, when the EL layer 786 is formed by separate coating, a structure in which the coloring film 736 is not provided may be adopted.

[0722] <3-4. Example of a structure in which an input / output device is provided in a display device>

[0723] Also available in Fig.54 and Fig.55 An input-output device is provided in the display device 700 shown in the figure. Examples of the input-output device include a touch screen and the like.

[0724] Fig.56 Shown in Fig.54 The display device 700 shown includes a touch screen 791 structure. Fig.57 Shown in Fig.55 The display device 700 shown includes a touch screen 791 structure.

[0725] Fig.56 is Fig.54 The cross-sectional view of the display device 700 shown in FIG. Fig.57 is Fig.55 The display device 700 is shown in a cross-sectional view in which a touch screen 791 is provided.

[0726] First, the following instructions Fig.56 and Fig.57 Touch screen 791 is shown.

[0727] Fig.56 and Fig.57 The touch panel 791 shown is a so-called In-Cell type touch panel provided between the substrate 705 and the coloring film 736. The touch panel 791 is formed on the substrate 705 side before the coloring film 736 is formed.

[0728] Note that the touch screen 791 includes a light shielding film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, when a detection object such as a finger or a stylus pen approaches, a change in mutual capacitance between the electrode 793 and the electrode 794 can be detected.

[0729] exist Fig.56 and Fig.57The portion where the electrode 793 and the electrode 794 intersect is shown above the transistor 750 shown in FIG. The electrode 796 is electrically connected to the two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795. Note that Fig.56 and Fig.57 7 shows a structure in which the region where the electrode 796 is provided is provided in the pixel portion 702 , but the present invention is not limited thereto. For example, the region where the electrode 796 is provided may also be provided in the source driver circuit portion 704 .

[0730] The electrodes 793 and 794 are provided in the region overlapping with the light shielding film 738. Fig.56 As shown, the electrode 793 preferably does not overlap with the light emitting element 782. Fig.57 As shown, the electrode 793 preferably does not overlap with the liquid crystal element 775. In other words, the electrode 793 has an opening in the area overlapping with the light-emitting element 782 and the liquid crystal element 775. That is, the electrode 793 has a grid shape. By adopting this structure, the electrode 793 does not need to block the light emitted by the light-emitting element 782. Alternatively, the electrode 793 does not need to block the light passing through the liquid crystal element 775. Therefore, since the brightness decrease caused by the configuration of the touch screen 791 is minimal, a display device with high visibility and reduced power consumption can be realized. Note that the electrode 794 can also have the same structure.

[0731] Electrodes 793 and 794 do not overlap with light emitting element 782, so metal materials with low visible light transmittance can be used for electrodes 793 and 794. Alternatively, electrodes 793 and 794 do not overlap with liquid crystal element 775, so metal materials with low visible light transmittance can be used for electrodes 793 and 794.

[0732] Therefore, compared with an electrode using an oxide material having high visible light transmittance, the resistance of the electrodes 793 and 794 can be reduced, thereby improving the sensor sensitivity of the touch screen.

[0733] For example, the electrodes 793, 794, and 796 may also use conductive nanowires. The average diameter of the nanowires may be greater than 1 nm and less than 100 nm, preferably greater than 5 nm and less than 50 nm, and more preferably greater than 5 nm and less than 25 nm. As the nanowires, metal nanowires such as Ag nanowires, Cu nanowires, and Al nanowires or carbon nanotubes may be used. For example, when Ag nanowires are used as any one or all of the electrodes 793, 794, and 796, a visible light transmittance of greater than 89% and a sheet resistance of greater than 40 Ω / square and less than 100 Ω / square may be achieved.

[0734] Although in Fig.56 and Fig.57, but the structure of the In-Cell touch screen is not limited thereto. For example, a so-called On-Cell touch screen formed on the display device 700 or a so-called Out-Cell touch screen attached to the display device 700 may be used.

[0735] In this way, the display device according to one embodiment of the present invention can be used in combination with touch panels of various types.

[0736] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0737] (Implementation 4)

[0738] In this embodiment, refer to FIG. 60A to FIG. 60C A display device including a semiconductor device according to one embodiment of the present invention will be described.

[0739] <4. Circuit Structure of Display Device>

[0740] Fig.60A The display device shown includes: a region having pixels of display elements (hereinafter referred to as a pixel portion 502); a circuit portion arranged outside the pixel portion 502 and having a circuit for driving the pixels (hereinafter referred to as a driving circuit portion 504); a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 506); and a terminal portion 507. Note that the protection circuit 506 may not be provided.

[0741] A part or all of the driver circuit portion 504 is preferably formed on the same substrate as the pixel portion 502. Thus, the number of components and the number of terminals can be reduced. When a part or all of the driver circuit portion 504 is not formed on the same substrate as the pixel portion 502, a part or all of the driver circuit portion 504 can be mounted by COG or tape automated bonding (TAB).

[0742] The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number greater than or equal to 2) and Y columns (Y is a natural number greater than or equal to 2). The driving circuit portion 504 includes a driving circuit such as a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving the display element in the pixel (hereinafter referred to as a source driver 504b).

[0743] The gate driver 504a includes a shift register, etc. The gate driver 504a receives a signal for driving the shift register through the terminal portion 507 and outputs a signal. For example, the gate driver 504a is input with a start pulse signal, a clock signal, etc. and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of the wiring (hereinafter referred to as the scanning lines GL_1 to GL_X) to which the scanning signal is supplied. Note that a plurality of gate drivers 504a may also be provided, and the scanning lines GL_1 to GL_X may be controlled individually by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, this is not limited to the above, and the gate driver 504a may also supply other signals.

[0744] The source driver 504b includes a shift register, etc. The source driver 504b receives a signal for driving the shift register and a signal (image signal) for deriving a data signal therefrom through a terminal portion 507. The source driver 504b has a function of generating a data signal written to the pixel circuit 501 according to the image signal. In addition, the source driver 504b has a function of controlling the output of the data signal according to a pulse signal generated by the input of a start pulse signal, a clock signal, etc. In addition, the source driver 504b has a function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) supplied with the data signal. Alternatively, the source driver 504b has a function of supplying an initialization signal. However, it is not limited thereto, and the source driver 504b can supply other signals.

[0745] The source driver 504b includes, for example, a plurality of analog switches. The source driver 504b can output a signal obtained by time-dividing an image signal as a data signal by sequentially turning on the plurality of analog switches. The source driver 504b can also include a shift register or the like.

[0746] The pulse signal and the data signal are input to each of the plurality of pixel circuits 501 through one of the plurality of scanning lines GL supplied with the scanning signal and one of the plurality of data lines DL supplied with the data signal, respectively. The gate driver 504a controls the writing and holding of the data signal in each of the plurality of pixel circuits 501. For example, the pulse signal is input from the gate driver 504a to the pixel circuit 501 in the mth row and nth column through the scanning line GL_m (m is a natural number less than X), and the data signal is input from the source driver 504b to the pixel circuit 501 in the mth row and nth column through the data line DL_n (n is a natural number less than Y) according to the potential of the scanning line GL_m.

[0747] Fig.60AThe protection circuit 506 in the display device is connected to, for example, a scanning line GL between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 may be connected to a wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 may be connected to a wiring between the source driver 504b and the terminal portion 507. Note that the terminal portion 507 refers to a portion having a terminal for inputting power, a control signal, and an image signal from an external circuit to the display device.

[0748] The protection circuit 506 electrically connects a wiring connected thereto to another wiring when a potential outside a certain range is supplied thereto.

[0749] like Fig.60A As shown, by providing the pixel portion 502 and the driver circuit portion 504 with a protection circuit 506, the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) or the like can be improved. Note that the structure of the protection circuit 506 is not limited to this, and for example, the protection circuit 506 can be connected to the gate driver 504a or the source driver 504b. Alternatively, the protection circuit 506 can be connected to the terminal portion 507.

[0750] Although in Fig.60A , the example in which the driver circuit portion 504 includes a gate driver 504a and a source driver 504b is shown, but one embodiment of the present invention is not limited to this. For example, only the gate driver 504a may be formed and a separately prepared substrate (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) formed with a source driver circuit may be mounted.

[0751] Fig.60A For example, each of the plurality of pixel circuits 501 may have Fig.60B The structure shown.

[0752] Fig.60B The pixel circuit 501 in FIG. 5 includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the previous embodiment can be applied to the transistor 550.

[0753] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the written data. In addition, a common potential may be supplied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. The potential of one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 may be different between rows.

[0754] Examples of driving methods for the display device including the liquid crystal element 570 include: TN mode; STN mode; VA mode; axisymmetrically aligned microcell (ASM) mode; optically compensated bend (OCB) mode; ferroelectric liquid crystal (FLC) mode; antiferroelectric liquid crystal (AFLC) mode; MVA mode; vertical alignment configuration (PVA) mode; IPS mode; FFS mode or transverse bend alignment (TBA) mode, etc. Other examples of driving methods for the display device include electrically controlled birefringence (ECB) mode, polymer dispersed liquid crystal (PDLC) mode, polymer network liquid crystal (PNLC) mode, and guest-host mode. However, it is not limited to this, and various liquid crystal elements and driving methods can be used.

[0755] In the pixel circuit 501 at the mth row and the nth column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other of the source electrode and the drain electrode of the transistor 550 is electrically connected to the other electrode of the pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the scanning line GL_m. The transistor 550 is configured to control the writing of the data signal by being turned on or off.

[0756] One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other of the pair of electrodes of the capacitor 560 is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 560 is used as a storage capacitor for storing written data.

[0757] For example, in the Fig.60B In the display device of the pixel circuit 501 shown in FIG. Fig.60A The gate driver 504a in the embodiment sequentially selects the pixel circuits 501 of each row and turns on the transistors 550 to write data signals.

[0758] When the transistor 550 is turned off, the pixel circuit 501 to which the data has been written is in a holding state. By sequentially performing the above steps row by row, an image can be displayed.

[0759] also, Fig.60A For example, each of the plurality of pixel circuits 501 shown may have Fig.60C The structure shown.

[0760] Fig.60C The pixel circuit 501 in FIG. 5 includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in the previous embodiment can be applied to the transistor 552 and / or the transistor 554.

[0761] One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a data line DL_n) to which a data signal is supplied. A gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied.

[0762] The transistor 552 is configured to control writing of a data signal by being turned on or off.

[0763] One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL_a), and the other of the pair of electrodes of the capacitor 562 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552 .

[0764] The capacitor 562 is used as a storage capacitor for storing written data.

[0765] One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a, and a gate electrode of the transistor 554 is electrically connected to the other of a source electrode and a drain electrode of the transistor 552 .

[0766] One of the anode and the cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other of the anode and the cathode of the light emitting element 572 is electrically connected to the other of the source electrode and the drain electrode of the transistor 554 .

[0767] As the light-emitting element 572, for example, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used. Note that the light-emitting element 572 is not limited to an organic EL element, and may be an inorganic EL element including an inorganic material.

[0768] One of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other of the potential supply line VL_a and the potential supply line VL_b is supplied with the low power supply potential VSS.

[0769] For example, in the Fig.60C In the display device of the pixel circuit 501, by Fig.60A The gate driver 504a in the circuit sequentially selects the pixel circuit 501 of each row, turns on the transistor 552 and writes the data signal.

[0770] When the transistor 552 is turned off, the pixel circuit 501 to which the data is written is in a hold state. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal. The light-emitting element 572 emits light at a brightness corresponding to the amount of current flowing. By performing the above steps in sequence row by row, an image can be displayed.

[0771] This embodiment mode may be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0772] (Implementation 5)

[0773] In this embodiment, refer to Fig.61 , Figures 62A to 62E , Figures 63A to 63G , Figures 64A to 64E , Fig.65A and Fig.65B as well as Fig.66A and Fig.66B A display module and an electronic device including a semiconductor device according to an embodiment of the present invention will be described.

[0774] <5-1. Display module>

[0775] exist Fig.61 In the display module 7000 shown, a touch screen 7004 connected to an FPC 7003 , a display panel 7006 connected to an FPC 7005 , a backlight 7007 , a frame 7009 , a printed circuit board 7010 , and a battery 7011 are arranged between an upper cover 7001 and a lower cover 7002 .

[0776] For example, the semiconductor device according to one embodiment of the present invention can be used for the display panel 7006 .

[0777] The shapes or sizes of the upper cover 7001 and the lower cover 7002 may be appropriately changed according to the sizes of the touch screen 7004 and the display panel 7006 .

[0778] The touch screen 7004 can be a resistive film touch screen or a capacitive touch screen, and can overlap with the display panel 7006. In addition, the opposing substrate (sealing substrate) of the display panel 7006 can also have the function of a touch screen. In addition, a light sensor can be provided in each pixel of the display panel 7006 to form an optical touch screen.

[0779] Backlight 7007 includes light source 7008. Note that although Fig.61 7007, but one embodiment of the present invention is not limited thereto. For example, a structure in which the light source 7008 is provided at the end of the backlight 7007 and a light diffusion plate is also provided may be adopted. Note that when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective panel or the like is used, the backlight 7007 may not be provided.

[0780] The frame 7009 protects the display panel 7006 and is used as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 7010. The frame 7009 may also function as a heat sink.

[0781] The printed circuit board 7010 includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply can be used, and a power supply using a separately provided battery 7011 can be used. When a commercial power supply is used, the battery 7011 can be omitted.

[0782] Components such as a polarizing plate, a phase difference plate, and a prism sheet may also be provided in the display module 7000 .

[0783] <5-2. Electronic equipment 1>

[0784] then, Figures 62A to 62E An example of an electronic device is shown.

[0785] Fig.62A FIG. 8 is an external view of a camera 8000 equipped with a viewfinder 8100 .

[0786] The camera 8000 includes a housing 8001 , a display portion 8002 , operation buttons 8003 , a shutter button 8004 , etc. The camera 8000 is also provided with a detachable lens 8006 .

[0787] Here, the camera 8000 can be replaced by removing the lens 8006 from the housing 8001 , or the lens 8006 can be included in the housing 8001 .

[0788] The camera 8000 can perform imaging by pressing a shutter button 8004. In addition, the display portion 8002 is used as a touch screen, and imaging can also be performed by touching the display portion 8002.

[0789] The housing 8001 of the camera 8000 includes an insert having electrodes, and can be connected to a flash device or the like in addition to the viewfinder 8100 .

[0790] The viewfinder 8100 includes a housing 8101 , a display portion 8102 , a button 8103 , and the like.

[0791] The housing 8101 includes an inserter that is fitted into the inserter of the camera 8000, and the viewfinder 8100 can be mounted on the camera 8000. The inserter includes electrodes, and an image or the like received from the camera 8000 through the electrodes can be displayed on the display portion 8102.

[0792] The button 8103 is used as a power button. By using the button 8103, display or non-display of the display portion 8102 can be switched.

[0793] The display device according to one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100 .

[0794] Although in Fig.62A The camera 8000 and the viewfinder 8100 are separate and detachable electronic devices, but a viewfinder including a display device may be included in the housing 8001 of the camera 8000 .

[0795] Fig.62B 8200 is a diagram showing the appearance of a head mounted display 8200 .

[0796] The head mounted display 8200 includes a mounting portion 8201 , a lens 8202 , a main body 8203 , a display portion 8204 , a cable 8205 , etc. The mounting portion 8201 includes a battery 8206 .

[0797] Power is supplied from a battery 8206 to a main body 8203 via a cable 8205. The main body 8203 includes a wireless receiver and the like, and can display image data such as received image data on a display portion 8204. By capturing the movement of the user's eyeballs and eyelids with a camera provided in the main body 8203 and calculating the coordinates of the user's viewpoint based on the data, the user's viewpoint can be used as an input method.

[0798] In addition, a plurality of electrodes may be provided at the position of the mounting portion 8201 that is touched by the user. The main body 8203 may also have a function of identifying the user's viewpoint by detecting the current flowing through the electrodes according to the movement of the user's eyeballs. The main body 8203 may be configured to monitor the user's pulse by detecting the current flowing through the electrodes. The mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may display the user's biological information on the display portion 8204. The main body 8203 may also be configured to detect the movement of the user's head, etc., and change the image displayed on the display portion 8204 in synchronization with the movement of the user's head, etc.

[0799] The display device of one embodiment of the present invention can be applied to the display portion 8204 .

[0800] Figures 62C to 62E 8300 is an external appearance of a head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, an item for fixing such as a belt 8304, and a pair of lenses 8305.

[0801] The user can see the display on the display unit 8302 through the lens 8305. Preferably, the display unit 8302 is configured to be curved. When the display unit 8302 is configured to be curved, the user can experience a high sense of reality. Although a structure in which one display unit 8302 is provided is exemplified in this embodiment, the number of display units 8302 is not limited to one. For example, two display units 8302 may be provided, and when one display unit is configured to correspond to one eye of the user, a three-dimensional display using parallax may be performed.

[0802] The display device of one embodiment of the present invention can be applied to the display portion 8302. Since the display device including the semiconductor device of one embodiment of the present invention has extremely high resolution, even if Fig.62E By using lens 8305 for magnification in this way, it is possible to display a more realistic image without causing the user to see the pixels.

[0803] <5-3. Electronic equipment 2>

[0804] then, Figures 63A to 63G , Figures 64A to 64E Shown with Figures 62A to 62E The electronic devices shown are examples of different electronic devices.

[0805] Figures 63A to 63G The electronic device shown includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connecting terminal 9006, a sensor 9007 (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc.

[0806] Figures 63A to 63G , Figures 64A to 64E The electronic device shown has various functions. For example, it may have the following functions: the function of displaying various information (static images, dynamic images, text images, etc.) on the display unit; the function of a touch panel; the function of displaying a calendar, date, or time, etc.; the function of controlling processing by using various software (programs); the function of wireless communication; the function of connecting to various computer networks by using the wireless communication function; the function of sending or receiving various data by using the wireless communication function; the function of reading programs or data stored in a storage medium and displaying them on the display unit; etc. Note that Figures 63A to 63G , Figures 64A to 64E The functions that the electronic device shown may have are not limited to the above functions, and the electronic device may have various functions. Figures 63A to 63G , Figures 64A to 64E Although not shown in the figure, each electronic device may include multiple display units. In addition, each electronic device may be provided with a camera or the like so as to have the following functions: a function of taking a still image; a function of taking a moving image; a function of storing the taken image in a storage medium (an external storage medium or a storage medium built into the camera); a function of displaying the taken image on a display unit; etc.

[0807] Below, we explain in detail Figures 63A to 63G , Figures 64A to 64E Electronic equipment shown.

[0808] Fig.63A 1 is a perspective view showing a television set 9100. The television set 9100 can include a large display portion 9001 of, for example, 50 inches or more or 100 inches or more.

[0809] Fig.63B 9101 is a stereoscopic diagram showing a portable information terminal 9101. The portable information terminal 9101 has, for example, one or more functions of a telephone, an electronic notebook, and an information reading device. Specifically, the portable information terminal 9101 can be used as a smart phone. Note that the portable information terminal 9101 may include a speaker, a connection terminal, a sensor, and the like. The portable information terminal 9101 can display text and image information on multiple faces thereof. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one face of the display unit 9001. In addition, information 9051 represented by a dotted rectangle can be displayed on another face of the display unit 9001. Examples of information 9051 include a display prompting the receipt of information from an email, SNS (Social Networking Services), or a phone call, etc.; a title of an email or SNS, etc.; a sender name of an email or SNS, etc.; a date; a time; a power level; and an antenna reception strength, etc. Alternatively, an operation button 9050, etc. can be displayed instead of information 9051 at a position where information 9051 is displayed.

[0810] Fig.63C9102 is a three-dimensional diagram of a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user of the portable information terminal 9102 can confirm its display (here, information 9053) while the portable information terminal 9102 is placed in a jacket pocket. Specifically, the phone number or name of the person calling is displayed at a position where such information can be viewed from above the portable information terminal 9102. The user can confirm the display without taking the portable information terminal 9102 out of his pocket, thereby being able to determine whether to answer the call.

[0811] Fig.63D : is a stereoscopic diagram showing a watch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as mobile phones, e-mails, reading and editing of articles, music playback, network communications, computer games, etc. The display surface of the display unit 9001 is curved, and display can be performed on the curved display surface. The portable information terminal 9200 can perform short-range wireless communications that are standardized by communications. For example, a hands-free call can be made by communicating with a headset capable of wireless communications through the portable information terminal 9200. In addition, the portable information terminal 9200 includes a connection terminal 9006, and data can be exchanged directly with other information terminals through a connector. In addition, charging can also be performed through the connection terminal 9006. Note that the charging operation can also be performed using wireless power supply instead of through the connection terminal 9006.

[0812] Fig.63E , Fig.63F and Figure 63G The three-dimensional diagrams of the foldable portable information terminal 9201 are respectively in an unfolded state, a folded state from an unfolded state, or a folded state from a folded state to an unfolded state and a folded state. The portable information terminal 9201 has good portability in the folded state. When the portable information terminal 9201 is in the unfolded state, the large display area that is seamlessly spliced ​​has a strong overview. The display unit 9001 of the portable information terminal 9201 is supported by three shells 9000 connected by hinges 9055. By bending the two shells 9000 through the hinges 9055, the portable information terminal 9201 can be reversibly changed from the unfolded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of more than 1 mm and less than 150 mm.

[0813] Fig.64A is with Fig.63AThe television set shown is a perspective view of a television set 9150 which is different from the television set shown. In the television set 9150, a display portion 9152 is incorporated in a housing 9151. Here, the housing 9151 is supported by a stand 9153. In the television set 9150, unlike the television set 9100, a display portion 9152 and a housing 9151 are formed.

[0814] The operation can be performed by using the operation switch provided in the housing 9151 and the remote control operation machine 9154 provided separately. Fig.64A The television device 9150 shown in FIG. 1 is operated. In addition, a touch sensor may be provided in the display portion 9152, and the display portion 9152 may be operated by touching the display portion 9152 with a finger or the like. In addition, the remote controller 9154 may be provided with a display portion for displaying data output from the remote controller 9154. By using the operation keys or the touch screen of the remote controller 9154, the channel and volume can be operated, and the image displayed on the display portion 9152 can be operated.

[0815] Note that the television set 9150 includes a receiver, a modem, and the like. General television broadcasts can be received by using the receiver. Furthermore, when the modem connects the television set 9150 to a wired or wireless communication network, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers, etc.) information communication can be performed.

[0816] Fig.64B 9250 is a perspective view showing a notebook computer 9250. The notebook computer 9250 includes a housing 9251, a display portion 9252, a keyboard 9253, a pointing device 9254, and the like.

[0817] Fig.64C 9300 is a perspective view showing a fixed-type slot machine 9300. In the slot machine 9300, a display unit 9303 is assembled in a housing 9301. In addition, the slot machine 9300 includes an operation unit such as a start lever 9304 or a stop switch 9305, a coin slot, a speaker, a light source 9306 for a sensor, a sensor 9302, and the like.

[0818] Fig.64D This is the exterior of the 9400 car. Fig.64E The driving seat of a car 9400 is shown. The car 9400 includes a body 9401, wheels 9402, a front windshield 9403, lights 9404, fog lights 9405, and the like.

[0819] The display device according to one embodiment of the present invention can be used for a display unit of the automobile 9400 or the like. For example, the display device according to one embodiment of the present invention can be used for Fig.64E Display portion 9410 to display portion 9417 are shown.

[0820] The display portion 9410 and the display portion 9411 are provided on the front windshield of the automobile. In one embodiment of the present invention, by using a light-transmitting conductive material to manufacture the electrodes in the display device, the display device of one embodiment of the present invention can be made into a so-called transparent display device that can see the opposite side. The transparent display device does not become an obstacle to the field of vision even when driving the automobile 9400. Therefore, the display device of one embodiment of the present invention can be provided on the front windshield of the automobile 9400. Note that when a transistor or the like is provided in the display device, it is preferable to use a light-transmitting transistor such as an organic transistor using an organic semiconductor material or a transistor using an oxide semiconductor.

[0821] The display unit 9412 is disposed on the pillar portion. The display unit 9413 is disposed on the instrument panel portion. For example, by displaying an image from an imaging unit disposed on the vehicle body on the display unit 9412, the field of view blocked by the pillar can be supplemented. Similarly, the display unit 9413 can supplement the field of view blocked by the instrument panel, and the display unit 9414 can supplement the field of view blocked by the door. In other words, by displaying the image from the imaging unit disposed on the outside of the vehicle, the blind spot can be supplemented, thereby improving safety. In addition, by displaying the image that supplements the part that the driver cannot see, safety can be confirmed more naturally and comfortably.

[0822] Display unit 9417 is provided in the steering wheel. Display unit 9415, display unit 9416 or display unit 9417 can provide navigation data, speedometer, tachometer, driving distance, fueling amount, gear status, air conditioning settings and other various information. The user can appropriately change the display content and layout displayed by the display unit. Display units 9410 to 9414 can also display the above information.

[0823] In addition, the display portions 9410 to 9417 can also be used as lighting devices.

[0824] Fig.65A 9600 is a perspective view showing a digital signage 9600. The digital signage 9600 may include a display portion 9601, a housing 9602, and a speaker 9603. Fig.65B As shown, the digital signage 9600 can be mounted on a cylindrical column.

[0825] then, Fig.66A and Fig.66B Shown with Figures 62A to 62E , Figures 63A to 63G as well as Figures 64A to 64E The electronic devices shown are examples of different electronic devices. Fig.66A and Fig.66Bis a perspective view of a display device including a plurality of display panels. Note that Fig.66A This is a three-dimensional image of multiple display panels being rolled up. Fig.66B This is a three-dimensional image when multiple display panels are unfolded.

[0826] Fig.66A and Fig.66B The display device 9500 shown includes a plurality of display panels 9501, a shaft portion 9511, and a bearing portion 9512. The plurality of display panels 9501 each include a display region 9502 and a light-transmitting region 9503.

[0827] Each of the plurality of display panels 9501 is flexible. Two adjacent display panels 9501 are arranged so that parts thereof overlap each other. For example, light-transmitting regions 9503 of two adjacent display panels 9501 may overlap. By using a plurality of display panels 9501, a display device with a large screen may be realized. In addition, the display panel 9501 may be rolled up according to the usage, so that a display device with high versatility may be realized.

[0828] Fig.66A and Fig.66B The display device shown may easily have a large screen and thus may also be used as the above-mentioned digital signage.

[0829] also, Fig.66A and Fig.66B The case where the display areas 9502 of adjacent display panels 9501 are separated from each other is shown, but the present invention is not limited to this structure. For example, a continuous display area 9502 can also be realized by overlapping the display areas 9502 of adjacent display panels 9501 without any gap.

[0830] Each of the electronic devices described in this embodiment includes a display portion for displaying some data. Note that the semiconductor device according to one embodiment of the present invention can be applied to an electronic device that does not include a display portion.

[0831] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0832] (Implementation 6)

[0833] In this embodiment, refer to Fig.67A and Fig.67B , Fig.68 as well as Fig.69 One embodiment of a semiconductor device will be described.

[0834] [Structure example]

[0835] Fig.67A and Fig.67B , Fig.68as well as Fig.69 An example of a semiconductor device (storage device) including a capacitor according to one embodiment of the present invention is shown. Note that Fig.67A yes Fig.68 and Fig.69 Circuit diagram of the .

[0836] <Circuit Structure of Semiconductor Device>

[0837] Fig.67A , Fig.68 and Fig.69 The semiconductor devices shown all include a transistor 3300 , a transistor 3200 , and a capacitor 3100 .

[0838] The transistor 3200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 3200 is low, the storage content can be retained for a long time by using the transistor 3200 in a semiconductor device (storage device). In other words, since a semiconductor device (storage device) that does not require a refresh operation or has an extremely low frequency of refresh operation can be formed, power consumption can be substantially reduced.

[0839] exist Fig.67A In the embodiment of the present invention, the first wiring 3001 is electrically connected to the source of the transistor 3300. The second wiring 3002 is electrically connected to the drain of the transistor 3300. The third wiring 3003 is electrically connected to one of the source and the drain of the transistor 3200. The fourth wiring 3004 is electrically connected to the gate of the transistor 3200. The gate of the transistor 3300 and the other of the source and the drain of the transistor 3200 are electrically connected to one electrode of the capacitor 3100. The fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3100.

[0840] Fig.67A The semiconductor device in has a feature of being able to hold the potential of the gate of the transistor 3300, and thus can write, hold, and read information as described below.

[0841] The writing and holding of data are described. First, the potential of the fourth wiring 3004 is set to a potential that makes the transistor 3200 in a conducting state, so that the transistor 3200 is in a conducting state. Thus, the potential of the third wiring 3003 is applied to the node FG electrically connected to the gate of the transistor 3300 and one electrode of the capacitor 3100. In other words, a predetermined charge is applied to the gate of the transistor 3300 (writing). Here, one of the charges given two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. Then, the transistor 3200 is put into a non-conducting state by setting the potential of the fourth wiring 3004 to a potential that makes the transistor 3200 non-conducting, so that the charge is maintained at the node FG (maintained).

[0842] When the off-state current of transistor 3200 is low, the charge of node FG is retained for a long time.

[0843] Next, the reading of data is described. When a proper potential (reading potential) is applied to the fifth wiring 3005 while a predetermined potential (constant potential) is applied to the first wiring 3001, the potential of the second wiring 3002 changes according to the amount of charge held in the node FG. This is because: when the transistor 3300 is an n-channel transistor, the apparent threshold voltage V when a high-level charge is applied to the gate of the transistor 3300 is th_H is lower than the apparent threshold voltage V when a low level charge is applied to the gate of transistor 3300 th_L Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 required to turn the transistor 3300 into the "on state". th_H With V th_L The potential between V 0 , the charge applied to the node FG can be distinguished. For example, when the node FG is supplied with a high-level charge during writing, if the potential of the fifth wiring 3005 is V 0 (>V th_H ), the transistor 3300 becomes "on state". On the other hand, when the node FG is supplied with low-level charge, even if the potential of the fifth wiring 3005 is V 0 ( <V th_L ), the transistor 3300 also remains in the "non-conductive state". Therefore, by identifying the potential of the second wiring 3002, the data held by the node FG can be read.

[0844] By Fig.67A The semiconductor devices shown are arranged in a matrix and can form a memory device (memory cell array).

[0845] Note that when the memory cells are arranged in an array, the data of the desired memory cell must be read out when reading. In the memory cell where the data is not to be read out, a potential that makes the transistor 3300 "non-conductive" regardless of the charge applied to the node FG, that is, a potential lower than V th_H Alternatively, in a memory cell where data is not to be read, a potential that causes the transistor 3300 to be in an “on state” regardless of the charge applied to the node FG, i.e., a potential higher than V th_L The potential is set to read only the data of the desired memory cell.

[0846] <Circuit Structure of Semiconductor Device 2>

[0847] Fig.67B Semiconductor devices and Fig.67A The semiconductor device in Fig.67B The semiconductor device in the embodiment does not include transistor 3300. In this case, it is also possible to Fig.67A The semiconductor device shown in the figure performs the same operation as that of writing and retaining data.

[0848] Below, the description Fig.67B When the transistor 3200 is turned on, the third wiring 3003 and the capacitor 3100 in the floating state are turned on, and the charge is redistributed between the third wiring 3003 and the capacitor 3100. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 has different values ​​depending on the potential of one electrode of the capacitor 3100 (or the charge accumulated in the capacitor 3100).

[0849] For example, when the potential of one electrode of the capacitor 3100 is V, the capacitance of the capacitor 3100 is C, and the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, assuming that the potential of one electrode of the capacitor 3100 becomes two states, namely V1 and V0 (V1>V0) as a state of a storage unit, it can be known that the potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C×V1) / (CB+C)) is higher than the potential of the third wiring 3003 when the potential V0 is maintained (=(CB×VB0+C×V0) / (CB+C)).

[0850] Then, data can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

[0851] In this case, the transistor including the first semiconductor can be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor as the transistor 3200 can be stacked on the driver circuit.

[0852] When a transistor with a low off-state current using an oxide semiconductor is included, the semiconductor device can retain the stored content for a long period of time. That is, no refresh operation is required or the frequency of the refresh operation can be made extremely low, thereby achieving low power consumption. In addition, the stored content can be retained for a long period of time even when there is no power supply (however, preferably a fixed potential).

[0853] In addition, since the semiconductor device does not require a high voltage when writing data, it is not easy for the element to deteriorate. For example, since electrons are not injected into or extracted from the floating gate like in the conventional non-volatile memory, problems such as degradation of the insulator do not occur. In other words, unlike the conventional non-volatile memory, the semiconductor device according to one embodiment of the present invention is a semiconductor device with no limit on the number of rewrites and greatly improved reliability. Furthermore, data is written according to the state of the transistor (conductive state or non-conductive state), so that high-speed operation can be performed.

[0854] <Structure of semiconductor device 1>

[0855] like Fig.68 As shown in FIG. 1 , the semiconductor device according to one embodiment of the present invention includes a transistor 3300 , a transistor 3200 , and a capacitor 3100 . The transistor 3200 is provided above the transistor 3300 , and the capacitor 3100 is provided above the transistor 3300 and the transistor 3200 .

[0856] The transistor 3300 is provided on a substrate 3311 and includes: a conductor 3316, an insulator 3314, a semiconductor region 3312 which is a portion of the substrate 3311; and low resistance regions 3318a and 3318b which are used as a source region and a drain region.

[0857] The transistor 3300 may be a p-channel transistor or an n-channel transistor.

[0858] The channel forming region of the semiconductor region 3312 or the region near it, the low resistance region 3318a and the low resistance region 3318b used as the source region or the drain region preferably include semiconductors such as silicon semiconductors, and more preferably include single crystal silicon. In addition, materials including germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium aluminum arsenide (GaAlAs), etc. may also be included. Silicon that applies stress to the lattice and changes the interplanar spacing to control the effective mass can be used. In addition, the transistor 3300 may also be a high electron mobility transistor (HEMT) using GaAs and GaAlAs.

[0859] The low resistance regions 3318 a and 3318 b contain, in addition to the semiconductor material used for the semiconductor region 3312 , an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0860] The conductor 3316 used as a gate electrode can be formed using a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0861] Note that the threshold voltage can be adjusted by setting the work function according to the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In addition, in order to make the conductor have both conductivity and embedding properties, a stack of metal materials such as tungsten and aluminum is preferably used as the conductor, and tungsten is particularly preferably used in terms of heat resistance.

[0862] exist Fig.68 In the transistor 3300 shown, the semiconductor region 3312 (a part of the substrate 3311) forming the channel has a convex shape. In addition, a conductor 3316 is provided in a manner that covers the side and top surfaces of the semiconductor region 3312 via an insulator 3314. Note that the conductor 3316 can be formed using a material that adjusts the work function. Since the convex portion of the semiconductor substrate is utilized, the transistor 3300 having such a structure is also referred to as a FIN-type transistor. In addition, an insulator used as a mask for forming the convex portion may also be provided in a manner that contacts the upper surface of the convex portion. Although a case where a part of the semiconductor substrate is processed to form the convex portion is shown here, the SOI substrate may also be processed to form a semiconductor film having a convex portion.

[0863] Notice, Fig.68 The structure of the transistor 3300 shown is only an example and is not limited to the above structure. An appropriate transistor can be used according to the circuit structure or driving method. For example, a planar structure can be used as the structure of the transistor 3300. Fig.67B In the case of the circuit structure shown, the transistor 3300 may not be omitted.

[0864] An insulator 3320 , an insulator 3322 , an insulator 3324 , and an insulator 3326 are stacked in this order so as to cover the transistor 3300 .

[0865] The insulator 3320 , the insulator 3322 , the insulator 3324 , and the insulator 3326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0866] The insulator 3322 is used as a planarizing film for planarizing a step generated by the transistor 3300 and the like provided under the insulator 3322. In order to improve the planarity of the top surface of the insulator 3322, the top surface may be planarized by planarization treatment using a CMP method or the like.

[0867] The insulator 3324 is preferably formed using, for example, a film having a barrier property that can prevent hydrogen or impurities from diffusing from the substrate 3311 , the transistor 3300 , or the like into a region where the transistor 3200 is provided.

[0868] For example, as an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 3200, causing the characteristics of the semiconductor element to deteriorate. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 3200 and transistor 3300. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0869] The amount of hydrogen released can be measured by TDS, for example. For example, in the range of 50°C to 500°C in TDS, the amount of hydrogen released from the insulator 3324 converted into hydrogen atoms per area of ​​the insulator 3324 is 10×10 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0870] Note that the dielectric constant of the insulator 3326 is preferably lower than that of the insulator 3324. For example, the relative dielectric constant of the insulator 3326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 3324 is preferably 0.7 times or less of the relative dielectric constant of the insulator 3326, more preferably 0.6 times or less of the relative dielectric constant of the insulator 3326. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance between wirings can be reduced.

[0871] Conductors 3328 and 3330, etc., which are electrically connected to capacitor 3100 or transistor 3200, are embedded in insulators 3320, 3322, 3324, and 3326. Note that conductors 3328 and 3330 are both used as plugs or wirings. Note that, as described later, the same reference numeral may be used to represent a plurality of conductors used as plugs or wirings. In addition, in this specification, wiring and a plug electrically connected to wirings may also be one component. That is, a part of a conductor may be used as wirings, and a part of a conductor may be used as a plug.

[0872] As the material of each plug and wiring (conductor 3328 and conductor 3330, etc.), a single-layer structure or a laminated structure of a conductive material such as a metal material, an alloy material, a metal nitride material or a metal oxide material can be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferred. Alternatively, it is preferred to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0873] A wiring layer may be formed on the insulator 3326 and the conductor 3330. Fig.68In the embodiment of the present invention, an insulator 3350, an insulator 3352, and an insulator 3354 are stacked in this order. In addition, a conductor 3356 is formed in the insulator 3350, the insulator 3352, and the insulator 3354. The conductor 3356 is used as a plug or wiring. Note that the conductor 3356 can be formed using the same material as that used to form the conductor 3328 and the conductor 3330.

[0874] Note that, similar to the insulator 3324, the insulator 3350 is preferably formed using, for example, an insulator having a barrier property to hydrogen. In addition, the conductor 3356 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening of the insulator 3350 having a barrier property to hydrogen. By adopting this structure, the barrier layer can separate the transistor 3300 from the transistor 3200, thereby suppressing the diffusion of hydrogen from the transistor 3300 to the transistor 3200.

[0875] Note that as a conductor having a barrier property to hydrogen, for example, tantalum nitride is preferably used. By stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 3300 can be suppressed while maintaining conductivity as wiring. At this time, the tantalum nitride layer having a barrier property to hydrogen is preferably in contact with the insulator 3350 having a barrier property to hydrogen.

[0876] An insulator 3358, an insulator 3210, an insulator 3212, and an insulator 3216 are stacked in this order over the insulator 3354. As one or all of the insulator 3358, the insulator 3210, the insulator 3212, and the insulator 3216, a substance having a barrier property against oxygen or hydrogen is preferably used.

[0877] The insulator 3358 and the insulator 3212 are preferably formed using, for example, a film having a barrier property that can prevent hydrogen or impurities from diffusing from a region where the substrate 3311 or the transistor 3300 is provided into a region where the transistor 3200 is provided. Therefore, the insulator 3358 and the insulator 3212 can be formed using the same material as that used to form the insulator 3324.

[0878] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Sometimes hydrogen diffuses into a semiconductor element having an oxide semiconductor such as transistor 3200, causing the characteristics of the semiconductor element to deteriorate. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 3200 and transistor 3300. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0879] For example, the insulator 3210 and the insulator 3216 can be formed using the same material as that used to form the insulator 3320. For example, as the insulator 3216, a silicon oxi...

Claims

1. A semiconductor device, include: An oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, Each of the plurality of first regions comprises indium, zinc and an element M selected from Al, Ga, Y and Sn, The second region includes indium, zinc and an element M selected from Al, Ga, Y and Sn, An atomic number ratio of indium to the element M in each of the plurality of first regions is greater than an atomic number ratio of indium to the element M in the second region, and the plurality of first regions are dispersed in the second region.

2. A semiconductor device, include: An oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, Each of the plurality of first regions comprises indium, zinc and an element M selected from Al, Ga, Y and Sn, The second region includes indium, zinc and an element M selected from Al, Ga, Y and Sn, The atomic number ratio of indium to the element M in each of the plurality of first regions is greater than the atomic number ratio of indium to the element M in the second region, and the plurality of first regions are dispersed in the second region, Each of the plurality of first regions includes a plurality of clusters, And, at least one of the plurality of clusters includes a portion longer than or equal to 0.1 nm and shorter than or equal to 2.5 nm.

3. A semiconductor device, include: An oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, Each of the plurality of first regions comprises indium, zinc and an element M selected from Al, Ga, Y and Sn, The second region includes indium, zinc and an element M selected from Al, Ga, Y and Sn, The atomic number ratio of indium to the element M in each of the plurality of first regions is greater than the atomic number ratio of indium to the element M in the second region, and the plurality of first regions are dispersed in the second region, Furthermore, the atomic number ratio of indium to element M and zinc in the second region is [In]:[M]:[Zn]=4:2:3 or in the vicinity thereof.

4. A semiconductor device, include: An oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, Each of the plurality of first regions comprises indium, zinc and an element M selected from Al, Ga, Y and Sn, The second region includes indium, zinc and an element M selected from Al, Ga, Y and Sn, The atomic number ratio of indium to the element M in each of the plurality of first regions is greater than the atomic number ratio of indium to the element M in the second region, The atomic number ratio of indium to the element M in each of the plurality of first regions is 1.1 times or more the atomic number ratio of indium to the element M in the second region, Furthermore, the plurality of first regions are dispersed in the second region.

5. A semiconductor device, include: An oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, Each of the plurality of first regions comprises indium, zinc and an element M selected from Al, Ga, Y and Sn, The second region includes indium, zinc and an element M selected from Al, Ga, Y and Sn, The atomic number ratio of indium to the element M in each of the plurality of first regions is greater than the atomic number ratio of indium to the element M in the second region, The atomic number ratio of indium to the element M in each of the plurality of first regions is 1.1 times or more the atomic number ratio of indium to the element M in the second region, The plurality of first regions are dispersed in the second region, Each of the plurality of first regions includes a plurality of clusters, And, at least one of the plurality of clusters includes a portion longer than or equal to 0.1 nm and shorter than or equal to 2.5 nm.

6. A semiconductor device, include: An oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a plurality of first regions and a second region; a gate electrode; a gate insulating layer between the oxide semiconductor film and the gate electrode; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, Each of the plurality of first regions comprises indium, zinc and an element M selected from Al, Ga, Y and Sn, The second region includes indium, zinc and an element M selected from Al, Ga, Y and Sn, The atomic number ratio of indium to the element M in each of the plurality of first regions is greater than the atomic number ratio of indium to the element M in the second region, the atomic number ratio of indium to the element M in each of the plurality of first regions is 2 to 10 times the atomic number ratio of indium to the element M in the second region, Furthermore, the plurality of first regions are dispersed in the second region.

7. A semiconductor device comprising a transistor, wherein the transistor include: a gate electrode; an oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a first region and a second region; a gate insulating film between the gate electrode and the oxide semiconductor film; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, wherein each of the first region and the second region includes indium and oxygen, the indium concentration in the first region is higher than the indium concentration in the second region, and the first region is surrounded by the second region, And, μ FE (max) / μ FE (Vg = 2V) is greater than 1 and less than 1.5, where μ FE (max) represents the maximum value of the field effect mobility of the transistor, and μ FE (Vg=2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V.

8. A semiconductor device comprising a transistor, wherein the transistor include: a gate electrode; an oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a first region and a second region; a gate insulating film between the gate electrode and the oxide semiconductor film; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, wherein each of the first region and the second region includes indium and oxygen, the indium concentration in the first region is higher than the indium concentration in the second region, and the first region is surrounded by the second region, μ FE (max) / μ FE (Vg = 2V) is greater than 1 and less than 1.5, where μ FE (max) represents the maximum value of the field effect mobility of the transistor, and μ FE (Vg=2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, Furthermore, the indium concentration in the first region is 1.1 times or more the indium concentration in the second region.

9. A semiconductor device comprising a transistor, wherein the transistor include: a gate electrode; an oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a first region and a second region; a gate insulating film between the gate electrode and the oxide semiconductor film; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, wherein each of the first region and the second region includes indium and oxygen, the indium concentration in the first region is higher than the indium concentration in the second region, and the first region is surrounded by the second region, And, μ FE (max) / μ FE (Vg = 2V) is greater than 1 and less than 1.5, where μ FE (max) represents the maximum value of the field effect mobility of the transistor, and μ FE (Vg=2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V, The indium concentration in the first region is 2 to 10 times the indium concentration in the second region, The first region includes indium oxide, Also, the first region and the second region have different crystallinity.

10. A semiconductor device comprising a transistor, wherein the transistor include: a gate electrode; an oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a first region and a second region; a gate insulating film between the gate electrode and the oxide semiconductor film; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, wherein each of the first region and the second region includes indium and oxygen, the indium concentration in the first region is higher than the indium concentration in the second region, and the first region is surrounded by the second region, And, μ FE (max) / μ FE (Vg = 2V) is greater than 1.5 and less than 3, where μ FE (max) represents the maximum value of the field effect mobility of the transistor, and μ FE (Vg=2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V.

11. A semiconductor device comprising a transistor, wherein the transistor include: a gate electrode; an oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a first region and a second region; a gate insulating film between the gate electrode and the oxide semiconductor film; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, wherein each of the first region and the second region includes indium and oxygen, the indium concentration in the first region is higher than the indium concentration in the second region, and the first region is surrounded by the second region, And, μ FE (max) / μ FE (Vg = 2V) is greater than 3 and less than 10, where μ FE (max) represents the maximum value of the field effect mobility of the transistor, and μ FE (Vg=2V) represents the value of field effect mobility when the gate voltage of the transistor is 2V.

12. A semiconductor device comprising a transistor, wherein the transistor include: a gate electrode; an oxide semiconductor film including a composite oxide semiconductor, the composite oxide semiconductor including a first region and a second region; a gate insulating film between the gate electrode and the oxide semiconductor film; a source electrode electrically connected to the oxide semiconductor film; as well as A drain electrode is electrically connected to the oxide semiconductor film.

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