Semiconductor device forming method and semiconductor device

Abstract

The invention discloses a semiconductor device forming method and a semiconductor device. The forming method comprises the steps that a stack structure is provided, the stack structure comprises a first metal layer, a first cut-off layer, a low dielectric layer, a second cut-off layer, a hard mask layer, an anti-reflection layer and a light resistance layer which are formed in a stacked mode in sequence, and a groove pattern is defined on the light resistance layer; etching to form a metal connecting hole and a groove; filling metal to form a second metal layer; and flattening the second metal layer. According to the invention, the second cut-off layer is arranged on the low dielectric layer, so that the loss of the low dielectric layer in the etching process and the chemical mechanical polishing process is avoided, the depth of the groove can be increased, and the purpose of thickening the second metal layer is achieved. Moreover, when the second metal layer is flattened, the second cut-off layer with a certain thickness is reserved, on one hand, the thickness of the second metal layer can be further increased, and on the other hand, parasitic capacitance generated by the thickened second metal layer can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and specifically to a method for forming a semiconductor device and a semiconductor device. Background Art

[0002] Semiconductor products such as CIS (CMOS Image Sensor) often have multiple layers of metal designed to achieve their functions. With the increasing requirements for frequency and power consumption, it is often necessary to design some thicker metal in the metal segment process to reduce resistance and thus reduce power consumption. In other words, some designs often design multiple layers of thicker metal on the surface of semiconductor products to achieve their low resistance and low power consumption requirements.

[0003] When trying to design a thicker metal layer to replace the original top metal layer, simulation data requires that the thickness of the connecting metal holes needs to be increased at the same time as the thickness of the top metal layer increases.

[0004] As the thickness of the metal layer increases, it is usually necessary to increase the height of the interlayer connection hole to reduce the parasitic capacitance caused by the thickened metal. However, when the thickness of the metal connection hole increases, the thickness of the etching main layer (such as the low dielectric constant oxide layer) that is etched to form the metal connection hole must be increased synchronously. However, due to process limitations, the greater the thickness of the etching main layer formed by deposition, the worse its uniformity. In other words, under the premise of ensuring deposition uniformity, the thickness of the etching main layer has a certain upper limit, and the purpose of thickening the metal layer cannot be achieved by increasing the thickness of the etching main layer.

[0005] Moreover, as the thickness of the metal layer and the height of the metal hole connected increase, the etching process requires that the thickness of the mask layer including the photoresist layer (PR) is increasingly larger. However, due to the limitation of the photolithography technology in the prior art, the thickness of the photoresist has an upper limit, which limits the process development of the high aspect ratio metal connection hole to a certain extent. For example, when the thickness of the photoresist is insufficient, it will cause the etching body layer to be damaged after dry etching or cause the adverse effects such as the height of the metal connection hole not being enough. This also limits the problem of thickening the metal layer by increasing the thickness of the etching body layer from another aspect. Further, considering the size requirements such as device thickness, increasing the height (or so-called thickness) of the interlayer metal connection hole will be limited, therefore, only by increasing the effect of reducing the parasitic capacitance of the height of the interlayer metal connection hole is not enough to meet the design requirements of semiconductor devices. Summary of the invention

[0006] The purpose of the present invention is to solve the problem of how to thicken the metal layer of a semiconductor device and the parasitic capacitance caused by the thickened metal layer, and to provide a method for forming a semiconductor structure, to make a thickened second metal layer and a higher metal connection hole, and to add a second cutoff layer on the etching main layer, so as to avoid the thickness reduction caused by insufficient hard mask and loss of low dielectric layer in chemical mechanical polishing during the etching process; and to avoid leakage caused by grooves generated by the low dielectric layer in the chemical mechanical polishing process due to the different polishing rate from the second metal layer. When flattening the second metal layer, retaining the second cutoff layer of a preset thickness can thicken the second metal layer and reduce the parasitic capacitance caused by the thickening of the second metal layer.

[0007] In order to achieve the above object, the present invention provides a method for forming a semiconductor device, comprising:

[0008] Step S1, providing a stack structure, which includes a first metal layer, a first cutoff layer, a low dielectric layer, a second cutoff layer, a hard mask layer, an anti-reflection layer and a photoresist layer stacked in sequence, wherein the photoresist layer defines a groove pattern;

[0009] Step S2, etching the anti-reflection layer and the hard mask layer, and transferring the groove pattern to the hard mask layer;

[0010] Step S3, depositing an anti-reflection layer and a photoresist layer in the groove pattern in sequence;

[0011] Step S4, defining a through-hole pattern in the photoresist layer on the groove pattern;

[0012] Step S5, etching the anti-reflection layer and the second cut-off layer at the bottom of the through-hole pattern in sequence to transfer the through-hole pattern to the second cut-off layer;

[0013] Step S6, partially etching the low dielectric layer at the bottom of the through hole pattern to a predetermined depth;

[0014] Step S7, simultaneously etching the through hole pattern and the groove pattern to form metal connection holes and grooves;

[0015] Step S8, filling metal in the metal connection holes and grooves to form a second metal layer;

[0016] Step S9, planarizing the second metal layer.

[0017] Optionally, the second cutoff layer is a SiCN layer or a SiN layer.

[0018] Optionally, in step S6, the low dielectric layer is partially etched by introducing a first etching gas, and under the first etching gas, the low dielectric layer has a high selectivity with respect to the second cutoff layer.

[0019] Optionally, the first etching gas is a carbon-hydrogen-fluorine gas, and the general formula of the carbon-hydrogen-fluorine gas is C x H y F z , where 0<x<5, y>0, z>0.

[0020] Optionally, in step S7, the step of forming the metal connection hole includes: etching the low dielectric layer and the first cutoff layer at the bottom of the through hole pattern until the first metal layer is exposed.

[0021] Optionally, in step S7, the step of forming the groove includes completely etching the second stop layer at the bottom of the groove pattern and partially etching the low dielectric layer at the bottom of the groove pattern.

[0022] Optionally, in the step S7, the metal connection hole and the groove are formed by etching by introducing a second etching gas, and under the second etching gas, the selection ratio of the first cutoff layer, the second cutoff layer and the low dielectric layer is 1:1.

[0023] Optionally, the second etching gas is a carbon fluorine gas, and the general formula of the carbon fluorine gas is C x F y , where 0<x<5, y>0.

[0024] Optionally, in step S8, filling the metal includes:

[0025] forming a barrier layer in the metal connection hole and the groove;

[0026] forming a seed layer on the barrier layer;

[0027] A metal layer is deposited to fill the metal connection holes and the grooves with metal to form a second metal layer, and redundant metal covers the upper surfaces of the hard mask layer and the second metal layer.

[0028] Optionally, the deposited metal layer is deposited by electrochemical plating.

[0029] Optionally, the metal is Cu or W.

[0030] Optionally, in step S9, the second metal layer is planarized by chemical mechanical polishing.

[0031] Optionally, planarizing the second metal layer includes: partially or completely removing the second cutoff layer.

[0032] Optionally, after step S9, the method further includes: forming a third cutoff layer on surfaces of the second cutoff layer and the second metal layer.

[0033] Optionally, the third cutoff layer is a SiCN layer.

[0034] Optionally, the metal connection hole has a high aspect ratio, which is greater than 4:1.

[0035] Optionally, the aspect ratio of the metal connection hole is 4:1 to 5:1.

[0036] Optionally, the first cutoff layer is a SiCN layer or a SiN layer.

[0037] Optionally, in the stack structure, the thickness of the second cutoff layer is greater than or equal to the thickness of the first cutoff layer.

[0038] Optionally, the low dielectric layer is a SICOH layer.

[0039] Optionally, the hard mask layer includes at least one of a TiN layer and a SION layer.

[0040] Optionally, in the stack structure, a buffer layer is further provided between the second cutoff layer and the hard mask layer, and the buffer layer is a silicon oxide layer.

[0041] Another object of the present invention is to provide a semiconductor device manufactured according to the above-mentioned method for forming a semiconductor device.

[0042] Optionally, the semiconductor device includes a second cutoff layer with a preset thickness, and the second cutoff layer with the preset thickness is formed by partially removing the second cutoff layer.

[0043] Optionally, the semiconductor device further includes a third cutoff layer covering the second cutoff layer and the second metal layer.

[0044] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0045] The method for forming a semiconductor device designed by the present invention provides a second cutoff layer on a low dielectric layer, and the second cutoff layer can have a high selectivity for the low dielectric layer. During etching, the second cutoff layer is basically not etched or is rarely etched, thereby effectively protecting the bottom low dielectric layer from being etched away, so that the height of the metal connection hole can be effectively adjusted. The higher the height of the metal connection hole is set, the further the parasitic capacitance caused by the thickened second metal layer and the first metal layer can be reduced. The method avoids the thickness reduction caused by insufficient hard mask and loss of the low dielectric layer in chemical mechanical polishing during the etching process to produce a thickened second metal layer and a higher metal connection hole; it can also avoid leakage caused by grooves in the low dielectric layer due to the different polishing rate from the second metal layer in the chemical mechanical polishing process.

[0046] In addition, since the added second cutoff layer is basically not etched or is rarely etched, the semiconductor device finally formed can also be designed to include a second cutoff layer of a preset thickness. Through the retained second cutoff layer of the preset thickness, on the one hand, the thickness design space of the second metal layer is more ample, and its thickness can be made thicker to further reduce the resistance, thereby further reducing the power consumption; on the other hand, the dielectric constant of the second cutoff layer material is small, and a certain thickness is retained near the second metal layer, which is beneficial to reduce the parasitic capacitance generated by the second metal layer and the conductive structure near it. It should be particularly noted that the second cutoff layer is made of SiCN material layer, which is a preferred material. Since SiCN has a lower dielectric constant than cutoff layer materials such as silicon nitride, and the material with a low dielectric constant is formed around the second metal layer, it is more beneficial to further reduce the parasitic capacitance generated by the second metal layer, and the effect is more obvious. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a cross-sectional view of an existing stacking structure (vertical to the metal direction).

[0048] Figure 2 A cross-sectional view (vertical to the metal direction) of a stacked structure formed by a conventional processing method.

[0049] Figure 3 It is a cross-sectional view (perpendicular to the metal direction) of a stacking structure of the present invention.

[0050] Figure 4 The present invention is a flow chart of a method for forming a semiconductor device.

[0051] Figure 5a-5i The present invention is a cross-sectional view of a stack structure after each step of a method for forming a semiconductor device. DETAILED DESCRIPTION

[0052] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0054] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0055] like Figure 1 FIG. 1 shows a conventional film stack structure, which includes a first metal layer 11, a stop layer 12, a low dielectric layer 13, a buffer layer 14, a hard mask layer 15, a bottom anti-reflection layer (BARC) 16, and a photoresist layer (PR) 17 stacked in sequence. The stack structure is used to form a Figure 2 The second metal layer 181 and the metal connection hole 182 shown in the figure. Through photolithography exposure and development, the opening pattern is defined in the photoresist layer 17, and then the through-hole structure is obtained by etching. However, due to the thickness limitation of the mask layer (such as the photoresist layer, the hard mask layer, etc.), it is difficult to etch to the required depth. On the other hand, when the cut-off layer 12 is etched through to form a through hole, due to the thickness limitation of the mask layer, insufficient protection leads to low dielectric layer loss, so that the thickness h1 of the second metal layer 181 and the thickness h2 of the metal connection hole 182 formed do not meet the requirements. Metal is deposited in the metal connection hole 182, and then treated by chemical mechanical polishing (CMP), and a passivation layer 19 is deposited to obtain the following. Figure 2 The structure shown. During the chemical mechanical polishing process, the low dielectric layer 13 suffers more losses due to the different materials and polishing rates of the metal and the low dielectric layer 13, resulting in larger dishings 131, which can easily lead to leakage. Moreover, due to the limitations of the deposition process, when the thickness of the low dielectric layer 13 that meets the uniformity is constant, the loss of the low dielectric layer 13 cannot be compensated by increasing the thickness of the original low dielectric layer 13, which will cause the thickness h1 of the second metal layer 181 to decrease, and the requirement of thickening the second metal layer 181 cannot be met.

[0056] As described in the background technology, due to the limitations of the deposition process and photolithography technology, the thickness of the etching main layer and the thickness of the mask layer have upper limits, and it is impossible to thicken the metal layer in the metal interconnection structure by thickening the etching main layer, especially the metal interconnection structure with a metal connection hole with a high aspect ratio. The aspect ratio is usually greater than 4:1. In this example, the aspect ratio of the metal connection hole is 4:1 to 5:1.

[0057] The present invention solves the problem of increasing the thickness h1 of the metal layer from at least the following two aspects:

[0058] 1) Minimize the loss of etching the main layer.

[0059] 2) Increase the depth of the trench filled with metal layer.

[0060] To this end, the present invention designs a new stack structure to replace the commonly used stack structure in the back end of line (BEOL) of the industry, and sets a stop layer on the etching main layer, which can not only avoid the loss of the etching main layer, especially the loss in the chemical mechanical polishing process. Moreover, the thickness of the stop layer can be used to increase the depth of the groove of the filling metal layer, thereby achieving the purpose of thickening the metal layer.

[0061] like Figure 3 As shown, a stack structure provided by the present invention includes a first metal layer 31, a first cutoff layer 32, a low dielectric layer 33, a second cutoff layer 34, a hard mask layer 35, an anti-reflection layer 36 and a photoresist layer 37 which are stacked in sequence, and the photoresist layer 37 defines a groove pattern 371.

[0062] The second cutoff layer 34 may be a SiCN layer or a SiN layer, but is not limited thereto. The present invention preferably uses a SiCN layer as the second cutoff layer 34, which has at least the following advantages:

[0063] 1) SiCN has a high selectivity relative to the low dielectric layer and can protect the low dielectric layer during the fabrication of the metal interconnect structure;

[0064] 2) The dielectric constant of SiCN is smaller than that of other materials such as silicon nitride (SiN). When flattening the second metal layer, retaining a certain thickness of SiCN is more effective in reducing the parasitic capacitance generated by the thickened second metal layer.

[0065] The metal of the first metal layer 31 is a conductive metal, which may be Cu or W, but is not limited thereto. In this example, the metal is Cu.

[0066] The first cutoff layer 32 has an etching selectivity relative to the low dielectric layer 33, and can avoid damage to the first metal layer 31 during the etching process. The first cutoff layer 32 also prevents the metal of the first metal layer 31 from diffusing into the low dielectric layer 33. The first cutoff layer is a SiCN layer or a SiN layer, but is not limited thereto.

[0067] The low dielectric layer 33 is a thin film with a low dielectric constant, and serves as an etching main layer. In this example, the low dielectric layer 33 is a SICOH layer.

[0068] The material of the second cutoff layer 34 may be the same as or different from that of the first cutoff layer 32. In this example, the second cutoff layer 34 is the same as the first cutoff layer 32, both of which are SiCN layers, so that the thickness h1 of the metal layer and the thickness h2 of the metal connection hole can be easily adjusted.

[0069] The hard mask layer 35 may be a TiN layer or a SION layer, or a stacked layer formed by alternately stacking at least one TiN layer and at least one SION layer, but is not limited thereto. In this example, the hard mask layer 35 is formed by stacking a TiN layer and a SION layer.

[0070] Optionally, a buffer layer 38 is further provided between the second cutoff layer 34 and the hard mask layer 35. The buffer layer 38 is a silicon oxide layer. As an example, the method for forming the stack structure includes:

[0071] 1) After forming the first metal layer 31 on the stack structure, a layer of NDC (SICN) is deposited as the first cutoff layer 32 with a thickness of 500 angstroms.

[0072] 2) A layer of low dielectric constant oxide SICOH is deposited on the first cutoff layer 32 as a low dielectric layer 33. In this example, the thickness of the low dielectric layer 33 is 4750 angstroms.

[0073] 3) Deposit a layer of NDC (SICN, silicon carbon nitride) with a thickness of 500 angstroms as the second cutoff layer 34, the thickness of which can be thicker or thinner than the thickness of the first cutoff layer 32 according to actual conditions. The sum of the thickness of the low dielectric layer 33 and the thickness of the second cutoff layer 34 is equivalent to the sum of the thickness h1 of the second metal layer and the thickness h2 of the metal connection hole, minus the thickness loss of the low dielectric layer 33 in the process. Since the present invention can effectively avoid the loss of the low dielectric layer 33, the thickness of the low dielectric layer 33 can be minimized. By adjusting the thickness of the second cutoff layer 34, not only can the thickness h1 of the second metal layer be increased to achieve the purpose of thickening the second metal layer 181, but also the thickness of the low dielectric layer 33 can be reduced to achieve better deposition uniformity.

[0074] 4) Deposit a 300 angstrom layer of SiO 2 As a buffer layer 38 .

[0075] 5) A 400 angstrom thick TIN (titanium nitride) layer and a 350 angstrom thick SION (silicon oxynitride) layer are sequentially deposited as a hard mask layer (HM) 35 .

[0076] 6) Deposit a 1200 angstrom anti-reflection layer 36 and a 2000 angstrom photoresist layer 37 in sequence. Define a groove pattern 371 on the photoresist layer 37 by photolithography exposure and development. The groove pattern 371 is consistent with the profile of the second metal layer 181 to be formed in the present invention.

[0077] The following combination Figure 4 , Figure 5a-5h The present invention is specifically described Figure 3 The stack structure is processed in a manner to thicken the second metal layer 181 .

[0078] like Figure 4 As shown, a method for forming a semiconductor device includes:

[0079] Step S1, providing a stack structure, comprising a first metal layer, a first cutoff layer, a low dielectric layer, a second cutoff layer, a hard mask layer, an anti-reflection layer and a photoresist layer stacked in sequence, wherein the photoresist layer defines a groove pattern.

[0080] The thickness of the second stop layer 34 is determined according to the thickness h1 of the second metal layer to be thickened.

[0081] The second cutoff layer is a SiCN layer, which can effectively reduce the parasitic capacitance of the metal interconnect structure.

[0082] Step S2, etching the anti-reflection layer and the hard mask layer, and transferring the groove pattern to the hard mask layer.

[0083] The photoresist layer 37 is used as a protective layer, and the anti-reflection layer 36 and the hard mask layer 35 at the bottom of the groove pattern 371 are sequentially etched by conventional process methods until the buffer layer 38 at the bottom of the groove pattern is exposed, and the groove pattern 371 is transferred to the hard mask layer 35. Figure 5a It should be noted that when the stack structure does not contain the buffer layer 38, the etching stops until the second stop layer 34 is exposed.

[0084] Step S3, filling the groove pattern with an anti-reflection layer and a photoresist layer in sequence.

[0085] The anti-reflection layer 36 is filled in the groove pattern 371 formed in step S2 until it is flush with the top of the anti-reflection layer 36 on both sides of the groove pattern; then, the photoresist layer 37 is filled by spin coating to make it flush with the photoresist layer 37 on both sides of the groove pattern, such as Figure 5b shown.

[0086] Step S4, defining a through-hole pattern in the photoresist layer on the groove pattern.

[0087] On the photoresist layer 37 formed by spin coating in step S3, a through-hole pattern 372 is defined by conventional photomask exposure and development steps, such as Figure 5c The through hole pattern 372 is consistent with the profile of the metal connection hole 182 to be formed in the present invention.

[0088] Step S5, etching the anti-reflection layer and the second cut-off layer at the bottom of the through-hole pattern in sequence to transfer the through-hole pattern to the second cut-off layer.

[0089] The photoresist layer 37 is used as a protective layer, and the anti-reflection layer 36 and the second cut-off layer 34 at the bottom of the through-hole pattern 372 are sequentially etched by conventional process methods to expose the low dielectric layer 33 at the bottom of the through-hole pattern 372. Figure 5d At this time, the photoresist layer 37 usually remains. Since a buffer layer 38 is deposited between the hard mask layer 35 and the second cut-off layer 34 in this example, the anti-reflection layer 36, the buffer layer 38, and the second cut-off layer 34 at the bottom of the through-hole pattern are sequentially etched in this step.

[0090] like Figure 5d As shown, after step S5 is completed, the groove pattern 371 includes a residual photoresist layer 37 and an anti-reflection layer 36 sequentially arranged from top to bottom, and the stacked structure on both sides of the groove pattern 371 includes a residual photoresist layer 37, an anti-reflection layer 36, and a hard mask layer 35 sequentially stacked from top to bottom. The sum of the thickness of the anti-reflection layer 36 and the hard mask layer 35 on both sides of the groove pattern 371 is equivalent to the thickness of the anti-reflection layer 36 in the groove pattern 371.

[0091] Step S6, partially etching the low dielectric layer at the bottom of the through hole pattern to a predetermined depth.

[0092] The low dielectric layer 33 at the bottom of the through hole pattern 372 is partially etched by introducing the first etching gas. Under the first etching gas, the low dielectric layer 33 has a high selectivity relative to the second stop layer 34. That is, under the first etching gas, the low dielectric layer 33 is more easily etched. As an example, the first etching gas can be a carbon-hydrogen-fluorine gas, and the general formula of the carbon-hydrogen-fluorine gas is C x H y F z , where 0<x<5, y>0, z>0.

[0093] After partial etching, the residual photoresist layer 37 and part of the anti-reflection layer 36 are removed, and the low dielectric layer 33 is etched to a preset depth h3. Figure 5eThe predetermined depth h3 is used to increase the height difference between h1 and h2, so as to adjust the height of the metal connection hole h2. The predetermined depth h3 can be adjusted according to the set values ​​of h1 and h2.

[0094] In some embodiments, the thickness of the second cut-off layer 34 is greater than or equal to the thickness of the first cut-off layer 32. The thickness of the second cut-off layer 34 can be used to increase the thickness of the second metal layer 181, so that the thickness h1 of the second metal layer finally formed is the sum of the depth of the groove formed by the low dielectric layer 33 and the thickness of the second cut-off layer 34 remaining after polishing. However, the thickness of the second cut-off layer 34 is not the larger the better, and there is also an upper limit. Because the thicker the second cut-off layer 34 is, the depth of the low dielectric layer 33 that continues to be etched after the second cut-off layer 34 at the bottom of the groove pattern 371 is etched through will be reduced accordingly under the same etching time, that is, the depth of the groove formed by the low dielectric layer 33 will be reduced.

[0095] Step S7, simultaneously etching the through hole pattern and the groove pattern to form metal connection holes and grooves.

[0096] The metal connection hole 182 and the groove 183 are formed by etching by introducing the second etching gas. Under the second etching gas, the selectivity ratio of the first stop layer 32, the second stop layer 34 and the low dielectric layer 33 is 1:1, that is, the etching rates of the three are the same. As an example, the second etching gas is a carbon fluorine gas, but it is not limited thereto. The general formula of the carbon fluorine gas is C x F y , where 0<x<5, y>0.

[0097] The step of forming the metal connection hole 182 includes: etching the low dielectric layer 33 and the first cutoff layer 32 remaining at the bottom of the through-hole pattern 372 after partial etching in step S6 until the first metal layer 31 is exposed, so that the second metal layer 181 deposited in the subsequent process is connected to the first metal layer 31, at which time the etching stops.

[0098] The step of forming the groove 183 includes: completely etching the anti-reflection layer 36, the buffer layer 38, and the second stop layer 34 in the groove pattern 371, and partially etching the low dielectric layer 33 at the bottom of the groove pattern 371. The etching depth of the low dielectric layer 33 at the bottom of the groove pattern 371 is determined according to the etching time for forming the metal connection hole 182. When the first metal layer 31 is exposed, the etching step of forming the groove 183 is also stopped. The required thickness h1 of the second metal layer can be adjusted according to the thickness and material of the first stop layer 32 and the second stop layer 34, and the value of the predetermined depth h3.

[0099] At this time, the stacked structure on both sides of the trench 183 has the second stop layer 34, the buffer layer 38 and a portion of the remaining hard mask layer 35 on the low dielectric layer 33, such as Figure 5f As shown. When ensuring that the thickness h1 of the second metal layer meets the thickening requirement, the low dielectric layer 33 is expected to be as thin as possible to better meet the uniformity of its deposition. To this end, in addition to minimizing the loss of the low dielectric layer 33, the present invention also increases the thickness h1 of the second metal layer by increasing the thickness of the second cutoff layer 34. That is, the sum of the thicknesses of the first cutoff layer 32, the low dielectric layer 33 and the second cutoff layer 34 is ≥ h1+h2. When the thickness of the second metal layer h1 increases, in order to reduce the greater parasitic capacitance caused by the increase in h1, the thickness of h2 needs to be increased. When h1 needs to be increased and h2 increases accordingly, since the thickness of the low dielectric layer 33 is not expected to increase, the present invention increases the thickness h1 of the second metal layer by increasing the thickness of the second cutoff layer 34 and minimizing or avoiding the loss of the low dielectric layer 33.

[0100] Step S8, filling metal in the metal connection holes and grooves to form a second metal layer.

[0101] The filler metal includes:

[0102] forming a barrier layer 184 in the metal connection hole 182 and the groove 183;

[0103] forming a seed layer 185 on the barrier layer 184;

[0104] A metal layer is deposited to fill the metal connection hole 182 and the groove 183 with metal to form a second metal layer 181. Redundant metal covers the upper surface of the hard mask layer 35 and the second metal layer 181. Figure 5g As shown. As an example, the metal layer is deposited by electrochemical plating. The metal is Cu or W.

[0105] The second metal layer 181 refers to a metal layer filled in the trench 183 .

[0106] Step S9, planarizing the second metal layer.

[0107] The redundant metal and the remaining hard mask layer 35 and the buffer layer 38 are removed by chemical mechanical polishing until the second stop layer 34 is exposed. Figure 5hAs shown, the second metal layer 181 is flattened. The thickness h1 of the second metal layer is the sum of the depth of the groove formed in the low dielectric layer 33 and the thickness of the second cutoff layer 34 remaining after chemical mechanical grinding. In some embodiments, part of the second cutoff layer 34 can be ground off according to the thickness h1 of the second metal layer required by the process, or even the second cutoff layer 34 can be completely ground off. In other words, the thickness h1 of the second cutoff layer 34 can also be adjusted according to the thickness of the second cutoff layer 34 to be ground off. Moreover, retaining a certain thickness of the second cutoff layer 34 after chemical mechanical grinding can further avoid the second metal layer 181 and the adjacent conductive structure from generating parasitic capacitance. In a preferred embodiment, the semiconductor device finally formed by design includes a second cutoff layer 34 of a preset thickness, so as to increase the thickness design space of the second metal layer 181, and reduce or even avoid the parasitic capacitance generated by the thickened second metal layer 181 and the adjacent conductive structure.

[0108] In some embodiments, after step S9, the method further includes: forming a third cutoff layer 341 on the surface of the second cutoff layer 34 and the second metal layer 181 to protect the second metal layer 181. The formed semiconductor device is as follows: Figure 5i As shown, it comprises a stack structure, the stack structure comprises a first metal layer 31, a first cutoff layer 32, and a low dielectric layer 33 stacked in sequence, the stack structure is further provided with a metal connection hole 182 and a groove 183, the groove 183 is provided on the upper surface of the low dielectric layer 33, one end of the metal connection hole 182 is connected to the groove 183, and the other end passes through the low dielectric layer 33 and the first cutoff layer 32 to connect the first metal layer 31, the groove 183 is filled with a second metal layer 181, the surface of the low dielectric layer 33 is provided with a second cutoff layer 34 of a preset thickness, the second cutoff layer 34 is flush with the upper surface of the second metal layer 181, and a third cutoff layer 341 is provided on the second metal layer 181 and the second cutoff layer 34. The material of the third cutoff layer 341 is preferably a SiCN layer.

[0109] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A method for forming a semiconductor device, It is characterized in that include: Step S1, providing a stack structure, which includes a first metal layer, a first cutoff layer, a low dielectric layer, a second cutoff layer, a hard mask layer, an anti-reflection layer and a photoresist layer stacked in sequence, wherein the photoresist layer defines a groove pattern; Step S2, etching the anti-reflection layer and the hard mask layer, and transferring the groove pattern to the hard mask layer; Step S3, depositing an anti-reflection layer and a photoresist layer in the groove pattern in sequence; Step S4, defining a through-hole pattern in the photoresist layer on the groove pattern; Step S5, etching the anti-reflection layer and the second cut-off layer at the bottom of the through-hole pattern in sequence to transfer the through-hole pattern to the second cut-off layer; Step S6, partially etching the low dielectric layer at the bottom of the through hole pattern to a predetermined depth; Step S7, simultaneously etching the through hole pattern and the groove pattern to form metal connection holes and grooves; Step S8, filling metal in the metal connection holes and grooves to form a second metal layer; Step S9, planarizing the second metal layer.

2. The method for forming a semiconductor device according to claim 1, It is characterized in that The second cutoff layer is a SiCN layer or a SiN layer.

3. The method for forming a semiconductor device according to claim 1, It is characterized in that In step S6, the low dielectric layer is partially etched by introducing a first etching gas. Under the first etching gas, the low dielectric layer has a high selectivity with respect to the second cutoff layer.

4. The method for forming a semiconductor device according to claim 3, It is characterized in that The first etching gas is a carbon-hydrogen-fluorine gas, and the general formula of the carbon-hydrogen-fluorine gas is C x H y F z , where 0<x<5, y>0, z>0.

5. The method for forming a semiconductor device according to claim 1, It is characterized in that In step S7, the step of forming the metal connection hole includes: etching the low dielectric layer and the first cutoff layer at the bottom of the through hole pattern until the first metal layer is exposed.

6. The method for forming a semiconductor device according to claim 1, It is characterized in that In the step S7, the step of forming the groove includes completely etching the second stop layer at the bottom of the groove pattern and partially etching the low dielectric layer at the bottom of the groove pattern.

7. The method for forming a semiconductor device according to claim 1, It is characterized in that In the step S7, the metal connection hole and the groove are formed by etching by introducing a second etching gas. Under the second etching gas, the selection ratio of the first stop layer, the second stop layer and the low dielectric layer is 1:

1.

8. The method for forming a semiconductor device according to claim 7, It is characterized in that The second etching gas is a carbon fluorine gas, and the general formula of the carbon fluorine gas is C x F y , where 0<x<5, y>0.

9. The method for forming a semiconductor device according to claim 1, It is characterized in that In the step S8, the filling metal includes: forming a barrier layer in the metal connection hole and the groove; forming a seed layer on the barrier layer; A metal layer is deposited to fill the metal connection holes and the grooves with metal to form a second metal layer, and redundant metal covers the upper surfaces of the hard mask layer and the second metal layer.

10. The method for forming a semiconductor device according to claim 9, It is characterized in that The deposited metal layer is deposited by electrochemical plating.

11. The method for forming a semiconductor device according to claim 9, It is characterized in that The metal is Cu or W.

12. The method for forming a semiconductor device according to claim 1, It is characterized in that In the step S9, the second metal layer is planarized by chemical mechanical polishing.

13. The method for forming a semiconductor device according to claim 1, It is characterized in that Planarizing the second metal layer includes: partially or completely removing the second cutoff layer.

14. The method for forming a semiconductor device according to claim 1, It is characterized in that After step S9, the method further includes: forming a third stop layer on the surfaces of the second stop layer and the second metal layer.

15. The method for forming a semiconductor device according to claim 14, It is characterized in that The third cutoff layer is a SiCN layer.

16. The method for forming a semiconductor device according to claim 1, It is characterized in that The metal connection hole has a high aspect ratio, which is greater than 4:

1.

17. The method for forming a semiconductor device according to claim 16, It is characterized in that The depth-to-width ratio of the metal connection hole is 4:1-5:

1.

18. The method for forming a semiconductor device according to claim 1, It is characterized in that The first cutoff layer is a SiCN layer or a SiN layer.

19. The method for forming a semiconductor device according to claim 1, It is characterized in that In the stack structure, the thickness of the second cutoff layer is greater than or equal to the thickness of the first cutoff layer.

20. The method for forming a semiconductor device according to claim 1, It is characterized in that The low dielectric layer is a SICOH layer.

21. The method for forming a semiconductor device according to claim 1, It is characterized in that The hard mask layer includes at least one of a TiN layer and a SION layer.

22. The method for forming a semiconductor device according to claim 1, It is characterized in that In the stack structure, a buffer layer is further disposed between the second cutoff layer and the hard mask layer, and the buffer layer is a silicon oxide layer.

23. A semiconductor device, It is characterized in that The semiconductor device is manufactured according to the method for forming a semiconductor device according to any one of claims 1 to 22.

24. The semiconductor device according to claim 23, It is characterized in that The semiconductor device includes a second cutoff layer with a preset thickness, and the second cutoff layer with the preset thickness is formed by partially removing the second cutoff layer.

25. The semiconductor device according to claim 24, It is characterized in that The semiconductor device further includes a third cutoff layer covering the second cutoff layer and the second metal layer.

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