Preparation method of solar cell and solar cell

Abstract

The embodiment of the invention discloses a preparation method of a solar cell and the solar cell, and the preparation method comprises the steps: firstly providing an N-type silicon-based process sheet, carrying out boron diffusion doping treatment on one side of a first surface of the N-type silicon-based process sheet, and carrying out phosphorus diffusion doping treatment on one side of a second surface of the N-type silicon-based process sheet; then, an extreme ultraviolet laser light source is adopted to carry out local doping propulsion processing on the grid line area on the second surface, and then annealing activation processing is carried out on the second surface after the local doping propulsion processing, so that the grid line area on the second surface forms a heavily doped area, and a non-grid line area on the second surface forms a lightly doped area; and then forming a first passivation film layer on the first surface, forming a second passivation film layer on the second surface, and finally respectively carrying out silk-screen printing and sintering treatment on one side, far away from the first surface, of the first passivation film layer and one side, far away from the second surface, of the second passivation film layer to form an electrode structure so as to prepare the solar cell.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of solar cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] The update and iteration of photovoltaic cell structure has led to the continuous accumulation of old production capacity, and cost reduction and efficiency improvement have become the key issues of the photovoltaic industry. Compared with P-type crystalline silicon cells, N-type crystalline silicon cells have the advantages of long minority carrier life, no photoinduced degradation, good weak light effect, and small temperature coefficient. They are the hope for crystalline silicon solar cells to break through the theoretical maximum efficiency.

[0003] At present, in the preparation process of N-type TOPCon (Tunnel Oxide Passivating Contact) cells, a high-temperature diffusion furnace is generally used to achieve phosphorus diffusion doping on the entire back of the cell, so as to form a higher phosphorus doping concentration in the polysilicon layer. However, in this process, some phosphorus atoms will penetrate the tunnel oxide layer from the polysilicon layer and enter the N-type silicon substrate, which will increase the impurity concentration in the N-type silicon substrate, thereby increasing Auger recombination. Among them, Auger recombination is a carrier recombination mechanism that causes the photogenerated carriers generated inside the cell to recombine before reaching the electrode, greatly reducing the short-circuit current density and photoelectric conversion efficiency of the cell. Summary of the invention

[0004] The embodiment of the present invention provides a method for preparing a solar cell and a solar cell, so as to improve the doping concentration and distribution of phosphorus atoms in a polysilicon layer on the back side of the solar cell, and make the gate line area on the back side heavily doped and the non-gate line area on the back side lightly doped, thereby effectively reducing metal recombination and surface recombination, improving open circuit voltage, short circuit current and fill factor, and improving the photoelectric conversion efficiency of the solar cell.

[0005] In a first aspect, an embodiment of the present invention provides a method for preparing a solar cell, comprising:

[0006] An N-type silicon-based process wafer is provided, and a first surface side of the N-type silicon-based process wafer is subjected to a boron diffusion doping treatment, and a second surface side of the N-type silicon-based process wafer is subjected to a phosphorus diffusion doping treatment; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer that are opposite to each other, and the first surface is a velvet surface, and the second surface is a polished surface;

[0007] Using an extreme ultraviolet laser light source, performing a local doping boost process on the grid line region on the second surface;

[0008] Performing an annealing activation treatment on the second surface after the local doping push-in treatment, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area;

[0009] forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface;

[0010] Screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface to form an electrode structure, thereby manufacturing the solar cell.

[0011] Optionally, the wavelength range of the extreme ultraviolet laser light source is 10-100 nm; and / or the energy range of the extreme ultraviolet laser light source is 2-100 mJ / cm 2 .

[0012] Optionally, the temperature range of the annealing activation treatment is 700-900°C.

[0013] Optionally, after using an extreme ultraviolet laser light source to perform local doping and driving-in treatment on the gate line region on the second surface, the method further includes:

[0014] A buffered oxide etching solution is used to clean the second surface after the local doping drive-in treatment.

[0015] Optionally, the N-type silicon-based process wafer comprises an N-type silicon substrate, a tunneling oxide layer and a polysilicon layer;

[0016] Provide N-type silicon-based process wafers, including:

[0017] forming the tunneling oxide layer on a surface of one side of the N-type silicon substrate;

[0018] The polysilicon layer is formed on a side surface of the tunneling oxide layer away from the N-type silicon substrate; wherein the side surface of the polysilicon layer away from the tunneling oxide layer is the second surface, and the side surface of the N-type silicon substrate on which the tunneling oxide layer is not formed is the first surface.

[0019] Optionally, the thickness of the polysilicon layer is in the range of 80-200 nm.

[0020] Optionally, the polysilicon layer is prepared at a temperature in a range of 550-650° C.; and / or, the polysilicon layer is prepared at a pressure in a range of 10-100 mTorr.

[0021] Optionally, the first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer;

[0022] Forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface, comprising:

[0023] forming the anti-ultraviolet attenuation film layer on the first surface;

[0024] forming the first anti-reflection layer on a side of the anti-ultraviolet attenuation film layer away from the first surface;

[0025] The second anti-reflection layer is formed on the second surface.

[0026] Optionally, the material of the anti-ultraviolet attenuation film layer includes aluminum oxide; and / or, the material of the first anti-reflection layer includes silicon nitride; and / or, the material of the second anti-reflection layer includes silicon nitride.

[0027] In a second aspect, an embodiment of the present invention further provides a solar cell, which is prepared by the method for preparing a solar cell as described in any one of the first aspects.

[0028] The embodiment of the present invention provides a method for preparing a solar cell and a solar cell. The preparation method first provides an N-type silicon-based process wafer, and performs a boron diffusion doping treatment on one side of the first surface of the N-type silicon-based process wafer, and performs a phosphorus diffusion doping treatment on one side of the second surface of the N-type silicon-based process wafer; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer that are opposite to each other, and the first surface is a velvet surface, and the second surface is a polished surface, and then an extreme ultraviolet laser light source is used to perform a local doping push-up treatment on the gate line area on the second surface, and then an annealing activation treatment is performed on the second surface after the local doping push-up treatment, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area, and then a first passivation film layer is formed on the first surface, and a second passivation film layer is formed on the second surface, and finally screen printing and sintering treatment are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface, respectively, to form an electrode structure, and to obtain a solar cell. By using the above method, the second surface of the N-type silicon-based process wafer is sequentially subjected to phosphorus diffusion doping treatment, local doping advancement treatment and annealing activation treatment, which effectively improves the doping concentration and distribution of phosphorus atoms in the polysilicon layer on the back of the solar cell, reduces metal recombination and surface recombination, and makes the gate line area on the back side heavily doped, that is, makes the contact area of ​​the metal electrode heavily doped, which can significantly reduce the contact resistance between the metal electrode on the back side and the N-type silicon substrate, reduces the scattering and recombination of carriers at the contact interface, improves the fill factor and short-circuit current density of the solar cell, and makes the non-gate line area on the back side lightly doped, that is, makes the non-metal electrode contact area The domain is lightly doped, which reduces the recombination rate of the non-gate line area, reduces the recombination losses such as Auger recombination inside the solar cell, improves the open circuit voltage and overall performance of the solar cell, and differentially dopes the gate line area and the non-gate line area on the back, optimizes the electrode structure, and significantly improves the carrier collection efficiency and transmission performance inside the solar cell, thereby improving the photoelectric conversion efficiency and operation reliability of the solar cell. The thickness of the polysilicon layer on the back of the solar cell can be made thinner, which increases the red light response in the long-wave region of sunlight, avoids the parasitic light absorption caused by an overly thick polysilicon layer, and is conducive to the realization of ultra-thin design of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1is a schematic flow chart of a method for preparing a solar cell provided by an embodiment of the present invention;

[0031] Figure 2 is a schematic flow chart of another method for preparing a solar cell provided by an embodiment of the present invention;

[0032] Figure 3 It is a schematic flow chart of another method for preparing a solar cell provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0034] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes and do not represent any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances.

[0035] The term “including” and its variations used in the present invention are open inclusions, that is, “including but not limited to.” The term “based on” means “based at least in part on.” The term “one embodiment” means “at least one embodiment.”

[0036] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish the corresponding contents, and are not used to limit the order or interdependence.

[0037] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0038] Figure 11 is a schematic flow chart of a method for preparing a solar cell provided by an embodiment of the present invention. The method for preparing a solar cell can be applied to the process of preparing a solar cell. The method for preparing a solar cell can be used to prepare a solar cell. Figure 1 As shown, the preparation method comprises:

[0039] S110. Provide an N-type silicon-based process wafer, and perform boron diffusion doping treatment on one side of the first surface of the N-type silicon-based process wafer, and perform phosphorus diffusion doping treatment on one side of the second surface of the N-type silicon-based process wafer; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer that are away from each other, and the first surface is a velvet surface, and the second surface is a polished surface.

[0040] Specifically, an N-type silicon-based process wafer is provided, and the N-type silicon-based process wafer includes a first surface and a second surface that are opposite to each other. Exemplarily, the first surface can be understood as the front side of the N-type silicon-based process wafer, and the second surface can be understood as the back side of the N-type silicon-based process wafer. Exemplarily, the N-type silicon-based process wafer may include an N-type silicon substrate, a tunneling oxide layer, and a polysilicon layer, wherein the tunneling oxide layer is located on a side surface of the N-type silicon substrate, and the polysilicon layer is located on a side surface of the tunneling oxide layer away from the N-type silicon substrate, so that the side surface of the polysilicon layer away from the tunneling oxide layer is the second surface of the N-type silicon-based process wafer, and the side surface of the N-type silicon substrate on which the tunneling oxide layer is not formed is the first surface of the N-type silicon-based process wafer.

[0041] The first surface of the N-type silicon-based process wafer is a velvet surface, that is, the surface of the side of the N-type silicon substrate on which the tunneling oxide layer is not formed is a velvet surface. Exemplarily, the first surface of the N-type silicon-based process wafer can be subjected to a velvet treatment so that the first surface of the N-type silicon-based process wafer is a velvet surface. Exemplarily, the velvet surface is a pyramid structure when tested under a microscope. The velvet treatment can remove organic dirt and metal impurities on the surface of the N-type silicon-based process wafer, remove the mechanical damage layer generated during the cutting process of the N-type silicon-based process wafer, reduce the recombination center, and form an undulating velvet surface, so as to utilize the light trapping effect, increase the absorption rate of the N-type silicon-based process wafer to sunlight, reduce the reflectivity, and at the same time increase the surface area of ​​the N-type silicon-based process wafer, and thus the area of ​​the PN junction formed on the surface is also increased.

[0042] After the first surface of the N-type silicon-based process wafer is textured, a boron diffusion doping process may be performed on one side of the first surface of the N-type silicon-based process wafer to form a PN junction on the first surface of the N-type silicon-based process wafer. The junction process is to generate semiconductor layers of different conductivity types on a piece of semiconductor substrate material. Exemplarily, the boron diffusion doping process may be performed in a high-temperature diffusion furnace.

[0043] The second surface of the N-type silicon-based process wafer is a polished surface, that is, the surface of the polysilicon layer away from the tunneling oxide layer is a polished surface. It should be noted that one side surface of the N-type silicon substrate can be polished, and then after the tunneling oxide layer and the polysilicon layer are formed on one side surface of the N-type silicon substrate, the side surface of the polysilicon layer away from the tunneling oxide layer can be understood as a polished surface. That is, after the first surface side of the N-type silicon-based process wafer is subjected to boron diffusion doping treatment, the second surface of the N-type silicon substrate can be chain pickled and alkaline polished to ensure that the second surface of the N-type silicon substrate is a polished surface, so that the N-type silicon-based process wafer forms a polished surface with high reflectivity, thereby improving the flatness of the battery surface, and increasing the reflection of long-wave light to promote secondary absorption of light, increase short-circuit current and reduce leakage current.

[0044] After the second surface of the N-type silicon-based process wafer is polished, phosphorus diffusion doping treatment can be continued on one side of the second surface of the N-type silicon-based process wafer to form a PN junction on the second surface of the N-type silicon-based process wafer. The junction process is to generate semiconductor layers of different conductivity types on a piece of semiconductor substrate material. Exemplarily, phosphorus diffusion doping treatment can be performed in a high-temperature diffusion furnace. It can be understood that this embodiment only describes the example of first performing boron diffusion doping treatment on one side of the first surface of the N-type silicon-based process wafer, and then performing phosphorus diffusion doping treatment on one side of the second surface of the N-type silicon-based process wafer. In fact, phosphorus diffusion doping treatment can also be performed on one side of the second surface of the N-type silicon-based process wafer, and then boron diffusion doping treatment can be performed on one side of the first surface of the N-type silicon-based process wafer, and at the same time, boron diffusion doping treatment can be performed on one side of the first surface of the N-type silicon-based process wafer and phosphorus diffusion doping treatment can be performed on one side of the second surface of the N-type silicon-based process wafer, without specific limitation.

[0045] In addition, after the second surface side of the N-type silicon-based process wafer is subjected to phosphorus diffusion doping treatment, the second surface of the N-type silicon-based process wafer can be subjected to chain pickling and etching treatment to ensure that the second surface of the N-type silicon-based process wafer is clean and free of impurities.

[0046] S120, using an extreme ultraviolet laser light source to perform local doping boost processing on the gate line area on the second surface.

[0047] Among them, the gate line area on the second surface of the N-type silicon-based process wafer refers to the area where the back electrode structure (or back gate line) is subsequently formed. Specifically, laser doping advancement refers to the process of bombarding the impurity atoms or ions (such as phosphorus atoms or phosphorus ions in this embodiment) deposited on the second surface of the N-type silicon-based process wafer with high energy density laser pulses, and then doping the impurity atoms or ions into the electrically active area in the N-type silicon-based process wafer. It should be noted that in this embodiment, an extreme ultraviolet laser light source can be used to perform local doping advancement treatment on the gate line area on the second surface of the N-type silicon-based process wafer after the phosphorus diffusion doping treatment, so that a part of the phosphorus silicon glass deposited on the second surface of the N-type silicon-based process wafer is melted, and then the phosphorus in the melted phosphorus silicon glass is diffused into the N-type silicon-based process wafer, increasing the phosphorus doping concentration in the laser irradiation area, so that the phosphorus source is redistributed in the N-type silicon-based process wafer. Exemplarily, after the local doping advancement treatment is performed using an extreme ultraviolet laser light source, a micron-level pyramid structure or a smooth etched surface needs to be formed on the second surface of the N-type silicon-based process wafer to reduce surface recombination and optimize electrode contact performance. Among them, the extreme ultraviolet laser light source has the characteristics of ultra-high energy density and precise penetration, which is far superior to other laser light sources, and can more easily, quickly, accurately and efficiently realize the laser doping propulsion process in this embodiment.

[0048] S130, performing annealing activation treatment on the second surface after the local doping drive-in treatment, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area.

[0049] Specifically, after the phosphorus diffusion doping treatment and the local doping advancement treatment, the phosphorus source is still mainly distributed on the surface of the N-type silicon-based process wafer. At this time, the N-type silicon-based process wafer needs to be placed in a high-temperature annealing furnace again for annealing activation treatment. In this process, the phosphorus source deposited on the surface of the N-type silicon-based process wafer can be used to further diffuse into the polysilicon layer at high temperature. During the diffusion process, the activation of the dopant is simultaneously achieved. At high temperature, the dopant that enters the polysilicon lattice, that is, the phosphorus atom, will occupy the position of the polysilicon lattice, thereby becoming an effective donor or acceptor impurity, changing the conductivity type and carrier concentration of the polysilicon. In addition, the annealing activation treatment can also form an oxidation protection layer on the second surface of the N-type silicon-based process wafer, which can repair the lattice loss caused by the laser doping advancement.

[0050] Among them, the area that has been treated with laser doping advancement and the area that has not been treated with laser doping advancement will have different advancement rates due to the different surface phosphorus source distributions, which will cause the laser-doped area to form the junction depth required for the solar cell after high-temperature treatment, thereby forming a heavily doped area in the gate line area on the second surface of the N-type silicon-based process wafer, and forming a lightly doped area in the non-gate line area on the second surface of the N-type silicon-based process wafer. That is, a heavily doped area is formed in the area where the metal gate line contacts the silicon wafer, and a lightly doped area is formed in the area between the metal gate lines. In a more understandable way, for the gate line area on the second surface of the N-type silicon-based process wafer, it has undergone laser doping advancement and annealing activation treatment, and heavy doping can be formed in this area, while for the non-gate line area on the second surface of the N-type silicon-based process wafer, it has undergone annealing activation treatment, and light doping can be formed in this area. It should be noted that the light doping and heavy doping mentioned here are relative, that is, the doping concentration of phosphorus atoms in the gate line area on the second surface of the N-type silicon-based process wafer is higher than the doping concentration of phosphorus atoms in the non-gate line area on the second surface of the N-type silicon-based process wafer. Therefore, the gate line area on the second surface of the N-type silicon-based process wafer is heavily doped relative to the non-gate line area on the second surface, and the non-gate line area on the second surface of the N-type silicon-based process wafer is lightly doped relative to the gate line area on the second surface.

[0051] S140 , forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface.

[0052] Specifically, atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), coating and other processes can be used to form a passivation film layer on the first surface and the second surface of the N-type silicon-based process wafer. It can be understood that the first passivation film layer and the second passivation film layer have passivation and anti-ultraviolet attenuation properties, which can effectively prevent the entire solar cell from being affected by ultraviolet and infrared, and further ensure the operational reliability of the entire solar cell. In addition, this embodiment does not limit the preparation order of the first passivation film layer and the second passivation film layer. For example, the first passivation film layer can be formed on the first surface first, and then the second passivation film layer can be formed on the second surface, or the second passivation film layer can be formed on the second surface first, and then the first passivation film layer can be formed on the first surface, or the first passivation film layer and the second passivation film layer can be formed at the same time.

[0053] S150, screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface to form an electrode structure, thereby manufacturing a solar cell.

[0054] Specifically, screen printing is one of the core processes in the manufacturing process of solar cells, and is mainly used for electrode formation of solar cells. This process uses the basic principle that the mesh holes of the graphic part of the screen are transparent to the slurry, while the mesh holes of the non-graphic part are not transparent to the slurry for printing. During the printing process, the slurry is accurately squeezed onto the N-type silicon substrate through the mesh holes of the screen, and the slurry is evenly distributed on the surface of the solar cell in the form of a wire to form the required electrode pattern. Generally, the slurry for screen printing may include but is not limited to silver paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to treat the electrode material screen-printed on the surface of the cell at high temperature, dry the slurry on the N-type silicon-based process wafer, burn out the organic components of the slurry, and the slurry can corrode through the passivation film layer and connect to the PN junction, so that the metal grid line forms a good ohmic contact with the N-type silicon-based process wafer, so as to achieve the purpose of collecting and conducting current.

[0055] Furthermore, the solar cells after the screen printing process are sintered at a sintering temperature range of 740-760°C, and then the light injection process is performed. The laser induced process after the light injection can induce the interdiffusion of silver and silicon, thereby significantly reducing the contact resistance, increasing the fill factor of the battery, and effectively improving the efficiency of the battery cell.

[0056] It should also be noted that Table 1 is a performance table of a solar cell prepared by a method for preparing a solar cell provided in an embodiment of the present invention. As shown in Table 1, the solar cell prepared in the embodiment of the present invention is subjected to relevant experiments, and it can be concluded that compared with the existing solar cell / control group, the performance parameters such as the photoelectric conversion efficiency Eta, the open circuit voltage Voc, the short circuit current Isc, the fill factor FF, the series resistance Rs, the parallel resistance Rsh and the reverse leakage current Irev of the solar cell in the embodiment of the present invention are better than those of the control group.

[0057] Table 1

[0058]

[0059] The technical solution in the embodiment of the present invention sequentially performs phosphorus diffusion doping treatment, local doping push-in treatment and annealing activation treatment on the second surface of the N-type silicon-based process wafer, effectively improving the doping concentration and distribution of phosphorus atoms in the polycrystalline silicon layer on the back of the solar cell, reducing metal recombination and surface recombination, so that the gate line area on the back is heavily doped, that is, the contact area of ​​the metal electrode is heavily doped, which can significantly reduce the contact resistance between the metal electrode on the back and the N-type silicon substrate, reduce the scattering and recombination of carriers at the contact interface, improve the fill factor and short-circuit current density of the solar cell, and make the non-gate line area on the back lightly doped, that is, the non-metal electrode The contact area is lightly doped, which reduces the recombination rate of the non-gate line area, reduces the recombination losses such as Auger recombination inside the solar cell, and improves the open circuit voltage and overall performance of the solar cell. In addition, the gate line area and the non-gate line area on the back are differentially doped, which optimizes the electrode structure, so that the carrier collection efficiency and transmission performance inside the solar cell are significantly improved, thereby improving the photoelectric conversion efficiency and operational reliability of the solar cell. The thickness of the polysilicon layer on the back of the solar cell can be made thinner, which increases the red light response in the long-wave region of sunlight, avoids parasitic light absorption due to an overly thick polysilicon layer, and is conducive to the realization of ultra-thin design of solar cells.

[0060] Optionally, the wavelength range of the extreme ultraviolet laser light source is 10-100 nm; and / or, the energy range of the extreme ultraviolet laser light source is 2-100 mJ / cm 2 .

[0061] Specifically, in this embodiment, an extreme ultraviolet (EUV) laser light source is used for local doping boost processing. The wavelength range of EUV (10-100nm) is much shorter than that of traditional laser light sources (such as infrared or visible light), and its photon energy is higher, which can achieve precise penetration at the nanometer level and directly act on the polysilicon layer without damaging the underlying tunneling oxide layer (SiO 2 ), which prevents phosphorus atoms from penetrating the tunnel oxide layer into the N-type silicon substrate and reduces the risk of Auger recombination. In addition, EUV, due to its short wavelength characteristics, can achieve high-precision local doping, reduce lateral diffusion, and improve the square resistance uniformity of the gate line area (such as square resistance difference <5%). Exemplarily, the wavelength of the extreme ultraviolet laser light source can be 13.5 nm. Exemplarily, the exposure energy of the extreme ultraviolet laser light source can be 50 mJ / cm 2. The EUV laser light source can perform laser grooving on the slurry printing area on the second surface side of the N-type silicon-based process wafer, and perform phosphorus atom heavy doping treatment on the grooved area of ​​the polysilicon layer. Exemplarily, the groove depth of the EUV laser light source needs to match the thickness of the polysilicon layer (80-200 nm), and the groove depth range of the EUV laser light source can be 50-150 nm, thus ensuring that the heavily doped area penetrates the polysilicon layer without damaging the tunneling oxide layer.

[0062] In addition, illustratively, the scanning speed of the extreme ultraviolet laser light source can range from 1 to 5 m / s. The scanning spot type design of the extreme ultraviolet laser light source is associated with the scanning speed. illustratively, the scanning spot type of the laser light source can be a square with a side length range of 10-100 μm, or a circle with a diameter range of 10-100 μm. illustratively, the overlap rate of the spot scanning of the laser light source can range from 10 to 80% to ensure uniform doping.

[0063] Optionally, the temperature range of the annealing activation treatment is 700-900°C.

[0064] Specifically, the N-type silicon-based process wafer after the polysilicon layer on one side of the second surface is grooved can be placed in a high-temperature annealing furnace for annealing activation treatment. Exemplarily, the temperature of the annealing activation treatment can be 800°C. In addition, the time of the annealing activation treatment can be adjusted according to the required doping depth and doping concentration, generally ranging from a few minutes to tens of minutes, to ensure that the phosphorus doping diffuses into the polysilicon. It should also be noted that this embodiment uses an extreme ultraviolet laser light source in conjunction with the annealing activation treatment. After the laser treatment, annealing at 700-900°C is required to activate the doped atoms and repair the lattice defects, and finally achieve a contact resistance corresponding to the heavily doped area of ​​less than 1 mΩ•cm², and a recombination rate corresponding to the lightly doped area of ​​less than 50 cm / s.

[0065] Optionally, after using an extreme ultraviolet laser light source to perform a local doping drive-in treatment on the gate line region on the second surface, the method further includes: using a buffered oxide etching solution to clean the second surface after the local doping drive-in treatment.

[0066] Specifically, the buffered oxide etchant (BOE) is a mixture of hydrofluoric acid aqueous solution and ammonium fluoride aqueous solution in a certain proportion. The BOE solution can remove the polysilicon layer on the front and edge of the N-type silicon-based process wafer, and can also remove the excess phosphosilicate glass or borosilicate glass on the front of the N-type silicon-based process wafer, thereby ensuring the surface cleanliness of the N-type silicon-based process wafer, that is, the BOE solution can effectively remove residues and optimize the quality of the passivation film layer.

[0067] Figure 21 is a flow chart of another method for preparing a solar cell provided by an embodiment of the present invention, and this embodiment is optimized on the basis of the above embodiment. Optionally, the N-type silicon-based process wafer includes an N-type silicon substrate, a tunneling oxide layer and a polysilicon layer;

[0068] Provide N-type silicon-based process wafers, including:

[0069] forming a tunneling oxide layer on a surface of one side of the N-type silicon substrate;

[0070] A polysilicon layer is formed on a surface of the tunneling oxide layer away from the N-type silicon substrate; wherein the surface of the polysilicon layer away from the tunneling oxide layer is the second surface, and the surface of the N-type silicon substrate without the tunneling oxide layer is the first surface.

[0071] For details not yet provided in this embodiment, please refer to the above embodiments. Figure 2 As shown, the preparation method comprises:

[0072] S210, forming a tunneling oxide layer on a surface of one side of the N-type silicon substrate.

[0073] S220, forming a polysilicon layer on a surface of the tunneling oxide layer away from the N-type silicon substrate; wherein the surface of the polysilicon layer away from the tunneling oxide layer is a second surface, and the surface of the N-type silicon substrate on which the tunneling oxide layer is not formed is a first surface.

[0074] Specifically, before the second surface side of the N-type silicon-based process wafer is subjected to phosphorus diffusion doping treatment, a tunneling oxide layer and a polysilicon layer need to be stacked in sequence on the surface of one side of the N-type silicon substrate. Among them, the tunneling oxide layer and the polysilicon layer are used to allow the majority carriers (electrons) to pass smoothly through the tunneling effect, while preventing the recombination of minority carriers (holes), so as to achieve selective collection of carriers, reduce surface recombination, and improve the open circuit voltage and fill factor of the battery, thereby improving the photoelectric conversion efficiency of the overall solar cell. The composite layer of the tunneling oxide layer and the polysilicon layer together forms a passivation contact structure, which can effectively reduce the surface recombination and metal contact recombination of the overall solar cell. In other words, depositing an ultra-thin tunneling oxide layer on the surface of the N-type silicon substrate can provide good interface passivation and provide different carrier tunneling barriers. Depositing a polysilicon layer on the tunneling oxide layer can increase the migration rate of electrons and suppress the migration rate of holes. In addition, the polysilicon layer contacts the subsequent metal electrode and acts as an electron transmission bridge. For example, LPCVD technology can be used to first prepare an ultra-thin silicon dioxide layer on the surface of an N-type silicon substrate as the tunneling oxide layer, and then a polysilicon thin layer is deposited on the ultra-thin silicon dioxide layer to form a polysilicon layer that satisfies the passivation effect. For example, the thickness of the tunneling oxide layer can range from 1 to 2 nm.

[0075] Optionally, the thickness of the polysilicon layer is in the range of 80-200 nm. Exemplarily, the thickness of the polysilicon layer is in the range of 100-150 nm.

[0076] Optionally, the preparation temperature of the polysilicon layer is in the range of 550-650° C.; and / or, the preparation pressure of the polysilicon layer is in the range of 10-100 mTorr.

[0077] Specifically, LPCVD technology can be used to deposit silane (SiH 4 ) is the reaction gas, and the reaction occurs at a preparation temperature of 550-650°C and a preparation pressure of 10-100mTorr. 4 →Si+2H 2 , so as to grow a polysilicon layer of required thickness on the surface of the tunnel oxide layer away from the N-type silicon substrate, and the polysilicon layer is also the object of subsequent phosphorus diffusion doping treatment.

[0078] S230, using an extreme ultraviolet laser light source to perform local doping boost processing on the gate line area on the second surface.

[0079] S240, performing annealing activation treatment on the second surface after the local doping drive-in treatment, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area.

[0080] S250 , forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface.

[0081] S260, screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface to form an electrode structure, thereby manufacturing a solar cell.

[0082] Figure 3 1 is a schematic flow chart of another method for preparing a solar cell provided by an embodiment of the present invention. This embodiment is optimized on the basis of the above embodiment. Optionally, the first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer;

[0083] Forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface, comprising:

[0084] forming an anti-ultraviolet attenuation film layer on the first surface;

[0085] forming a first anti-reflection layer on a side of the anti-ultraviolet attenuation film layer away from the first surface;

[0086] A second anti-reflection layer is formed on the second surface.

[0087] For details not yet provided in this embodiment, please refer to the above embodiments. Figure 3 As shown, the preparation method comprises:

[0088] S310, providing an N-type silicon-based process wafer, and performing boron diffusion doping treatment on one side of the first surface of the N-type silicon-based process wafer, and performing phosphorus diffusion doping treatment on one side of the second surface of the N-type silicon-based process wafer; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer that are away from each other, and the first surface is a velvet surface, and the second surface is a polished surface.

[0089] S320, using an extreme ultraviolet laser light source to perform local doping boost processing on the gate line area on the second surface.

[0090] S330, performing annealing activation treatment on the second surface after the local doping drive-in treatment, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area.

[0091] S340, forming an anti-ultraviolet attenuation film layer on the first surface.

[0092] Specifically, the first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer. Exemplarily, an atomic layer deposition (ALD) technology can be used to form an anti-ultraviolet attenuation film layer on the first surface of an N-type silicon-based process wafer, which can effectively resist ultraviolet attenuation and passivate the front side of the N-type silicon-based process wafer. Exemplarily, the temperature of the ALD process can be 200-300°C and the deposition time can be 8-10min. The deposition can be cyclically deposited 20 times under the conditions of a TMA flow rate of 1500sccm, an oxygen flow rate of 1800sccm, and a temperature of 278°C, and the deposition time can be 6min. Optionally, the material of the anti-ultraviolet attenuation film layer includes aluminum oxide. Optionally, the thickness of the anti-ultraviolet attenuation film layer ranges from 6-10nm.

[0093] S350, forming a first anti-reflection layer on a side of the anti-ultraviolet attenuation film layer away from the first surface.

[0094] Specifically, a coating process can be used to form a first anti-reflection layer on the side of the anti-ultraviolet attenuation film layer away from the first surface. The first anti-reflection layer can further improve the passivation and anti-ultraviolet attenuation performance of the overall solar cell, and can also reduce the reflection of sunlight, increase the absorption of sunlight, and improve the photoelectric conversion efficiency of the overall solar cell. At the same time, it reduces surface recombination, increases the mobility of carriers, and improves the overall performance of the overall solar cell. Optionally, the material of the first anti-reflection layer includes silicon nitride. Optionally, the refractive index range of the first anti-reflection layer is 2.2%-2.3%.

[0095] S360, forming a second anti-reflection layer on the second surface.

[0096] Specifically, the second passivation film layer includes a second anti-reflection layer. A coating process can be used to form a second anti-reflection layer on the second surface of the N-type silicon-based process wafer, and the second anti-reflection layer can further enhance the passivation and anti-ultraviolet attenuation performance of the overall solar cell. Optionally, the material of the second anti-reflection layer includes silicon nitride. Optionally, the refractive index range of the second anti-reflection layer is 2.2%-2.3%. In addition, the first anti-reflection layer and the second anti-reflection layer can be understood as being prepared at the same time, and the first anti-reflection layer and the second anti-reflection layer are only different in position, and the rest of the materials, parameters, etc. are the same.

[0097] S370, screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface to form an electrode structure, thereby manufacturing a solar cell.

[0098] Based on the same inventive concept, an embodiment of the present invention further provides a solar cell. The solar cell is prepared by a method for preparing a solar cell provided in any one of the embodiments of the present invention. Therefore, the solar cell has functional modules and beneficial effects corresponding to the method for preparing a solar cell.

[0099] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: An N-type silicon-based process wafer is provided, and a first surface side of the N-type silicon-based process wafer is subjected to a boron diffusion doping treatment, and a second surface side of the N-type silicon-based process wafer is subjected to a phosphorus diffusion doping treatment; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer that are opposite to each other, and the first surface is a velvet surface, and the second surface is a polished surface; Using an extreme ultraviolet laser light source, performing a local doping boost process on the grid line region on the second surface; Performing an annealing activation treatment on the second surface after the local doping push-in treatment, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area; forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface; Screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface to form an electrode structure, thereby manufacturing the solar cell.

2. The preparation method according to claim 1, characterized in that: The wavelength range of the extreme ultraviolet laser light source is 10-100nm; and / or the energy range of the extreme ultraviolet laser light source is 2-100mJ / cm 2 .

3. The preparation method according to claim 1, characterized in that: The temperature range of the annealing activation treatment is 700-900°C.

4. The preparation method according to claim 1, characterized in that: After the gate line region on the second surface is locally doped and driven by an extreme ultraviolet laser light source, the method further includes: A buffered oxide etching solution is used to clean the second surface after the local doping drive-in treatment.

5. The preparation method according to claim 1, characterized in that: The N-type silicon-based process wafer comprises an N-type silicon substrate, a tunneling oxide layer and a polysilicon layer; Provide N-type silicon-based process wafers, including: forming the tunneling oxide layer on a surface of one side of the N-type silicon substrate; The polysilicon layer is formed on a side surface of the tunneling oxide layer away from the N-type silicon substrate; wherein the side surface of the polysilicon layer away from the tunneling oxide layer is the second surface, and the side surface of the N-type silicon substrate where the tunneling oxide layer is not formed is the first surface.

6. The preparation method according to claim 5, characterized in that: The thickness of the polysilicon layer is in the range of 80-200 nm.

7. The preparation method according to claim 5, characterized in that: The polysilicon layer is prepared at a temperature in a range of 550-650° C.; and / or the polysilicon layer is prepared at a pressure in a range of 10-100 mTorr.

8. The preparation method according to claim 1, characterized in that: The first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer; Forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface, comprising: forming the anti-ultraviolet attenuation film layer on the first surface; forming the first anti-reflection layer on a side of the anti-ultraviolet attenuation film layer away from the first surface; The second anti-reflection layer is formed on the second surface.

9. The preparation method according to claim 8, characterized in that: The material of the anti-ultraviolet attenuation film layer includes aluminum oxide; and / or the material of the first anti-reflection layer includes silicon nitride; and / or the material of the second anti-reflection layer includes silicon nitride.

10. A solar cell, characterized in that: The solar cell is prepared by the method for preparing the solar cell according to any one of claims 1 to 9.

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