HJT solar cell and cell preparation method

Abstract

The invention discloses an HJT solar cell and a cell preparation method. A first tunneling passivation layer, a doped N-type polycrystalline silicon layer and a first passivation anti-reflection layer are sequentially stacked on the surface of a silicon substrate; wherein the N-type polycrystalline silicon and the silicon substrate form a high-low junction to promote carrier separation and improve the conversion efficiency of the solar cell, and the cell structure does not comprise a TCO film layer and an amorphous silicon thin film layer, so that the optical parasitic absorption of the cell is reduced, the series resistance is reduced, and the short-circuit current and the photoelectric conversion efficiency of the cell are improved. Besides, the metal grid lines on the front side and the back side of the solar cell are formed through the electroplating technology, the metal grid lines are formed in the metal grid line arrangement area through the electroplating technology, and a more uniform grid line pattern with a better line shape can be obtained, so that shading is reduced, and the current collection efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cell preparation, and in particular relates to a HJT solar cell and a method for preparing the cell. Background Art

[0002] Heterojunction (HJT) solar cells have become one of the key research and development directions in the photovoltaic industry in recent years due to their light and thin physical properties and high photoelectric conversion efficiency.

[0003] Due to the high optical parasitic absorption of the TCO (transparent conductive oxide) film layer and amorphous silicon film in heterojunction (HJT) solar cells, the short-circuit current of HJT cells is lower than that of Topcon (tunnel oxide passivation contact) or BC (back contact) cells, thus limiting the further improvement of their cell conversion efficiency. In addition, in the prior art, HJT cells mostly use low-temperature silver paste process to prepare metal grid lines, and low-temperature silver paste materials have the problems of low conductivity and high cost, which not only further limits the conversion efficiency of HJT cells, but also increases the design cost of HJT cells. Summary of the invention

[0004] The present invention provides a HJT solar cell and a method for preparing the cell, which can reduce optical parasitic absorption of the cell, lower series resistance, and improve short-circuit current and photoelectric conversion efficiency.

[0005] The present invention provides a HJT solar cell, comprising: a silicon substrate;

[0006] A first tunnel passivation layer, a doped N-type polysilicon layer and a first passivation anti-reflection layer are sequentially stacked along a first direction;

[0007] and, a metal gate line disposed on the surface of the doped N-type polysilicon layer;

[0008] The first direction is the direction from the silicon substrate to the first passivation anti-reflection layer.

[0009] Furthermore, the first passivation anti-reflection layer includes an aluminum oxide layer, a first silicon nitride layer, and a second silicon nitride layer which are sequentially stacked along a first direction.

[0010] Furthermore, the refractive index of the first silicon nitride layer is greater than the refractive index of the second silicon nitride layer.

[0011] Furthermore, it also includes a second tunnel passivation layer;

[0012] The second tunnel passivation layer and the metal gate line are sequentially stacked on the surface of the doped N-type polysilicon layer.

[0013] Furthermore, the thickness of the second tunneling passivation layer is less than or equal to 0.5 nm.

[0014] The present invention also discloses a method for preparing a solar cell, and the method comprises:

[0015] Providing a silicon substrate;

[0016] A first tunnel passivation layer, a doped N-type polysilicon layer and a first passivation anti-reflection layer are sequentially stacked along the first direction;

[0017] After a metal gate line setting region is formed in the doped N-type polysilicon layer, the first metal gate line is deposited in the metal gate line setting region by using an electroplating process.

[0018] Furthermore, sequentially stacking a first tunnel passivation layer, a doped N-type polysilicon layer and a passivation anti-reflection layer along the first direction includes:

[0019] The first tunnel passivation layer is formed by a high temperature thermal oxidation process.

[0020] Furthermore, forming a metal gate line setting area in the doped N-type polysilicon layer also includes:

[0021] The surface of the metal gate line setting area is treated by dry etching process.

[0022] Furthermore, the preparation method further comprises:

[0023] After a metal gate line setting region is formed in the doped N-type polysilicon layer, an oxygen plasma etching process is used to form a second tunnel passivation layer in the metal gate line setting region.

[0024] The present invention also discloses a HJT solar cell, comprising:

[0025] Silicon substrate;

[0026] A first tunnel passivation layer, an amorphous silicon layer, an in-situ doped microcrystalline silicon layer, a TCO film layer, and a second passivation anti-reflection layer are sequentially stacked along a second direction; and a metal gate line is arranged on the surface of the TCO film layer;

[0027] Wherein, the second direction is the direction from the silicon substrate to the surface of the TCO film layer;

[0028] The refractive index of the TCO film layer is greater than the refractive index of the second passivation anti-reflection layer.

[0029] Furthermore, the second passivation anti-reflection layer includes a third silicon nitride layer.

[0030] The present invention also discloses a method for preparing a HJT solar cell, and the method comprises:

[0031] Providing a silicon substrate;

[0032] A first tunnel passivation layer, an amorphous silicon layer, a doped microcrystalline silicon layer, a TCO film layer and a second passivation anti-reflection layer are sequentially stacked along the second direction;

[0033] After a metal gate line setting region is formed in the TCO film layer, the metal gate line is deposited in the metal gate line setting region by using an electroplating process.

[0034] Furthermore, forming a metal gate line setting area in the TCO film layer includes:

[0035] The surface of the metal gate line setting area is treated by dry etching process.

[0036] Compared with the prior art, the present invention has at least the following technical effects:

[0037] By stacking a first tunnel passivation layer, a doped N-type polysilicon layer and a first passivation anti-reflection layer in sequence on the surface of a silicon substrate; the N-type polysilicon and the silicon substrate form a high-low junction, which promotes carrier separation and improves the conversion efficiency of the solar cell. The above-mentioned battery structure does not include a TCO film layer and an amorphous silicon thin film layer, which reduces the optical parasitic absorption of the battery, thereby reducing the series resistance and improving the short-circuit current and photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of the structure of the HJT solar cell in the first and third embodiments of the present invention;

[0039] Figure 2 Another schematic diagram of the preparation process of the HJT solar cell in the fifth embodiment of the present invention;

[0040] Figure 3 Another schematic diagram of the preparation process of the HJT solar cell in the fifth embodiment of the present invention;

[0041] Figure 4 Another schematic diagram of the preparation process of the HJT solar cell in the fifth embodiment of the present invention;

[0042] Figure 5 Another schematic diagram of the preparation process of the HJT solar cell in the fifth embodiment of the present invention;

[0043] Figure 6 Another schematic diagram of the preparation process of the HJT solar cell in the fifth embodiment of the present invention;

[0044] Figure 7Another schematic diagram of the preparation process of the HJT solar cell in the fifth embodiment of the present invention;

[0045] Figure 8 This is another simplified diagram of the preparation process of the HJT solar cell in the fifth embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following is a description of a HJT solar cell and a method for preparing the cell of the present invention in conjunction with a schematic diagram, wherein preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art may modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

[0047] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0048] Embodiment 1

[0049] Please refer to Figure 1 This embodiment provides a HJT solar cell, whose cell structure includes:

[0050] A silicon substrate 100; a first tunnel passivation layer 200, a doped N-type polysilicon layer 300, and a first passivation anti-reflection layer stacked in sequence along a first direction; and a metal gate line, the metal gate line being deposited on the surface of the doped N-type polysilicon layer 300. The first direction is the direction from the silicon substrate 100 to the first passivation anti-reflection layer.

[0051] There is a doping concentration difference between the N-type polysilicon and the silicon substrate 100 in the HJT solar cell structure, thereby forming a high-low junction, forming a built-in electric field in the first direction, promoting carrier separation, reducing the series resistance of the battery, and improving the conversion efficiency of the solar cell. In addition, the front structure of the HJT solar cell no longer has a TCO film layer and an amorphous silicon film layer, reducing the optical parasitic absorption of the battery caused by the above two film layers, thereby reducing the series resistance of the battery and improving the short-circuit current and photoelectric conversion efficiency of the battery.

[0052] In this embodiment, the material of the first tunnel passivation layer 200 is silicon dioxide (SiO 2 ), a SiO 2 The tunneling layer can effectively passivate surface defects, optimize the energy band structure, and reduce surface recombination, thereby improving the performance of solar cells.

[0053] In this embodiment, the doping element in the doped N-type polysilicon layer 300 may be phosphorus or other elements, which are not specifically limited here.

[0054] Furthermore, in this embodiment, the first passivation anti-reflection layer includes aluminum oxide (AlO X ) layer 400, a first silicon nitride (SiN) layer 500 and a second silicon nitride layer 600. The first passivation anti-reflection layer is used to reduce the reflection loss of light and improve the light absorption rate, thereby improving the efficiency of the solar cell.

[0055] The aluminum oxide layer 400 plays a passivation role, effectively passivating the defect states on the silicon surface and reducing the chance of electrons and holes recombinating on the surface. The two silicon nitride film layers are used to reduce the reflection of light on the surface of the solar cell, thereby increasing the probability of light entering the cell and being absorbed.

[0056] In a specific embodiment, the thickness of the first silicon nitride layer 500 and the second silicon nitride layer 600 ranges from 60 to 100 nm, and the thickness of the first silicon nitride layer 500 is set to be less than the thickness of the second silicon nitride layer 600. For example, the thicknesses of the first and second silicon nitride layers are 60 nm and 75 nm respectively.

[0057] In another specific embodiment, the silicon content of the first silicon nitride layer 500 is set to be higher than that of the second silicon nitride layer 600, so that the refractive index of the two silicon nitride film layers gradually increases from the surface layer to the lower layer (that is, in the direction opposite to the first direction), thereby improving the utilization rate of the incident light. For example, the refractive index of the first silicon nitride layer 500 is 1.9-2.4, and the refractive index of the second silicon nitride layer 600 is 1.8-1.9.

[0058] Furthermore, in this embodiment, the solar cell further includes a second tunneling passivation layer 11 , which is disposed on the surface of the doped N-type polysilicon layer 300 , and the metal gate line is deposited on the surface of the doped N-type polysilicon layer 300 .

[0059] In a specific embodiment, the material of the second tunneling passivation layer 11 is silicon oxide.

[0060] Providing the second tunnel passivation layer 11 of silicon oxide material helps to reduce interface defects between metal and silicon, improve the collection efficiency of electrons from the silicon surface to the metal grid line, and further improve the photoelectric conversion efficiency of the solar cell.

[0061] In a specific embodiment, the thickness of the second tunnel passivation layer 11 is less than or equal to 0.5 nm, for example, 0.1 nm, 0.3 nm, or 0.4 nm.

[0062] The thin second tunnel passivation layer 11 is provided to facilitate electron transmission into the metal gate line, reduce interface defects between the metal gate line and the doped N-type polysilicon layer 300, and further improve the photoelectric conversion efficiency of the HJT solar cell.

[0063] In this embodiment, the metal gate line includes: a seed layer 12 , a gate line 13 and a protection layer 14 .

[0064] In a specific embodiment, the seed layer 12 is made of nickel, the gate line 13 is made of copper, and the protective layer 14 is made of tin. Tin as the protective layer 14 can prevent oxidation of copper.

[0065] Embodiment 2

[0066] This embodiment discloses a method for preparing a solar cell, and the method comprises:

[0067] S1. Providing a silicon substrate 100;

[0068] S2. A first tunnel passivation layer 200, a doped N-type polysilicon layer 300 and a first passivation anti-reflection layer are sequentially stacked along the first direction;

[0069] S3. After a metal gate line setting region is formed in the doped N-type polysilicon layer 300, the metal gate line is deposited in the metal gate line setting region by using an electroplating process.

[0070] In this embodiment, metal grid lines are formed in the metal grid line setting area through an electroplating process, which can obtain a more uniform grid line 13 pattern with better linearity (for example, a thinner grid line 13 structure), thereby reducing shading and improving current collection efficiency.

[0071] In step S2, a first tunnel passivation layer 200 (SiO 2 film layer).

[0072] Furthermore, PECVD or LPCVD process is used to deposit SiO 2 The surface is sequentially formed with doped N-type polysilicon 300 (P-Sin + ); forming an aluminum oxide layer 400 by an ALD (atomic layer deposition) process on the basis of the doped N-type polysilicon 300; and then sequentially forming a first silicon nitride layer 500 and a second silicon nitride layer 600 on the surface of the aluminum oxide layer 400 by a PECVD or LPCVD process.

[0073] A possible operation process is as follows: put the silicon wafer with the first tunnel passivation layer 200 formed thereon into the PECVD operating chamber, and introduce silane (SiH4) and nitrogen source gas (such as ammonia NH3 or phosphine PH3) as precursors. Turn on the RF power supply to excite the gas to generate plasma. With the help of the plasma, the silane and nitrogen source gas are deposited on the SiO 2 On the basis of the doped N-type polysilicon layer, an ALD process is used, using a specific aluminum source gas and water or oxygen as an operating agent, to form an aluminum oxide layer 400 on the basis of the doped N-type polysilicon layer 300; silane (SiH 4 ) and ammonia (NH 3 ) as a precursor gas, with the help of radio frequency plasma, a first silicon nitride layer 500 and a second silicon nitride layer 600 are sequentially formed on the surface of the silicon wafer.

[0074] In step S3, the metal gate line setting area is formed in the N-type polysilicon layer by using a photolithography process and a dry etching process in sequence.

[0075] A possible operation process is as follows: In the photolithography process, the photoresist is spin-coated on the front side of the silicon wafer (the surface of the first passivation anti-reflection layer) and cured by heating. Then, a photolithography machine is used to transfer the pattern on the mask (the pattern of the etching area, which can be dissolved later to form the metal gate line setting area) to the photoresist, and then the photoresist is selectively irradiated with ultraviolet light, for example, so that the photoresist in the etching area changes, and the photoresist in the unirradiated area remains unchanged. In the dry etching process, the etching gas (such as hydrogen fluoride and chlorine, etc.) reacts chemically with the N-type polysilicon layer in a plasma state, selectively etches the silicon area not protected by the photoresist, thereby obtaining the metal gate line setting area.

[0076] After the metal gate line setting area is obtained, the metal gate line setting area is surface treated by dry etching plasma process to increase the position roughness of the gate line 13 and improve the subsequent adhesion between the gate line 13 and the substrate.

[0077] Furthermore, in the present embodiment, after a metal gate line setting region is formed in the doped N-type polysilicon layer 300 , a second tunnel passivation layer 11 is formed in the metal gate line setting region by an oxygen plasma process.

[0078] A possible operation process is as follows: After forming the metal gate line setting area, the silicon wafer is placed in a plasma operation chamber. Oxygen is introduced as the plasma gas, and radio frequency power is applied to generate plasma. The active oxygen species in the plasma (such as O 2+ or / and 3 etc.) chemically reacts with the metal gate line setting area to form a second tunnel passivation layer 11.

[0079] After the second tunnel passivation layer 11 is formed, the seed layer 12 of the metal gate line, the gate line 13 and the protection layer 14 are electroplated in sequence on the surface of the second tunnel passivation layer 11 .

[0080] A possible electroplating process is as follows: First, select a suitable seed layer 12 material, such as nickel. Place the silicon wafer in an electroplating tank and introduce a precursor gas (such as a nickel salt) of the seed layer 12 material. Apply an appropriate current density and electroplating time to allow the seed layer 12 material to be uniformly deposited on the surface of the passivation layer. Further electroplate the gate line 13 material, such as copper, on the surface of the seed layer 12. Then electroplate a protective layer 14, such as tin, on the surface of the gate line 13. After the electroplating is completed, annealing is performed to eliminate the stress between the electroplated material and the silicon substrate 100.

[0081] Finally, the excess photoresist on the surface of the first passivation anti-reflection layer that is not dissolved is removed by a wet etching process.

[0082] Embodiment 3

[0083] Please continue to refer to Figure 1 Based on the first embodiment, the present embodiment provides another HJT solar cell structure. Compared with the first embodiment, the structure of the HJT solar cell is mainly modified in that: a first tunnel passivation layer 200, an amorphous silicon layer 700, a doped microcrystalline silicon layer 800, a TCO (transparent conductive oxide) film layer 900 and a second passivation anti-reflection layer 1000 are sequentially stacked along the second direction, and a metal grid line is deposited on the surface of the TCO film layer 900.

[0084] In this embodiment, the refractive index of the TCO film layer 900 is greater than the refractive index of the second passivation anti-reflection layer 1000, so that the TCO film layer 900 and the second passivation anti-reflection layer 1000 form a stacked anti-reflection. In this structure, the incident light is reflected and refracted multiple times between the TCO film layer 900 and the second passivation anti-reflection layer 1000, reducing reflection losses and thereby improving the optical utilization of the HJT solar cell.

[0085] In this embodiment, the second direction is a direction opposite to the first direction. The battery structure arranged in the first direction is the same as that in the first embodiment, and the details can be referred to the description in the first embodiment, which will not be repeated in this embodiment.

[0086] Furthermore, in this embodiment, the first tunnel passivation layer 200 is the same as the first tunnel passivation layer 200 disclosed in the first embodiment, and the technical effects brought about are also the same, which will not be described in detail here.

[0087] In a specific embodiment, the amorphous silicon layer 700 is a hydrogenated amorphous silicon (a-Si:H(i)) layer, and the a-Si:H(i) layer can serve as the i layer in the pin structure, that is, as a generation region for photogenerated carriers (electrons and holes) for passivating interface defects.

[0088] In another specific embodiment, the in-situ doped microcrystalline silicon layer 800 is a p-type doped layer of hydrogenated microcrystalline silicon. The p-type doped layer serves as another electrode of the HJT solar cell and forms a pn junction with the doped N-type polycrystalline silicon layer disclosed in the first embodiment, thereby achieving photoelectric conversion.

[0089] In this embodiment, the material of the TCO film layer 900 can be an indium oxide film layer doped with one or more different metals (such as tin, tungsten, titanium, etc.), such as ITO (indium tin oxide), IWO (indium zinc oxide), ITiO (indium titanium oxide), etc.; or a zinc oxide film layer doped with one or more different metals (such as aluminum, indium, gallium, etc.), such as AZO (aluminum zinc nitride), GZO (gallium zinc oxide) and IZO (indium zinc oxide), etc.

[0090] In this embodiment, the second passivation anti-reflection layer 1000 includes a third silicon nitride layer. Silicon nitride has a low refractive index and can improve the anti-reflection effect of the stacked layer.

[0091] In a specific embodiment, the thickness of the third silicon nitride layer is 70-100 nm.

[0092] In this embodiment, the metal gate line includes: a seed layer 12 , a gate line 13 and a protection layer 14 .

[0093] In a specific embodiment, the seed layer 12 is made of nickel, the gate line 13 is made of copper, and the protective layer 14 is made of tin. Tin as the protective layer 14 can prevent oxidation of copper.

[0094] Embodiment 4

[0095] This embodiment discloses a method for preparing a HJT solar cell, and the HJT solar cell disclosed in the third embodiment is prepared, and the method comprises:

[0096] S11. Providing a silicon substrate 100;

[0097] S12. A first tunnel passivation layer 200, an amorphous silicon layer 700, an in-situ doped microcrystalline silicon layer 800, a TCO film layer 900 and a second passivation anti-reflection layer 1000 are sequentially stacked along the second direction;

[0098] S13. After a metal gate line setting region is formed in the TCO film layer 900, the metal gate line is deposited in the metal gate line setting region by using an electroplating process.

[0099] In this embodiment, metal grid lines are formed in the metal grid line setting area through an electroplating process, which can obtain a more uniform grid line 13 pattern with better linearity (for example, a thinner grid line 13 structure), thereby reducing the shading area and improving the current collection efficiency.

[0100] In step S12, a first tunnel passivation layer 200 (SiO 2 film layer).

[0101] Furthermore, the PECVD (plasma enhanced chemical vapor deposition) process is used to sequentially deposit low-temperature amorphous silicon (a-Si:H(i)) on the back side and in-situ doped microcrystalline silicon (a-Si:HP + Next, a TCO film layer is deposited on the surface of the in-situ doped microcrystalline silicon layer 800 by PVD (physical vapor deposition) or RPD (plasma assisted chemical vapor deposition).

[0102] In step S13, a mask layer is prepared on the surface of the TCO by coating, and then a metal gate line setting area is obtained by exposure and development.

[0103] A possible specific operation step is as follows: a layer of mask layer solution is evenly coated on the surface of the second passivation anti-reflection layer 1000. After coating, the battery is placed in an oven for curing treatment to solidify the photoresist component in the solution to form a thin film. The cured battery is placed in a photolithography machine, and the front pattern on the mask (i.e., the pattern of the etched area) is transferred to the photoresist using the photolithography machine. The photoresist is then selectively irradiated with ultraviolet light so that the etched area can be dissolved in the developer, and the exposed battery is placed in the developer for development. The developer dissolves the photoresist in the etched area, thereby forming a metal grid line setting area on the TCO surface.

[0104] After the metal gate line setting area is obtained, the metal gate line setting area is surface treated by dry etching plasma process to increase the position roughness of the gate line 13 and improve the subsequent adhesion between the gate line 13 and the substrate.

[0105] Furthermore, on the surface of the metal gate line setting area, the seed layer 12 of the metal gate line, the gate line 13 and the protection layer 14 are electroplated in sequence.

[0106] In a specific embodiment, the specific operation steps of electroplating are as follows: first, select a suitable seed layer 12 material, such as nickel. Place the silicon wafer in an electroplating tank, introduce a precursor gas (such as a nickel salt) of the seed layer 12 material, apply an appropriate current density and electroplating time, so that the seed layer 12 material is uniformly deposited on the surface of the passivation layer. Further electroplate the gate line 13 material, such as copper, on the surface of the seed layer 12. Then electroplate a protective layer 14, such as tin, on the surface of the gate line 13. After the electroplating is completed, annealing is performed to eliminate the stress between the electroplating material and the silicon substrate 100.

[0107] Finally, the undissolved photoresist on the surface of the second passivation anti-reflection layer 1000 is removed by a wet etching process.

[0108] Embodiment 5

[0109] This embodiment discloses a method for preparing a HJT solar cell, and prepares the HJT solar cell structure disclosed in the first and third embodiments to obtain a complete HJT solar cell.

[0110] Please refer to Figure 2-Figure 8 , the specific preparation method is as follows:

[0111] S100. Please refer to Figure 2 The CVD process is used to perform a high-temperature thermal oxidation process on the front and back surfaces of the silicon substrate 100 to form a first tunnel passivation layer 200 (SiO 2 ).

[0112] S200. Please refer to Figure 3 The doped N-type polysilicon layer 300 (P-Sin + ); using ALD process, an aluminum oxide layer 400 is formed on the basis of the doped N-type polysilicon layer 300; using PECVD or LPCVD process, a first silicon nitride layer 500 and a second silicon nitride layer 600 are sequentially formed on the surface of the aluminum oxide layer 400.

[0113] S300.Please refer to Figure 4 , the SiO2 on the back side of the silicon substrate 100 is deposited by PECVD process. 2 A low-temperature amorphous silicon layer 700 and an in-situ doped microcrystalline silicon layer 800 are sequentially formed on the surface of the layer.

[0114] S400. Please refer to Figure 5 . A TCO film layer 900 is deposited on the surface of the in-situ doped microcrystalline silicon layer 800 by using a PVD or RPD process; a second passivation anti-reflection layer 1000 (SiN) is deposited on the TCO film 900 by using a CVD process.

[0115] S500. Please refer to Figure 6 The front and back sides of the silicon substrate 100 are patterned by photolithography, and a metal gate line setting area 1001 is formed by dry etching on the front side, and a metal gate line setting area 1001 is formed by development on the back side, and a photoresist 1002 is left in the non-metal gate line setting area.

[0116] S600. Please refer to Figure 7 The second tunnel passivation layer 11 (SiO 2 ).

[0117] S700. Please refer to Figure 8 The metal gate lines (seed layer 12 / gate lines 13 / protective layer 14) are electroplated on the surface of the second tunnel passivation layer 11 on the front side and in the metal gate line setting area 1001 on the back side using an electroplating process.

[0118] S800. Finally, a wet etching process is used to strip off the remaining photoresist 1002 on the front and back sides to obtain Figure 1 The HJT solar cell shown.

[0119] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A HJT solar cell, characterized in that: include: Silicon substrate; A first tunnel passivation layer, a doped N-type polysilicon layer and a first passivation anti-reflection layer are sequentially stacked along a first direction; and, a metal gate line disposed on the surface of the doped N-type polysilicon layer; The first direction is the direction from the silicon substrate to the first passivation anti-reflection layer.

2. The HJT solar cell according to claim 1, characterized in that: The first passivation anti-reflection layer includes an aluminum oxide layer, a first silicon nitride layer, and a second silicon nitride layer which are sequentially stacked along a first direction.

3. The HJT solar cell according to claim 2, characterized in that: The refractive index of the first silicon nitride layer is greater than the refractive index of the second silicon nitride layer.

4. The HJT solar cell according to claim 1, characterized in that: Also comprising a second tunnel passivation layer; The second tunnel passivation layer and the metal gate line are sequentially stacked on the surface of the doped N-type polysilicon layer.

5. The HJT solar cell according to claim 4, characterized in that: The thickness of the second tunneling passivation layer is less than or equal to 0.5 nm.

6. A method for preparing a HJT solar cell, characterized in that: A HJT solar cell is prepared as claimed in any one of claims 1 to 5, wherein the preparation method comprises: Providing a silicon substrate; A first tunnel passivation layer, a doped N-type polysilicon layer and a first passivation anti-reflection layer are sequentially stacked along the first direction; After a metal gate line setting region is formed in the doped N-type polysilicon layer, the first metal gate line is deposited in the metal gate line setting region by using an electroplating process.

7. The method for preparing a HJT solar cell according to claim 6, characterized in that: The first tunnel passivation layer, the doped N-type polysilicon layer and the passivation anti-reflection layer are sequentially stacked along the first direction, comprising: The first tunnel passivation layer is formed by a high temperature thermal oxidation process.

8. The method for preparing a HJT solar cell according to claim 7, characterized in that: Forming a metal gate line setting area in the doped N-type polysilicon layer also includes: The surface of the metal gate line setting area is treated by dry etching process.

9. The method for preparing a HJT solar cell according to claim 8, characterized in that: The preparation method further comprises: After a metal gate line setting region is formed in the doped N-type polysilicon layer, an oxygen plasma etching process is used to form a second tunnel passivation layer in the metal gate line setting region.

10. A HJT solar cell, characterized in that: include: Silicon substrate; A first tunnel passivation layer, an amorphous silicon layer, an in-situ doped microcrystalline silicon layer, a TCO film layer, and a second passivation anti-reflection layer are sequentially stacked along a second direction; and, a metal grid line disposed on the surface of the TCO film layer; Wherein, the second direction is the direction from the silicon substrate to the surface of the TCO film layer; The refractive index of the TCO film layer is greater than the refractive index of the second passivation anti-reflection layer.

11. The HJT solar cell according to claim 10, characterized in that: The second passivation anti-reflection layer includes a third silicon nitride layer.

12. A method for preparing a HJT solar cell, characterized in that: A method for preparing a solar cell according to any one of claims 10 to 11, wherein the method comprises: Providing a silicon substrate; A first tunnel passivation layer, an amorphous silicon layer, a doped microcrystalline silicon layer, a TCO film layer and a second passivation anti-reflection layer are sequentially stacked along the second direction; After a metal gate line setting region is formed in the TCO film layer, the metal gate line is deposited in the metal gate line setting region by using an electroplating process.

13. The method for preparing a HJT solar cell according to claim 12, wherein: Forming a metal gate line setting area in the TCO film layer includes: The surface of the metal gate line setting area is treated by dry etching process.

Images