Light-emitting chip epitaxial layer, manufacturing method and light-emitting chip
By introducing an insertion layer into the active layer of the light emitting chip, the carrier recombination rate is improved by using doped N-type and P-type doping elements, the problem of low luminous luminance of the light emitting chip is solved, and higher luminous luminance and lower production difficulty is achieved.
Patent Information
- Application Number
- CN202311642660.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-01
- Publication Date
- 2025-06-06
AI Technical Summary
The light luminous brightness of the existing light emitting chips is low, which leads to the need to use matrix to improve the overall brightness in the display device, which increases the difficulty of production.
By introducing an insertion layer into the active layer of the light emitting chip, the insertion layer includes a hierarchical structure doped with N-type and P-type doped elements, the relative number of carriers is increased, and the probability of holes and electrons are increased, thereby enhancing the luminous luminance of the light emitting chip.
The luminous brightness of the luminescent chip is improved, the dependence on the matrix method is reduced, and the production difficulty is reduced.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a light-emitting chip epitaxial layer and a manufacturing method, and a light-emitting chip. Background Art
[0002] Micro-LED (Micro Light Emitting Diode) has been sought after by various manufacturers due to its advantages of high brightness, wide color gamut coverage and high contrast, and is called the next-generation display device. In the light-emitting chip, electrons and holes will move to the active layer, recombine in the quantum well to emit light. At present, the active layer of the light-emitting chip is usually composed of alternating well layers and barrier layers. The luminous brightness of a single light-emitting chip is low, and only a matrix method can be used to improve the overall brightness of the display, which increases the difficulty of production.
[0003] Therefore, how to improve the luminous brightness of the light-emitting chip is an urgent problem to be solved. Summary of the invention
[0004] In view of the deficiencies of the above-mentioned related technologies, the purpose of the present application is to provide a light-emitting chip epitaxial layer and a manufacturing method, and a light-emitting chip, aiming to solve the problem of low luminous brightness of the light-emitting chip.
[0005] A light-emitting chip epitaxial layer, comprising:
[0006] A first semiconductor layer, an active layer, and a second semiconductor layer are grown in sequence;
[0007] The active layer includes a first quantum well barrier layer, an insertion layer, and a second quantum well barrier layer stacked in sequence, wherein the well layers and barrier layers in the first quantum well barrier layer and the second quantum well barrier layer are stacked in sequence; the insertion layer is grown on the well layer in the first quantum well barrier layer, and the insertion layer includes a first doped layer and a second doped layer stacked and having the same band gap, wherein the first doped layer is doped with an N-type doping element, and the second doped layer is doped with a P-type doping element.
[0008] The active layer of the epitaxial layer of the light-emitting chip includes an insertion layer, wherein the first doping layer of the insertion layer is doped with an N-type doping element, and the second doping layer of the insertion layer is doped with a P-type doping element. Doping with the N-type doping element enables the first doping layer to provide electrons, and doping with the P-type doping element enables the second doping layer to provide holes, thereby increasing the relative number of carriers in the active layer, improving the probability of recombination of holes and electrons, and enhancing the luminous brightness of the light-emitting chip.
[0009] Optionally, the insertion layer further includes a first barrier layer and a second barrier layer, and the first doping layer and the second doping layer are arranged between the first barrier layer and the second barrier layer. The first barrier layer and the second barrier layer can prevent N-type doping elements and P-type doping elements from entering the first quantum well barrier layer and the second quantum well barrier layer to affect the luminous efficiency.
[0010] Optionally, the first semiconductor layer is a P-type semiconductor layer, the second semiconductor layer is an N-type semiconductor layer, and the first doped layer is disposed between the first quantum well barrier layer and the second doped layer; or, the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, and the second doped layer is disposed between the first quantum well barrier layer and the first doped layer. Thus, a double quantum well light-emitting structure can be formed, thereby increasing the light-emitting brightness of the light-emitting chip.
[0011] Based on the same inventive concept, the present application also provides a light-emitting chip, including:
[0012] The light-emitting chip epitaxial layer as described above;
[0013] And, a first electrode and a second electrode electrically connected to the first semiconductor layer and the second semiconductor layer respectively.
[0014] In the above-mentioned light-emitting chip, the active layer includes an insertion layer, the first doping layer of the insertion layer is doped with an N-type doping element, and the second doping layer of the insertion layer is doped with a P-type doping element. Doping with the N-type doping element enables the first doping layer to provide electrons, and doping with the P-type doping element enables the second doping layer to provide holes, thereby increasing the relative number of carriers in the active layer, improving the probability of recombination of holes and electrons, and enhancing the luminous brightness of the light-emitting chip.
[0015] Based on the same inventive concept, the present application also provides a method for manufacturing the epitaxial layer of the light-emitting chip as described above, comprising:
[0016] growing the first quantum well barrier layer on the first semiconductor layer;
[0017] Growing the insertion layer on the well layer in the first quantum well barrier layer, the insertion layer comprising the first doping layer and the second doping layer, the first doping layer being doped with an N-type doping element, and the second doping layer being doped with a P-type doping element;
[0018] The second quantum well barrier layer is grown on the insertion layer.
[0019] In the above-mentioned method for manufacturing the epitaxial layer of the light-emitting chip, an insertion layer is grown on the well layer in the first quantum well barrier layer, the first doping layer of the insertion layer is doped with an N-type doping element, and the second doping layer of the insertion layer is doped with a P-type doping element. Doping with the N-type doping element enables the first doping layer to provide electrons, and doping with the P-type doping element enables the second doping layer to provide holes, thereby increasing the relative number of carriers in the active layer, improving the probability of recombination of holes and electrons, and enhancing the luminous brightness of the light-emitting chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A schematic diagram of the structure of the epitaxial layer of the light-emitting chip provided in an embodiment of the present application;
[0021] Figure 2 A schematic diagram of the structure of the active layer provided in an embodiment of the present application;
[0022] Figure 3 A schematic diagram of the structure of the insertion layer provided in the embodiment of the present application;
[0023] Figure 4 A flow chart of a method for manufacturing an epitaxial layer of a light-emitting chip provided in an optional embodiment of the present application;
[0024] Description of reference numerals:
[0025] 1-first semiconductor layer; 2-active layer; 201-first quantum well barrier layer; 202-insertion layer; 203-second quantum well barrier layer; 204-barrier layer; 205-well layer; 206-first barrier layer; 207-first doped layer; 208-second doped layer, 209-second barrier layer; 3-second semiconductor layer. DETAILED DESCRIPTION
[0026] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0028] In a light-emitting chip, electrons and holes move to the active layer and recombine in the quantum well to emit light. The active layer of a light-emitting chip is usually composed of alternating well layers and barrier layers. The brightness of a single light-emitting chip is low, and the overall brightness of the display can only be improved by using a matrix method, which increases the difficulty of production.
[0029] Based on this, the present application hopes to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in the subsequent embodiments.
[0030] This embodiment provides a light-emitting chip epitaxial layer, such as Figure 1-Figure 3 As shown, it includes a first semiconductor layer 1, an active layer 2, and a second semiconductor layer 3 grown in sequence. Among them, the active layer 2 includes a first quantum well barrier layer 201, an insertion layer 202, and a second quantum well barrier layer 203 stacked in sequence, and the well layer 205 and the barrier layer 204 in the first quantum well barrier layer 201 and the second quantum well barrier layer 203 are stacked in sequence. It can be understood that the first quantum well barrier layer 201 can be a well layer 205 and a barrier layer 204 stacked in sequence for 1 to 4 periods, and the second quantum well barrier layer 203 can be a well layer 205 and a barrier layer 204 stacked in sequence for 1 to 5 periods, but it is not limited to this, and can be actually set according to needs. However, at the end of the growth, the first quantum well barrier layer 201 and the second quantum well barrier layer 203 are both grown well layers 205, that is, the edge of the first quantum well barrier layer 201 close to the insertion layer 202 is the well layer 205, and the edge of the second quantum well barrier layer 203 away from the insertion layer 202 is also the well layer 205. In some embodiments, the first quantum well barrier layer 201 and the second quantum well barrier layer 203 may be non-doped layers. In some application scenarios, doping elements may also be present in the first quantum well barrier layer 201 and the second quantum well barrier layer 203. In this embodiment, the material of the first quantum well barrier layer 201 and the second quantum well barrier layer 203 may be but not limited to AlGaInP. In the first quantum well barrier layer 201 and the second quantum well barrier layer 203, the thickness of the well layer 205 may be but not limited to 4 to 8 nm, and the thickness of the barrier layer 204 may be but not limited to 5 to 8 nm. The well layer 205 and the barrier layer 204 are superlattice structures.
[0031] In this embodiment, if Figure 3 As shown, the insertion layer 202 is grown on the well layer 205 in the first quantum well barrier layer 201, and the insertion layer 202 includes a first doping layer 207 and a second doping layer 208 with a band gap arranged in a stacked manner, wherein the first doping layer 207 is doped with an N-type doping element, and the second doping layer 208 is doped with a P-type doping element. Doping with the N-type doping element enables the first doping layer 207 to provide electrons, and doping with the P-type doping element enables the second doping layer 208 to provide holes, thereby increasing the relative number of carriers in the active layer 2, improving the probability of recombination of holes and electrons, and enhancing the luminous brightness of the light-emitting chip.
[0032] It is understood that the N-type doping element and the P-type doping element in this embodiment can be selected as needed, and can be an element that can provide electrons to the first doping layer 207 and an element that can provide holes to the second doping layer 208. In some embodiments, the N-type doping element may include Si, and the doping concentration of Si may be 8×10 17 cm 3 ~1×10 18 cm 3 ; The P-type doping element may include Mg, and the doping concentration of Mg is 2×10 17 cm 3 ~7×10 17 cm 3 . However, this doping concentration is only used as an example, and the specific doping concentration can be set according to actual needs. The band gap of the insertion layer 202 in this embodiment is larger than the band gap of the well layer 205 in the first quantum well barrier layer 201, and the band gap of the well layer 205 in the second quantum well barrier layer 203, thereby avoiding the insertion layer 202 from affecting the luminescence of the well layer 205. The material of the insertion layer 202 can be set as needed, for example, it can be but not limited to AlGaInP or AlInP. In this embodiment, the band gaps of the first doping layer 207 and the second doping layer 208 are the same. In some application scenarios, the band gaps of the first doping layer 207 and the second doping layer 208 can be but not limited to the same as the band gap of the barrier layer 204.
[0033] In some embodiments, Figure 3 As shown, the insertion layer 202 further includes a first barrier layer 206 and a second barrier layer 209, and a first doping layer 207 and a second doping layer 208 are disposed between the first barrier layer 206 and the second barrier layer 209. The first barrier layer 206 and the second barrier layer 209 are non-doped layers, and the first barrier layer 206 and the second barrier layer 209 can prevent N-type doping elements and P-type doping elements from entering the first quantum well barrier layer 201 and the second quantum well barrier layer 203 by adjusting the Al component, thereby affecting the luminous efficiency. In this embodiment, the thickness of the first barrier layer 206 and the second barrier layer 209 is less than the thickness of the first doping layer 207 and the second doping layer 208. The first barrier layer 206 and the second barrier layer 209 can form a barrier to the doping elements, and do not need to be too thick, thereby saving materials. Optionally, the thickness of the first barrier layer 206 and the second barrier layer 209 may be, but not limited to, 3 nm to 5 nm, and the thickness of the first doping layer 207 and the second doping layer 208 may be, but not limited to, 10 nm to 15 nm.
[0034] In some embodiments, the first semiconductor layer 1 is a P-type semiconductor layer, the second semiconductor layer 3 is an N-type semiconductor layer, and the first doped layer 207 is disposed between the first quantum well barrier layer 201 and the second doped layer 208. At this time, the stacking order in the epitaxial layer is the P-type semiconductor layer, the first quantum well barrier layer 201, the first barrier layer 206, the N-type doped first doped layer 207, the P-type doped second doped layer 208, the second barrier layer 209, the second quantum well barrier layer 203, and the N-type semiconductor layer. The P-type semiconductor layer is disposed close to the N-type doped first doped layer 207, and the P-type doped second doped layer 208 is disposed close to the N-type semiconductor layer, forming a double quantum well light-emitting structure, thereby increasing the light-emitting brightness of the light-emitting chip.
[0035] In other embodiments, the first semiconductor layer 1 is an N-type semiconductor layer, the second semiconductor layer 3 is a P-type semiconductor layer, and the second doped layer 208 is disposed between the first quantum well barrier layer 201 and the first doped layer 207. At this time, the stacking order of the epitaxial layers is N-type semiconductor layer, first quantum well barrier layer 201, first barrier layer 206, P-type doped second doped layer 208, N-type doped first doped layer 207, second barrier layer 209, second quantum well barrier layer 203, and P-type semiconductor layer. Similarly, a double quantum well light-emitting structure can be formed to increase the light-emitting brightness of the light-emitting chip.
[0036] In some application scenarios, the order of stacking in the epitaxial layer can also be P-type semiconductor layer, first quantum well barrier layer 201, first barrier layer 206, P-type doped second doped layer 208, N-type doped first doped layer 207, second barrier layer 209, second quantum well barrier layer 203, N-type semiconductor layer; or N-type semiconductor layer, first quantum well barrier layer 201, first barrier layer 206, N-type doped first doped layer 207, P-type doped second doped layer 208, second barrier layer 209, second quantum well barrier layer 203, P-type semiconductor layer. The P-type doped second doped layer 208 can provide holes, and the N-type doped first doped layer 207 can provide electrons, which can still increase the probability of recombination of holes and electrons and enhance the luminous brightness of the light-emitting chip. This embodiment does not limit the specific structure of the P-type semiconductor layer and the N-type semiconductor layer as long as light emission can be achieved. For example, in one embodiment, the epitaxial layer may include a buffer layer, a P-type corrosion stop layer, a P-type ohmic contact layer, a P-type AGIP current spreading layer, a P-type AlInP confinement layer, a P-type waveguide layer, an active layer, an N-type waveguide layer, an N-type AlInP confinement layer, and an N-type window layer stacked in sequence on a substrate.
[0037] The active layer 2 of the epitaxial layer of the light-emitting chip includes an insertion layer 202, wherein the first doping layer 207 of the insertion layer 202 is doped with an N-type doping element, and the second doping layer 208 of the insertion layer 202 is doped with a P-type doping element. The doping of the N-type doping element enables the first doping layer 207 to provide electrons, and the doping of the P-type doping element enables the second doping layer 208 to provide holes, thereby increasing the response speed of carriers to a small current, increasing the relative number of carriers in the active layer 2, increasing the probability of recombination of holes and electrons, and enhancing the luminous brightness of the light-emitting chip.
[0038] Another optional embodiment of the present application:
[0039] This embodiment provides a light-emitting chip, including a first electrode, a second electrode, and the light-emitting chip epitaxial layer as described above, wherein the first electrode and the second electrode are electrically connected to the first semiconductor layer 1 and the second semiconductor layer 3 respectively.
[0040] This embodiment does not specifically limit the material and shape of the positive electrode and the negative electrode. For example, the material of the electrode may include but is not limited to at least one of Cr, Ni, Al, Ti, Au, Pt, W, Pb, Rh, Sn, Cu, and Ag.
[0041] The light-emitting chip in this embodiment includes but is not limited to at least one of a high-brightness LED light-emitting chip, a Mini LED (Mini Light Emitting Diode), a Micro LED (Micro Light Emitting Diode), and a nanometer-level light-emitting diode. The light-emitting chip in this embodiment can be a front-mounted LED chip or a flip-chip LED chip. The light-emitting chip in this embodiment can be a red light LED chip that emits red light, and of course, it can also be set to an LED chip that emits light of other colors according to needs, which will not be repeated here.
[0042] In the above-mentioned light-emitting chip, its active layer 2 includes an insertion layer 202, a first doping layer 207 of the insertion layer 202 is doped with an N-type doping element, and a second doping layer 208 of the insertion layer 202 is doped with a P-type doping element. Doping with the N-type doping element enables the first doping layer 207 to provide electrons, and doping with the P-type doping element enables the second doping layer 208 to provide holes, thereby improving the response speed of carriers to a small current, increasing the relative number of carriers in the active layer 2, increasing the probability of recombination of holes and electrons, and enhancing the luminous brightness of the light-emitting chip.
[0043] Another optional embodiment of the present application:
[0044] This embodiment provides a method for manufacturing the epitaxial layer of the light-emitting chip as described above. Figure 4 , including the following steps:
[0045] S1: growing a first quantum well barrier layer on the first semiconductor layer.
[0046] In some embodiments, the temperature can be set to 640-660° C., the chamber pressure can be set to 50 mbar, phosphine can be used as a group V source, hydrogen can be used as a carrier gas, and a certain amount of trimethylaluminum, trimethylgallium, and trimethylindium can be introduced as group III sources to grow the first quantum well barrier layer 201. During the growth, the well layer 205 is grown first, then the barrier layer 204 is grown, and finally the well layer 205 is grown.
[0047] Before growing the first quantum well barrier layer 201, it is necessary to grow the first semiconductor layer 1. For example, when the first semiconductor layer 1 is a P-type semiconductor layer, it can be specifically grown on a GaAs substrate in sequence using a MOCVD (Metal-organic Chemical Vapor Deposition) device, including a buffer layer, an etching stop layer, a P-type ohmic contact layer, a P-type current spreading layer, a P-type AlInP limiting layer, and a P-type waveguide layer. This growth sequence is only used as an example, and the specific growth steps before growing the first quantum well barrier layer 201 can be set according to actual needs, and this embodiment does not limit this.
[0048] S2: growing an insertion layer on the well layer in the first quantum well barrier layer.
[0049] The insertion layer 202 in this embodiment includes a first doping layer 207 and a second doping layer 208, wherein the first doping layer 207 is doped with an N-type doping element, and the second doping layer 208 is doped with a P-type doping element. The specific configuration of the insertion layer 202 is the same as that of the above embodiment, and will not be described in detail here. In some embodiments, growing the insertion layer 202 includes: growing a first barrier layer 206; growing a first doping layer 207 and a second doping layer 208 on the first barrier layer 206; and finally growing a second barrier layer 209. The first barrier layer 206 and the second barrier layer 209 can prevent N-type doping elements and P-type doping elements from entering the first quantum well barrier layer 201 and the second quantum well barrier layer 203, thereby affecting the luminous efficiency.
[0050] S3: growing a second quantum well barrier layer on the insertion layer.
[0051] The parameter setting for the growth of the second quantum well barrier layer 203 may be the same as the parameter setting for the growth of the first quantum well barrier layer 201. After the growth of the second quantum well barrier layer 203, the second semiconductor layer 3 may be grown. For example, when the second semiconductor layer 3 is an N-type semiconductor layer, an N-type waveguide layer, an N-type AlInP confinement layer, and an N-type window layer may be grown in sequence on the second quantum well barrier layer 203. This growth sequence is also only used as an example. The specific growth steps after the growth of the second quantum well barrier layer 203 may be set according to actual needs, and this embodiment does not limit this.
[0052] In the above-mentioned method for manufacturing the epitaxial layer of the light-emitting chip, an insertion layer 202 is grown on the well layer 205 in the first quantum well barrier layer 201, and an N-type doping element is doped in the first doping layer 207 of the insertion layer 202, and a P-type doping element is doped in the second doping layer 208 of the insertion layer 202. Doping with the N-type doping element enables the first doping layer 207 to provide electrons, and doping with the P-type doping element enables the second doping layer 208 to provide holes, thereby improving the response speed of carriers to a small current, increasing the relative number of carriers in the active layer 2, increasing the probability of recombination of holes and electrons, and enhancing the luminous brightness of the light-emitting chip.
[0053] It should be understood that the application of the present application is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to this application.
Claims
1. A light-emitting chip epitaxial layer, It is characterized in that include: A first semiconductor layer, an active layer, and a second semiconductor layer are grown in sequence; The active layer includes a first quantum well barrier layer, an insertion layer, and a second quantum well barrier layer stacked in sequence, wherein the well layers and barrier layers in the first quantum well barrier layer and the second quantum well barrier layer are stacked in sequence; the insertion layer is grown on the well layer in the first quantum well barrier layer, and the insertion layer includes a first doped layer and a second doped layer stacked and having the same band gap, wherein the first doped layer is doped with an N-type doping element, and the second doped layer is doped with a P-type doping element.
2. The light-emitting chip epitaxial layer according to claim 1, It is characterized in that The insertion layer further includes a first barrier layer and a second barrier layer, and the first doping layer and the second doping layer are arranged between the first barrier layer and the second barrier layer.
3. The light-emitting chip epitaxial layer according to claim 2, It is characterized in that The thickness of the first barrier layer and the second barrier layer are both smaller than the thickness of the first doping layer and the second doping layer.
4. The light-emitting chip epitaxial layer according to claim 3, It is characterized in that The thickness of the first barrier layer and the second barrier layer is 3 nm to 5 nm.
5. The light-emitting chip epitaxial layer according to any one of claims 1 to 4, It is characterized in that The first semiconductor layer is a P-type semiconductor layer, the second semiconductor layer is an N-type semiconductor layer, and the first doped layer is disposed between the first quantum well barrier layer and the second doped layer; Alternatively, the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, and the second doped layer is disposed between the first quantum well barrier layer and the first doped layer.
6. The light-emitting chip epitaxial layer according to any one of claims 1 to 4, It is characterized in that The N-type doping element includes Si, and the doping concentration of Si is 8×10 17 cm 3 ~1×10 18 cm 3 The P-type doping element includes Mg, and the doping concentration of Mg is 2×10 17 cm 3 ~7×10 17 cm 3 .
7. The light-emitting chip epitaxial layer according to any one of claims 1 to 4, It is characterized in that The first quantum well barrier layer and the second quantum well barrier layer are non-doped layers.
8. The light-emitting chip epitaxial layer according to any one of claims 1 to 4, It is characterized in that The band gap of the insertion layer is larger than the band gap of the well layer in the first quantum well barrier layer and the band gap of the well layer in the second quantum well barrier layer.
9. A light-emitting chip, It is characterized in that include: The light-emitting chip epitaxial layer according to any one of claims 1 to 8; And, a first electrode and a second electrode electrically connected to the first semiconductor layer and the second semiconductor layer respectively.
10. A method for manufacturing an epitaxial layer of a light-emitting chip according to any one of claims 1 to 8, It is characterized in that include: growing the first quantum well barrier layer on the first semiconductor layer; Growing the insertion layer on the well layer in the first quantum well barrier layer, the insertion layer comprising the first doping layer and the second doping layer, the first doping layer being doped with an N-type doping element, and the second doping layer being doped with a P-type doping element; The second quantum well barrier layer is grown on the insertion layer.