Organic field effect transistor memory based on P (VDF-TrFE-CTFE) / PHPS double insulating layers and preparation method thereof

Abstract

The invention belongs to the field of memories, and particularly relates to an organic field effect transistor memory based on P (VDF-TrFE-CTFE) / PHPS double insulating layers and a preparation method of the organic field effect transistor memory. The organic field effect transistor memory comprises a substrate, a gate electrode, a P (VDF-TrFE-CTFE) insulating layer, a PHPS derivative insulating layer, an organic semiconductor layer, a source electrode and a drain electrode, is a flexible ferroelectric organic field effect transistor nonvolatile memory Fe-OFET-NVMs, and has the advantages of low working voltage, high mobility, large storage window, reliable durability and mechanical bending durability. A new thought is provided for application of the organic ferroelectric material in the ferroelectric memory device, and development of the ferroelectric memory device can be promoted.

Description

Technical Field

[0001] The present invention belongs to the field of memory, and in particular relates to an organic field effect transistor memory based on a P (VDF-TrFE-CTFE) / PHPS double insulating layer and a preparation method thereof. Background Art

[0002] Field effect is a phenomenon in which the electrical properties of a semiconductor change due to changes in an external electric field. Field effect transistors that use organic semiconductor materials as semiconductor layers are organic field effect transistors. Organic field effect transistor memory has excellent stability and strong data retention capabilities, and has great application potential. Organic field effect transistor non-volatile memory can be divided into polymer electret organic field effect transistor non-volatile memory, floating gate organic field effect transistor non-volatile memory, and ferroelectric organic field effect transistor non-volatile memory.

[0003] Ferroelectric organic field effect transistor non-volatile memory (Fe-OFET-NVMs) is a memory device that uses ferroelectric materials as insulating layers. Its function stems from the polarization of the ferroelectric material as a gate insulator to control the carriers in the semiconductor. Even after the external voltage is removed, there is still residual polarization charge in the ferroelectric layer, realizing the non-volatile property. After decades of research, field effect transistor memories based on inorganic ferroelectric materials have achieved storage performance with practical value in recent years. However, with the development of flexible devices, organic ferroelectric materials that can be used in memory devices have received increasing attention.

[0004] Research on organic ferroelectric materials mainly focuses on polyvinylidene fluoride (PVDF) and its derivative polymers. Among them, P(VDF-TrFE) (vinylidene fluoride-trifluoroethylene) is the most interesting, with large remnant polarization, fast switching ability and good thermal stability. P(VDF-TrFE) has a high remnant polarization intensity (Pr, about 10μC / cm 2 ), which is used in memory to maintain storage function for a long time. However, its coercive electric field is relatively high (Ec, about 50MV / m), and the operating voltage of the memory device made of this material is relatively high, generally 80-100V. In contrast, the coercive electric field of the ternary ferroelectric polymer P(VDF-TrFE-CTFE) (vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene) is relatively low (about 14MV / m) and can be used for Fe-OFET-NVMs with low operating voltage. Compared with P(VDF-TrFE), P(VDF-TrFE-CTFE) has a lower Pr (about 1.2μC / cm 2) is more suitable for low operating voltage devices. Although the insulating layer prepared using P(VDF-TrFE-CTFE) has the advantage of low coercive electric field, it still has the same problem of large surface roughness as the P(VDF-TrFE) layer. Large surface roughness will seriously affect the charge flow between the semiconductor layer and the insulating layer. In addition, the polarization fluctuation of the ferroelectric layer will also affect the transport of carriers. High mobility is conducive to improving the switching and response speed of the device, which is of great significance for improving performance and reducing power consumption. For Fe-OFET-NVMs, mobility directly affects the storage performance of the memory device. A larger mobility helps to improve the storage switching current ratio and storage window of the device, which is beneficial for the device to clearly distinguish between the storage and erase states.

[0005] CN114203908A discloses an optically transparent non-volatile transistor memory and a preparation method thereof. The memory is a top gate structure, which includes a substrate, a source-drain electrode, a polymer semiconductor layer, a ferroelectric gate insulating layer and a gate electrode from bottom to top; wherein the substrate, the source-drain electrode, the polymer semiconductor layer, the ferroelectric gate insulating layer and the gate electrode are all made of optically transparent materials; the operating voltage of the non-volatile transistor memory is ±70V, which is relatively high, and under the large operating voltage of 70V, the switching of the device is only 10 4, the performance is not excellent enough. CN110047996A discloses an ultra-low power consumption ferroelectric transistor memory based on two-dimensional organic functional materials and a preparation method thereof, wherein an aluminum oxide insulating layer is grown on a substrate by an atomic beam deposition method, and then an ultra-thin ferroelectric polymer crystalline film is prepared at room temperature by an anti-solvent assisted crystallization method, and then an ultra-thin polymethyl methacrylate layer and an ultra-thin dioctylbenzothiophene layer are grown simultaneously by a floating coffee ring effect and a phase separation method, and finally a gold film is transferred to the dioctylbenzothiophene layer as a source and a drain by a non-invasive gold film transfer process. CN107275483A discloses a fast ferroelectric transistor memory based on a two-dimensional organic molecular semiconductor. The invention adopts heavily doped p-type silicon as a substrate, grows 50-250nm silicon dioxide as an insulating layer, prepares a 20-50nm gold layer as a gate electrode on the silicon dioxide by a thermal evaporation method, and then spin-coats a layer of ferroelectric polymer material, namely poly(vinylidene fluoride-triethylene), on the gate electrode, and grows an ultra-thin layer of polymethyl methacrylate (PMMA) with a thickness of 2-10nm and a dioctylbenzothiophene benzothiophene semiconductor layer (C8-BTBT) with a thickness of 5-10nm on the P(VDF-TrFE) by a floating coffee ring effect and a phase separation method, wherein the passivation layer PMMA is below the two-dimensional semiconductor layer C8-BTBT, and gold is evaporated on the semiconductor layer as a source and a drain electrode to prepare a two-dimensional organic molecular semiconductor ferroelectric transistor memory with a bottom gate and a top contact structure. In order to reduce the operating voltage of the device, CN110047996A and CN107275483A adopt an extremely complex preparation process to reduce the thickness of the ferroelectric insulating layer (only 2-10nm), which greatly increases the cost of device preparation, reduces the stability of the device, and makes it difficult to achieve large-scale production. Summary of the invention

[0006] In view of the shortcomings of the prior art, the present invention provides an organic field effect transistor memory based on P(VDF-TrFE-CTFE) / PHPS double insulating layer, which is a flexible ferroelectric organic field effect transistor non-volatile memory Fe-OFET-NVMs, with low operating voltage (±15V), high mobility (mobility reaches 1.85cm 2 V -1 s -1 ), large storage window, reliable durability and mechanical bending durability.

[0007] The technical solution of the present invention is an organic field effect transistor based on a P (VDF-TrFE-CTFE) / PHPS double insulating layer, comprising a substrate, a gate electrode, a P (VDF-TrFE-CTFE) insulating layer, a PHPS-derived insulating layer, an organic semiconductor layer, a source electrode and a drain electrode.

[0008] The gate electrode is located between the substrate and the P(VDF-TrFE-CTFE) insulating layer, the PHPS-derived insulating layer is located between the P(VDF-TrFE-CTFE) insulating layer and the organic semiconductor layer, and the source and drain electrodes are attached to the organic semiconductor layer. After PHPS is irradiated with ultraviolet light, the ultraviolet light causes the Si-H or NH bonds to break, generating free radicals, and then forming dense SiO X Thin films (especially SiO 2 The PHPS-derived insulating layer contains dense SiO X Films, especially dense SiO 2 The thickness of the PHPS-derived insulating layer is 10-50 nm, preferably 15-25 nm.

[0009] The substrate includes but is not limited to any one of PET, PI, PEN, etc., and is preferably a PET substrate.

[0010] The material of the gate electrode includes but is not limited to any one or any combination of gold, aluminum, copper, silver, molybdenum, tungsten, palladium, nickel-based alloys (such as nickel-manganese, nickel-chromium, nickel-molybdenum-iron, etc.), tungsten-rhenium alloys, tungsten-molybdenum alloys, polysilicon, etc., preferably gold; the thickness of the gate electrode is 20-60nm, preferably 25-35nm.

[0011] The molar fractions of VDF, TrFE and CTFE in the P(VDF-TrFE-CTFE) insulating layer are 50% to 80%, 15% to 30% and 5% to 20%, respectively, preferably 64% to 65%, 27% to 28% and 8% to 9%. The thickness of the P(VDF-TrFE-CTFE) insulating layer is 300 to 1000 nm, preferably 450 to 550 nm.

[0012] The organic semiconductor includes but is not limited to any one or any combination of pentacene, PTCDI-C8, C8-BTBT, and P3HT, preferably pentacene or PTCDI-C8. The thickness of the organic semiconductor layer is 30-80 nm, preferably 35-45 nm.

[0013] The shape and size of the source and drain are determined by the mask, and the channel width between the source and drain is 200 μm, and the channel length is 110 μm. The materials of the source and drain include, but are not limited to, any one or any combination of gold, aluminum, copper, silver, molybdenum, tungsten, palladium, nickel-based alloys (such as nickel-manganese, nickel-chromium, nickel-molybdenum-iron, etc.), tungsten-rhenium alloy, tungsten-molybdenum alloy, polysilicon, etc., preferably gold. The thickness of the source and drain is 20-60 nm, preferably 25-35 nm.

[0014] The present invention also provides a method for preparing an organic field effect transistor based on a P(VDF-TrFE-CTFE) / PHPS double insulating layer, the steps comprising:

[0015] S1: using an evaporation method to generate a gate electrode on a substrate;

[0016] S2: Spin-coating a P (VDF-TrFE-CTFE) solution on the gate electrode, and performing an annealing treatment to form a P (VDF-TrFE-CTFE) insulating layer on the gate electrode;

[0017] S3: Spin coating the PHPS solution on the P(VDF-TrFE-CTFE) insulating layer, and treating with ultraviolet light to generate a PHPS-derived insulating layer on the P(VDF-TrFE-CTFE) insulating layer;

[0018] S4: using an evaporation method to generate an organic semiconductor layer on the PHPS-derived insulating layer;

[0019] S5: preparing a source electrode and a drain electrode on the organic semiconductor layer by using an evaporation method.

[0020] In step S1, the substrate includes but is not limited to any one of PET, PI, PEN, etc., preferably a PET substrate. The substrate is sequentially placed in deionized water, acetone, and isopropanol for ultrasonic cleaning, and then blown dry with nitrogen.

[0021] In step S1, the material of the gate electrode includes but is not limited to any one or any combination of gold, platinum, aluminum, copper, silver, molybdenum, tungsten, palladium, nickel-based alloys (such as nickel-manganese, nickel-chromium, nickel-molybdenum-iron, etc.), tungsten-rhenium alloys, tungsten-molybdenum alloys, polysilicon, etc., preferably a gold gate electrode; the thickness of the gate electrode is 20-60nm, preferably 25-35nm.

[0022] In step S2, the mass fraction of the ternary ferroelectric copolymer P(VDF-TrFE-CTFE) in the P(VDF-TrFE-CTFE) solution is 5%-13%, preferably 7%-8%; the molar fractions of VDF, TrFE and CTFE in the P(VDF-TrFE-CTFE) are 50%-80%, 15%-30% and 5%-20%, preferably 64%-65%, 27%-28% and 8%-9% respectively. The preparation method of the P(VDF-TrFE-CTFE) solution is: dissolving the ternary ferroelectric copolymer P(VDF-TrFE-CTFE) in an organic solvent to prepare a solution, wherein the organic solvent includes but is not limited to any one or any combination of butyl acetate, ethyl acetate, cyclohexanone and dimethylformamide, preferably butyl acetate (BA).

[0023] In step S2, the thickness of P(VDF-TrFE-CTFE) spin-coated on the gate electrode is 300-1000 nm, preferably 450-550 nm, and the coating is performed at 2000-4000 r / min for 50-60 s, preferably 2000 r / min for 60 s.

[0024] In step S2, the thickness of the P (VDF-TrFE-CTFE) insulating layer on the gate electrode is 300-1000 nm, preferably 450-550 nm.

[0025] In step S2, annealing is performed at 110-130° C. for 110-150 minutes, preferably at 120° C. for 120 minutes.

[0026] In step S3, the mass fraction of PHPS in the PHPS solution is 1%-10%, preferably 2-3%. The preparation method of the PHPS solution is: dilute the PHPS solution with dibutyl ether.

[0027] In step S3, the thickness of the PHPS spin-coated on the P(VDF-TrFE-CTFE) insulating layer is 10-50 nm, preferably 15-25 nm; the spin coating is performed at 6000-7000 r / min for 20-30 s, preferably 6000 r / min for 30 s.

[0028] In step S3, 256 Hz ultraviolet light is irradiated for 1-1.5 hours. After PHPS is irradiated with ultraviolet light, the ultraviolet light causes the Si-H or NH bonds to break, generating free radicals, and then dense SiO X Thin films (especially SiO 2 The PHPS-derived insulating layer contains dense SiO X Films, especially dense SiO 2 The thickness of the PHPS-derived insulating layer is 10-50 nm, preferably 15-25 nm.

[0029] In step S4, the organic semiconductor includes but is not limited to any one or any combination of pentacene, PTCDI-C8, C8-BTBT, and P3HT, preferably pentacene or PTCDI-C8. The thickness of the organic semiconductor layer is 30-80 nm, preferably 35-45 nm.

[0030] In step S5, the shape and size of the source and drain are determined by the mask, and the channel width between the source and drain is 200 μm, and the channel length is 110 μm. The materials of the source and drain include, but are not limited to, any one or any combination of gold, aluminum, chromium, copper, silver, molybdenum, tungsten, palladium, nickel-based alloys (such as nickel-manganese, nickel-chromium, nickel-molybdenum-iron, etc.), tungsten-rhenium alloys, tungsten-molybdenum alloys, polysilicon, etc., preferably gold. The thickness of the source and drain is 20-60 nm, preferably 25-35 nm.

[0031] Compared with the prior art, the advantages of the present invention are:

[0032] Aiming at the limitations of traditional P (VDF-TrFE) organic field effect transistors, the present invention provides a novel organic field effect transistor memory device based on P (VDF-TrFE-CTFE) / PHPS double insulating layers. The organic field effect transistor memory device can significantly improve mobility while reducing programming / erasing voltage.

[0033] 1. In order to meet the requirements of flexible devices, a flexible device was prepared on a flexible substrate PET, which can still maintain good storage performance in a bent state.

[0034] 2. Using ternary ferroelectric polymer P (VDF-TrFE-CTFE) as the gate dielectric, the operating voltage of the device was successfully reduced to ±15V.

[0035] 3. A simple spin coating of PHPS was performed on the P(VDF-TrFE-CTFE) layer to generate a dense SiO2 layer between the P(VDF-TrFE-CTFE) insulating layer and the organic semiconductor layer under ultraviolet light irradiation. X This method improves the surface roughness of the P(VDF-TrFE-CTFE) insulating layer and the influence of polarization fluctuation on device performance, thereby reducing leakage current and improving device mobility. In addition, the PHPS layer has a smaller surface energy, which is conducive to the growth of large-sized crystals in the upper organic semiconductor layer, further improving the mobility and storage performance of the device.

[0036] The device of the present invention has a best performance of 1.85cm at a low operating voltage of ±15V. 2 V -1 s -1 high mobility, a large memory window of 13.2V and 3×10 4 The high storage switching current ratio shows good storage performance. After more than 5000s of retention test, the current switching ratio of the device is about 5×10 3, showing stable data storage retention capability. When the device is bent with a curvature radius of r = 5 mm, its storage window and storage switching current ratio are 11.8 V and 10 4 After 600 mechanical bending cycles, the device storage switching ratio also tends to decrease, but remains at 10 3 The above proves that the device can work normally in a bent state.

[0037] Therefore, the present invention provides a new idea for the application of organic ferroelectric materials in ferroelectric memory devices, and can promote the development of ferroelectric memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic diagram of the three-dimensional structure of the organic field effect transistor based on the P (VDF-TrFE-CTFE) / PHPS double insulating layer of the present invention; in the figure: 1, substrate; 2, Au gate electrode; 3, P (VDF-TrFE-CTFE) layer; 4, PHPS derivative layer; 5, organic semiconductor layer; 6, source / drain electrodes.

[0039] Figure 2 It is a schematic diagram of the preparation process of the organic field effect transistor based on the P(VDF-TrFE-CTFE) / PHPS double insulating layer of the present invention.

[0040] Figure 3 This is the device storage performance curve provided in Example 1. (The data that can be extracted from the figure include: mobility, storage window and storage switching current ratio)

[0041] Figure 4 is the retention characteristic curve of the device provided in Example 1.

[0042] Figure 5 1 is a bending performance curve of the device provided in Example 1. (a) Transfer curve of the device under different curvature radii, (b) Transfer curve of the device after multiple bendings. DETAILED DESCRIPTION

[0043] Embodiment 1:

[0044] (1) A polyethylene terephthalate (PET) substrate was placed in deionized water, acetone solution, and isopropanol solution in turn and ultrasonically cleaned for 10 minutes each. After cleaning, the substrate was blown dry with a nitrogen gun.

[0045] (2) 30 nm Au was grown on the PET substrate by evaporation as the gate electrode.

[0046] (3) Dissolve vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene [P(VDF-TrFE-CTFE)] with a composition of 64.2 / 27.1 / 8.7 mol% in butyl acetate (BA) to prepare a 7% (mass fraction) solution. The completely dissolved P(VDF-TrFE-CTFE) solution is spin-coated (2000 r / min, 60 s) on the Au gate electrode. The thickness of the spin-coated P(VDF-TrFE-CTFE) film is about 500 nm. The device spin-coated with the P(VDF-TrFE-CTFE) solution is placed in an annealing furnace and annealed for 120 minutes at an annealing temperature of 120°C.

[0047] (4) The original 20% (mass fraction) perhydropolysilazane (PHPS) solution was diluted to 2% (mass fraction) using anhydrous dibutyl ether (DBE). The diluted PHPS solution was then spin-coated (6000 r / min, 30 s) on the P(VDF-TrFE-CTFE) film. The thickness of the spin-coated PHPS film was about 20 nm. The device with the spin-coated PHPS solution was irradiated under 256 Hz ultraviolet light for 1 hour.

[0048] (5) 40 nm of pentacene was prepared on the PHPS-derived layer by evaporation.

[0049] (6) A source electrode and a drain electrode are prepared on the pentacene layer using an evaporation device. The channel width and length between the source electrode and the drain electrode are 200 μm and 110 μm, and the electrode pattern is determined by a mask.

[0050] Embodiment 2:

[0051] (1) The PET substrate was placed in deionized water, acetone solution, and isopropanol solution in turn and ultrasonically cleaned for 10 minutes each. After cleaning, the substrate was blown dry with a nitrogen gun.

[0052] (2) 30 nm Au was grown on the PET substrate by evaporation as the gate electrode.

[0053] (3) P(VDF-TrFE-CTFE) with a composition of 64.2 / 27.1 / 8.7 mol% was dissolved in BA to prepare a 7% (mass fraction) solution. The completely dissolved P(VDF-TrFE-CTFE) solution was spin-coated on the Au gate electrode. The thickness of the spin-coated P(VDF-TrFE-CTFE) film was 500 nm. The device spin-coated with the P(VDF-TrFE-CTFE) solution was placed in a vacuum oven and annealed for 120 minutes at a temperature of 120°C.

[0054] (4) DBE was used to dilute the original 20% (mass fraction) fully hydrogenated polysilazane solution to a concentration of 2% (mass fraction). The diluted PHPS solution was then spin-coated on the P(VDF-TrFE-CTFE) film. The thickness of the spin-coated PHPS film was 15 nm. The device with the spin-coated PHPS solution was placed under 256 Hz ultraviolet light for 1 hour.

[0055] (5) 40 nm PTCDI-C8 was prepared on the PHPS-derived layer by evaporation.

[0056] (6) The source and drain electrodes are prepared on the PTCDI-C8 layer using an evaporation device. The channel width and length between the source and drain electrodes are 200 μm and 110 μm, and the electrode pattern is determined by the mask.

[0057] according to Figure 3 The storage performance curves are compared with the transfer curves of the devices under the scanning gate voltage of ±15V and ±20V. The two are approximately coincident, proving that the P(VDF-TrFE-CTFE) layer has been completely polarized under the scanning gate voltage of ±15V. Therefore, the working voltage of the Fe-OFET-NVMs prepared in this experiment can be defined as ±15V. The average storage window and storage switching current ratio of the device under the scanning gate voltage of ±15V are calculated to be 13.2 and 3×10 4 .

[0058] according to Figure 4 Keeping the characteristic curve, apply a write voltage V to the device P =-15V or erase voltage V E =15V, repeatedly switch and monitor the reading current I SD Changes over time and organize data in Figure 4 In the overall test time of 5000s I SD The fluctuation is small. During the entire 5000s test time, the switching ratio of the device decreased slightly, and the residual current switching ratio was 5×10 3 For memory devices, this is sufficient to distinguish the device's ON and OFF states, and it also proves that the device still has great retention potential.

[0059] according to Figure 5 The bending performance curves, as shown in Figure 5(a), show that the device transfer curves under different bending states are approximately overlapped, indicating that the device has good mechanical flexibility. When the device curvature radius r is 10.0 mm and 5.0 mm, the average storage window can still maintain 95% (12.5 V) and 90% (11.8 V) of the device in the flat state, and the storage current switching ratio is 2×10 4 and 10 4, the flexible Fe-OFET-NVMs can work normally in the bent state.

[0060] In order to further test the mechanical bending durability of the device, the device was subjected to multiple bending tests. A total of 600 mechanical bendings were performed. After every 100 bendings, the transfer curve of the device was tested in a flat state for comparison. Figure 5 (b) As shown. By comparison, it is found that the maximum on-state current (I ON ) decreases slightly, and the storage switching ratio also tends to decrease, but it always remains at 10 3 above.

[0061] The above tests all show that the device has good mechanical flexibility.

[0062] The device prepared in Example 2 has the same storage performance, retention characteristics and bending performance as the device prepared in Example 1.

[0063] It should be pointed out that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology of this project to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. An organic field effect transistor based on P(VDF-TrFE-CTFE) / PHPS double insulating layer, characterized in that: The invention comprises a substrate, a gate electrode, a P (VDF-TrFE-CTFE) insulating layer, a PHPS-derived insulating layer, an organic semiconductor layer, a source electrode and a drain electrode.

2. The organic field effect transistor according to claim 1, characterized in that: The molar fractions of VDF, TrFE and CTFE in the P (VDF-TrFE-CTFE) insulating layer are 50% to 80%, 15% to 30% and 5% to 20% respectively.

3. The organic field effect transistor according to claim 1, characterized in that: The PHPS-derived insulating layer contains SiO X Film layer, thickness is 10-50nm.

4. A method for preparing an organic field effect transistor based on a P(VDF-TrFE-CTFE) / PHPS double insulating layer, characterized in that the steps include: S1: using an evaporation method to generate a gate electrode on a substrate; S2: Spin-coating a P (VDF-TrFE-CTFE) solution on the gate electrode, and performing an annealing treatment to form a P (VDF-TrFE-CTFE) insulating layer on the gate electrode; S3: Spin coating the PHPS solution on the P(VDF-TrFE-CTFE) insulating layer, and treating with ultraviolet light to generate a PHPS-derived insulating layer on the P(VDF-TrFE-CTFE) insulating layer; S4: using an evaporation method to generate an organic semiconductor layer on the PHPS-derived insulating layer; S5: preparing a source electrode and a drain electrode on the organic semiconductor layer by using an evaporation method.

5. The preparation method according to claim 4, characterized in that: In step S2, the mass fraction of the ternary ferroelectric copolymer P(VDF-TrFE-CTFE) in the P(VDF-TrFE-CTFE) solution is 5%-13%, and the molar fractions of VDF, TrFE and CTFE in P(VDF-TrFE-CTFE) are 50%-80%, 15%-30% and 5%-20% respectively.

6. The preparation method according to claim 4, characterized in that: In step S2, annealing is performed at 110-130° C. for 110-150 minutes.

7. The preparation method according to claim 4, characterized in that: In step S3, the mass fraction of PHPS in the PHPS solution is 1%-10%.

8. The preparation method according to claim 4, characterized in that: In step S3, irradiation is performed under 256 Hz ultraviolet light for 1-1.5 hours.

9. The preparation method according to claim 4, characterized in that: In step S3, the PHPS-derived insulating layer contains SiO X The thickness of the PHPS-derived insulating layer is 10-50 nm.

10. The preparation method according to claim 4, characterized in that: In step S4, the organic semiconductor includes but is not limited to any one or any combination of pentacene, PTCDI-C8, C8-BTBT, and P3HT.

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