A low-power-consumption organic field effect transistor memory array and a preparation method and application thereof

Abstract

The application relates to a low-power-consumption organic field effect transistor (OFET) memory array and a preparation method and application thereof, and belongs to the technical field of semiconductor memory arrays. The memory array of the application adopts an OFET memory as a basic device unit, a dielectric layer of which uses a zinc salt doped polyelectrolyte dielectric material processed by a solution, so that low-voltage operation of the device and effective electrical property regulation can be realized. The OFET memory array of the application has good storage characteristics, and can realize differentiation and effective writing and reading of different pixel points in a figure image through programming of a gate pulse voltage. Compared with traditional technologies, the OFET memory array of the application can simplify a manufacturing process and reduce cost, has advantages such as simple structure, excellent performance and low energy consumption, and is easy to be integrated into a high-density flexible storage array to realize effective electrical pulse imaging and smooth processing and calculation of pictures, thereby providing a new idea for development of storage technologies and imaging, image processing and neuromorphic computing applications.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor memory array, and relates to a low-power organic field-effect transistor memory array and a preparation method and application thereof. BACKGROUND

[0002] With the deepening of the informatization degree of social development, a large amount of data is continuously generated, and higher requirements are put forward for advanced storage technology. In information storage, it is currently desired that the memory can be integrated into a storage array to realize large-scale information storage, and the stored information can be read at any time; it is also desired that the storage array can efficiently compute and process the stored information to realize parallel storage and computation. In order to solve the problems of high energy consumption and high cost caused by large-scale information storage and computation, it is particularly important to develop advanced low-power memory and its array.

[0003] Organic field-effect transistor (OFET) has important potential in the field of new generation storage devices, because it can realize effective writing and reading of information, data storage, and in-memory computing, etc. by virtue of its characteristics of flexibility, thinness, and easy regulation of organic semiconductor and dielectric materials. When OFET is integrated into a storage array, not only can its tunable storage characteristics be guaranteed, but also large-scale information storage at the array level can be realized. Therefore, this integrated structure makes it possible for the storage array to break through the current von Neumann structure adopted by computer systems, greatly reduce the large amount of time required for data information transmission between the processor and the memory, and thus significantly improve the data processing speed. At the same time, OFET is also an excellent sensor carrier with rich sensing mechanisms and unique signal amplification characteristics. Various sensors based on OFET have been widely used in intelligent wear, electronic skin, biomedical detection, environmental protection, etc. Moreover, the OFET memory can further enhance the application value by virtue of its sensing and storage capabilities in practical applications, can store the detected information directly in the array, realize long-term storage and be used for subsequent information computation and processing, thereby improving the storage efficiency and running speed of the OFET memory array.

[0004] By using the response of the OFET memory array to photoelectric signals, the input signals can be converted into electrical signals to realize electrical pulse imaging, and the imaging graph can be directly processed and computed to enhance the data processing speed and function, which provides an effective way to improve the running speed of computers. Therefore, there is a wide demand and important practical significance to design and develop integrated low-power OFET memory arrays, which will show great potential and application value in the fields of pulse imaging, image processing, intelligent sensing chips, and neuromorphic computing, etc. SUMMARY

[0005] Therefore, one of the purposes of the present application is to provide a low-power-consumption organic field effect transistor memory array; another purpose of the present application is to provide a preparation method of the low-power-consumption organic field effect transistor memory array; and a third purpose of the present application is to provide an application of the low-power-consumption organic field effect transistor memory array in pulse imaging, image processing, artificial synapse or neuromorphic computing technology.

[0006] To achieve the above purposes, the present application provides the following technical solutions:

[0007] 1. According to one aspect of the present application, a low-power-consumption organic field effect transistor memory array is provided, wherein the memory array is formed by integrating organic field effect transistor memories based on ion migration effect to realize storage function.

[0008] The memory array is of a top-gate bottom-contact structure, and sequentially comprises, from bottom to top, a substrate 1, a source / drain electrode pair, an organic semiconductor layer 4, a dielectric passivation layer 5, a doped polyelectrolyte dielectric layer 6 and a gate 7.

[0009] The source / drain electrode pair is located between the surface of the substrate 1 and the organic semiconductor layer 4, and is composed of a source electrode 2 and a drain electrode 3 arranged side by side, and a micro-nano scale spacing channel is formed between the source electrode 2 and the drain electrode 3.

[0010] The number of the source / drain electrode pair and the gate 7 is 4 or more, and the gate 7 region covers the channel region of the corresponding source / drain electrode pair.

[0011] Preferably, the material of the substrate 1 is any one or several of polyethylene terephthalate, polyethylene naphthalate, polyimide, polydimethylsiloxane, polycarbonate, polyvinyl alcohol, glass, silicon wafer (i.e. silicon dioxide / silicon) or sapphire.

[0012] Further preferably, the material of the substrate 1 is any one of polyethylene naphthalate, polyethylene terephthalate, polyimide or polydimethylsiloxane.

[0013] Preferably, the material of the source electrode 2, the drain electrode 3 or the gate 7 is any one or several of gold, silver, aluminum, copper, chromium, platinum, titanium, nickel, indium tin oxide, fluorine-doped tin oxide, zinc aluminum oxide, carbon nanotube, graphene or conductive polymer.

[0014] The conductive polymer has a conjugated main electron system on the main chain and is a high molecular material in a conductive state achieved by doping, and the conductive polymer includes any one of polypyrrole, polyaniline, polythiophene, poly(3,4-ethylenedioxythiophene) or polyacetylene.

[0015] Further preferably, the material of the source electrode 2, the drain electrode 3 or the gate electrode 7 is any one of gold, silver, aluminum or copper.

[0016] Preferably, the material of the organic semiconductor layer 4 is any one of an organic small molecule semiconductor material or a conjugated polymer semiconductor material.

[0017] The organic small molecule semiconductor material includes any one or several of pentacene or its derivative, 7,7,8,8-tetracyanoquinodimethane or its derivative, or copper phthalocyanine.

[0018] The conjugated polymer semiconductor material includes any one or several of poly(3-hexylthiophene) or its derivative, indacenodithiophene-benzothiadiazole copolymer, 7,7,8,8-tetracyanoquinodimethane doped indacenodithiophene-benzothiadiazole copolymer, poly{4,8-bis[(2-ethylhexyl)oxy]benzo[l,2-b:4,5-b']dithiophene-2,6-diyl}{3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]thiophenediyl} or its derivative, or copolymer of dithiophene and perylene imide units.

[0019] Further preferably, the material of the organic semiconductor layer 4 is a conjugated polymer semiconductor material selected from any one or several of poly(3-hexylthiophene) and its derivative, indacenodithiophene-benzothiadiazole copolymer, 7,7,8,8-tetracyanoquinodimethane doped indacenodithiophene-benzothiadiazole copolymer.

[0020] Preferably, the material of the dielectric passivation layer 5 includes any one or several of polymethyl methacrylate or its derivative, polystyrene or its derivative, amorphous fluorine resin or its derivative, aluminum oxide, hafnium dioxide or zirconium dioxide.

[0021] Further preferably, the material of the dielectric passivation layer 5 includes any one or several of polymethyl methacrylate or its derivative, polystyrene or its derivative, amorphous fluorine resin or its derivative.

[0022] Preferably, the doped polyelectrolyte dielectric layer 6 is a dielectric film material of a soluble zinc salt doped polyelectrolyte.

[0023] The material of the polyelectrolyte in the dielectric film material of the soluble zinc salt doped polyelectrolyte is at least one of polyacrylic acid or its derivative, polyacrylamide or its derivative, a polyelectrolyte composite dielectric material formed by compounding polyacrylic acid and polymethyl methacrylate, a polyelectrolyte composite dielectric material formed by compounding polyacrylic acid and polyethylene glycol, or a polyelectrolyte composite dielectric material formed by compounding polyacrylic acid and polyvinyl alcohol.

[0024] The soluble zinc salt is any one or several of zinc chloride, zinc bromide, zinc iodide, zinc acetate, zinc sulfate, zinc nitrate, zinc fluosilicate, zinc fluoroborate or zinc gluconate.

[0025] Further preferably, the material of the polyelectrolyte in the dielectric thin film material doped with the soluble zinc salt is at least one of polyacrylic acid and its derivatives, polyacrylamide and its derivatives, and a polyelectrolyte composite dielectric material composed of polyacrylic acid and polyethylene glycol.

[0026] The soluble zinc salt is any one or several of zinc chloride, zinc bromide, zinc iodide.

[0027] Still further preferably, the dielectric thin film material doped with the soluble zinc salt is prepared by the following method:

[0028] First, the polyelectrolyte material is dissolved in a solvent to obtain a polyelectrolyte precursor solution; then, the soluble zinc salt is added and fully dissolved to obtain a solution of the dielectric material doped with the soluble zinc salt; finally, the solution is processed into a film by a solution processing method, and the dielectric thin film material doped with the soluble zinc salt is prepared after annealing treatment.

[0029] The doping content of the soluble zinc salt accounts for 0.5-10 wt.% of the total mass of the polyelectrolyte material and the zinc salt material.

[0030] 2. According to another aspect of the present application, there is provided a preparation method of the above-mentioned low-power-consumption organic field effect transistor memory array, which comprises the following steps:

[0031] (1) forming more than or equal to 4 pairs of source / drain electrode pairs each composed of a source electrode and a drain electrode in parallel on the surface of a substrate by any one of vacuum thermal evaporation, magnetron sputtering, atomic layer deposition, inkjet printing or drop coating, and forming a micro / nano-scale channel between the source electrode and the drain electrode;

[0032] (2) forming an organic semiconductor layer on the surface of the source electrode, the drain electrode and the substrate by any one of spin coating, blade coating or inkjet printing;

[0033] (3) forming a dielectric passivation layer on the surface of the organic semiconductor layer by any one of atomic layer deposition, vacuum thermal evaporation, magnetron sputtering, spin coating, blade coating or inkjet printing;

[0034] (4) forming a dielectric layer doped with a polyelectrolyte by processing a solution of the dielectric material doped with the polyelectrolyte into a film on the surface of the dielectric passivation layer by a solution processing method, and preparing the dielectric layer doped with the polyelectrolyte after annealing treatment;

[0035] (5) on the surface of the doped polyelectrolyte dielectric layer, a mask plate is combined and a gate is prepared by any one of magnetron sputtering, vacuum thermal evaporation, atomic layer deposition, inkjet printing or drop coating, wherein the number of the gate is the same as the logarithm of the source / drain electrode pair, thereby obtaining a low-power-consumption organic field effect transistor memory array.

[0036] Preferably, in step (4), the solution processing method is any one of spin coating, blade coating or inkjet printing.

[0037] In step (4), the concentration of the polyelectrolyte material in the solution used in the spin coating processing method is 5-50 mg / mL, the rotation speed of the spin coating is 200-4000 rpm, and the spin coating time is 30-120 s.

[0038] In step (4), the annealing temperature is 50-200℃, and the annealing time is not less than 60 min.

[0039] Further preferably, in step (4), the concentration of the polyelectrolyte material in the solution used in the spin coating processing method is 10-40 mg / mL, and the annealing temperature is 60-180℃.

[0040] More preferably, in step (4), the concentration of the polyelectrolyte material in the solution used in the spin coating processing method is 15-35 mg / mL, and the annealing temperature is 70-150℃.

[0041] 3. According to another aspect of the present application, the above-mentioned low-power-consumption organic field effect transistor memory array is provided for use in pulse imaging, image processing, artificial synapse or neuromorphic computing technology.

[0042] The low-power-consumption organic field effect transistor memory array disclosed in the present application has the following advantages:

[0043] (1) The organic field effect transistor memory array of the present application realizes storage function based on the ion migration enhancement effect of the zinc salt doped polyelectrolyte dielectric layer, a novel dielectric material system, and the memory storage characteristics of ion migration can be controlled by voltage size, thereby successfully developing a flexible organic field effect transistor memory array with low voltage and multi-level storage characteristics. This new type of organic field effect transistor memory array breaks through the traditional strategy of realizing storage characteristics based on floating gate device structure, and provides a new choice and beneficial idea for high-performance low-power-consumption transistor memory array.

[0044] (2) The organic field effect transistor memory array of the present application can fully utilize the three-terminal structure advantage of a single memory cell in the device array, realize writing of different amplitude electric pulses by applying different voltages to the gate, and can realize reverse programming gate pulse voltage erasing and fast writing of electric pulses to meet the application requirements of information learning and memory function type memory, and has great potential in machine vision, deep learning and other aspects.

[0045] (3) The organic field effect transistor memory array of the present application also has the advantages of simple structure, excellent performance, low energy consumption, and can be effectively integrated into a high-density multi-pixel storage array for electric pulse imaging, image processing and other applications. The storage and computing applications of such organic field effect transistor memory array can output the smoothing processing results of the imaging graph at the same time while completing imaging, and can efficiently and accurately complete storage, imaging and computing. Compared with the traditional technology, the low-power organic field effect transistor memory array of the present application not only has a simple manufacturing process, but also has the characteristics of simple process, low preparation cost, effective promotion, and can effectively integrate the characteristics of flexible organic semiconductors and dielectric materials and flexible substrates to construct large-area flexible storage arrays and integrated devices, providing new inspiration for the application and development of future new storage technologies and neuromorphic computing technologies.

[0046] (4) The organic field effect transistor memory array of the present application can also be used as an important carrier to integrate and integrate various flexible sensing materials, devices and chips, greatly improve the data processing speed, and combine sensing, storage and computing functions, thereby providing an important basis for the development and application of new sensing-storage-computing function integrated electronic equipment and intelligent terminals.

[0047] Other advantages, objects, and features of the present application will be in part apparent and in part pointed out hereinafter in the specification, and will be learned from a reading of the following specification and by practicing the present application. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and claims hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to make the objects, technical solutions and advantages of the present application clearer, the preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings, in which:

[0049] Figure 1 Structure diagram of the organic field effect transistor memory array prepared for Example 1;

[0050] Figure 2 Typical transfer (a) and output (b) characteristic curves of a single organic field effect transistor memory in the organic field effect transistor memory array prepared for Example 1;

[0051] Figure 3 (a) positive bias and (b) negative bias pulse response characteristics of a single unit organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 1;

[0052] Figure 4 Typical transfer (a) and output (b) characteristics curves of a single unit organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 2;

[0053] Figure 5 Transfer (a) and output (b) characteristics curves of a single unit organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 3;

[0054] Figure 6 Equivalent circuit schematic (a) and additional equivalent circuit schematic (b) based on image processing of the organic field effect transistor memory array prepared in Example 1;

[0055] Figure 7 Person original image (a) and electrical pulse imaging image (b) of the organic field effect transistor memory array prepared in Example 1;

[0056] Figure 8 Imaging smoothing processing image of the organic field effect transistor memory array prepared in Example 1;

[0057] Figure 9 Imaging conceptual model schematic of the organic field effect transistor memory array prepared in Example 1;

[0058] In the structural schematic of the organic field effect transistor memory array, 1 is a substrate, 2 is a source electrode, 3 is a drain electrode, 4 is an organic semiconductor layer, 5 is a dielectric passivation layer, 6 is a doped polyelectrolyte dielectric layer, and 7 is a gate electrode. DETAILED DESCRIPTION

[0059] The present application is described herein with reference to specific embodiments thereof which are illustrated in the attached drawings. These embodiments are described in detail to enable practitioners in the art to practice the application in various embodiments, and it is understood that the descriptions given herein are not to be taken as limiting the application. Although specific embodiments of the application can be illustrated and described herein, it is well understood that various presentments are not intended to limit the spirit or scope of the present application. The embodiments presented herein are merely for illustrative purposes, and various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application. It is therefore desired that what is claimed should be understood to be within the spirit and purview of the application.

[0060] In the following examples, the polyelectrolyte in the dielectric material doped with a soluble zinc salt is a cross-linked compound of polyacrylic acid and polyethylene glycol (mass ratio 7:3), and the doped soluble zinc salt is zinc chloride.

[0061] In the following examples, if no specific conditions are specified, all the reactions were carried out under conventional conditions or conditions recommended by the manufacturer. Unless otherwise specified, the raw materials and solvents in the examples of the present invention were purchased from commercial sources, including:

[0062] The organic polymer semiconductor material indocyanine-dithiophene-benzothiadiazole copolymer was purchased from Shenzhen Ruixun Optoelectronic Material Technology Co., Ltd.

[0063] Chlorobenzene solvent and methanol solvent were purchased from Sigma-Aldrich (Shanghai) Trading Co., Ltd.;

[0064] Polyacrylic acid and polyethylene glycol were purchased from Sigma-Aldrich (Shanghai) Trading Co., Ltd.;

[0065] Zinc chloride was purchased from Shanghai MacLean Biochemical Technology Co., Ltd.

[0066] Polystyrene was purchased from Sigma-Aldrich (Shanghai) Trading Co., Ltd.;

[0067] Butyl acetate solvent was purchased from Sinopharm Chemical Reagent Co., Ltd.

[0068] Example 1

[0069] A low-power organic field-effect transistor memory array, the specific structure is as follows Figure 1 As shown, it comprises, from bottom to top, a substrate 1, an organic semiconductor layer 4, a dielectric passivation layer 5, a doped polyelectrolyte dielectric layer 6, and a gate 7. There are 100 source / drain electrode pairs (the source / drain electrode pairs are formed by a source electrode 2 and a drain electrode 3 arranged side by side) disposed between the surface of the substrate 1 and the organic semiconductor layer 4. The method for preparing the low-power organic field-effect transistor memory array is as follows:

[0070] (1) Using 125 μm thick polyethylene naphthalate as the substrate;

[0071] (2) On the surface of the substrate, a vacuum thermal evaporation process (vacuum degree of about 2×10 -4 Pa, evaporation rate is about ) preparing 50 nm thick gold as a 10×10 array of source and drain electrodes (wherein the width and length of the channel between the source and drain electrodes are 3.75 mm and 0.15 mm, respectively), to obtain a substrate having a 10×10 array of source and drain electrodes;

[0072] (3) A solution of the indacenenediyl-benzothiadiazole copolymer in chlorobenzene with a concentration of 5 mg / mL was prepared under a nitrogen atmosphere and spin-coated onto the substrate with the 10 x 10 array of source and drain electrodes obtained in step (2) (the spin-coating process was performed at a rotation speed of 2000 rpm for 30 s), and after spin-coating, annealing was performed on a hot plate at 90°C for 20 min to form the organic semiconductor layer;

[0073] (4) A solution of polystyrene in butyl acetate with a concentration of 5 mg / mL was spin-coated onto the organic semiconductor layer obtained in step (3) (the spin-coating process was performed at a rotation speed of 2000 rpm for 30 s), and after spin-coating, the sample was left to stand for 10 min to form the dielectric passivation layer;

[0074] (5) A polyelectrolyte solution of poly(acrylic acid) and poly(ethylene glycol) was prepared by dissolving poly(acrylic acid) and poly(ethylene glycol) in a mass ratio of 7:3 in methanol (the concentration of poly(acrylic acid) in the solution was 30 mg / mL), and zinc chloride was added for doping (the mass of zinc chloride accounted for 2.62 wt.% of the total mass of the solutes of poly(acrylic acid), poly(ethylene glycol) and zinc chloride), to obtain a dielectric material solution of a soluble zinc salt-doped polyelectrolyte, which was spin-coated onto the dielectric passivation layer obtained in step (4) (the spin-coating process was performed at a rotation speed of 500 rpm for 30 s, and the spin-coating was performed twice), and after spin-coating, annealing was performed on a hot plate at 90°C for 120 min to form the doped polyelectrolyte dielectric layer;

[0075] (6) A 50 nm-thick gold gate electrode was prepared on the doped polyelectrolyte dielectric layer by a vacuum thermal evaporation process (the vacuum degree was about 2 x 10 -4 Pa, and the evaporation rate was about ) through a mask, wherein the 100 gate electrodes covered the channel portions formed between the source and drain electrodes in the 100 source / drain electrode pairs, respectively, to form the low-power-consumption organic field effect transistor memory array.

[0076] Examples 2-12

[0077] The different parts of the preparation processes of the low-power-consumption organic field effect transistor memory arrays in Examples 2-12 and Example 1 are shown in Table 1, and the parts not mentioned are the same as in Example 1.

[0078] Table 1 Various materials used in the preparation of low-power-consumption organic field effect transistor memory arrays in different examples

[0079]

[0080]

[0081] Performance test

[0082] 1. Performance test of low power consumption OFET memory array prepared in the example

[0083] Each single OFET memory in the OFET memory array prepared in the above Example 1 was tested for electrical performance by using Agilent 4155C semiconductor parameter analyzer, and the performance fluctuation between the memory units was small. Figure 2 Typical transfer (a) and output (b) characteristic curves of a single OFET memory in the OFET memory array prepared in Example 1 are shown in Figures 1 and 2, respectively. Figure 2 It can be seen that the single OFET memory in the OFET memory array of the present application can work at a low voltage of -1.5 V, and has good low power consumption transistor characteristics. Further, the single OFET memory in the OFET memory array prepared in the above Example 1 was tested for electrical pulse response characteristics by using 4155C semiconductor parameter analyzer, and the electrical pulse response characteristics of the single OFET memory in the OFET memory array prepared in Example 1 are shown in Figures 3 and 4, respectively, by adjusting the programming gate pulse voltage, wherein a is the positive bias electrical pulse response characteristics of the OFET memory, and b is the negative bias electrical pulse response characteristics of the OFET memory. Figure 3 Figure 3 It can be seen that the pulse current changes with the change of the applied programming gate pulse voltage, the higher the programming gate pulse voltage, the greater the pulse current, and the longer the current duration, which indicates that the OFET memory based on the soluble zinc salt doped polyelectrolyte dielectric layer of the present application has excellent dynamic storage characteristics. At the same time, the erasing operation of the OFET memory in the array can be achieved by applying a reverse programming gate pulse voltage, and fast erasing or reverse writing can be achieved by ultraviolet irradiation.

[0084] The single OFET memory in the OFET memory array prepared in the above Example 2 and Example 3 was tested for performance by using Agilent 4155C semiconductor parameter analyzer, Figure 4 Typical transfer (a) and output (b) characteristic curves of a single OFET memory in the OFET memory array prepared in Example 2 are shown in Figures 5 and 6, respectively. Figure 5 ​The transfer (a) and output (b) characteristics of the single element OFET memory in the OFET memory array prepared in Example 3 were measured. Comparison of the typical transfer and output characteristics of the single element OFET memory in the OFET memory array in different examples shows that the performance of the OFET memory of the present application has a dependence on the polymeric electrolyte dielectric layer with different doping contents of zinc chloride, and has the potential of storage characteristics that can be easily adjusted.

[0085] Similarly, the performance of the single element OFET memory in the OFET memory array prepared in other examples was tested according to the above test method, and the results were similar to the performance of the single element OFET memory in the OFET memory array prepared in Example 1 above, indicating that the single element OFET memory unit in the OFET memory array prepared according to the present application can also realize a low-power storage device and its array by using the ion migration characteristics, and has a good prospect in the future research and development of polymeric electrolyte system dielectric layer materials and storage applications.

[0086] 2. Application of electrical pulse imaging to OFET memory array

[0087] First, based on the low-power OFET memory array prepared in Example 1, 36 such 10x10 OFET memory arrays were further expanded and combined into a 60x60 array. Then, the 60x60 storage array was used to realize the electrical pulse imaging of the original image of a person, and the equivalent circuit diagram of the array, the additional equivalent circuit diagram based on image processing, and the additional equivalent circuit schematic diagram based on image processing are shown in Figure 6 a and 6b, respectively. As can be seen from Figure 6 a, the prepared 60x60 storage array has 3600 mutually independent gates, 60 drain lead wires, and 60 mutually parallel drains on each drain lead wire, totaling 3600 drains, and similarly, there are 3600 sources, finally forming 3600 source / drain electrode pairs. Figure 6 b is a mean current calculation circuit, which introduces the adjacent 4 output currents in the 60x60 storage array into the mean current calculation circuit, and the circuit outputs the average of the 4 output currents.

[0088] The original image of a person of the OFET memory array prepared in Example 1 is shown in Figure 7 a, and the programming gate pulse voltages of +1.5, -1.5, -2.5, -3.5 and -4.5 V were sequentially applied to the storage array to distinguish the pixel points in the pixel image of the person and to image, and the results are shown in Figure 7b's electrical pulse imaging diagram, and at the same time stores the image information in an organic field effect transistor memory array. Figure 7 It can be seen that the character electric pulse imaging image realized by the memory array can clearly present the image details in the character pixel image, but the clarity at the edge still needs to be improved ( Figure 7 b) In particular, the clarity of the eyes and collars in the electrical impulse imaging of people is poor and needs to be further improved.

[0089] 3. Smoothing calculation of organic field effect transistor memory array imaging

[0090] Thanks to the fast and convenient memory characteristics of the prepared low-power organic field-effect transistor memory, especially the wide memory window, multi-level storage characteristics, and effective erase function of the organic field-effect transistor memory with a zinc chloride doping content of 2.62 wt.%, this type of organic field-effect transistor memory can be further integrated into a flexible memory array for image processing and analog computing. Therefore, four adjacent pixels in the organic field-effect transistor memory array are first used as the calculation area, and five levels of programming gate pulse voltage corresponding to the pixel levels in the original image of the person in the organic field-effect transistor memory array are applied to the calculation area. The organic field-effect transistor memory array converts the received five levels of programming gate pulse voltage into a current signal and outputs it. At the same time, the output current enters an additional average current circuit to calculate the average current of the pulse within the calculation area and output it. After completion, it is transferred to the next calculation area. After completion, the average current of the calculation area is output in sequence and used as the center point of the calculation area to replace the entire calculation area, thus completing the smoothing of the current output by the four transistors in the calculation area. Finally, the obtained average current is arranged and mapped to form an image, resulting in a smoothed image, as shown in the figure. Figure 8 As shown. Figure 8 It can be seen that compared with the character electric pulse imaging image of the storage array, the character image after smoothing processing has better imaging in parts such as the eyes and clothing collar, and the image after image smoothing processing has a better sense of character image and three-dimensionality. This shows that the use of mean filtering to process the pixels in the storage array can better preserve the key point information data in the character imaging process. The comprehensive comparison shows the superiority of using mean filtering in the storage array. While successfully retaining the key information in the character pixel image, it reduces the original Figure Four It can save one-third of the storage space and make the image smoother and more three-dimensional.

[0091] Therefore, we propose a conceptual model for imaging of low-power organic field-effect transistor memory arrays. Figure 9As shown, that is, the point-to-point writing information of the organic field effect transistor memory array is realized by using the electric pulse signal, and the writing information can be erased by using ultraviolet light irradiation, and the output current of the point-to-point writing information of the programming gate pulse voltage is calculated by the additional mean current calculation circuit, and the smooth processing of the whole imaging graph of the memory array is realized, so that the low-power-consumption organic field effect transistor memory array of the present application not only realizes the electric pulse imaging of the human image, but also guarantees the corresponding image basic information, and in addition, the smooth processing and calculation of the imaging graph can be realized by using a simple additional circuit. The organic field effect transistor memory array shows the characteristics of fast storage and convenient memory, and by using the simple storage array circuit filtering processing, the display effect of the imaging graph can be directly and effectively processed, and the application value of the organic field effect transistor storage array in the direction of pulse imaging and array simulation calculation is shown.

[0092] In summary, the low-power-consumption organic field effect transistor memory array is disclosed, which is mainly constructed by using zinc chloride doped polyacrylic acid and polyethylene glycol composite cross-linked material to construct a doped polyelectrolyte dielectric film, and the ion migration ability in the new type of polyelectrolyte dielectric film is regulated by voltage, so that a low-power-consumption, high-performance flexible organic field effect transistor memory array is successfully developed. The low-power-consumption organic field effect transistor memory of the present application can fully utilize the advantages of the three-terminal structure of the organic field effect transistor, and by applying different programming gate pulse voltages to the gate, the dynamic storage regulation of the basic storage unit in the memory array is realized, so as to meet the needs of fast storage and erasing of the information learning and memory function type storage device. In addition, the storage and calculation application of the organic field effect transistor memory array can output the smooth processing result of the imaging graph at the same time when completing imaging, which further improves the running speed of the storage and calculation. Compared with the traditional technology, the organic field effect transistor memory array of the present application simplifies the manufacturing process and reduces the cost, has the advantages of simple structure, excellent performance, low energy consumption, and can be designed as a high-density multi-pixel storage array and a large-area flexible storage array, effectively writes or erases the electric pulse, and provides a beneficial idea for the research of new type of storage material and device, and the popularization and application of electric pulse imaging, image processing, sensing chip, neuromorphic computing and other technologies.

[0093] Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting, although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should be covered in the scope of the claims of the present application.

Claims

1. A low-power organic field-effect transistor memory array, characterized in that: The memory array is formed by integrating organic field effect transistor memories that realize storage functions based on ion migration effects; The memory array is a top-gate bottom-contact structure, comprising, from bottom to top, a substrate (1), a source / drain electrode pair, an organic semiconductor layer (4), a dielectric passivation layer (5), a doped polyelectrolyte dielectric layer (6), and a gate (7); The source / drain electrode pair is located between the surface of the substrate (1) and the organic semiconductor layer (4), and the source / drain electrode pair is composed of a source electrode (2) and a drain electrode (3) arranged side by side, and a channel with a micro-nanoscale spacing is formed between the source electrode (2) and the drain electrode (3); The number of the source / drain electrode pairs and the gate (7) is 4 or more, and the gate (7) region covers the channel region of the corresponding source / drain electrode pair; The doped polyelectrolyte dielectric layer (6) is a dielectric film material of a soluble zinc salt doped polyelectrolyte.

2. The low-power organic field-effect transistor memory array according to claim 1, wherein: The material of the substrate (1) is any one or more of polyethylene terephthalate, polyethylene naphthalate, polyimide, polydimethylsiloxane, polycarbonate, polyvinyl alcohol, glass, silicon wafer or sapphire.

3. The low-power organic field-effect transistor memory array according to claim 1, wherein: The material of the source electrode (2), drain electrode (3) or gate electrode (7) is any one or more of gold, silver, aluminum, copper, chromium, platinum, titanium, nickel, indium tin oxide, fluorine-doped tin oxide, zinc aluminum oxide, carbon nanotubes, graphene or conductive polymer; The conductive polymer has a conjugated main electron system on its main chain and is a polymer material that achieves a conductive state through doping. The conductive polymer includes any one of polypyrrole, polyaniline, polythiophene, poly(3,4-ethylenedioxythiophene) or polyacetylene.

4. The low-power organic field-effect transistor memory array according to claim 1, wherein: The material of the organic semiconductor layer (4) is an organic small molecule semiconductor material or a conjugated polymer semiconductor material; The organic small molecule semiconductor material includes any one or more of pentacene or its derivatives, 7,7,8,8-tetracyanoquinodimethane or its derivatives, and copper phthalocyanine; The conjugated polymer semiconductor material includes any one or more of poly 3-hexylthiophene or its derivatives, indobenzothiadiazole copolymer, 7,7,8,8-tetracyanoquinodimethane-doped indobenzothiadiazole copolymer, poly{4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']disulfide-2,6-diyl}{3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]thiophenediyl} or its derivatives, and copolymers of terthiophene and perylene imide units.

5. The low-power organic field-effect transistor memory array according to claim 1, wherein: The material of the dielectric passivation layer (5) includes any one or more of polymethyl methacrylate or its derivatives, polystyrene or its derivatives, amorphous fluororesin or its derivatives, aluminum oxide, hafnium dioxide or zirconium dioxide.

6. The low-power organic field-effect transistor memory array according to claim 1, wherein: The polyelectrolyte material in the dielectric film material of the soluble zinc salt doped polyelectrolyte is at least one of polyacrylic acid or its derivatives, polyacrylamide or its derivatives, a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polymethyl methacrylate, a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polyethylene glycol, and a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polyvinyl alcohol; The soluble zinc salt is any one or more of zinc chloride, zinc bromide, zinc iodide, zinc acetate, zinc sulfate, zinc nitrate, zinc fluorosilicate, zinc fluoroborate or zinc gluconate.

7. The low-power organic field-effect transistor memory array according to claim 6, wherein: The dielectric film material of the soluble zinc salt-doped polyelectrolyte is prepared according to the following method: First, a polyelectrolyte material is dissolved in a solvent to obtain a polyelectrolyte precursor solution; then, a soluble zinc salt is added and fully dissolved to obtain a soluble zinc salt-doped polyelectrolyte dielectric material solution; finally, the solution is processed into a film by a solution processing method and annealed to prepare a soluble zinc salt-doped polyelectrolyte dielectric thin film material; The doping content of the soluble zinc salt accounts for 0.5-10 wt.% of the total mass of the entire polyelectrolyte material and the zinc salt material.

8. The method for preparing a low-power organic field-effect transistor memory array according to any one of claims 1 to 7, characterized in that: The preparation method comprises the following steps: (1) Forming four or more pairs of source / drain electrodes consisting of a source electrode and a drain electrode arranged side by side on the surface of a substrate by any one of vacuum thermal evaporation, magnetron sputtering, atomic layer deposition, inkjet printing or drop coating, wherein a channel with a micro-nanoscale spacing is formed between the source electrode and the drain electrode; (2) forming an organic semiconductor layer on the surface of the source electrode, the drain electrode and the substrate by any one of spin coating, blade coating or inkjet printing; (3) forming a dielectric passivation layer on the surface of the organic semiconductor layer by any one of atomic layer deposition, vacuum thermal evaporation, magnetron sputtering, spin coating, blade coating or inkjet printing; (4) processing a solution of a dielectric material of a soluble zinc salt doped with a polyelectrolyte into a film on the surface of the dielectric passivation layer by a solution processing method, and preparing a doped polyelectrolyte dielectric layer after annealing; (5) On the surface of the doped polyelectrolyte dielectric layer, a mask is combined and a gate is formed by any one of magnetron sputtering, vacuum thermal evaporation, atomic layer deposition, inkjet printing or drop coating, wherein the number of the gates is the same as the number of pairs of source / drain electrode pairs, thereby obtaining a low-power organic field-effect transistor memory array.

9. The preparation method according to claim 8, characterized in that In step (4), the solution processing method is any one of spin coating, blade coating or inkjet printing; In step (4), the concentration of the polyelectrolyte material in the solution used in the spin coating method is 5-50 mg / mL, the spin coating speed is 200-4000 rpm, and the spin coating time is 30-120 s; In step (4), the annealing temperature is 50-200°C, and the annealing time is not less than 60 minutes.

10. Application of the low-power organic field-effect transistor memory array according to any one of claims 1 to 7 in pulse imaging, image processing, artificial synapses or neuromorphic computing technologies.

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